From 2d70fc90f6df72c1de9376383879ad0860a624fb Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 23 Jan 2018 18:03:20 +0100 Subject: [PATCH 1/9] Updated STM32L1xx CMSIS to v2.2.3 Included in STM32CubeL1 FW V1.8.1 Signed-off-by: Frederic.Pillon --- .../Device/ST/STM32L1xx/Include/stm32l100xb.h | 28 ++- .../ST/STM32L1xx/Include/stm32l100xba.h | 28 ++- .../Device/ST/STM32L1xx/Include/stm32l100xc.h | 218 ++++++++++++++++-- .../Device/ST/STM32L1xx/Include/stm32l151xb.h | 9 +- .../ST/STM32L1xx/Include/stm32l151xba.h | 9 +- .../Device/ST/STM32L1xx/Include/stm32l151xc.h | 199 ++++++++++++++-- .../ST/STM32L1xx/Include/stm32l151xca.h | 41 ++-- .../Device/ST/STM32L1xx/Include/stm32l151xd.h | 41 ++-- .../ST/STM32L1xx/Include/stm32l151xdx.h | 41 ++-- .../Device/ST/STM32L1xx/Include/stm32l151xe.h | 41 ++-- .../Device/ST/STM32L1xx/Include/stm32l152xb.h | 9 +- .../ST/STM32L1xx/Include/stm32l152xba.h | 9 +- .../Device/ST/STM32L1xx/Include/stm32l152xc.h | 199 ++++++++++++++-- .../ST/STM32L1xx/Include/stm32l152xca.h | 41 ++-- .../Device/ST/STM32L1xx/Include/stm32l152xd.h | 41 ++-- .../ST/STM32L1xx/Include/stm32l152xdx.h | 41 ++-- .../Device/ST/STM32L1xx/Include/stm32l152xe.h | 41 ++-- .../Device/ST/STM32L1xx/Include/stm32l162xc.h | 199 ++++++++++++++-- .../ST/STM32L1xx/Include/stm32l162xca.h | 41 ++-- .../Device/ST/STM32L1xx/Include/stm32l162xd.h | 41 ++-- .../ST/STM32L1xx/Include/stm32l162xdx.h | 41 ++-- .../Device/ST/STM32L1xx/Include/stm32l162xe.h | 41 ++-- .../Device/ST/STM32L1xx/Include/stm32l1xx.h | 2 +- .../Device/ST/STM32L1xx/Release_Notes.html | 15 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 25 files changed, 1086 insertions(+), 332 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h index 3ceb7f8e56..ff3c36a8ad 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h @@ -423,10 +423,12 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */ } RI_TypeDef; /** @@ -5584,6 +5586,26 @@ typedef struct #define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */ #define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */ +/******************** Bit definition for RI_HYSCR3 register ********************/ +#define RI_HYSCR3_PE_Pos (0U) +#define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */ +#define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */ +#define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */ +#define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */ +#define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */ +#define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */ +#define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */ +#define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */ +#define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */ +#define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */ +#define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */ +#define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */ +#define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */ +#define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */ +#define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */ +#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */ +#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */ +#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */ /******************************************************************************/ /* */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h index 9af4e87420..0194931f19 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h @@ -423,10 +423,12 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */ } RI_TypeDef; /** @@ -5732,6 +5734,26 @@ typedef struct #define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */ #define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */ +/******************** Bit definition for RI_HYSCR3 register ********************/ +#define RI_HYSCR3_PE_Pos (0U) +#define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */ +#define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */ +#define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */ +#define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */ +#define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */ +#define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */ +#define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */ +#define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */ +#define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */ +#define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */ +#define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */ +#define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */ +#define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */ +#define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */ +#define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */ +#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */ +#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */ +#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */ /******************************************************************************/ /* */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xc.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xc.h index 7b606b9824..f5d4a41658 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xc.h @@ -435,20 +435,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -5929,6 +5936,65 @@ typedef struct #define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */ #define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */ +/******************** Bit definition for RI_HYSCR3 register ********************/ +#define RI_HYSCR3_PE_Pos (0U) +#define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */ +#define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */ +#define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */ +#define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */ +#define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */ +#define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */ +#define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */ +#define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */ +#define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */ +#define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */ +#define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */ +#define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */ +#define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */ +#define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */ +#define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */ +#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */ +#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */ +#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */ +#define RI_HYSCR3_PF_Pos (16U) +#define RI_HYSCR3_PF_Msk (0xFFFFU << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */ +#define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */ +#define RI_HYSCR3_PF_0 (0x0001U << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */ +#define RI_HYSCR3_PF_1 (0x0002U << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */ +#define RI_HYSCR3_PF_2 (0x0004U << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */ +#define RI_HYSCR3_PF_3 (0x0008U << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */ +#define RI_HYSCR3_PF_4 (0x0010U << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */ +#define RI_HYSCR3_PF_5 (0x0020U << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */ +#define RI_HYSCR3_PF_6 (0x0040U << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */ +#define RI_HYSCR3_PF_7 (0x0080U << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */ +#define RI_HYSCR3_PF_8 (0x0100U << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */ +#define RI_HYSCR3_PF_9 (0x0200U << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */ +#define RI_HYSCR3_PF_10 (0x0400U << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */ +#define RI_HYSCR3_PF_11 (0x0800U << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */ +#define RI_HYSCR3_PF_12 (0x1000U << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */ +#define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ +#define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ +#define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ +/******************** Bit definition for RI_HYSCR4 register ********************/ +#define RI_HYSCR4_PG_Pos (0U) +#define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ +#define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */ +#define RI_HYSCR4_PG_0 (0x0001U << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */ +#define RI_HYSCR4_PG_1 (0x0002U << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */ +#define RI_HYSCR4_PG_2 (0x0004U << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */ +#define RI_HYSCR4_PG_3 (0x0008U << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */ +#define RI_HYSCR4_PG_4 (0x0010U << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */ +#define RI_HYSCR4_PG_5 (0x0020U << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */ +#define RI_HYSCR4_PG_6 (0x0040U << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */ +#define RI_HYSCR4_PG_7 (0x0080U << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */ +#define RI_HYSCR4_PG_8 (0x0100U << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */ +#define RI_HYSCR4_PG_9 (0x0200U << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */ +#define RI_HYSCR4_PG_10 (0x0400U << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */ +#define RI_HYSCR4_PG_11 (0x0800U << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */ +#define RI_HYSCR4_PG_12 (0x1000U << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */ +#define RI_HYSCR4_PG_13 (0x2000U << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */ +#define RI_HYSCR4_PG_14 (0x4000U << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */ +#define RI_HYSCR4_PG_15 (0x8000U << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */ /******************** Bit definition for RI_ASMR1 register ********************/ #define RI_ASMR1_PA_Pos (0U) @@ -6119,6 +6185,132 @@ typedef struct #define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /*!< 0x00004000 */ #define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /*!< 0x00008000 */ +/******************** Bit definition for RI_ASMR4 register ********************/ +#define RI_ASMR4_PF_Pos (0U) +#define RI_ASMR4_PF_Msk (0xFFFFU << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */ +#define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */ +#define RI_ASMR4_PF_0 (0x0001U << RI_ASMR4_PF_Pos) /*!< 0x00000001 */ +#define RI_ASMR4_PF_1 (0x0002U << RI_ASMR4_PF_Pos) /*!< 0x00000002 */ +#define RI_ASMR4_PF_2 (0x0004U << RI_ASMR4_PF_Pos) /*!< 0x00000004 */ +#define RI_ASMR4_PF_3 (0x0008U << RI_ASMR4_PF_Pos) /*!< 0x00000008 */ +#define RI_ASMR4_PF_4 (0x0010U << RI_ASMR4_PF_Pos) /*!< 0x00000010 */ +#define RI_ASMR4_PF_5 (0x0020U << RI_ASMR4_PF_Pos) /*!< 0x00000020 */ +#define RI_ASMR4_PF_6 (0x0040U << RI_ASMR4_PF_Pos) /*!< 0x00000040 */ +#define RI_ASMR4_PF_7 (0x0080U << RI_ASMR4_PF_Pos) /*!< 0x00000080 */ +#define RI_ASMR4_PF_8 (0x0100U << RI_ASMR4_PF_Pos) /*!< 0x00000100 */ +#define RI_ASMR4_PF_9 (0x0200U << RI_ASMR4_PF_Pos) /*!< 0x00000200 */ +#define RI_ASMR4_PF_10 (0x0400U << RI_ASMR4_PF_Pos) /*!< 0x00000400 */ +#define RI_ASMR4_PF_11 (0x0800U << RI_ASMR4_PF_Pos) /*!< 0x00000800 */ +#define RI_ASMR4_PF_12 (0x1000U << RI_ASMR4_PF_Pos) /*!< 0x00001000 */ +#define RI_ASMR4_PF_13 (0x2000U << RI_ASMR4_PF_Pos) /*!< 0x00002000 */ +#define RI_ASMR4_PF_14 (0x4000U << RI_ASMR4_PF_Pos) /*!< 0x00004000 */ +#define RI_ASMR4_PF_15 (0x8000U << RI_ASMR4_PF_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CMR4 register ********************/ +#define RI_CMR4_PF_Pos (0U) +#define RI_CMR4_PF_Msk (0xFFFFU << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */ +#define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */ +#define RI_CMR4_PF_0 (0x0001U << RI_CMR4_PF_Pos) /*!< 0x00000001 */ +#define RI_CMR4_PF_1 (0x0002U << RI_CMR4_PF_Pos) /*!< 0x00000002 */ +#define RI_CMR4_PF_2 (0x0004U << RI_CMR4_PF_Pos) /*!< 0x00000004 */ +#define RI_CMR4_PF_3 (0x0008U << RI_CMR4_PF_Pos) /*!< 0x00000008 */ +#define RI_CMR4_PF_4 (0x0010U << RI_CMR4_PF_Pos) /*!< 0x00000010 */ +#define RI_CMR4_PF_5 (0x0020U << RI_CMR4_PF_Pos) /*!< 0x00000020 */ +#define RI_CMR4_PF_6 (0x0040U << RI_CMR4_PF_Pos) /*!< 0x00000040 */ +#define RI_CMR4_PF_7 (0x0080U << RI_CMR4_PF_Pos) /*!< 0x00000080 */ +#define RI_CMR4_PF_8 (0x0100U << RI_CMR4_PF_Pos) /*!< 0x00000100 */ +#define RI_CMR4_PF_9 (0x0200U << RI_CMR4_PF_Pos) /*!< 0x00000200 */ +#define RI_CMR4_PF_10 (0x0400U << RI_CMR4_PF_Pos) /*!< 0x00000400 */ +#define RI_CMR4_PF_11 (0x0800U << RI_CMR4_PF_Pos) /*!< 0x00000800 */ +#define RI_CMR4_PF_12 (0x1000U << RI_CMR4_PF_Pos) /*!< 0x00001000 */ +#define RI_CMR4_PF_13 (0x2000U << RI_CMR4_PF_Pos) /*!< 0x00002000 */ +#define RI_CMR4_PF_14 (0x4000U << RI_CMR4_PF_Pos) /*!< 0x00004000 */ +#define RI_CMR4_PF_15 (0x8000U << RI_CMR4_PF_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CICR4 register ********************/ +#define RI_CICR4_PF_Pos (0U) +#define RI_CICR4_PF_Msk (0xFFFFU << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */ +#define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */ +#define RI_CICR4_PF_0 (0x0001U << RI_CICR4_PF_Pos) /*!< 0x00000001 */ +#define RI_CICR4_PF_1 (0x0002U << RI_CICR4_PF_Pos) /*!< 0x00000002 */ +#define RI_CICR4_PF_2 (0x0004U << RI_CICR4_PF_Pos) /*!< 0x00000004 */ +#define RI_CICR4_PF_3 (0x0008U << RI_CICR4_PF_Pos) /*!< 0x00000008 */ +#define RI_CICR4_PF_4 (0x0010U << RI_CICR4_PF_Pos) /*!< 0x00000010 */ +#define RI_CICR4_PF_5 (0x0020U << RI_CICR4_PF_Pos) /*!< 0x00000020 */ +#define RI_CICR4_PF_6 (0x0040U << RI_CICR4_PF_Pos) /*!< 0x00000040 */ +#define RI_CICR4_PF_7 (0x0080U << RI_CICR4_PF_Pos) /*!< 0x00000080 */ +#define RI_CICR4_PF_8 (0x0100U << RI_CICR4_PF_Pos) /*!< 0x00000100 */ +#define RI_CICR4_PF_9 (0x0200U << RI_CICR4_PF_Pos) /*!< 0x00000200 */ +#define RI_CICR4_PF_10 (0x0400U << RI_CICR4_PF_Pos) /*!< 0x00000400 */ +#define RI_CICR4_PF_11 (0x0800U << RI_CICR4_PF_Pos) /*!< 0x00000800 */ +#define RI_CICR4_PF_12 (0x1000U << RI_CICR4_PF_Pos) /*!< 0x00001000 */ +#define RI_CICR4_PF_13 (0x2000U << RI_CICR4_PF_Pos) /*!< 0x00002000 */ +#define RI_CICR4_PF_14 (0x4000U << RI_CICR4_PF_Pos) /*!< 0x00004000 */ +#define RI_CICR4_PF_15 (0x8000U << RI_CICR4_PF_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_ASMR5 register ********************/ +#define RI_ASMR5_PG_Pos (0U) +#define RI_ASMR5_PG_Msk (0xFFFFU << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */ +#define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */ +#define RI_ASMR5_PG_0 (0x0001U << RI_ASMR5_PG_Pos) /*!< 0x00000001 */ +#define RI_ASMR5_PG_1 (0x0002U << RI_ASMR5_PG_Pos) /*!< 0x00000002 */ +#define RI_ASMR5_PG_2 (0x0004U << RI_ASMR5_PG_Pos) /*!< 0x00000004 */ +#define RI_ASMR5_PG_3 (0x0008U << RI_ASMR5_PG_Pos) /*!< 0x00000008 */ +#define RI_ASMR5_PG_4 (0x0010U << RI_ASMR5_PG_Pos) /*!< 0x00000010 */ +#define RI_ASMR5_PG_5 (0x0020U << RI_ASMR5_PG_Pos) /*!< 0x00000020 */ +#define RI_ASMR5_PG_6 (0x0040U << RI_ASMR5_PG_Pos) /*!< 0x00000040 */ +#define RI_ASMR5_PG_7 (0x0080U << RI_ASMR5_PG_Pos) /*!< 0x00000080 */ +#define RI_ASMR5_PG_8 (0x0100U << RI_ASMR5_PG_Pos) /*!< 0x00000100 */ +#define RI_ASMR5_PG_9 (0x0200U << RI_ASMR5_PG_Pos) /*!< 0x00000200 */ +#define RI_ASMR5_PG_10 (0x0400U << RI_ASMR5_PG_Pos) /*!< 0x00000400 */ +#define RI_ASMR5_PG_11 (0x0800U << RI_ASMR5_PG_Pos) /*!< 0x00000800 */ +#define RI_ASMR5_PG_12 (0x1000U << RI_ASMR5_PG_Pos) /*!< 0x00001000 */ +#define RI_ASMR5_PG_13 (0x2000U << RI_ASMR5_PG_Pos) /*!< 0x00002000 */ +#define RI_ASMR5_PG_14 (0x4000U << RI_ASMR5_PG_Pos) /*!< 0x00004000 */ +#define RI_ASMR5_PG_15 (0x8000U << RI_ASMR5_PG_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CMR5 register ********************/ +#define RI_CMR5_PG_Pos (0U) +#define RI_CMR5_PG_Msk (0xFFFFU << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */ +#define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */ +#define RI_CMR5_PG_0 (0x0001U << RI_CMR5_PG_Pos) /*!< 0x00000001 */ +#define RI_CMR5_PG_1 (0x0002U << RI_CMR5_PG_Pos) /*!< 0x00000002 */ +#define RI_CMR5_PG_2 (0x0004U << RI_CMR5_PG_Pos) /*!< 0x00000004 */ +#define RI_CMR5_PG_3 (0x0008U << RI_CMR5_PG_Pos) /*!< 0x00000008 */ +#define RI_CMR5_PG_4 (0x0010U << RI_CMR5_PG_Pos) /*!< 0x00000010 */ +#define RI_CMR5_PG_5 (0x0020U << RI_CMR5_PG_Pos) /*!< 0x00000020 */ +#define RI_CMR5_PG_6 (0x0040U << RI_CMR5_PG_Pos) /*!< 0x00000040 */ +#define RI_CMR5_PG_7 (0x0080U << RI_CMR5_PG_Pos) /*!< 0x00000080 */ +#define RI_CMR5_PG_8 (0x0100U << RI_CMR5_PG_Pos) /*!< 0x00000100 */ +#define RI_CMR5_PG_9 (0x0200U << RI_CMR5_PG_Pos) /*!< 0x00000200 */ +#define RI_CMR5_PG_10 (0x0400U << RI_CMR5_PG_Pos) /*!< 0x00000400 */ +#define RI_CMR5_PG_11 (0x0800U << RI_CMR5_PG_Pos) /*!< 0x00000800 */ +#define RI_CMR5_PG_12 (0x1000U << RI_CMR5_PG_Pos) /*!< 0x00001000 */ +#define RI_CMR5_PG_13 (0x2000U << RI_CMR5_PG_Pos) /*!< 0x00002000 */ +#define RI_CMR5_PG_14 (0x4000U << RI_CMR5_PG_Pos) /*!< 0x00004000 */ +#define RI_CMR5_PG_15 (0x8000U << RI_CMR5_PG_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CICR5 register ********************/ +#define RI_CICR5_PG_Pos (0U) +#define RI_CICR5_PG_Msk (0xFFFFU << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */ +#define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */ +#define RI_CICR5_PG_0 (0x0001U << RI_CICR5_PG_Pos) /*!< 0x00000001 */ +#define RI_CICR5_PG_1 (0x0002U << RI_CICR5_PG_Pos) /*!< 0x00000002 */ +#define RI_CICR5_PG_2 (0x0004U << RI_CICR5_PG_Pos) /*!< 0x00000004 */ +#define RI_CICR5_PG_3 (0x0008U << RI_CICR5_PG_Pos) /*!< 0x00000008 */ +#define RI_CICR5_PG_4 (0x0010U << RI_CICR5_PG_Pos) /*!< 0x00000010 */ +#define RI_CICR5_PG_5 (0x0020U << RI_CICR5_PG_Pos) /*!< 0x00000020 */ +#define RI_CICR5_PG_6 (0x0040U << RI_CICR5_PG_Pos) /*!< 0x00000040 */ +#define RI_CICR5_PG_7 (0x0080U << RI_CICR5_PG_Pos) /*!< 0x00000080 */ +#define RI_CICR5_PG_8 (0x0100U << RI_CICR5_PG_Pos) /*!< 0x00000100 */ +#define RI_CICR5_PG_9 (0x0200U << RI_CICR5_PG_Pos) /*!< 0x00000200 */ +#define RI_CICR5_PG_10 (0x0400U << RI_CICR5_PG_Pos) /*!< 0x00000400 */ +#define RI_CICR5_PG_11 (0x0800U << RI_CICR5_PG_Pos) /*!< 0x00000800 */ +#define RI_CICR5_PG_12 (0x1000U << RI_CICR5_PG_Pos) /*!< 0x00001000 */ +#define RI_CICR5_PG_13 (0x2000U << RI_CICR5_PG_Pos) /*!< 0x00002000 */ +#define RI_CICR5_PG_14 (0x4000U << RI_CICR5_PG_Pos) /*!< 0x00004000 */ +#define RI_CICR5_PG_15 (0x8000U << RI_CICR5_PG_Pos) /*!< 0x00008000 */ + /******************************************************************************/ /* */ /* Timers (TIM) */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xb.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xb.h index f6666cdcd6..9d7d64ab16 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xb.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xb.h @@ -408,11 +408,12 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */ } RI_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xba.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xba.h index 0ae22b40f1..1c49a3d53c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xba.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xba.h @@ -408,11 +408,12 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */ } RI_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xc.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xc.h index 42a182b90c..0bd035c771 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xc.h @@ -437,21 +437,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -6117,6 +6123,45 @@ typedef struct #define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */ #define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */ #define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */ +#define RI_HYSCR3_PF_Pos (16U) +#define RI_HYSCR3_PF_Msk (0xFFFFU << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */ +#define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */ +#define RI_HYSCR3_PF_0 (0x0001U << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */ +#define RI_HYSCR3_PF_1 (0x0002U << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */ +#define RI_HYSCR3_PF_2 (0x0004U << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */ +#define RI_HYSCR3_PF_3 (0x0008U << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */ +#define RI_HYSCR3_PF_4 (0x0010U << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */ +#define RI_HYSCR3_PF_5 (0x0020U << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */ +#define RI_HYSCR3_PF_6 (0x0040U << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */ +#define RI_HYSCR3_PF_7 (0x0080U << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */ +#define RI_HYSCR3_PF_8 (0x0100U << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */ +#define RI_HYSCR3_PF_9 (0x0200U << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */ +#define RI_HYSCR3_PF_10 (0x0400U << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */ +#define RI_HYSCR3_PF_11 (0x0800U << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */ +#define RI_HYSCR3_PF_12 (0x1000U << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */ +#define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ +#define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ +#define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ +/******************** Bit definition for RI_HYSCR4 register ********************/ +#define RI_HYSCR4_PG_Pos (0U) +#define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ +#define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */ +#define RI_HYSCR4_PG_0 (0x0001U << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */ +#define RI_HYSCR4_PG_1 (0x0002U << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */ +#define RI_HYSCR4_PG_2 (0x0004U << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */ +#define RI_HYSCR4_PG_3 (0x0008U << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */ +#define RI_HYSCR4_PG_4 (0x0010U << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */ +#define RI_HYSCR4_PG_5 (0x0020U << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */ +#define RI_HYSCR4_PG_6 (0x0040U << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */ +#define RI_HYSCR4_PG_7 (0x0080U << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */ +#define RI_HYSCR4_PG_8 (0x0100U << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */ +#define RI_HYSCR4_PG_9 (0x0200U << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */ +#define RI_HYSCR4_PG_10 (0x0400U << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */ +#define RI_HYSCR4_PG_11 (0x0800U << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */ +#define RI_HYSCR4_PG_12 (0x1000U << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */ +#define RI_HYSCR4_PG_13 (0x2000U << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */ +#define RI_HYSCR4_PG_14 (0x4000U << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */ +#define RI_HYSCR4_PG_15 (0x8000U << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */ /******************** Bit definition for RI_ASMR1 register ********************/ #define RI_ASMR1_PA_Pos (0U) @@ -6307,6 +6352,132 @@ typedef struct #define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /*!< 0x00004000 */ #define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /*!< 0x00008000 */ +/******************** Bit definition for RI_ASMR4 register ********************/ +#define RI_ASMR4_PF_Pos (0U) +#define RI_ASMR4_PF_Msk (0xFFFFU << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */ +#define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */ +#define RI_ASMR4_PF_0 (0x0001U << RI_ASMR4_PF_Pos) /*!< 0x00000001 */ +#define RI_ASMR4_PF_1 (0x0002U << RI_ASMR4_PF_Pos) /*!< 0x00000002 */ +#define RI_ASMR4_PF_2 (0x0004U << RI_ASMR4_PF_Pos) /*!< 0x00000004 */ +#define RI_ASMR4_PF_3 (0x0008U << RI_ASMR4_PF_Pos) /*!< 0x00000008 */ +#define RI_ASMR4_PF_4 (0x0010U << RI_ASMR4_PF_Pos) /*!< 0x00000010 */ +#define RI_ASMR4_PF_5 (0x0020U << RI_ASMR4_PF_Pos) /*!< 0x00000020 */ +#define RI_ASMR4_PF_6 (0x0040U << RI_ASMR4_PF_Pos) /*!< 0x00000040 */ +#define RI_ASMR4_PF_7 (0x0080U << RI_ASMR4_PF_Pos) /*!< 0x00000080 */ +#define RI_ASMR4_PF_8 (0x0100U << RI_ASMR4_PF_Pos) /*!< 0x00000100 */ +#define RI_ASMR4_PF_9 (0x0200U << RI_ASMR4_PF_Pos) /*!< 0x00000200 */ +#define RI_ASMR4_PF_10 (0x0400U << RI_ASMR4_PF_Pos) /*!< 0x00000400 */ +#define RI_ASMR4_PF_11 (0x0800U << RI_ASMR4_PF_Pos) /*!< 0x00000800 */ +#define RI_ASMR4_PF_12 (0x1000U << RI_ASMR4_PF_Pos) /*!< 0x00001000 */ +#define RI_ASMR4_PF_13 (0x2000U << RI_ASMR4_PF_Pos) /*!< 0x00002000 */ +#define RI_ASMR4_PF_14 (0x4000U << RI_ASMR4_PF_Pos) /*!< 0x00004000 */ +#define RI_ASMR4_PF_15 (0x8000U << RI_ASMR4_PF_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CMR4 register ********************/ +#define RI_CMR4_PF_Pos (0U) +#define RI_CMR4_PF_Msk (0xFFFFU << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */ +#define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */ +#define RI_CMR4_PF_0 (0x0001U << RI_CMR4_PF_Pos) /*!< 0x00000001 */ +#define RI_CMR4_PF_1 (0x0002U << RI_CMR4_PF_Pos) /*!< 0x00000002 */ +#define RI_CMR4_PF_2 (0x0004U << RI_CMR4_PF_Pos) /*!< 0x00000004 */ +#define RI_CMR4_PF_3 (0x0008U << RI_CMR4_PF_Pos) /*!< 0x00000008 */ +#define RI_CMR4_PF_4 (0x0010U << RI_CMR4_PF_Pos) /*!< 0x00000010 */ +#define RI_CMR4_PF_5 (0x0020U << RI_CMR4_PF_Pos) /*!< 0x00000020 */ +#define RI_CMR4_PF_6 (0x0040U << RI_CMR4_PF_Pos) /*!< 0x00000040 */ +#define RI_CMR4_PF_7 (0x0080U << RI_CMR4_PF_Pos) /*!< 0x00000080 */ +#define RI_CMR4_PF_8 (0x0100U << RI_CMR4_PF_Pos) /*!< 0x00000100 */ +#define RI_CMR4_PF_9 (0x0200U << RI_CMR4_PF_Pos) /*!< 0x00000200 */ +#define RI_CMR4_PF_10 (0x0400U << RI_CMR4_PF_Pos) /*!< 0x00000400 */ +#define RI_CMR4_PF_11 (0x0800U << RI_CMR4_PF_Pos) /*!< 0x00000800 */ +#define RI_CMR4_PF_12 (0x1000U << RI_CMR4_PF_Pos) /*!< 0x00001000 */ +#define RI_CMR4_PF_13 (0x2000U << RI_CMR4_PF_Pos) /*!< 0x00002000 */ +#define RI_CMR4_PF_14 (0x4000U << RI_CMR4_PF_Pos) /*!< 0x00004000 */ +#define RI_CMR4_PF_15 (0x8000U << RI_CMR4_PF_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CICR4 register ********************/ +#define RI_CICR4_PF_Pos (0U) +#define RI_CICR4_PF_Msk (0xFFFFU << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */ +#define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */ +#define RI_CICR4_PF_0 (0x0001U << RI_CICR4_PF_Pos) /*!< 0x00000001 */ +#define RI_CICR4_PF_1 (0x0002U << RI_CICR4_PF_Pos) /*!< 0x00000002 */ +#define RI_CICR4_PF_2 (0x0004U << RI_CICR4_PF_Pos) /*!< 0x00000004 */ +#define RI_CICR4_PF_3 (0x0008U << RI_CICR4_PF_Pos) /*!< 0x00000008 */ +#define RI_CICR4_PF_4 (0x0010U << RI_CICR4_PF_Pos) /*!< 0x00000010 */ +#define RI_CICR4_PF_5 (0x0020U << RI_CICR4_PF_Pos) /*!< 0x00000020 */ +#define RI_CICR4_PF_6 (0x0040U << RI_CICR4_PF_Pos) /*!< 0x00000040 */ +#define RI_CICR4_PF_7 (0x0080U << RI_CICR4_PF_Pos) /*!< 0x00000080 */ +#define RI_CICR4_PF_8 (0x0100U << RI_CICR4_PF_Pos) /*!< 0x00000100 */ +#define RI_CICR4_PF_9 (0x0200U << RI_CICR4_PF_Pos) /*!< 0x00000200 */ +#define RI_CICR4_PF_10 (0x0400U << RI_CICR4_PF_Pos) /*!< 0x00000400 */ +#define RI_CICR4_PF_11 (0x0800U << RI_CICR4_PF_Pos) /*!< 0x00000800 */ +#define RI_CICR4_PF_12 (0x1000U << RI_CICR4_PF_Pos) /*!< 0x00001000 */ +#define RI_CICR4_PF_13 (0x2000U << RI_CICR4_PF_Pos) /*!< 0x00002000 */ +#define RI_CICR4_PF_14 (0x4000U << RI_CICR4_PF_Pos) /*!< 0x00004000 */ +#define RI_CICR4_PF_15 (0x8000U << RI_CICR4_PF_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_ASMR5 register ********************/ +#define RI_ASMR5_PG_Pos (0U) +#define RI_ASMR5_PG_Msk (0xFFFFU << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */ +#define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */ +#define RI_ASMR5_PG_0 (0x0001U << RI_ASMR5_PG_Pos) /*!< 0x00000001 */ +#define RI_ASMR5_PG_1 (0x0002U << RI_ASMR5_PG_Pos) /*!< 0x00000002 */ +#define RI_ASMR5_PG_2 (0x0004U << RI_ASMR5_PG_Pos) /*!< 0x00000004 */ +#define RI_ASMR5_PG_3 (0x0008U << RI_ASMR5_PG_Pos) /*!< 0x00000008 */ +#define RI_ASMR5_PG_4 (0x0010U << RI_ASMR5_PG_Pos) /*!< 0x00000010 */ +#define RI_ASMR5_PG_5 (0x0020U << RI_ASMR5_PG_Pos) /*!< 0x00000020 */ +#define RI_ASMR5_PG_6 (0x0040U << RI_ASMR5_PG_Pos) /*!< 0x00000040 */ +#define RI_ASMR5_PG_7 (0x0080U << RI_ASMR5_PG_Pos) /*!< 0x00000080 */ +#define RI_ASMR5_PG_8 (0x0100U << RI_ASMR5_PG_Pos) /*!< 0x00000100 */ +#define RI_ASMR5_PG_9 (0x0200U << RI_ASMR5_PG_Pos) /*!< 0x00000200 */ +#define RI_ASMR5_PG_10 (0x0400U << RI_ASMR5_PG_Pos) /*!< 0x00000400 */ +#define RI_ASMR5_PG_11 (0x0800U << RI_ASMR5_PG_Pos) /*!< 0x00000800 */ +#define RI_ASMR5_PG_12 (0x1000U << RI_ASMR5_PG_Pos) /*!< 0x00001000 */ +#define RI_ASMR5_PG_13 (0x2000U << RI_ASMR5_PG_Pos) /*!< 0x00002000 */ +#define RI_ASMR5_PG_14 (0x4000U << RI_ASMR5_PG_Pos) /*!< 0x00004000 */ +#define RI_ASMR5_PG_15 (0x8000U << RI_ASMR5_PG_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CMR5 register ********************/ +#define RI_CMR5_PG_Pos (0U) +#define RI_CMR5_PG_Msk (0xFFFFU << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */ +#define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */ +#define RI_CMR5_PG_0 (0x0001U << RI_CMR5_PG_Pos) /*!< 0x00000001 */ +#define RI_CMR5_PG_1 (0x0002U << RI_CMR5_PG_Pos) /*!< 0x00000002 */ +#define RI_CMR5_PG_2 (0x0004U << RI_CMR5_PG_Pos) /*!< 0x00000004 */ +#define RI_CMR5_PG_3 (0x0008U << RI_CMR5_PG_Pos) /*!< 0x00000008 */ +#define RI_CMR5_PG_4 (0x0010U << RI_CMR5_PG_Pos) /*!< 0x00000010 */ +#define RI_CMR5_PG_5 (0x0020U << RI_CMR5_PG_Pos) /*!< 0x00000020 */ +#define RI_CMR5_PG_6 (0x0040U << RI_CMR5_PG_Pos) /*!< 0x00000040 */ +#define RI_CMR5_PG_7 (0x0080U << RI_CMR5_PG_Pos) /*!< 0x00000080 */ +#define RI_CMR5_PG_8 (0x0100U << RI_CMR5_PG_Pos) /*!< 0x00000100 */ +#define RI_CMR5_PG_9 (0x0200U << RI_CMR5_PG_Pos) /*!< 0x00000200 */ +#define RI_CMR5_PG_10 (0x0400U << RI_CMR5_PG_Pos) /*!< 0x00000400 */ +#define RI_CMR5_PG_11 (0x0800U << RI_CMR5_PG_Pos) /*!< 0x00000800 */ +#define RI_CMR5_PG_12 (0x1000U << RI_CMR5_PG_Pos) /*!< 0x00001000 */ +#define RI_CMR5_PG_13 (0x2000U << RI_CMR5_PG_Pos) /*!< 0x00002000 */ +#define RI_CMR5_PG_14 (0x4000U << RI_CMR5_PG_Pos) /*!< 0x00004000 */ +#define RI_CMR5_PG_15 (0x8000U << RI_CMR5_PG_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CICR5 register ********************/ +#define RI_CICR5_PG_Pos (0U) +#define RI_CICR5_PG_Msk (0xFFFFU << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */ +#define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */ +#define RI_CICR5_PG_0 (0x0001U << RI_CICR5_PG_Pos) /*!< 0x00000001 */ +#define RI_CICR5_PG_1 (0x0002U << RI_CICR5_PG_Pos) /*!< 0x00000002 */ +#define RI_CICR5_PG_2 (0x0004U << RI_CICR5_PG_Pos) /*!< 0x00000004 */ +#define RI_CICR5_PG_3 (0x0008U << RI_CICR5_PG_Pos) /*!< 0x00000008 */ +#define RI_CICR5_PG_4 (0x0010U << RI_CICR5_PG_Pos) /*!< 0x00000010 */ +#define RI_CICR5_PG_5 (0x0020U << RI_CICR5_PG_Pos) /*!< 0x00000020 */ +#define RI_CICR5_PG_6 (0x0040U << RI_CICR5_PG_Pos) /*!< 0x00000040 */ +#define RI_CICR5_PG_7 (0x0080U << RI_CICR5_PG_Pos) /*!< 0x00000080 */ +#define RI_CICR5_PG_8 (0x0100U << RI_CICR5_PG_Pos) /*!< 0x00000100 */ +#define RI_CICR5_PG_9 (0x0200U << RI_CICR5_PG_Pos) /*!< 0x00000200 */ +#define RI_CICR5_PG_10 (0x0400U << RI_CICR5_PG_Pos) /*!< 0x00000400 */ +#define RI_CICR5_PG_11 (0x0800U << RI_CICR5_PG_Pos) /*!< 0x00000800 */ +#define RI_CICR5_PG_12 (0x1000U << RI_CICR5_PG_Pos) /*!< 0x00001000 */ +#define RI_CICR5_PG_13 (0x2000U << RI_CICR5_PG_Pos) /*!< 0x00002000 */ +#define RI_CICR5_PG_14 (0x4000U << RI_CICR5_PG_Pos) /*!< 0x00004000 */ +#define RI_CICR5_PG_15 (0x8000U << RI_CICR5_PG_Pos) /*!< 0x00008000 */ + /******************************************************************************/ /* */ /* Timers (TIM) */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xca.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xca.h index 07108561fc..aa0c3e4781 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xca.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xca.h @@ -437,27 +437,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -6227,7 +6227,6 @@ typedef struct #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ - /******************** Bit definition for RI_HYSCR4 register ********************/ #define RI_HYSCR4_PG_Pos (0U) #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xd.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xd.h index cbfb5e03e7..894249aa2a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xd.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xd.h @@ -461,27 +461,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -6901,7 +6901,6 @@ typedef struct #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ - /******************** Bit definition for RI_HYSCR4 register ********************/ #define RI_HYSCR4_PG_Pos (0U) #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xdx.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xdx.h index a915d3ca8e..a2021e5b7f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xdx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xdx.h @@ -446,27 +446,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -6272,7 +6272,6 @@ typedef struct #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ - /******************** Bit definition for RI_HYSCR4 register ********************/ #define RI_HYSCR4_PG_Pos (0U) #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xe.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xe.h index d819545662..eb205089e2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xe.h @@ -446,27 +446,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -6272,7 +6272,6 @@ typedef struct #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ - /******************** Bit definition for RI_HYSCR4 register ********************/ #define RI_HYSCR4_PG_Pos (0U) #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xb.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xb.h index da45b13de6..c1eb217cc1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xb.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xb.h @@ -423,11 +423,12 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */ } RI_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xba.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xba.h index c0107789d9..5c9374188f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xba.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xba.h @@ -423,11 +423,12 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */ } RI_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xc.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xc.h index f7ff0b5df2..4fadb8155b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xc.h @@ -452,21 +452,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -6267,6 +6273,45 @@ typedef struct #define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */ #define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */ #define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */ +#define RI_HYSCR3_PF_Pos (16U) +#define RI_HYSCR3_PF_Msk (0xFFFFU << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */ +#define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */ +#define RI_HYSCR3_PF_0 (0x0001U << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */ +#define RI_HYSCR3_PF_1 (0x0002U << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */ +#define RI_HYSCR3_PF_2 (0x0004U << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */ +#define RI_HYSCR3_PF_3 (0x0008U << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */ +#define RI_HYSCR3_PF_4 (0x0010U << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */ +#define RI_HYSCR3_PF_5 (0x0020U << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */ +#define RI_HYSCR3_PF_6 (0x0040U << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */ +#define RI_HYSCR3_PF_7 (0x0080U << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */ +#define RI_HYSCR3_PF_8 (0x0100U << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */ +#define RI_HYSCR3_PF_9 (0x0200U << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */ +#define RI_HYSCR3_PF_10 (0x0400U << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */ +#define RI_HYSCR3_PF_11 (0x0800U << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */ +#define RI_HYSCR3_PF_12 (0x1000U << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */ +#define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ +#define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ +#define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ +/******************** Bit definition for RI_HYSCR4 register ********************/ +#define RI_HYSCR4_PG_Pos (0U) +#define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ +#define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */ +#define RI_HYSCR4_PG_0 (0x0001U << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */ +#define RI_HYSCR4_PG_1 (0x0002U << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */ +#define RI_HYSCR4_PG_2 (0x0004U << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */ +#define RI_HYSCR4_PG_3 (0x0008U << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */ +#define RI_HYSCR4_PG_4 (0x0010U << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */ +#define RI_HYSCR4_PG_5 (0x0020U << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */ +#define RI_HYSCR4_PG_6 (0x0040U << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */ +#define RI_HYSCR4_PG_7 (0x0080U << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */ +#define RI_HYSCR4_PG_8 (0x0100U << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */ +#define RI_HYSCR4_PG_9 (0x0200U << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */ +#define RI_HYSCR4_PG_10 (0x0400U << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */ +#define RI_HYSCR4_PG_11 (0x0800U << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */ +#define RI_HYSCR4_PG_12 (0x1000U << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */ +#define RI_HYSCR4_PG_13 (0x2000U << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */ +#define RI_HYSCR4_PG_14 (0x4000U << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */ +#define RI_HYSCR4_PG_15 (0x8000U << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */ /******************** Bit definition for RI_ASMR1 register ********************/ #define RI_ASMR1_PA_Pos (0U) @@ -6457,6 +6502,132 @@ typedef struct #define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /*!< 0x00004000 */ #define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /*!< 0x00008000 */ +/******************** Bit definition for RI_ASMR4 register ********************/ +#define RI_ASMR4_PF_Pos (0U) +#define RI_ASMR4_PF_Msk (0xFFFFU << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */ +#define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */ +#define RI_ASMR4_PF_0 (0x0001U << RI_ASMR4_PF_Pos) /*!< 0x00000001 */ +#define RI_ASMR4_PF_1 (0x0002U << RI_ASMR4_PF_Pos) /*!< 0x00000002 */ +#define RI_ASMR4_PF_2 (0x0004U << RI_ASMR4_PF_Pos) /*!< 0x00000004 */ +#define RI_ASMR4_PF_3 (0x0008U << RI_ASMR4_PF_Pos) /*!< 0x00000008 */ +#define RI_ASMR4_PF_4 (0x0010U << RI_ASMR4_PF_Pos) /*!< 0x00000010 */ +#define RI_ASMR4_PF_5 (0x0020U << RI_ASMR4_PF_Pos) /*!< 0x00000020 */ +#define RI_ASMR4_PF_6 (0x0040U << RI_ASMR4_PF_Pos) /*!< 0x00000040 */ +#define RI_ASMR4_PF_7 (0x0080U << RI_ASMR4_PF_Pos) /*!< 0x00000080 */ +#define RI_ASMR4_PF_8 (0x0100U << RI_ASMR4_PF_Pos) /*!< 0x00000100 */ +#define RI_ASMR4_PF_9 (0x0200U << RI_ASMR4_PF_Pos) /*!< 0x00000200 */ +#define RI_ASMR4_PF_10 (0x0400U << RI_ASMR4_PF_Pos) /*!< 0x00000400 */ +#define RI_ASMR4_PF_11 (0x0800U << RI_ASMR4_PF_Pos) /*!< 0x00000800 */ +#define RI_ASMR4_PF_12 (0x1000U << RI_ASMR4_PF_Pos) /*!< 0x00001000 */ +#define RI_ASMR4_PF_13 (0x2000U << RI_ASMR4_PF_Pos) /*!< 0x00002000 */ +#define RI_ASMR4_PF_14 (0x4000U << RI_ASMR4_PF_Pos) /*!< 0x00004000 */ +#define RI_ASMR4_PF_15 (0x8000U << RI_ASMR4_PF_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CMR4 register ********************/ +#define RI_CMR4_PF_Pos (0U) +#define RI_CMR4_PF_Msk (0xFFFFU << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */ +#define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */ +#define RI_CMR4_PF_0 (0x0001U << RI_CMR4_PF_Pos) /*!< 0x00000001 */ +#define RI_CMR4_PF_1 (0x0002U << RI_CMR4_PF_Pos) /*!< 0x00000002 */ +#define RI_CMR4_PF_2 (0x0004U << RI_CMR4_PF_Pos) /*!< 0x00000004 */ +#define RI_CMR4_PF_3 (0x0008U << RI_CMR4_PF_Pos) /*!< 0x00000008 */ +#define RI_CMR4_PF_4 (0x0010U << RI_CMR4_PF_Pos) /*!< 0x00000010 */ +#define RI_CMR4_PF_5 (0x0020U << RI_CMR4_PF_Pos) /*!< 0x00000020 */ +#define RI_CMR4_PF_6 (0x0040U << RI_CMR4_PF_Pos) /*!< 0x00000040 */ +#define RI_CMR4_PF_7 (0x0080U << RI_CMR4_PF_Pos) /*!< 0x00000080 */ +#define RI_CMR4_PF_8 (0x0100U << RI_CMR4_PF_Pos) /*!< 0x00000100 */ +#define RI_CMR4_PF_9 (0x0200U << RI_CMR4_PF_Pos) /*!< 0x00000200 */ +#define RI_CMR4_PF_10 (0x0400U << RI_CMR4_PF_Pos) /*!< 0x00000400 */ +#define RI_CMR4_PF_11 (0x0800U << RI_CMR4_PF_Pos) /*!< 0x00000800 */ +#define RI_CMR4_PF_12 (0x1000U << RI_CMR4_PF_Pos) /*!< 0x00001000 */ +#define RI_CMR4_PF_13 (0x2000U << RI_CMR4_PF_Pos) /*!< 0x00002000 */ +#define RI_CMR4_PF_14 (0x4000U << RI_CMR4_PF_Pos) /*!< 0x00004000 */ +#define RI_CMR4_PF_15 (0x8000U << RI_CMR4_PF_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CICR4 register ********************/ +#define RI_CICR4_PF_Pos (0U) +#define RI_CICR4_PF_Msk (0xFFFFU << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */ +#define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */ +#define RI_CICR4_PF_0 (0x0001U << RI_CICR4_PF_Pos) /*!< 0x00000001 */ +#define RI_CICR4_PF_1 (0x0002U << RI_CICR4_PF_Pos) /*!< 0x00000002 */ +#define RI_CICR4_PF_2 (0x0004U << RI_CICR4_PF_Pos) /*!< 0x00000004 */ +#define RI_CICR4_PF_3 (0x0008U << RI_CICR4_PF_Pos) /*!< 0x00000008 */ +#define RI_CICR4_PF_4 (0x0010U << RI_CICR4_PF_Pos) /*!< 0x00000010 */ +#define RI_CICR4_PF_5 (0x0020U << RI_CICR4_PF_Pos) /*!< 0x00000020 */ +#define RI_CICR4_PF_6 (0x0040U << RI_CICR4_PF_Pos) /*!< 0x00000040 */ +#define RI_CICR4_PF_7 (0x0080U << RI_CICR4_PF_Pos) /*!< 0x00000080 */ +#define RI_CICR4_PF_8 (0x0100U << RI_CICR4_PF_Pos) /*!< 0x00000100 */ +#define RI_CICR4_PF_9 (0x0200U << RI_CICR4_PF_Pos) /*!< 0x00000200 */ +#define RI_CICR4_PF_10 (0x0400U << RI_CICR4_PF_Pos) /*!< 0x00000400 */ +#define RI_CICR4_PF_11 (0x0800U << RI_CICR4_PF_Pos) /*!< 0x00000800 */ +#define RI_CICR4_PF_12 (0x1000U << RI_CICR4_PF_Pos) /*!< 0x00001000 */ +#define RI_CICR4_PF_13 (0x2000U << RI_CICR4_PF_Pos) /*!< 0x00002000 */ +#define RI_CICR4_PF_14 (0x4000U << RI_CICR4_PF_Pos) /*!< 0x00004000 */ +#define RI_CICR4_PF_15 (0x8000U << RI_CICR4_PF_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_ASMR5 register ********************/ +#define RI_ASMR5_PG_Pos (0U) +#define RI_ASMR5_PG_Msk (0xFFFFU << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */ +#define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */ +#define RI_ASMR5_PG_0 (0x0001U << RI_ASMR5_PG_Pos) /*!< 0x00000001 */ +#define RI_ASMR5_PG_1 (0x0002U << RI_ASMR5_PG_Pos) /*!< 0x00000002 */ +#define RI_ASMR5_PG_2 (0x0004U << RI_ASMR5_PG_Pos) /*!< 0x00000004 */ +#define RI_ASMR5_PG_3 (0x0008U << RI_ASMR5_PG_Pos) /*!< 0x00000008 */ +#define RI_ASMR5_PG_4 (0x0010U << RI_ASMR5_PG_Pos) /*!< 0x00000010 */ +#define RI_ASMR5_PG_5 (0x0020U << RI_ASMR5_PG_Pos) /*!< 0x00000020 */ +#define RI_ASMR5_PG_6 (0x0040U << RI_ASMR5_PG_Pos) /*!< 0x00000040 */ +#define RI_ASMR5_PG_7 (0x0080U << RI_ASMR5_PG_Pos) /*!< 0x00000080 */ +#define RI_ASMR5_PG_8 (0x0100U << RI_ASMR5_PG_Pos) /*!< 0x00000100 */ +#define RI_ASMR5_PG_9 (0x0200U << RI_ASMR5_PG_Pos) /*!< 0x00000200 */ +#define RI_ASMR5_PG_10 (0x0400U << RI_ASMR5_PG_Pos) /*!< 0x00000400 */ +#define RI_ASMR5_PG_11 (0x0800U << RI_ASMR5_PG_Pos) /*!< 0x00000800 */ +#define RI_ASMR5_PG_12 (0x1000U << RI_ASMR5_PG_Pos) /*!< 0x00001000 */ +#define RI_ASMR5_PG_13 (0x2000U << RI_ASMR5_PG_Pos) /*!< 0x00002000 */ +#define RI_ASMR5_PG_14 (0x4000U << RI_ASMR5_PG_Pos) /*!< 0x00004000 */ +#define RI_ASMR5_PG_15 (0x8000U << RI_ASMR5_PG_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CMR5 register ********************/ +#define RI_CMR5_PG_Pos (0U) +#define RI_CMR5_PG_Msk (0xFFFFU << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */ +#define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */ +#define RI_CMR5_PG_0 (0x0001U << RI_CMR5_PG_Pos) /*!< 0x00000001 */ +#define RI_CMR5_PG_1 (0x0002U << RI_CMR5_PG_Pos) /*!< 0x00000002 */ +#define RI_CMR5_PG_2 (0x0004U << RI_CMR5_PG_Pos) /*!< 0x00000004 */ +#define RI_CMR5_PG_3 (0x0008U << RI_CMR5_PG_Pos) /*!< 0x00000008 */ +#define RI_CMR5_PG_4 (0x0010U << RI_CMR5_PG_Pos) /*!< 0x00000010 */ +#define RI_CMR5_PG_5 (0x0020U << RI_CMR5_PG_Pos) /*!< 0x00000020 */ +#define RI_CMR5_PG_6 (0x0040U << RI_CMR5_PG_Pos) /*!< 0x00000040 */ +#define RI_CMR5_PG_7 (0x0080U << RI_CMR5_PG_Pos) /*!< 0x00000080 */ +#define RI_CMR5_PG_8 (0x0100U << RI_CMR5_PG_Pos) /*!< 0x00000100 */ +#define RI_CMR5_PG_9 (0x0200U << RI_CMR5_PG_Pos) /*!< 0x00000200 */ +#define RI_CMR5_PG_10 (0x0400U << RI_CMR5_PG_Pos) /*!< 0x00000400 */ +#define RI_CMR5_PG_11 (0x0800U << RI_CMR5_PG_Pos) /*!< 0x00000800 */ +#define RI_CMR5_PG_12 (0x1000U << RI_CMR5_PG_Pos) /*!< 0x00001000 */ +#define RI_CMR5_PG_13 (0x2000U << RI_CMR5_PG_Pos) /*!< 0x00002000 */ +#define RI_CMR5_PG_14 (0x4000U << RI_CMR5_PG_Pos) /*!< 0x00004000 */ +#define RI_CMR5_PG_15 (0x8000U << RI_CMR5_PG_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CICR5 register ********************/ +#define RI_CICR5_PG_Pos (0U) +#define RI_CICR5_PG_Msk (0xFFFFU << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */ +#define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */ +#define RI_CICR5_PG_0 (0x0001U << RI_CICR5_PG_Pos) /*!< 0x00000001 */ +#define RI_CICR5_PG_1 (0x0002U << RI_CICR5_PG_Pos) /*!< 0x00000002 */ +#define RI_CICR5_PG_2 (0x0004U << RI_CICR5_PG_Pos) /*!< 0x00000004 */ +#define RI_CICR5_PG_3 (0x0008U << RI_CICR5_PG_Pos) /*!< 0x00000008 */ +#define RI_CICR5_PG_4 (0x0010U << RI_CICR5_PG_Pos) /*!< 0x00000010 */ +#define RI_CICR5_PG_5 (0x0020U << RI_CICR5_PG_Pos) /*!< 0x00000020 */ +#define RI_CICR5_PG_6 (0x0040U << RI_CICR5_PG_Pos) /*!< 0x00000040 */ +#define RI_CICR5_PG_7 (0x0080U << RI_CICR5_PG_Pos) /*!< 0x00000080 */ +#define RI_CICR5_PG_8 (0x0100U << RI_CICR5_PG_Pos) /*!< 0x00000100 */ +#define RI_CICR5_PG_9 (0x0200U << RI_CICR5_PG_Pos) /*!< 0x00000200 */ +#define RI_CICR5_PG_10 (0x0400U << RI_CICR5_PG_Pos) /*!< 0x00000400 */ +#define RI_CICR5_PG_11 (0x0800U << RI_CICR5_PG_Pos) /*!< 0x00000800 */ +#define RI_CICR5_PG_12 (0x1000U << RI_CICR5_PG_Pos) /*!< 0x00001000 */ +#define RI_CICR5_PG_13 (0x2000U << RI_CICR5_PG_Pos) /*!< 0x00002000 */ +#define RI_CICR5_PG_14 (0x4000U << RI_CICR5_PG_Pos) /*!< 0x00004000 */ +#define RI_CICR5_PG_15 (0x8000U << RI_CICR5_PG_Pos) /*!< 0x00008000 */ + /******************************************************************************/ /* */ /* Timers (TIM) */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xca.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xca.h index 863e1f9c37..25650c2e88 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xca.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xca.h @@ -452,27 +452,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -6377,7 +6377,6 @@ typedef struct #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ - /******************** Bit definition for RI_HYSCR4 register ********************/ #define RI_HYSCR4_PG_Pos (0U) #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xd.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xd.h index 7e33c30f76..a7bed9db14 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xd.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xd.h @@ -476,27 +476,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -7051,7 +7051,6 @@ typedef struct #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ - /******************** Bit definition for RI_HYSCR4 register ********************/ #define RI_HYSCR4_PG_Pos (0U) #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xdx.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xdx.h index 48357f0f7d..db3a55ca13 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xdx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xdx.h @@ -461,27 +461,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -6422,7 +6422,6 @@ typedef struct #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ - /******************** Bit definition for RI_HYSCR4 register ********************/ #define RI_HYSCR4_PG_Pos (0U) #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h index c7375a3dda..269861d0f1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h @@ -461,27 +461,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -6422,7 +6422,6 @@ typedef struct #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ - /******************** Bit definition for RI_HYSCR4 register ********************/ #define RI_HYSCR4_PG_Pos (0U) #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xc.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xc.h index 867ddd7249..4d7c924008 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xc.h @@ -473,21 +473,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -6406,6 +6412,45 @@ typedef struct #define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */ #define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */ #define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */ +#define RI_HYSCR3_PF_Pos (16U) +#define RI_HYSCR3_PF_Msk (0xFFFFU << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */ +#define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */ +#define RI_HYSCR3_PF_0 (0x0001U << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */ +#define RI_HYSCR3_PF_1 (0x0002U << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */ +#define RI_HYSCR3_PF_2 (0x0004U << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */ +#define RI_HYSCR3_PF_3 (0x0008U << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */ +#define RI_HYSCR3_PF_4 (0x0010U << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */ +#define RI_HYSCR3_PF_5 (0x0020U << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */ +#define RI_HYSCR3_PF_6 (0x0040U << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */ +#define RI_HYSCR3_PF_7 (0x0080U << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */ +#define RI_HYSCR3_PF_8 (0x0100U << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */ +#define RI_HYSCR3_PF_9 (0x0200U << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */ +#define RI_HYSCR3_PF_10 (0x0400U << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */ +#define RI_HYSCR3_PF_11 (0x0800U << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */ +#define RI_HYSCR3_PF_12 (0x1000U << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */ +#define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ +#define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ +#define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ +/******************** Bit definition for RI_HYSCR4 register ********************/ +#define RI_HYSCR4_PG_Pos (0U) +#define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ +#define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */ +#define RI_HYSCR4_PG_0 (0x0001U << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */ +#define RI_HYSCR4_PG_1 (0x0002U << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */ +#define RI_HYSCR4_PG_2 (0x0004U << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */ +#define RI_HYSCR4_PG_3 (0x0008U << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */ +#define RI_HYSCR4_PG_4 (0x0010U << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */ +#define RI_HYSCR4_PG_5 (0x0020U << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */ +#define RI_HYSCR4_PG_6 (0x0040U << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */ +#define RI_HYSCR4_PG_7 (0x0080U << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */ +#define RI_HYSCR4_PG_8 (0x0100U << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */ +#define RI_HYSCR4_PG_9 (0x0200U << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */ +#define RI_HYSCR4_PG_10 (0x0400U << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */ +#define RI_HYSCR4_PG_11 (0x0800U << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */ +#define RI_HYSCR4_PG_12 (0x1000U << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */ +#define RI_HYSCR4_PG_13 (0x2000U << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */ +#define RI_HYSCR4_PG_14 (0x4000U << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */ +#define RI_HYSCR4_PG_15 (0x8000U << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */ /******************** Bit definition for RI_ASMR1 register ********************/ #define RI_ASMR1_PA_Pos (0U) @@ -6596,6 +6641,132 @@ typedef struct #define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /*!< 0x00004000 */ #define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /*!< 0x00008000 */ +/******************** Bit definition for RI_ASMR4 register ********************/ +#define RI_ASMR4_PF_Pos (0U) +#define RI_ASMR4_PF_Msk (0xFFFFU << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */ +#define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */ +#define RI_ASMR4_PF_0 (0x0001U << RI_ASMR4_PF_Pos) /*!< 0x00000001 */ +#define RI_ASMR4_PF_1 (0x0002U << RI_ASMR4_PF_Pos) /*!< 0x00000002 */ +#define RI_ASMR4_PF_2 (0x0004U << RI_ASMR4_PF_Pos) /*!< 0x00000004 */ +#define RI_ASMR4_PF_3 (0x0008U << RI_ASMR4_PF_Pos) /*!< 0x00000008 */ +#define RI_ASMR4_PF_4 (0x0010U << RI_ASMR4_PF_Pos) /*!< 0x00000010 */ +#define RI_ASMR4_PF_5 (0x0020U << RI_ASMR4_PF_Pos) /*!< 0x00000020 */ +#define RI_ASMR4_PF_6 (0x0040U << RI_ASMR4_PF_Pos) /*!< 0x00000040 */ +#define RI_ASMR4_PF_7 (0x0080U << RI_ASMR4_PF_Pos) /*!< 0x00000080 */ +#define RI_ASMR4_PF_8 (0x0100U << RI_ASMR4_PF_Pos) /*!< 0x00000100 */ +#define RI_ASMR4_PF_9 (0x0200U << RI_ASMR4_PF_Pos) /*!< 0x00000200 */ +#define RI_ASMR4_PF_10 (0x0400U << RI_ASMR4_PF_Pos) /*!< 0x00000400 */ +#define RI_ASMR4_PF_11 (0x0800U << RI_ASMR4_PF_Pos) /*!< 0x00000800 */ +#define RI_ASMR4_PF_12 (0x1000U << RI_ASMR4_PF_Pos) /*!< 0x00001000 */ +#define RI_ASMR4_PF_13 (0x2000U << RI_ASMR4_PF_Pos) /*!< 0x00002000 */ +#define RI_ASMR4_PF_14 (0x4000U << RI_ASMR4_PF_Pos) /*!< 0x00004000 */ +#define RI_ASMR4_PF_15 (0x8000U << RI_ASMR4_PF_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CMR4 register ********************/ +#define RI_CMR4_PF_Pos (0U) +#define RI_CMR4_PF_Msk (0xFFFFU << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */ +#define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */ +#define RI_CMR4_PF_0 (0x0001U << RI_CMR4_PF_Pos) /*!< 0x00000001 */ +#define RI_CMR4_PF_1 (0x0002U << RI_CMR4_PF_Pos) /*!< 0x00000002 */ +#define RI_CMR4_PF_2 (0x0004U << RI_CMR4_PF_Pos) /*!< 0x00000004 */ +#define RI_CMR4_PF_3 (0x0008U << RI_CMR4_PF_Pos) /*!< 0x00000008 */ +#define RI_CMR4_PF_4 (0x0010U << RI_CMR4_PF_Pos) /*!< 0x00000010 */ +#define RI_CMR4_PF_5 (0x0020U << RI_CMR4_PF_Pos) /*!< 0x00000020 */ +#define RI_CMR4_PF_6 (0x0040U << RI_CMR4_PF_Pos) /*!< 0x00000040 */ +#define RI_CMR4_PF_7 (0x0080U << RI_CMR4_PF_Pos) /*!< 0x00000080 */ +#define RI_CMR4_PF_8 (0x0100U << RI_CMR4_PF_Pos) /*!< 0x00000100 */ +#define RI_CMR4_PF_9 (0x0200U << RI_CMR4_PF_Pos) /*!< 0x00000200 */ +#define RI_CMR4_PF_10 (0x0400U << RI_CMR4_PF_Pos) /*!< 0x00000400 */ +#define RI_CMR4_PF_11 (0x0800U << RI_CMR4_PF_Pos) /*!< 0x00000800 */ +#define RI_CMR4_PF_12 (0x1000U << RI_CMR4_PF_Pos) /*!< 0x00001000 */ +#define RI_CMR4_PF_13 (0x2000U << RI_CMR4_PF_Pos) /*!< 0x00002000 */ +#define RI_CMR4_PF_14 (0x4000U << RI_CMR4_PF_Pos) /*!< 0x00004000 */ +#define RI_CMR4_PF_15 (0x8000U << RI_CMR4_PF_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CICR4 register ********************/ +#define RI_CICR4_PF_Pos (0U) +#define RI_CICR4_PF_Msk (0xFFFFU << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */ +#define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */ +#define RI_CICR4_PF_0 (0x0001U << RI_CICR4_PF_Pos) /*!< 0x00000001 */ +#define RI_CICR4_PF_1 (0x0002U << RI_CICR4_PF_Pos) /*!< 0x00000002 */ +#define RI_CICR4_PF_2 (0x0004U << RI_CICR4_PF_Pos) /*!< 0x00000004 */ +#define RI_CICR4_PF_3 (0x0008U << RI_CICR4_PF_Pos) /*!< 0x00000008 */ +#define RI_CICR4_PF_4 (0x0010U << RI_CICR4_PF_Pos) /*!< 0x00000010 */ +#define RI_CICR4_PF_5 (0x0020U << RI_CICR4_PF_Pos) /*!< 0x00000020 */ +#define RI_CICR4_PF_6 (0x0040U << RI_CICR4_PF_Pos) /*!< 0x00000040 */ +#define RI_CICR4_PF_7 (0x0080U << RI_CICR4_PF_Pos) /*!< 0x00000080 */ +#define RI_CICR4_PF_8 (0x0100U << RI_CICR4_PF_Pos) /*!< 0x00000100 */ +#define RI_CICR4_PF_9 (0x0200U << RI_CICR4_PF_Pos) /*!< 0x00000200 */ +#define RI_CICR4_PF_10 (0x0400U << RI_CICR4_PF_Pos) /*!< 0x00000400 */ +#define RI_CICR4_PF_11 (0x0800U << RI_CICR4_PF_Pos) /*!< 0x00000800 */ +#define RI_CICR4_PF_12 (0x1000U << RI_CICR4_PF_Pos) /*!< 0x00001000 */ +#define RI_CICR4_PF_13 (0x2000U << RI_CICR4_PF_Pos) /*!< 0x00002000 */ +#define RI_CICR4_PF_14 (0x4000U << RI_CICR4_PF_Pos) /*!< 0x00004000 */ +#define RI_CICR4_PF_15 (0x8000U << RI_CICR4_PF_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_ASMR5 register ********************/ +#define RI_ASMR5_PG_Pos (0U) +#define RI_ASMR5_PG_Msk (0xFFFFU << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */ +#define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */ +#define RI_ASMR5_PG_0 (0x0001U << RI_ASMR5_PG_Pos) /*!< 0x00000001 */ +#define RI_ASMR5_PG_1 (0x0002U << RI_ASMR5_PG_Pos) /*!< 0x00000002 */ +#define RI_ASMR5_PG_2 (0x0004U << RI_ASMR5_PG_Pos) /*!< 0x00000004 */ +#define RI_ASMR5_PG_3 (0x0008U << RI_ASMR5_PG_Pos) /*!< 0x00000008 */ +#define RI_ASMR5_PG_4 (0x0010U << RI_ASMR5_PG_Pos) /*!< 0x00000010 */ +#define RI_ASMR5_PG_5 (0x0020U << RI_ASMR5_PG_Pos) /*!< 0x00000020 */ +#define RI_ASMR5_PG_6 (0x0040U << RI_ASMR5_PG_Pos) /*!< 0x00000040 */ +#define RI_ASMR5_PG_7 (0x0080U << RI_ASMR5_PG_Pos) /*!< 0x00000080 */ +#define RI_ASMR5_PG_8 (0x0100U << RI_ASMR5_PG_Pos) /*!< 0x00000100 */ +#define RI_ASMR5_PG_9 (0x0200U << RI_ASMR5_PG_Pos) /*!< 0x00000200 */ +#define RI_ASMR5_PG_10 (0x0400U << RI_ASMR5_PG_Pos) /*!< 0x00000400 */ +#define RI_ASMR5_PG_11 (0x0800U << RI_ASMR5_PG_Pos) /*!< 0x00000800 */ +#define RI_ASMR5_PG_12 (0x1000U << RI_ASMR5_PG_Pos) /*!< 0x00001000 */ +#define RI_ASMR5_PG_13 (0x2000U << RI_ASMR5_PG_Pos) /*!< 0x00002000 */ +#define RI_ASMR5_PG_14 (0x4000U << RI_ASMR5_PG_Pos) /*!< 0x00004000 */ +#define RI_ASMR5_PG_15 (0x8000U << RI_ASMR5_PG_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CMR5 register ********************/ +#define RI_CMR5_PG_Pos (0U) +#define RI_CMR5_PG_Msk (0xFFFFU << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */ +#define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */ +#define RI_CMR5_PG_0 (0x0001U << RI_CMR5_PG_Pos) /*!< 0x00000001 */ +#define RI_CMR5_PG_1 (0x0002U << RI_CMR5_PG_Pos) /*!< 0x00000002 */ +#define RI_CMR5_PG_2 (0x0004U << RI_CMR5_PG_Pos) /*!< 0x00000004 */ +#define RI_CMR5_PG_3 (0x0008U << RI_CMR5_PG_Pos) /*!< 0x00000008 */ +#define RI_CMR5_PG_4 (0x0010U << RI_CMR5_PG_Pos) /*!< 0x00000010 */ +#define RI_CMR5_PG_5 (0x0020U << RI_CMR5_PG_Pos) /*!< 0x00000020 */ +#define RI_CMR5_PG_6 (0x0040U << RI_CMR5_PG_Pos) /*!< 0x00000040 */ +#define RI_CMR5_PG_7 (0x0080U << RI_CMR5_PG_Pos) /*!< 0x00000080 */ +#define RI_CMR5_PG_8 (0x0100U << RI_CMR5_PG_Pos) /*!< 0x00000100 */ +#define RI_CMR5_PG_9 (0x0200U << RI_CMR5_PG_Pos) /*!< 0x00000200 */ +#define RI_CMR5_PG_10 (0x0400U << RI_CMR5_PG_Pos) /*!< 0x00000400 */ +#define RI_CMR5_PG_11 (0x0800U << RI_CMR5_PG_Pos) /*!< 0x00000800 */ +#define RI_CMR5_PG_12 (0x1000U << RI_CMR5_PG_Pos) /*!< 0x00001000 */ +#define RI_CMR5_PG_13 (0x2000U << RI_CMR5_PG_Pos) /*!< 0x00002000 */ +#define RI_CMR5_PG_14 (0x4000U << RI_CMR5_PG_Pos) /*!< 0x00004000 */ +#define RI_CMR5_PG_15 (0x8000U << RI_CMR5_PG_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for RI_CICR5 register ********************/ +#define RI_CICR5_PG_Pos (0U) +#define RI_CICR5_PG_Msk (0xFFFFU << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */ +#define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */ +#define RI_CICR5_PG_0 (0x0001U << RI_CICR5_PG_Pos) /*!< 0x00000001 */ +#define RI_CICR5_PG_1 (0x0002U << RI_CICR5_PG_Pos) /*!< 0x00000002 */ +#define RI_CICR5_PG_2 (0x0004U << RI_CICR5_PG_Pos) /*!< 0x00000004 */ +#define RI_CICR5_PG_3 (0x0008U << RI_CICR5_PG_Pos) /*!< 0x00000008 */ +#define RI_CICR5_PG_4 (0x0010U << RI_CICR5_PG_Pos) /*!< 0x00000010 */ +#define RI_CICR5_PG_5 (0x0020U << RI_CICR5_PG_Pos) /*!< 0x00000020 */ +#define RI_CICR5_PG_6 (0x0040U << RI_CICR5_PG_Pos) /*!< 0x00000040 */ +#define RI_CICR5_PG_7 (0x0080U << RI_CICR5_PG_Pos) /*!< 0x00000080 */ +#define RI_CICR5_PG_8 (0x0100U << RI_CICR5_PG_Pos) /*!< 0x00000100 */ +#define RI_CICR5_PG_9 (0x0200U << RI_CICR5_PG_Pos) /*!< 0x00000200 */ +#define RI_CICR5_PG_10 (0x0400U << RI_CICR5_PG_Pos) /*!< 0x00000400 */ +#define RI_CICR5_PG_11 (0x0800U << RI_CICR5_PG_Pos) /*!< 0x00000800 */ +#define RI_CICR5_PG_12 (0x1000U << RI_CICR5_PG_Pos) /*!< 0x00001000 */ +#define RI_CICR5_PG_13 (0x2000U << RI_CICR5_PG_Pos) /*!< 0x00002000 */ +#define RI_CICR5_PG_14 (0x4000U << RI_CICR5_PG_Pos) /*!< 0x00004000 */ +#define RI_CICR5_PG_15 (0x8000U << RI_CICR5_PG_Pos) /*!< 0x00008000 */ + /******************************************************************************/ /* */ /* Timers (TIM) */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xca.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xca.h index 6d761a72c4..1a5bc33c64 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xca.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xca.h @@ -473,27 +473,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -6516,7 +6516,6 @@ typedef struct #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ - /******************** Bit definition for RI_HYSCR4 register ********************/ #define RI_HYSCR4_PG_Pos (0U) #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xd.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xd.h index da5c0e12b8..a9f8d927e1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xd.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xd.h @@ -497,27 +497,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -7190,7 +7190,6 @@ typedef struct #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ - /******************** Bit definition for RI_HYSCR4 register ********************/ #define RI_HYSCR4_PG_Pos (0U) #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xdx.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xdx.h index e12ab413b2..7fd15d3e30 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xdx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xdx.h @@ -482,27 +482,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -6561,7 +6561,6 @@ typedef struct #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ - /******************** Bit definition for RI_HYSCR4 register ********************/ #define RI_HYSCR4_PG_Pos (0U) #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xe.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xe.h index a275fcb2a9..f9f0da0961 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l162xe.h @@ -482,27 +482,27 @@ typedef struct typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ + __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ + __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ + __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ + __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ + __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** @@ -6561,7 +6561,6 @@ typedef struct #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ - /******************** Bit definition for RI_HYSCR4 register ********************/ #define RI_HYSCR4_PG_Pos (0U) #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h index b7200d5af9..d7b2e53163 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h @@ -120,7 +120,7 @@ */ #define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\ |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Release_Notes.html index 28ba6f7d85..79c85d8b53 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L1xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32L1xx/Release_Notes.html @@ -283,7 +283,20 @@

Update history

-

V2.2.2 +

V2.2.3 +/ 12-January-2018

+

Main +Changes + + + + + + + + +

+
  • Corrected devices supporting RI_HYSCR3, RI_HYSCR4, RI_ASMRx, RI_CMRx, RI_CICRx registers in CMSIS files.

V2.2.2 / 25-August-2017

Main Changes diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index e031949d76..d15f1dd730 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -7,7 +7,7 @@ * STM32F4: 2.6.2 * STM32F7: 1.2.1 * STM32L0: 1.7.2 - * STM32L1: 2.2.2 + * STM32L1: 2.2.3 * STM32L4: 1.4.1 Release notes of each STM32YYxx CMSIS available here: From e99cb1745182bf3e6144ab13617d9eaff7f01440 Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 23 Jan 2018 18:12:59 +0100 Subject: [PATCH 2/9] Updated STM32L4xx CMSIS to v1.4.2 Included in STM32CubeL4 FW V1.11.0 Signed-off-by: Frederic.Pillon --- .../Device/ST/STM32L4xx/Include/stm32l431xx.h | 4 +- .../Device/ST/STM32L4xx/Include/stm32l432xx.h | 4 +- .../Device/ST/STM32L4xx/Include/stm32l433xx.h | 4 +- .../Device/ST/STM32L4xx/Include/stm32l442xx.h | 4 +- .../Device/ST/STM32L4xx/Include/stm32l443xx.h | 4 +- .../Device/ST/STM32L4xx/Include/stm32l451xx.h | 4 +- .../Device/ST/STM32L4xx/Include/stm32l452xx.h | 4 +- .../Device/ST/STM32L4xx/Include/stm32l462xx.h | 4 +- .../Device/ST/STM32L4xx/Include/stm32l471xx.h | 4 +- .../Device/ST/STM32L4xx/Include/stm32l475xx.h | 4 +- .../Device/ST/STM32L4xx/Include/stm32l476xx.h | 4 +- .../Device/ST/STM32L4xx/Include/stm32l485xx.h | 4 +- .../Device/ST/STM32L4xx/Include/stm32l486xx.h | 4 +- .../Device/ST/STM32L4xx/Include/stm32l496xx.h | 11 +-- .../Device/ST/STM32L4xx/Include/stm32l4a6xx.h | 11 +-- .../Device/ST/STM32L4xx/Include/stm32l4r5xx.h | 73 ++-------------- .../Device/ST/STM32L4xx/Include/stm32l4r7xx.h | 85 ++----------------- .../Device/ST/STM32L4xx/Include/stm32l4r9xx.h | 85 ++----------------- .../Device/ST/STM32L4xx/Include/stm32l4s5xx.h | 73 ++-------------- .../Device/ST/STM32L4xx/Include/stm32l4s7xx.h | 85 ++----------------- .../Device/ST/STM32L4xx/Include/stm32l4s9xx.h | 85 ++----------------- .../Device/ST/STM32L4xx/Include/stm32l4xx.h | 2 +- .../Device/ST/STM32L4xx/Release_Notes.html | 2 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 24 files changed, 70 insertions(+), 496 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h index db24d9565e..cda513ca29 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h @@ -772,12 +772,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h index 049aa1196d..967e908147 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h @@ -739,12 +739,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h index 08c22ebd88..2e51f1b0ac 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h @@ -788,12 +788,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h index 0a0d7418de..4c01b1ceea 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h @@ -740,12 +740,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l443xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l443xx.h index d68b9ec050..97ebfe85c4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l443xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l443xx.h @@ -789,12 +789,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l451xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l451xx.h index 338fa6b40f..af2ade8868 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l451xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l451xx.h @@ -811,12 +811,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l452xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l452xx.h index dd174e90a5..9a37ebe691 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l452xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l452xx.h @@ -812,12 +812,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l462xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l462xx.h index 2741f41106..1b03ec30da 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l462xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l462xx.h @@ -813,12 +813,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l471xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l471xx.h index 5a05dc610f..81d828d02e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l471xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l471xx.h @@ -846,12 +846,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h index d709b00eb1..f07164d9fe 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h @@ -847,12 +847,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h index ec28f55356..4f2b2a1017 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h @@ -862,12 +862,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l485xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l485xx.h index 28be72c73e..4a3bca3aa3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l485xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l485xx.h @@ -848,12 +848,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l486xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l486xx.h index 1e196b3665..7df92805e9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l486xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l486xx.h @@ -863,12 +863,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h index 78bafce325..757732902c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h @@ -505,9 +505,9 @@ typedef struct __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ - uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ - __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ - __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ + uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ } DMA2D_TypeDef; /** @@ -934,12 +934,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; @@ -7777,7 +7775,6 @@ typedef struct #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */ #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */ - /******************** Bit definition for DMA2D_FGCLUT register **************/ /******************** Bit definition for DMA2D_BGCLUT register **************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h index c7e8381adf..af3b163b21 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h @@ -506,9 +506,9 @@ typedef struct __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ - uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ - __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ - __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ + uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ } DMA2D_TypeDef; /** @@ -935,12 +935,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ } SPI_TypeDef; @@ -8022,7 +8020,6 @@ typedef struct #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */ #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */ - /******************** Bit definition for DMA2D_FGCLUT register **************/ /******************** Bit definition for DMA2D_BGCLUT register **************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h index 0cceb7563a..56825cfac9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h @@ -350,9 +350,7 @@ typedef struct typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ @@ -519,11 +517,9 @@ typedef struct __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ - uint32_t RESERVED[233]; /*!< Reserved, 0x50-0x3F0 */ - __IO uint32_t VERR; /*!< DMA2D version register, Address offset: 0x3F4 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x3F8-0x3FF */ - __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ - __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ + uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ } DMA2D_TypeDef; /** @@ -795,8 +791,6 @@ typedef struct __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ uint32_t RESERVED17[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ - uint32_t RESERVED18[124]; /*!< Reserved, Address offset: 0x204-0x3F0 */ - __IO uint32_t VERR; /*!< OCTOSPI Version register, Address offset: 0x3F4 */ } OCTOSPI_TypeDef; /** @@ -973,8 +967,6 @@ typedef struct __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ - uint32_t RESERVED2[220]; /*!< Reserved, 0x84-0x3F0 */ - __IO uint32_t VERR; /*!< SDMMC Version register Address offset: 0x3F4 */ } SDMMC_TypeDef; /** * @brief Serial Peripheral Interface @@ -985,12 +977,10 @@ typedef struct __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ - uint32_t RESERVED[246]; /*!< Reserved, 0x1C-0x3F0 */ - __IO uint32_t VERR; /*!< SPI version register, Address offset: 0x3F4 */ } SPI_TypeDef; @@ -1090,8 +1080,6 @@ typedef struct __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ uint16_t RESERVED5; /*!< Reserved, 0x2A */ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ - uint32_t RESERVED[241]; /*!< Reserved Address offset: 0x30-0x3F0 */ - __IO uint32_t VERR; /*!< USART Version register, Address offset: 0x3F4 */ } USART_TypeDef; /** @@ -6150,8 +6138,8 @@ typedef struct /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) -#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ -#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR_Msk (0xFFFFFFFFU << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET_Pos (0U) @@ -7920,15 +7908,6 @@ typedef struct #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */ #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */ -/******************** Bit definition for DMA2D_VERR register *****************/ -#define DMA2D_VERR_MINREV_Pos (0U) -#define DMA2D_VERR_MINREV_Msk (0xFU << DMA2D_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define DMA2D_VERR_MINREV DMA2D_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */ -#define DMA2D_VERR_MAJREV_Pos (4U) -#define DMA2D_VERR_MAJREV_Msk (0xFU << DMA2D_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define DMA2D_VERR_MAJREV DMA2D_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */ - - /******************** Bit definition for DMA2D_FGCLUT register **************/ /******************** Bit definition for DMA2D_BGCLUT register **************/ @@ -14583,14 +14562,6 @@ typedef struct #define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */ #define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */ -/****************** Bit definition for SDMMC_VERR register ********************/ -#define SDMMC_VERR_MINREV_Pos (0U) -#define SDMMC_VERR_MINREV_Msk (0xFU << SDMMC_VERR_MINREV_Pos) /*!< 0x0000000F */ -#define SDMMC_VERR_MINREV SDMMC_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */ -#define SDMMC_VERR_MAJREV_Pos (4U) -#define SDMMC_VERR_MAJREV_Msk (0xFU << SDMMC_VERR_MAJREV_Pos) /*!< 0x000000F0 */ -#define SDMMC_VERR_MAJREV SDMMC_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */ - /******************************************************************************/ /* */ /* Serial Peripheral Interface (SPI) */ @@ -14746,14 +14717,6 @@ typedef struct #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!

Update History

-

V1.4.1 / 13-October-2017

Main Changes

  • stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h devices description files
    • Fix SDMMC_STA_DPSMACT and SDMMC_STA_CPSMACT definitions
  • stm32l4r5xx.h and stm32l4s5xx.h devices description files
    • Remove LTDC peripheral definitions as LTDC not available on STM32L4R5xx/STM32L4S5xx devices

V1.4.0 / 25-August-2017

Main Changes

  • Add the support of STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx devices
    • Add stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h device description files
    • Add startup files startup_stm32l4r5xx.s, startup_stm32l4r7xx.s,  startup_stm32l4r9xx.s,  startup_stm32l4s5xx.s,  startup_stm32l4s7xx.s and startup_stm32l4s9xx.s for EWARM, MDK-ARM and SW4STM32 toolchains
    • Add EWARM associated linker files for execution from internal RAM or internal FLASH 
  • stm32l4xx.h
    • Add the following device defines:
      • "#define STM32L4R5xx" for all STM32L4R5xx devices
      • "#define STM32L4R7xx" for all STM32L4R7xx devices
      • "#define STM32L4R9xx" for all STM32L4R9xx devices
      • "#define STM32L4S5xx" for all STM32L4S5xx devices
      • "#define STM32L4S7xx" for all STM32L4S7xx devices
      • "#define STM32L4S9xx" for all STM32L4S9xx devices
  • all adequate stm32l4XXxx.h device description files
    • PWR: Rename PWR_CR3_EIWF to PWR_CR3_EIWUL
    • TIM: Add missing TIM8 check in debug macro IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE() devices
    • USB: Fix USB_EP0R...USB_EP7R definitions
  • system_stm32l4xx.c
    • Fix MISRA C 2004 rule 10.6 : a 'U' suffix shall be applied to all constants of 'unsigned' type

V1.3.2 +

V1.4.2 / 22-December-2017

Main Changes

  • SPI_TypeDef cleanup of Reserved fields.

V1.4.1 / 13-October-2017

Main Changes

  • stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h devices description files
    • Fix SDMMC_STA_DPSMACT and SDMMC_STA_CPSMACT definitions
  • stm32l4r5xx.h and stm32l4s5xx.h devices description files
    • Remove LTDC peripheral definitions as LTDC not available on STM32L4R5xx/STM32L4S5xx devices

V1.4.0 / 25-August-2017

Main Changes

  • Add the support of STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx devices
    • Add stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h device description files
    • Add startup files startup_stm32l4r5xx.s, startup_stm32l4r7xx.s,  startup_stm32l4r9xx.s,  startup_stm32l4s5xx.s,  startup_stm32l4s7xx.s and startup_stm32l4s9xx.s for EWARM, MDK-ARM and SW4STM32 toolchains
    • Add EWARM associated linker files for execution from internal RAM or internal FLASH 
  • stm32l4xx.h
    • Add the following device defines:
      • "#define STM32L4R5xx" for all STM32L4R5xx devices
      • "#define STM32L4R7xx" for all STM32L4R7xx devices
      • "#define STM32L4R9xx" for all STM32L4R9xx devices
      • "#define STM32L4S5xx" for all STM32L4S5xx devices
      • "#define STM32L4S7xx" for all STM32L4S7xx devices
      • "#define STM32L4S9xx" for all STM32L4S9xx devices
  • all adequate stm32l4XXxx.h device description files
    • PWR: Rename PWR_CR3_EIWF to PWR_CR3_EIWUL
    • TIM: Add missing TIM8 check in debug macro IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE() devices
    • USB: Fix USB_EP0R...USB_EP7R definitions
  • system_stm32l4xx.c
    • Fix MISRA C 2004 rule 10.6 : a 'U' suffix shall be applied to all constants of 'unsigned' type

V1.3.2 / 16-June-2017

Main Changes

diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index d15f1dd730..1b81cc0269 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -8,7 +8,7 @@ * STM32F7: 1.2.1 * STM32L0: 1.7.2 * STM32L1: 2.2.3 - * STM32L4: 1.4.1 + * STM32L4: 1.4.2 Release notes of each STM32YYxx CMSIS available here: From 1286dc679c8d868d6c8d9ee943cbc03bb7fdbb6f Mon Sep 17 00:00:00 2001 From: "Frederic.Pillon" Date: Tue, 23 Jan 2018 18:21:01 +0100 Subject: [PATCH 3/9] Updated STM32L4xx HAL Drivers to v1.8.2 Included in STM32CubeL4 FW V1.11.0 Signed-off-by: Frederic.Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 44 +- .../Inc/Legacy/stm32l4xx_hal_can_legacy.h | 769 +++++ .../Inc/stm32l4xx_hal_can.h | 730 ++--- .../Inc/stm32l4xx_hal_comp.h | 8 +- .../Inc/stm32l4xx_hal_conf_template.h | 5 + .../Inc/stm32l4xx_hal_cortex.h | 36 +- .../Inc/stm32l4xx_hal_crc.h | 12 +- .../Inc/stm32l4xx_hal_ospi.h | 28 +- .../Inc/stm32l4xx_hal_rcc.h | 383 ++- .../Inc/stm32l4xx_hal_rcc_ex.h | 258 +- .../Inc/stm32l4xx_hal_sai.h | 18 +- .../Inc/stm32l4xx_hal_spi.h | 216 +- .../Inc/stm32l4xx_hal_tim.h | 110 +- .../Inc/stm32l4xx_ll_adc.h | 10 +- .../Inc/stm32l4xx_ll_crc.h | 21 +- .../Inc/stm32l4xx_ll_rcc.h | 53 +- .../Inc/stm32l4xx_ll_tim.h | 58 +- .../Inc/stm32l4xx_ll_utils.h | 6 +- .../STM32L4xx_HAL_Driver/Release_Notes.html | 33 +- .../Src/Legacy/stm32l4xx_hal_can.c | 1480 ++++++++++ .../STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c | 2 +- .../Src/stm32l4xx_hal_adc.c | 9 +- .../Src/stm32l4xx_hal_adc_ex.c | 7 - .../Src/stm32l4xx_hal_can.c | 2534 ++++++++++------- .../Src/stm32l4xx_hal_cortex.c | 49 + .../Src/stm32l4xx_hal_crc.c | 235 +- .../Src/stm32l4xx_hal_flash.c | 14 +- .../Src/stm32l4xx_hal_rcc.c | 262 +- .../Src/stm32l4xx_hal_rcc_ex.c | 44 +- .../Src/stm32l4xx_hal_rng.c | 4 - .../Src/stm32l4xx_hal_sai.c | 142 +- .../Src/stm32l4xx_hal_sai_ex.c | 4 +- .../Src/stm32l4xx_hal_spi.c | 280 +- .../Src/stm32l4xx_hal_spi_ex.c | 6 +- .../Src/stm32l4xx_hal_tim.c | 400 +-- .../Src/stm32l4xx_hal_tim_ex.c | 148 +- .../Src/stm32l4xx_ll_lptim.c | 42 +- .../Src/stm32l4xx_ll_rcc.c | 44 +- .../Src/stm32l4xx_ll_tim.c | 38 +- .../Src/stm32l4xx_ll_utils.c | 2 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 41 files changed, 5798 insertions(+), 2748 deletions(-) create mode 100644 system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32l4xx_hal_can_legacy.h create mode 100644 system/Drivers/STM32L4xx_HAL_Driver/Src/Legacy/stm32l4xx_hal_can.c diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 6e64e55f96..c37602b2a3 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -431,12 +431,12 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -2119,6 +2119,21 @@ #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE @@ -2787,7 +2802,9 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32WB) || defined(STM32G0) +#if defined(STM32L4) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#elif defined(STM32WB) || defined(STM32G0) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3038,6 +3055,16 @@ #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif +#if defined(STM32H7) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#endif /** * @} */ @@ -3252,6 +3279,17 @@ * @} */ +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32l4xx_hal_can_legacy.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32l4xx_hal_can_legacy.h new file mode 100644 index 0000000000..bb986120f0 --- /dev/null +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32l4xx_hal_can_legacy.h @@ -0,0 +1,769 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_can_legacy.h + * @author MCD Application Team + * @brief Header file of CAN HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L4xx_CAN_LEGACY_H +#define __STM32L4xx_CAN_LEGACY_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(CAN1) +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal_def.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */ + HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */ + HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */ + +}HAL_CAN_StateTypeDef; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE */ +}CAN_InitTypeDef; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. + This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ + + uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint32_t FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + uint32_t FilterActivation; /*!< Enable or disable the filter. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t BankNumber; /*!< Select the start slave bank filter. + This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + +}CAN_FilterConfTypeDef; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + +}CanTxMsgTypeDef; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t FIFONumber; /*!< Specifies the receive FIFO number. + This parameter can be CAN_FIFO0 or CAN_FIFO1 */ + +}CanRxMsgTypeDef; + +/** + * @brief CAN handle Structure definition + */ +typedef struct +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + + CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */ + + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + + HAL_LockTypeDef Lock; /*!< CAN locking object */ + + __IO uint32_t ErrorCode; /*!< CAN Error code */ + +}CAN_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CAN_Exported_Constants CAN Exported Constants + * @{ + */ + +/** @defgroup CAN_Error_Code CAN Error Code + * @{ + */ +#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_CAN_ERROR_EWG ((uint32_t)0x00000001) /*!< EWG error */ +#define HAL_CAN_ERROR_EPV ((uint32_t)0x00000002) /*!< EPV error */ +#define HAL_CAN_ERROR_BOF ((uint32_t)0x00000004) /*!< BOF error */ +#define HAL_CAN_ERROR_STF ((uint32_t)0x00000008) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR ((uint32_t)0x00000010) /*!< Form error */ +#define HAL_CAN_ERROR_ACK ((uint32_t)0x00000020) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040) /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080) /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100) /*!< LEC transfer error */ +#define HAL_CAN_ERROR_FOV0 ((uint32_t)0x00000200) /*!< FIFO0 overrun error */ +#define HAL_CAN_ERROR_FOV1 ((uint32_t)0x00000400) /*!< FIFO1 overrun error */ +/** + * @} + */ + +/** @defgroup CAN_InitStatus CAN initialization Status + * @{ + */ +#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */ +/** + * @} + */ + +/** @defgroup CAN_operating_mode CAN Operating Mode + * @{ + */ +#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ +#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ +/** + * @} + */ + + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width + * @{ + */ +#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ +#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ +#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 + * @{ + */ +#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ +#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ +#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ +#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ +#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ +#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ +#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ +#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ +#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ +#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ +#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ +#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ +#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ +#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ +#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 + * @{ + */ +#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ +#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ +#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ +#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ +#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ +#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ +#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode CAN Filter Mode + * @{ + */ +#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +/** + * @} + */ + +/** @defgroup CAN_filter_scale CAN Filter Scale + * @{ + */ +#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO CAN Filter FIFO + * @{ + */ +#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +/** + * @} + */ + +/** @defgroup CAN_identifier_type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request + * @{ + */ +#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number + * @{ + */ +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +/** + * @} + */ + +/** @defgroup CAN_flags CAN Flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with + CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */ +#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */ +#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */ +#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */ +#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */ + +/* Receive Flags */ +#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */ + +#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */ +/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */ +#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */ +#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */ +/** + * @} + */ + +/** @defgroup CAN_interrupts CAN Interrupts + * @{ + */ +#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ + +/** + * @} + */ + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CAN_Exported_Macro CAN Exported Macros + * @{ + */ + +/** @brief Reset CAN handle state. + * @param __HANDLE__: CAN handle. + * @retval None + */ +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) + +/** + * @brief Enable the specified CAN interrupt. + * @param __HANDLE__: CAN handle. + * @param __INTERRUPT__: CAN Interrupt. + * @retval None + */ +#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified CAN interrupt. + * @param __HANDLE__: CAN handle. + * @param __INTERRUPT__: CAN Interrupt. + * @retval None + */ +#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** + * @brief Return the number of pending received messages. + * @param __HANDLE__: CAN handle. + * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval The number of pending message. + */ +#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03))) + +/** @brief Check whether the specified CAN flag is set or not. + * @param __HANDLE__: specifies the CAN Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + +/** @brief Clear the specified CAN pending flag. + * @param __HANDLE__: specifies the CAN Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0) + + +/** @brief Check whether the specified CAN interrupt source is enabled or not. + * @param __HANDLE__: specifies the CAN Handle. + * @param __INTERRUPT__: specifies the CAN interrupt source to check. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable + * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable + * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Check the transmission status of a CAN Frame. + * @param __HANDLE__: specifies the CAN Handle. + * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. + * @retval The new status of transmission (TRUE or FALSE). + */ +#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ + ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) + + + +/** + * @brief Release the specified receive FIFO. + * @param __HANDLE__: CAN handle. + * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval None + */ +#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) + +/** + * @brief Cancel a transmit request. + * @param __HANDLE__: specifies the CAN Handle. + * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. + * @retval None + */ +#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\ + ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2)) + +/** + * @brief Enable or disable the DBG Freeze for CAN. + * @param __HANDLE__: specifies the CAN Handle. + * @param __NEWSTATE__: new state of the CAN peripheral. + * This parameter can be: ENABLE (CAN reception/transmission is frozen + * during debug. Reception FIFO can still be accessed/controlled normally) + * or DISABLE (CAN is working during debug). + * @retval None + */ +#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ +((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ +/* addtogroup and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); +void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +/** @defgroup CAN_transmit_constants CAN Transmit Constants + * @{ + */ +#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ +/** + * @} + */ +#define CAN_FLAG_MASK ((uint32_t)0x000000FF) + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) + +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) + +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) + +#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) + +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) + +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) + +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) + +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ +#endif /* CAN1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L4xx_HAL_CAN_LEGACY_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h index 3ac5bf1ebf..37bf98b9f8 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h @@ -34,11 +34,11 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_CAN_H -#define __STM32L4xx_CAN_H +#ifndef STM32L4xx_HAL_CAN_H +#define STM32L4xx_HAL_CAN_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -48,6 +48,7 @@ * @{ */ +#if defined (CAN1) /** @addtogroup CAN * @{ */ @@ -56,63 +57,60 @@ /** @defgroup CAN_Exported_Types CAN Exported Types * @{ */ - /** * @brief HAL State structures definition */ typedef enum { - HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */ - HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */ - HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ + HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ + HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ + HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ -}HAL_CAN_StateTypeDef; +} HAL_CAN_StateTypeDef; /** * @brief CAN init structure definition */ typedef struct { - uint32_t Prescaler; /*!< Specifies the length of a time quantum. - This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ - uint32_t Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ + uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ - uint32_t SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ + uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ - uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set to ENABLE or DISABLE. */ + FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set to ENABLE or DISABLE */ -}CAN_InitTypeDef; +} CAN_InitTypeDef; /** * @brief CAN filter configuration structure definition @@ -121,27 +119,30 @@ typedef struct { uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ - uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. - This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ + uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. + For single CAN instance(14 dedicated filter banks), + this parameter must be a number between Min_Data = 0 and Max_Data = 13. + For dual CAN instances(28 filter banks shared), + this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ @@ -150,23 +151,27 @@ typedef struct This parameter can be a value of @ref CAN_filter_scale */ uint32_t FilterActivation; /*!< Enable or disable the filter. - This parameter can be set to ENABLE or DISABLE */ + This parameter can be set to ENABLE or DISABLE. */ - uint32_t BankNumber; /*!< Select the start slave bank filter. - This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. + For single CAN instances, this parameter is meaningless. + For dual CAN instances, all filter banks with lower index are assigned to master + CAN instance, whereas all filter banks with greater index are assigned to slave + CAN instance. + This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ -}CAN_FilterConfTypeDef; +} CAN_FilterTypeDef; /** - * @brief CAN Tx message structure definition + * @brief CAN Tx message header structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref CAN_identifier_type */ @@ -175,70 +180,67 @@ typedef struct This parameter can be a value of @ref CAN_remote_transmission_request */ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start + of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. + @note: Time Triggered Communication Mode must be enabled. + @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. + This parameter can be set to ENABLE or DISABLE. */ -}CanTxMsgTypeDef; +} CAN_TxHeaderTypeDef; /** - * @brief CAN Rx message structure definition + * @brief CAN Rx message header structure definition */ typedef struct { - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. - This parameter can be a value of @ref CAN_identifier_type */ + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - uint32_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of @ref CAN_remote_transmission_request */ + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ - uint32_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ - uint8_t Data[8]; /*!< Contains the data to be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + @note: Time Triggered Communication Mode must be enabled. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ - uint32_t FIFONumber; /*!< Specifies the receive FIFO number. - This parameter can be CAN_FIFO0 or CAN_FIFO1 */ + uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ -}CanRxMsgTypeDef; +} CAN_RxHeaderTypeDef; /** * @brief CAN handle Structure definition */ -typedef struct +typedef struct __CAN_HandleTypeDef { - CAN_TypeDef *Instance; /*!< Register base address */ - - CAN_InitTypeDef Init; /*!< CAN required parameters */ - - CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ - - CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */ + CAN_TypeDef *Instance; /*!< Register base address */ - __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + CAN_InitTypeDef Init; /*!< CAN required parameters */ - HAL_LockTypeDef Lock; /*!< CAN locking object */ + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - __IO uint32_t ErrorCode; /*!< CAN Error code */ + __IO uint32_t ErrorCode; /*!< CAN Error code. + This parameter can be a value of @ref CAN_Error_Code */ -}CAN_HandleTypeDef; +} CAN_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup CAN_Exported_Constants CAN Exported Constants * @{ */ @@ -246,27 +248,39 @@ typedef struct /** @defgroup CAN_Error_Code CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_CAN_ERROR_EWG ((uint32_t)0x00000001) /*!< EWG error */ -#define HAL_CAN_ERROR_EPV ((uint32_t)0x00000002) /*!< EPV error */ -#define HAL_CAN_ERROR_BOF ((uint32_t)0x00000004) /*!< BOF error */ -#define HAL_CAN_ERROR_STF ((uint32_t)0x00000008) /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR ((uint32_t)0x00000010) /*!< Form error */ -#define HAL_CAN_ERROR_ACK ((uint32_t)0x00000020) /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040) /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080) /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100) /*!< LEC transfer error */ -#define HAL_CAN_ERROR_FOV0 ((uint32_t)0x00000200) /*!< FIFO0 overrun error */ -#define HAL_CAN_ERROR_FOV1 ((uint32_t)0x00000400) /*!< FIFO1 overrun error */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ +#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ +#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ +#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ +#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ +#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ +#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ + /** * @} */ -/** @defgroup CAN_InitStatus CAN initialization Status +/** @defgroup CAN_InitStatus CAN InitStatus * @{ */ -#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ /** * @} */ @@ -274,7 +288,7 @@ typedef struct /** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ -#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ @@ -286,7 +300,7 @@ typedef struct /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width * @{ */ -#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ @@ -297,7 +311,7 @@ typedef struct /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 * @{ */ -#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ @@ -320,7 +334,7 @@ typedef struct /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 * @{ */ -#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ @@ -335,8 +349,8 @@ typedef struct /** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ -#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ -#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ /** * @} */ @@ -344,8 +358,8 @@ typedef struct /** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ -#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ /** * @} */ @@ -353,8 +367,8 @@ typedef struct /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ -#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ /** * @} */ @@ -362,8 +376,8 @@ typedef struct /** @defgroup CAN_identifier_type CAN Identifier Type * @{ */ -#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ /** * @} */ @@ -371,332 +385,329 @@ typedef struct /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ -#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ /** * @} */ -/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number +/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number * @{ */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ +#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ /** * @} */ -/** @defgroup CAN_flags CAN Flags +/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes * @{ */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ +#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ +#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ +#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ +/** + * @} + */ +/** @defgroup CAN_flags CAN Flags + * @{ + */ /* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */ -#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */ -#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */ -#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */ -#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ +#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ +#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ +#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ +#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ +#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ +#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ +#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ +#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ +#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ /* Receive Flags */ -#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */ - -#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ /* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */ -#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ /* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */ -#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */ -#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ /** * @} */ -/** @defgroup CAN_interrupts CAN Interrupts + +/** @defgroup CAN_Interrupts CAN Interrupts * @{ */ -#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ +/* Transmit Interrupt */ +#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ /* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ -#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ -#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ -#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ -#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ -#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ +#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ /* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ -#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ +#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ /* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ -#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ -#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ -#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ -#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ - +#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ /** * @} */ -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - /** * @} */ /* Exported macros -----------------------------------------------------------*/ -/** @defgroup CAN_Exported_Macro CAN Exported Macros +/** @defgroup CAN_Exported_Macros CAN Exported Macros * @{ */ -/** @brief Reset CAN handle state. - * @param __HANDLE__: CAN handle. +/** @brief Reset CAN handle state + * @param __HANDLE__ CAN handle. * @retval None */ #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) /** - * @brief Enable the specified CAN interrupt. - * @param __HANDLE__: CAN handle. - * @param __INTERRUPT__: CAN Interrupt. + * @brief Enable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to enable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) /** - * @brief Disable the specified CAN interrupt. - * @param __HANDLE__: CAN handle. - * @param __INTERRUPT__: CAN Interrupt. + * @brief Disable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to disable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) -/** - * @brief Return the number of pending received messages. - * @param __HANDLE__: CAN handle. - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval The number of pending message. +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be a value of @arg CAN_Interrupts + * @retval The state of __IT__ (TRUE or FALSE). */ -#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03))) +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) /** @brief Check whether the specified CAN flag is set or not. - * @param __HANDLE__: specifies the CAN Handle. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @arg CAN_flags + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** @brief Clear the specified CAN pending flag. - * @param __HANDLE__: specifies the CAN Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag + * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag + * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag + * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag + * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag + * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag + * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag + * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag + * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag + * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag + * @retval None */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0) + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) +/** + * @} + */ -/** @brief Check whether the specified CAN interrupt source is enabled or not. - * @param __HANDLE__: specifies the CAN Handle. - * @param __INTERRUPT__: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable - * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable - * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ */ -#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); /** - * @brief Check the transmission status of a CAN Frame. - * @param __HANDLE__: specifies the CAN Handle. - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. - * @retval The new status of transmission (TRUE or FALSE). - */ -#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ - ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) + * @} + */ +/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); /** - * @brief Release the specified receive FIFO. - * @param __HANDLE__: CAN handle. - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval None - */ -#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) + * @} + */ -/** - * @brief Cancel a transmit request. - * @param __HANDLE__: specifies the CAN Handle. - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. - * @retval None - */ -#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\ - ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2)) +/** @addtogroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ -/** - * @brief Enable or disable the DBG Freeze for CAN. - * @param __HANDLE__: specifies the CAN Handle. - * @param __NEWSTATE__: new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFO can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ -((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); /** * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CAN_Exported_Functions CAN Exported Functions - * @{ - */ - -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + */ + +/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management * @{ */ -/* addtogroup and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + /** * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions + */ + +/** @addtogroup CAN_Exported_Functions_Group5 Callback functions + * @brief Callback functions * @{ */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); -void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); -void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +/* Callbacks functions ********************************************************/ + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); + /** * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions + */ + +/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions * @{ */ /* Peripheral State and Error functions ***************************************/ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); + /** * @} - */ + */ /** * @} - */ + */ /* Private types -------------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Constants CAN Private Constants +/** @defgroup CAN_Private_Types CAN Private Types * @{ */ -/** @defgroup CAN_transmit_constants CAN Transmit Constants + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Variables CAN Private Variables * @{ */ -#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ + /** * @} */ -#define CAN_FLAG_MASK ((uint32_t)0x000000FF) - +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_FLAG_MASK (0x000000FFU) /** * @} */ -/* Private macros ------------------------------------------------------------*/ +/* Private Macros -----------------------------------------------------------*/ /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ @@ -705,64 +716,69 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); ((MODE) == CAN_MODE_LOOPBACK)|| \ ((MODE) == CAN_MODE_SILENT) || \ ((MODE) == CAN_MODE_SILENT_LOOPBACK)) - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) - -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) - -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) - +#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ + ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ + ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ + ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ + ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ + ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ + ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ + ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) +#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ + ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ + ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ + ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) +#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) - #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ ((SCALE) == CAN_FILTERSCALE_32BIT)) - #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) - -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) - -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) - -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) - -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - +#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ ((IDTYPE) == CAN_ID_EXT)) - #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) +#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) +#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ + CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ + CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ + CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ + CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ + CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) /** * @} */ - -/* Private functions ---------------------------------------------------------*/ +/* End of private macros -----------------------------------------------------*/ /** * @} */ + +#endif /* CAN1 */ /** * @} */ - #ifdef __cplusplus } #endif -#endif /* __STM32L4xx_CAN_H */ +#endif /* STM32L4xx_HAL_CAN_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h index 06558d652b..51f573a3b3 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h @@ -189,10 +189,10 @@ typedef struct /** @defgroup COMP_Hysteresis COMP hysteresis * @{ */ -#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */ -#define COMP_HYSTERESIS_LOW (COMP_CSR_HYST_0) /*!< Hysteresis level low */ -#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1) /*!< Hysteresis level medium */ -#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST) /*!< Hysteresis level high */ +#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */ +#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ +#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ +#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */ /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h index 594777d72a..c647a79075 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h @@ -53,6 +53,7 @@ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED #define HAL_CAN_MODULE_ENABLED +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ #define HAL_COMP_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED @@ -243,6 +244,10 @@ #include "stm32l4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "Legacy/stm32l4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_COMP_MODULE_ENABLED #include "stm32l4xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h index aea3ad13c7..ced44790a0 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h @@ -287,40 +287,6 @@ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_SystemReset(void); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); -#if (__MPU_PRESENT == 1) -/** - * @brief Disable the MPU. - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Disable(void) -{ - /* Disable fault exceptions */ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU */ - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -/** - * @brief Enable the MPU. - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged accessto the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) -{ - /* Enable the MPU */ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - - /* Enable fault exceptions */ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -} -#endif /* __MPU_PRESENT */ /** * @} */ @@ -341,6 +307,8 @@ void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h index 389d22423f..c663af46f2 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h @@ -263,17 +263,19 @@ typedef struct #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) /** - * @brief Store a 8-bit data in the Independent Data(ID) register. + * @brief Store data in the Independent Data (ID) register. * @param __HANDLE__: CRC handle - * @param __VALUE__: 8-bit value to be stored in the ID register + * @param __VALUE__: Value to be stored in the ID register + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits * @retval None */ -#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))) /** - * @brief Return the 8-bit data stored in the Independent Data(ID) register. + * @brief Return the data stored in the Independent Data (ID) register. * @param __HANDLE__: CRC handle - * @retval 8-bit value of the ID register + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval Value of the ID register */ #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h index d20f34fff7..7910439c6e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_ospi.h @@ -603,18 +603,6 @@ typedef struct #define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1)) /*!< Port 1 - IO[7:4] */ #define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2)) /*!< Port 2 - IO[3:0] */ #define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2)) /*!< Port 2 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3)) /*!< Port 3 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3)) /*!< Port 3 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4)) /*!< Port 4 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4)) /*!< Port 4 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5)) /*!< Port 5 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5)) /*!< Port 5 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6)) /*!< Port 6 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6)) /*!< Port 6 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7)) /*!< Port 7 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7)) /*!< Port 7 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8)) /*!< Port 8 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8)) /*!< Port 8 - IO[7:4] */ /** * @} */ @@ -949,24 +937,12 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31) -#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1) && ((NUMBER) <= 8)) +#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1) && ((NUMBER) <= 2)) #define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \ - ((PORT) == HAL_OSPIM_IOPORT_3_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_3_HIGH) || \ - ((PORT) == HAL_OSPIM_IOPORT_4_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_4_HIGH) || \ - ((PORT) == HAL_OSPIM_IOPORT_5_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_5_HIGH) || \ - ((PORT) == HAL_OSPIM_IOPORT_6_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_6_HIGH) || \ - ((PORT) == HAL_OSPIM_IOPORT_7_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \ - ((PORT) == HAL_OSPIM_IOPORT_8_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_8_HIGH)) + ((PORT) == HAL_OSPIM_IOPORT_2_HIGH)) /** @endcond */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h index e1aadfd545..16aeffbb68 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h @@ -161,7 +161,7 @@ typedef struct /** @defgroup RCC_Timeout_Value Timeout Values * @{ */ -#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /** * @} @@ -170,14 +170,14 @@ typedef struct /** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ -#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /*!< Oscillator configuration unchanged */ -#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /*!< HSE to configure */ -#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /*!< HSI to configure */ -#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /*!< LSE to configure */ -#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /*!< LSI to configure */ -#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /*!< MSI to configure */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ +#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ +#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ +#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ +#define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */ #if defined(RCC_HSI48_SUPPORT) -#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U) /*!< HSI48 to configure */ +#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ #endif /* RCC_HSI48_SUPPORT */ /** * @} @@ -186,9 +186,9 @@ typedef struct /** @defgroup RCC_HSE_Config HSE Config * @{ */ -#define RCC_HSE_OFF ((uint32_t)0x00000000U) /*!< HSE clock deactivation */ -#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ -#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ /** * @} */ @@ -196,9 +196,9 @@ typedef struct /** @defgroup RCC_LSE_Config LSE Config * @{ */ -#define RCC_LSE_OFF ((uint32_t)0x00000000U) /*!< LSE clock deactivation */ -#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ -#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ +#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ /** * @} */ @@ -206,14 +206,14 @@ typedef struct /** @defgroup RCC_HSI_Config HSI Config * @{ */ -#define RCC_HSI_OFF ((uint32_t)0x00000000U) /*!< HSI clock deactivation */ -#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ +#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ #else -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x40U) /* Default HSI calibration trimming value */ +#define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */ #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ /** @@ -223,8 +223,8 @@ typedef struct /** @defgroup RCC_LSI_Config LSI Config * @{ */ -#define RCC_LSI_OFF ((uint32_t)0x00000000U) /*!< LSI clock deactivation */ -#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ /** * @} */ @@ -232,10 +232,10 @@ typedef struct /** @defgroup RCC_MSI_Config MSI Config * @{ */ -#define RCC_MSI_OFF ((uint32_t)0x00000000U) /*!< MSI clock deactivation */ -#define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ +#define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ +#define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ -#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /*!< Default MSI calibration trimming value */ +#define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ /** * @} */ @@ -244,8 +244,8 @@ typedef struct /** @defgroup RCC_HSI48_Config HSI48 Config * @{ */ -#define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */ -#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ +#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ +#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ /** * @} */ @@ -253,7 +253,7 @@ typedef struct /** @defgroup RCC_HSI48_Config HSI48 Config * @{ */ -#define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */ +#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ /** * @} */ @@ -262,9 +262,9 @@ typedef struct /** @defgroup RCC_PLL_Config PLL Config * @{ */ -#define RCC_PLL_NONE ((uint32_t)0x00000000U) /*!< PLL configuration unchanged */ -#define RCC_PLL_OFF ((uint32_t)0x00000001U) /*!< PLL deactivation */ -#define RCC_PLL_ON ((uint32_t)0x00000002U) /*!< PLL activation */ +#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ +#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ +#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ /** * @} */ @@ -273,39 +273,39 @@ typedef struct * @{ */ #if defined(RCC_PLLP_DIV_2_31_SUPPORT) -#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) /*!< PLLP division factor = 2 */ -#define RCC_PLLP_DIV3 ((uint32_t)0x00000003U) /*!< PLLP division factor = 3 */ -#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) /*!< PLLP division factor = 4 */ -#define RCC_PLLP_DIV5 ((uint32_t)0x00000005U) /*!< PLLP division factor = 5 */ -#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) /*!< PLLP division factor = 6 */ -#define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */ -#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) /*!< PLLP division factor = 8 */ -#define RCC_PLLP_DIV9 ((uint32_t)0x00000009U) /*!< PLLP division factor = 9 */ -#define RCC_PLLP_DIV10 ((uint32_t)0x0000000AU) /*!< PLLP division factor = 10 */ -#define RCC_PLLP_DIV11 ((uint32_t)0x0000000BU) /*!< PLLP division factor = 11 */ -#define RCC_PLLP_DIV12 ((uint32_t)0x0000000CU) /*!< PLLP division factor = 12 */ -#define RCC_PLLP_DIV13 ((uint32_t)0x0000000DU) /*!< PLLP division factor = 13 */ -#define RCC_PLLP_DIV14 ((uint32_t)0x0000000EU) /*!< PLLP division factor = 14 */ -#define RCC_PLLP_DIV15 ((uint32_t)0x0000000FU) /*!< PLLP division factor = 15 */ -#define RCC_PLLP_DIV16 ((uint32_t)0x00000010U) /*!< PLLP division factor = 16 */ -#define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */ -#define RCC_PLLP_DIV18 ((uint32_t)0x00000012U) /*!< PLLP division factor = 18 */ -#define RCC_PLLP_DIV19 ((uint32_t)0x00000013U) /*!< PLLP division factor = 19 */ -#define RCC_PLLP_DIV20 ((uint32_t)0x00000014U) /*!< PLLP division factor = 20 */ -#define RCC_PLLP_DIV21 ((uint32_t)0x00000015U) /*!< PLLP division factor = 21 */ -#define RCC_PLLP_DIV22 ((uint32_t)0x00000016U) /*!< PLLP division factor = 22 */ -#define RCC_PLLP_DIV23 ((uint32_t)0x00000017U) /*!< PLLP division factor = 23 */ -#define RCC_PLLP_DIV24 ((uint32_t)0x00000018U) /*!< PLLP division factor = 24 */ -#define RCC_PLLP_DIV25 ((uint32_t)0x00000019U) /*!< PLLP division factor = 25 */ -#define RCC_PLLP_DIV26 ((uint32_t)0x0000001AU) /*!< PLLP division factor = 26 */ -#define RCC_PLLP_DIV27 ((uint32_t)0x0000001BU) /*!< PLLP division factor = 27 */ -#define RCC_PLLP_DIV28 ((uint32_t)0x0000001CU) /*!< PLLP division factor = 28 */ -#define RCC_PLLP_DIV29 ((uint32_t)0x0000001DU) /*!< PLLP division factor = 29 */ -#define RCC_PLLP_DIV30 ((uint32_t)0x0000001EU) /*!< PLLP division factor = 30 */ -#define RCC_PLLP_DIV31 ((uint32_t)0x0000001FU) /*!< PLLP division factor = 31 */ +#define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ +#define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ +#define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ +#define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ +#define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ +#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ +#define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ +#define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ +#define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ +#define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ +#define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ +#define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ +#define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ +#define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ +#define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ +#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ +#define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ +#define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ +#define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ +#define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ +#define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ +#define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ +#define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ +#define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ +#define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ +#define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ +#define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ +#define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ +#define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ +#define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ #else -#define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */ -#define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */ +#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ +#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ /** * @} @@ -314,10 +314,10 @@ typedef struct /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider * @{ */ -#define RCC_PLLQ_DIV2 ((uint32_t)0x00000002U) /*!< PLLQ division factor = 2 */ -#define RCC_PLLQ_DIV4 ((uint32_t)0x00000004U) /*!< PLLQ division factor = 4 */ -#define RCC_PLLQ_DIV6 ((uint32_t)0x00000006U) /*!< PLLQ division factor = 6 */ -#define RCC_PLLQ_DIV8 ((uint32_t)0x00000008U) /*!< PLLQ division factor = 8 */ +#define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ +#define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ +#define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ +#define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ /** * @} */ @@ -325,10 +325,10 @@ typedef struct /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider * @{ */ -#define RCC_PLLR_DIV2 ((uint32_t)0x00000002U) /*!< PLLR division factor = 2 */ -#define RCC_PLLR_DIV4 ((uint32_t)0x00000004U) /*!< PLLR division factor = 4 */ -#define RCC_PLLR_DIV6 ((uint32_t)0x00000006U) /*!< PLLR division factor = 6 */ -#define RCC_PLLR_DIV8 ((uint32_t)0x00000008U) /*!< PLLR division factor = 8 */ +#define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ +#define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ +#define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ +#define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ /** * @} */ @@ -336,7 +336,7 @@ typedef struct /** @defgroup RCC_PLL_Clock_Source PLL Clock Source * @{ */ -#define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U) /*!< No clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ @@ -410,10 +410,10 @@ typedef struct /** @defgroup RCC_System_Clock_Type System Clock Type * @{ */ -#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /*!< SYSCLK to configure */ -#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /*!< HCLK to configure */ -#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /*!< PCLK1 to configure */ -#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /*!< PCLK2 to configure */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ /** * @} */ @@ -471,10 +471,10 @@ typedef struct /** @defgroup RCC_RTC_Clock_Source RTC Clock Source * @{ */ -#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) /*!< No clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ /** * @} */ @@ -482,8 +482,8 @@ typedef struct /** @defgroup RCC_MCO_Index MCO Index * @{ */ -#define RCC_MCO1 ((uint32_t)0x00000000U) -#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ +#define RCC_MCO1 0x00000000U +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ /** * @} */ @@ -491,7 +491,7 @@ typedef struct /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source * @{ */ -#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U) /*!< MCO1 output disabled, no clock on MCO1 */ +#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ @@ -509,7 +509,7 @@ typedef struct /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler * @{ */ -#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ +#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ @@ -551,34 +551,34 @@ typedef struct * @{ */ /* Flags in the CR register */ -#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI Ready flag */ -#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ -#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ -#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL Ready flag */ -#define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos)) /*!< PLLSAI1 Ready flag */ +#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ +#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ +#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ +#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ +#define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ #if defined(RCC_PLLSAI2_SUPPORT) -#define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos)) /*!< PLLSAI2 Ready flag */ +#define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ #endif /* RCC_PLLSAI2_SUPPORT */ /* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */ -#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ +#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ +#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ /* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< LSI Ready flag */ -#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */ -#define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos)) /*!< Firewall reset flag */ -#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */ -#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ -#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)) /*!< BOR reset flag */ -#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ -#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ -#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ -#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ +#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ +#define RCC_FLAG_RMVF ((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos) /*!< Remove reset flag */ +#define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */ +#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ +#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ +#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ +#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ #if defined(RCC_HSI48_SUPPORT) /* Flags in the CRRCR register */ -#define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */ +#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ #endif /* RCC_HSI48_SUPPORT */ /** * @} @@ -587,19 +587,19 @@ typedef struct /** @defgroup RCC_LSEDrive_Config LSE Drive Config * @{ */ -#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< LSE low drive capability */ -#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ -#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ -#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ +#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ /** * @} */ -/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock +/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock * @{ */ -#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /*!< MSI selection after wake-up from STOP */ -#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ +#define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ +#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ /** * @} */ @@ -671,7 +671,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ UNUSED(tmpreg); \ } while(0) - + #if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -680,7 +680,7 @@ typedef struct tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ UNUSED(tmpreg); \ } while(0) -#endif /* DMA2D */ +#endif /* DMA2D */ #if defined(GFXMMU) #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ @@ -709,7 +709,7 @@ typedef struct #if defined(DMA2D) #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) -#endif /* DMA2D */ +#endif /* DMA2D */ #if defined(GFXMMU) #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) @@ -834,7 +834,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ UNUSED(tmpreg); \ - } while(0) + } while(0) #endif /* DCMI */ #if defined(AES) @@ -854,7 +854,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ UNUSED(tmpreg); \ - } while(0) + } while(0) #endif /* HASH */ #define __HAL_RCC_RNG_CLK_ENABLE() do { \ @@ -1213,7 +1213,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ UNUSED(tmpreg); \ } while(0) - + #if defined(CAN2) #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -3641,8 +3641,8 @@ typedef struct */ /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset - * @{ - */ + * @{ + */ /** @brief Macros to force or release the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) @@ -3659,8 +3659,8 @@ typedef struct */ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration - * @{ - */ + * @{ + */ /** @brief Macros to enable or disable the RTC clock. * @note As the RTC is in the Backup domain and write access is denied to @@ -3701,13 +3701,13 @@ typedef struct /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. - * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value * (default is RCC_HSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices). * @retval None */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) /** * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) @@ -3759,13 +3759,13 @@ typedef struct * and temperature that influence the frequency of the internal MSI RC. * Refer to the Application Note AN3300 for more details on how to * calibrate the MSI. - * @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value + * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value * (default is RCC_MSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 255. * @retval None */ #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8) + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos) /** * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode @@ -3777,7 +3777,7 @@ typedef struct * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready * (MSIRDY=1). * @note The MSI clock range after reset can be modified on the fly. - * @param __MSIRANGEVALUE__: specifies the MSI clock range. + * @param __MSIRANGEVALUE__ specifies the MSI clock range. * This parameter must be one of the following values: * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz @@ -3802,7 +3802,7 @@ typedef struct /** * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). - * @param __MSIRANGEVALUE__: specifies the MSI clock range. + * @param __MSIRANGEVALUE__ specifies the MSI clock range. * This parameter must be one of the following values: * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz @@ -3831,8 +3831,8 @@ typedef struct */ #define __HAL_RCC_GET_MSI_RANGE() \ ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \ - (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \ - (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4)) + READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ + READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U) /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on @@ -3862,7 +3862,7 @@ typedef struct * @note This function reset the CSSON bit, so if the clock security system(CSS) * was previously enabled you have to enable it again after calling this * function. - * @param __STATE__: specifies the new state of the HSE. + * @param __STATE__ specifies the new state of the HSE. * This parameter can be one of the following values: * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. @@ -3891,8 +3891,8 @@ typedef struct /** * @brief Macro to configure the External Low Speed oscillator (LSE). * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this macro. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE @@ -3900,7 +3900,7 @@ typedef struct * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. - * @param __STATE__: specifies the new state of the LSE. + * @param __STATE__ specifies the new state of the LSE. * This parameter can be one of the following values: * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. @@ -3950,9 +3950,9 @@ typedef struct * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). * - * @param __RTC_CLKSOURCE__: specifies the RTC clock source. + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. * This parameter can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected @@ -3971,12 +3971,12 @@ typedef struct /** @brief Macro to get the RTC clock source. * @retval The returned value can be one of the following: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected */ -#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) /** @brief Macros to enable or disable the main PLL. * @note After enabling the main PLL, the application software should wait on @@ -3992,7 +3992,7 @@ typedef struct /** @brief Macro to configure the PLL clock source. * @note This function must be used only when the main PLL is disabled. - * @param __PLLSOURCE__: specifies the PLL entry clock source. + * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry @@ -4000,21 +4000,21 @@ typedef struct * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). * @retval None - * + * */ #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) /** @brief Macro to configure the PLL source division factor M. * @note This function must be used only when the main PLL is disabled. - * @param __PLLM__: specifies the division factor for PLL VCO input clock + * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency * of 16 MHz to limit PLL jitter. * @retval None - * + * */ #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U) @@ -4023,7 +4023,7 @@ typedef struct * @brief Macro to configure the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. * - * @param __PLLSOURCE__: specifies the PLL entry clock source. + * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry @@ -4031,29 +4031,29 @@ typedef struct * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). * - * @param __PLLM__: specifies the division factor for PLL VCO input clock. + * @param __PLLM__ specifies the division factor for PLL VCO input clock. * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency * of 16 MHz to limit PLL jitter. * - * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. * This parameter must be a number between 8 and 86. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 64 and 344 MHz. * - * @param __PLLP__: specifies the division factor for SAI clock. + * @param __PLLP__ specifies the division factor for SAI clock. * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x * else (2 to 31). * - * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks. + * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. * This parameter must be in the range (2, 4, 6 or 8). * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work * correctly. - * @param __PLLR__: specifies the division factor for the main system clock. + * @param __PLLR__ specifies the division factor for the main system clock. * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. * This parameter must be in the range (2, 4, 6 or 8). * @retval None @@ -4062,14 +4062,14 @@ typedef struct #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ - (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ - (uint32_t)((__PLLP__) << 27U)) - + (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ + ((uint32_t)(__PLLP__) << 27U)) #else - + #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ - (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ - (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) + (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ + (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ + (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ @@ -4081,14 +4081,14 @@ typedef struct * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) +#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) /** * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) - * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime - * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot + * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime + * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot * be stopped if used as System Clock. - * @param __PLLCLOCKOUT__: specifies the PLL clock to be output. + * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. * This parameter can be one or a combination of the following values: * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve * high-quality audio performance on SAI interface in case. @@ -4103,7 +4103,7 @@ typedef struct /** * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) - * @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked. + * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. * This parameter can be one of the following values: * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve * high-quality audio performance on SAI interface in case. @@ -4116,7 +4116,7 @@ typedef struct /** * @brief Macro to configure the system clock source. - * @param __SYSCLKSOURCE__: specifies the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. * This parameter can be one of the following values: * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. @@ -4135,7 +4135,7 @@ typedef struct * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) +#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) /** * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. @@ -4143,7 +4143,7 @@ typedef struct * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE * (to be done once after reset). - * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. + * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. * This parameter can be one of the following values: * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. @@ -4152,11 +4152,11 @@ typedef struct * @retval None */ #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) /** * @brief Macro to configure the wake up from stop clock. - * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. + * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. * This parameter can be one of the following values: * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source @@ -4199,9 +4199,8 @@ typedef struct * @{ */ -/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable - * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. +/** @brief Enable RCC interrupt(s). + * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt @@ -4222,9 +4221,8 @@ typedef struct */ #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) -/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable - * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. +/** @brief Disable RCC interrupt(s). + * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt @@ -4245,9 +4243,8 @@ typedef struct */ #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) -/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] - * bits to clear the selected interrupt pending bits. - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. +/** @brief Clear the RCC's interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt @@ -4267,10 +4264,10 @@ typedef struct @endif * @retval None */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) /** @brief Check whether the RCC interrupt has occurred or not. - * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt @@ -4290,17 +4287,17 @@ typedef struct @endif * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Set RMVF bit to clear the reset flags. * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. * @retval None */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) +#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) /** @brief Check whether the selected RCC flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready @@ -4329,18 +4326,16 @@ typedef struct * @retval The new state of __FLAG__ (TRUE or FALSE). */ #if defined(RCC_HSI48_SUPPORT) -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ - ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ - ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ - ? 1U : 0U) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ + ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ + ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) #else #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ - ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ - ? 1U : 0U) + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) #endif /* RCC_HSI48_SUPPORT */ /** @@ -4350,20 +4345,20 @@ typedef struct /** * @} */ - + /* Private constants ---------------------------------------------------------*/ /** @defgroup RCC_Private_Constants RCC Private Constants * @{ */ /* Defines used for Flags */ -#define CR_REG_INDEX ((uint32_t)1U) -#define BDCR_REG_INDEX ((uint32_t)2U) -#define CSR_REG_INDEX ((uint32_t)3U) +#define CR_REG_INDEX 1U +#define BDCR_REG_INDEX 2U +#define CSR_REG_INDEX 3U #if defined(RCC_HSI48_SUPPORT) -#define CRRCR_REG_INDEX ((uint32_t)4U) +#define CRRCR_REG_INDEX 4U #endif /* RCC_HSI48_SUPPORT */ -#define RCC_FLAG_MASK ((uint32_t)0x1FU) +#define RCC_FLAG_MASK 0x1FU /** * @} */ @@ -4398,13 +4393,13 @@ typedef struct #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) -#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) -#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U) +#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) #if defined(RCC_HSI48_SUPPORT) #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) @@ -4447,12 +4442,12 @@ typedef struct #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \ - (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) + (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \ (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \ - (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U)) + (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U)) #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ #endif /* RCC_PLLSAI2_SUPPORT */ @@ -4491,7 +4486,7 @@ typedef struct ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ ((__PCLK__) == RCC_HCLK_DIV16)) -#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) @@ -4548,7 +4543,7 @@ typedef struct */ /* Initialization and de-initialization functions ******************************/ -void HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h index 90b8301c80..136881c73b 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h @@ -342,8 +342,8 @@ typedef struct /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source * @{ */ -#define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */ -#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ +#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ +#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ /** * @} */ @@ -351,58 +351,58 @@ typedef struct /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection * @{ */ -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U) +#define RCC_PERIPHCLK_USART1 0x00000001U +#define RCC_PERIPHCLK_USART2 0x00000002U #if defined(USART3) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004U) +#define RCC_PERIPHCLK_USART3 0x00000004U #endif #if defined(UART4) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008U) +#define RCC_PERIPHCLK_UART4 0x00000008U #endif #if defined(UART5) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010U) +#define RCC_PERIPHCLK_UART5 0x00000010U #endif -#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020U) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040U) +#define RCC_PERIPHCLK_LPUART1 0x00000020U +#define RCC_PERIPHCLK_I2C1 0x00000040U #if defined(I2C2) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080U) +#define RCC_PERIPHCLK_I2C2 0x00000080U #endif -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U) -#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200U) -#define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400U) -#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800U) +#define RCC_PERIPHCLK_I2C3 0x00000100U +#define RCC_PERIPHCLK_LPTIM1 0x00000200U +#define RCC_PERIPHCLK_LPTIM2 0x00000400U +#define RCC_PERIPHCLK_SAI1 0x00000800U #if defined(SAI2) -#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000U) +#define RCC_PERIPHCLK_SAI2 0x00001000U #endif #if defined(USB_OTG_FS) || defined(USB) -#define RCC_PERIPHCLK_USB ((uint32_t)0x00002000U) +#define RCC_PERIPHCLK_USB 0x00002000U #endif -#define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000U) +#define RCC_PERIPHCLK_ADC 0x00004000U #if defined(SWPMI1) -#define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000U) +#define RCC_PERIPHCLK_SWPMI1 0x00008000U #endif #if defined(DFSDM1_Filter0) -#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000U) +#define RCC_PERIPHCLK_DFSDM1 0x00010000U #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define RCC_PERIPHCLK_DFSDM1AUDIO ((uint32_t)0x00200000U) +#define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000U) -#define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000U) +#define RCC_PERIPHCLK_RTC 0x00020000U +#define RCC_PERIPHCLK_RNG 0x00040000U #if defined(SDMMC1) -#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000U) +#define RCC_PERIPHCLK_SDMMC1 0x00080000U #endif #if defined(I2C4) -#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00100000U) +#define RCC_PERIPHCLK_I2C4 0x00100000U #endif #if defined(LTDC) -#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00400000U) +#define RCC_PERIPHCLK_LTDC 0x00400000U #endif #if defined(DSI) -#define RCC_PERIPHCLK_DSI ((uint32_t)0x00800000U) +#define RCC_PERIPHCLK_DSI 0x00800000U #endif #if defined(OCTOSPI1) || defined(OCTOSPI2) -#define RCC_PERIPHCLK_OSPI ((uint32_t)0x01000000U) +#define RCC_PERIPHCLK_OSPI 0x01000000U #endif /** * @} @@ -412,7 +412,7 @@ typedef struct /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source * @{ */ -#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) @@ -423,7 +423,7 @@ typedef struct /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source * @{ */ -#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) @@ -435,7 +435,7 @@ typedef struct /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source * @{ */ -#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) @@ -448,7 +448,7 @@ typedef struct /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source * @{ */ -#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) @@ -461,7 +461,7 @@ typedef struct /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source * @{ */ -#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) @@ -473,7 +473,7 @@ typedef struct /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source * @{ */ -#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) @@ -484,7 +484,7 @@ typedef struct /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source * @{ */ -#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 /** @@ -495,7 +495,7 @@ typedef struct /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source * @{ */ -#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 /** @@ -506,7 +506,7 @@ typedef struct /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source * @{ */ -#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 /** @@ -517,7 +517,7 @@ typedef struct /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source * @{ */ -#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 /** @@ -528,7 +528,7 @@ typedef struct /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source * @{ */ -#define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U) +#define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U #if defined(RCC_PLLSAI2_SUPPORT) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0 @@ -552,7 +552,7 @@ typedef struct /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source * @{ */ -#define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U) +#define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 @@ -571,7 +571,7 @@ typedef struct /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source * @{ */ -#define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL @@ -582,7 +582,7 @@ typedef struct /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source * @{ */ -#define RCC_LPTIM2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL @@ -595,9 +595,9 @@ typedef struct * @{ */ #if defined(RCC_HSI48_SUPPORT) -#define RCC_SDMMC1CLKSOURCE_HSI48 ((uint32_t)0x00000000U) /*!< HSI48 clock selected as SDMMC1 clock */ +#define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock selected as SDMMC1 clock */ #else -#define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U) /*!< No clock selected as SDMMC1 clock */ +#define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U /*!< No clock selected as SDMMC1 clock */ #endif /* RCC_HSI48_SUPPORT */ #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */ #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */ @@ -614,9 +614,9 @@ typedef struct * @{ */ #if defined(RCC_HSI48_SUPPORT) -#define RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000U) +#define RCC_RNGCLKSOURCE_HSI48 0x00000000U #else -#define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000U) +#define RCC_RNGCLKSOURCE_NONE 0x00000000U #endif /* RCC_HSI48_SUPPORT */ #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 @@ -630,9 +630,9 @@ typedef struct * @{ */ #if defined(RCC_HSI48_SUPPORT) -#define RCC_USBCLKSOURCE_HSI48 ((uint32_t)0x00000000U) +#define RCC_USBCLKSOURCE_HSI48 0x00000000U #else -#define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000U) +#define RCC_USBCLKSOURCE_NONE 0x00000000U #endif /* RCC_HSI48_SUPPORT */ #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 @@ -645,7 +645,7 @@ typedef struct /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source * @{ */ -#define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000U) +#define RCC_ADCCLKSOURCE_NONE 0x00000000U #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 @@ -659,7 +659,7 @@ typedef struct /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source * @{ */ -#define RCC_SWPMI1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL /** * @} @@ -670,7 +670,7 @@ typedef struct /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source * @{ */ -#define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL #else @@ -684,7 +684,7 @@ typedef struct /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source * @{ */ -#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U #define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 #define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /** @@ -697,7 +697,7 @@ typedef struct /** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source * @{ */ -#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 ((uint32_t)0x00000000U) +#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR @@ -710,7 +710,7 @@ typedef struct /** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source * @{ */ -#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) +#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U #define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL /** * @} @@ -721,7 +721,7 @@ typedef struct /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source * @{ */ -#define RCC_OSPICLKSOURCE_SYSCLK ((uint32_t)0x00000000U) +#define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U #define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 #define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /** @@ -742,13 +742,13 @@ typedef struct /** @defgroup RCCEx_CRS_Status RCCEx CRS Status * @{ */ -#define RCC_CRS_NONE ((uint32_t)0x00000000U) -#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001U) -#define RCC_CRS_SYNCOK ((uint32_t)0x00000002U) -#define RCC_CRS_SYNCWARN ((uint32_t)0x00000004U) -#define RCC_CRS_SYNCERR ((uint32_t)0x00000008U) -#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010U) -#define RCC_CRS_TRIMOVF ((uint32_t)0x00000020U) +#define RCC_CRS_NONE 0x00000000U +#define RCC_CRS_TIMEOUT 0x00000001U +#define RCC_CRS_SYNCOK 0x00000002U +#define RCC_CRS_SYNCWARN 0x00000004U +#define RCC_CRS_SYNCERR 0x00000008U +#define RCC_CRS_SYNCMISS 0x00000010U +#define RCC_CRS_TRIMOVF 0x00000020U /** * @} */ @@ -756,7 +756,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource * @{ */ -#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ /** @@ -766,7 +766,7 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider * @{ */ -#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ @@ -781,8 +781,8 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity * @{ */ -#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */ -#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ /** * @} */ @@ -790,8 +790,8 @@ typedef struct /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault * @{ */ -#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds - to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ +#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ /** * @} */ @@ -799,7 +799,7 @@ typedef struct /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault * @{ */ -#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */ +#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ /** * @} */ @@ -807,7 +807,7 @@ typedef struct /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault * @{ */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency */ /** @@ -817,8 +817,8 @@ typedef struct /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection * @{ */ -#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ -#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ +#define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ /** * @} */ @@ -1341,10 +1341,10 @@ typedef struct */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__)) #else #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @brief Macro to get the SAI1 clock source. @@ -1361,9 +1361,9 @@ typedef struct * */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))) +#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL)) #else -#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))) +#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined(SAI2) @@ -1385,10 +1385,10 @@ typedef struct */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__)) #else #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__)) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @brief Macro to get the SAI2 clock source. @@ -1399,9 +1399,9 @@ typedef struct * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))) +#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL)) #else -#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))) +#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* SAI2 */ @@ -1416,7 +1416,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) /** @brief Macro to get the I2C1 clock source. * @retval The clock source can be one of the following values: @@ -1424,7 +1424,7 @@ typedef struct * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock */ -#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) +#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) #if defined(I2C2) @@ -1438,7 +1438,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) /** @brief Macro to get the I2C2 clock source. * @retval The clock source can be one of the following values: @@ -1446,7 +1446,7 @@ typedef struct * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock */ -#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))) +#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) #endif /* I2C2 */ @@ -1460,7 +1460,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) /** @brief Macro to get the I2C3 clock source. * @retval The clock source can be one of the following values: @@ -1468,7 +1468,7 @@ typedef struct * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock */ -#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))) +#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) #if defined(I2C4) @@ -1482,7 +1482,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) /** @brief Macro to get the I2C4 clock source. * @retval The clock source can be one of the following values: @@ -1490,7 +1490,7 @@ typedef struct * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock */ -#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))) +#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) #endif /* I2C4 */ @@ -1506,7 +1506,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) /** @brief Macro to get the USART1 clock source. * @retval The clock source can be one of the following values: @@ -1515,7 +1515,7 @@ typedef struct * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock */ -#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) +#define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) /** @brief Macro to configure the USART2 clock (USART2CLK). * @@ -1528,7 +1528,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) /** @brief Macro to get the USART2 clock source. * @retval The clock source can be one of the following values: @@ -1537,7 +1537,7 @@ typedef struct * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock */ -#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))) +#define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) #if defined(USART3) @@ -1552,7 +1552,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) /** @brief Macro to get the USART3 clock source. * @retval The clock source can be one of the following values: @@ -1561,7 +1561,7 @@ typedef struct * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock */ -#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))) +#define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) #endif /* USART3 */ @@ -1578,7 +1578,7 @@ typedef struct * @retval None */ #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) /** @brief Macro to get the UART4 clock source. * @retval The clock source can be one of the following values: @@ -1587,7 +1587,7 @@ typedef struct * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock */ -#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))) +#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) #endif /* UART4 */ @@ -1604,7 +1604,7 @@ typedef struct * @retval None */ #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) /** @brief Macro to get the UART5 clock source. * @retval The clock source can be one of the following values: @@ -1613,7 +1613,7 @@ typedef struct * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock */ -#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))) +#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) #endif /* UART5 */ @@ -1628,7 +1628,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) /** @brief Macro to get the LPUART1 clock source. * @retval The clock source can be one of the following values: @@ -1637,7 +1637,7 @@ typedef struct * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock */ -#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))) +#define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). * @@ -1650,7 +1650,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) /** @brief Macro to get the LPTIM1 clock source. * @retval The clock source can be one of the following values: @@ -1659,7 +1659,7 @@ typedef struct * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock */ -#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) +#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). * @@ -1672,7 +1672,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__)) /** @brief Macro to get the LPTIM2 clock source. * @retval The clock source can be one of the following values: @@ -1681,7 +1681,7 @@ typedef struct * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock */ -#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))) +#define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)) #if defined(SDMMC1) @@ -1727,12 +1727,12 @@ typedef struct else \ { \ CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)); \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \ } \ } while(0) #else #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)) #endif /* RCC_CCIPR2_SDMMCSEL */ /** @brief Macro to get the SDMMC1 clock. @@ -1757,10 +1757,10 @@ typedef struct */ #if defined(RCC_CCIPR2_SDMMCSEL) #define __HAL_RCC_GET_SDMMC1_SOURCE() \ - ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))) + ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) #else #define __HAL_RCC_GET_SDMMC1_SOURCE() \ - ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) + (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) #endif /* RCC_CCIPR2_SDMMCSEL */ #endif /* SDMMC1 */ @@ -1783,7 +1783,7 @@ typedef struct * @retval None */ #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) /** @brief Macro to get the RNG clock. * @retval The clock source can be one of the following values: @@ -1797,7 +1797,7 @@ typedef struct * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock */ -#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) +#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) #if defined(USB_OTG_FS) || defined(USB) @@ -1819,7 +1819,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) /** @brief Macro to get the USB clock source. * @retval The clock source can be one of the following values: @@ -1833,7 +1833,7 @@ typedef struct * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock */ -#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) +#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) #endif /* USB_OTG_FS || USB */ @@ -1849,7 +1849,7 @@ typedef struct * @retval None */ #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__)) /** @brief Macro to get the ADC clock source. * @retval The clock source can be one of the following values: @@ -1860,7 +1860,7 @@ typedef struct @endif * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock */ -#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))) +#define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)) #if defined(SWPMI1) @@ -1872,14 +1872,14 @@ typedef struct * @retval None */ #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__)) /** @brief Macro to get the SWPMI1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock */ -#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))) +#define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)) #endif /* SWPMI1 */ @@ -1893,10 +1893,10 @@ typedef struct */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) #else #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /** @brief Macro to get the DFSDM1 clock source. @@ -1905,9 +1905,9 @@ typedef struct * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL))) +#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL)) #else -#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL))) +#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) @@ -1921,7 +1921,7 @@ typedef struct * @retval None */ #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__)) /** @brief Macro to get the DFSDM1 audio clock source. * @retval The clock source can be one of the following values: @@ -1929,7 +1929,7 @@ typedef struct * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock */ -#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL))) +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL)) #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ @@ -1947,7 +1947,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (uint32_t)(__LTDC_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__)) /** @brief Macro to get the LTDC clock source. * @retval The clock source can be one of the following values: @@ -1956,7 +1956,7 @@ typedef struct * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock */ -#define __HAL_RCC_GET_LTDC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR))) +#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)) #endif /* LTDC */ @@ -1970,14 +1970,14 @@ typedef struct * @retval None */ #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__)) /** @brief Macro to get the DSI clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock */ -#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL))) +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL)) #endif /* DSI */ @@ -1992,7 +1992,7 @@ typedef struct * @retval None */ #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__)) /** @brief Macro to get the OctoSPI clock source. * @retval The clock source can be one of the following values: @@ -2000,7 +2000,7 @@ typedef struct * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock */ -#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL))) +#define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL)) #endif /* OCTOSPI1 || OCTOSPI2 */ @@ -2203,7 +2203,7 @@ typedef struct * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt */ /* CRS IT Error Mask */ -#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) +#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ @@ -2247,7 +2247,7 @@ typedef struct */ /* CRS Flag Error Mask */ -#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) +#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h index 12df8c3dc4..9cd91dabba 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h @@ -617,14 +617,14 @@ typedef struct __SAI_HandleTypeDef */ /** @brief Reset SAI handle state. - * @param __HANDLE__: specifies the SAI Handle. + * @param __HANDLE__ specifies the SAI Handle. * @retval None */ #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) /** @brief Enable or disable the specified SAI interrupts. - * @param __HANDLE__: specifies the SAI Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -639,8 +639,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) /** @brief Check whether the specified SAI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SAI Handle. - * @param __INTERRUPT__: specifies the SAI interrupt source to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the SAI interrupt source to check. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -654,8 +654,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SAI flag is set or not. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SAI_FLAG_OVRUDR: Overrun underrun flag. * @arg SAI_FLAG_MUTEDET: Mute detection flag. @@ -669,8 +669,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified SAI pending flag. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun * @arg SAI_FLAG_MUTEDET: Clear Mute detection diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h index 900d204339..9fb6b07edc 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h @@ -396,16 +396,16 @@ typedef struct __SPI_HandleTypeDef */ /** @brief Reset SPI handle state. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) /** @brief Enable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable. + * @param __INTERRUPT__ specifies the interrupt source to enable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -415,9 +415,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) /** @brief Disable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI handle. + * @param __HANDLE__ specifies the SPI handle. * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to disable. + * @param __INTERRUPT__ specifies the interrupt source to disable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -427,9 +427,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) /** @brief Check whether the specified SPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -439,9 +439,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag @@ -457,14 +457,14 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) /** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -477,7 +477,7 @@ typedef struct __SPI_HandleTypeDef } while(0U) /** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -490,7 +490,7 @@ typedef struct __SPI_HandleTypeDef } while(0U) /** @brief Clear the SPI FRE pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -502,14 +502,14 @@ typedef struct __SPI_HandleTypeDef }while(0U) /** @brief Enable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) /** @brief Disable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -525,92 +525,168 @@ typedef struct __SPI_HandleTypeDef */ /** @brief Set the SPI transmit-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) /** @brief Set the SPI receive-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) /** @brief Reset the CRC calculation of the SPI. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ - ((MODE) == SPI_MODE_MASTER)) - -#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ - ((MODE) == SPI_DIRECTION_1LINE)) - -#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) - -#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_1LINE)) +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Mode. + * This parameter can be a value of @ref SPI_Mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ - ((DATASIZE) == SPI_DATASIZE_15BIT) || \ - ((DATASIZE) == SPI_DATASIZE_14BIT) || \ - ((DATASIZE) == SPI_DATASIZE_13BIT) || \ - ((DATASIZE) == SPI_DATASIZE_12BIT) || \ - ((DATASIZE) == SPI_DATASIZE_11BIT) || \ - ((DATASIZE) == SPI_DATASIZE_10BIT) || \ - ((DATASIZE) == SPI_DATASIZE_9BIT) || \ - ((DATASIZE) == SPI_DATASIZE_8BIT) || \ - ((DATASIZE) == SPI_DATASIZE_7BIT) || \ - ((DATASIZE) == SPI_DATASIZE_6BIT) || \ - ((DATASIZE) == SPI_DATASIZE_5BIT) || \ - ((DATASIZE) == SPI_DATASIZE_4BIT)) +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction + * @retval None + */ +#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ - ((CPOL) == SPI_POLARITY_HIGH)) +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ - ((CPHA) == SPI_PHASE_2EDGE)) +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ - ((NSS) == SPI_NSS_HARD_INPUT) || \ - ((NSS) == SPI_NSS_HARD_OUTPUT)) +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__ specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_Data_Size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_4BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) -#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ - ((NSSP) == SPI_NSS_PULSE_DISABLE)) +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__ specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) +/** @brief Checks if SPI Slave Select parameter is in allowed range. + * @param __NSS__ specifies the SPI Slave Slelect management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ - ((BIT) == SPI_FIRSTBIT_LSB)) +/** @brief Checks if SPI NSS Pulse parameter is in allowed range. + * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. + * This parameter can be a value of @ref SPI_NSSP_Mode + * @retval None + */ +#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ + ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) -#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ - ((MODE) == SPI_TIMODE_ENABLE)) +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__ specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) -#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ - ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__ specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) -#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\ - ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_16BIT)) +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__ specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U)) +/** @brief Checks if SPI CRC length is in allowed range. + * @param __LENGTH__ specifies the SPI CRC length. + * This parameter can be a value of @ref SPI_CRC_length + * @retval None + */ +#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\ + ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) -#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL) +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) +/** @brief Checks if DMA handle is valid. + * @param __HANDLE__ specifies a DMA Handle. + * @retval None + */ +#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) /** * @} diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h index b5e10ed759..9b8375ec07 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h @@ -1009,28 +1009,28 @@ typedef struct */ /** @brief Reset TIM handle state. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval None */ #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) /** * @brief Enable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** * @brief Enable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) /** * @brief Disable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ @@ -1046,7 +1046,7 @@ typedef struct /** * @brief Disable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ @@ -1063,15 +1063,15 @@ typedef struct /** * @brief Disable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled unconditionally */ #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) /** @brief Enable the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1087,8 +1087,8 @@ typedef struct /** @brief Disable the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1103,8 +1103,8 @@ typedef struct #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) /** @brief Enable the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -1118,8 +1118,8 @@ typedef struct #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) /** @brief Disable the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -1133,8 +1133,8 @@ typedef struct #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) /** @brief Check whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to check. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1157,8 +1157,8 @@ typedef struct #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) /** @brief Clear the specified TIM interrupt flag. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to clear. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1182,8 +1182,8 @@ typedef struct /** * @brief Check whether the specified TIM interrupt source is enabled or not. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt source to check. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1198,8 +1198,8 @@ typedef struct #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Clear the TIM interrupt pending bits. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1215,7 +1215,7 @@ typedef struct /** * @brief Indicates whether or not the TIM Counter is used as downcounter. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode. @@ -1225,23 +1225,23 @@ mode. /** * @brief Set the TIM Prescaler on runtime. - * @param __HANDLE__: TIM handle. - * @param __PRESC__: specifies the Prescaler new value. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. * @retval None */ #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) /** * @brief Set the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __COUNTER__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Get the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ @@ -1249,8 +1249,8 @@ mode. /** * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __AUTORELOAD__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ @@ -1261,7 +1261,7 @@ mode. /** * @brief Get the TIM Autoreload Register value on runtime. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ @@ -1269,8 +1269,8 @@ mode. /** * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __CKD__: specifies the clock division value. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. * This parameter can be one of the following value: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT @@ -1286,7 +1286,7 @@ mode. /** * @brief Get the TIM Clock Division value on runtime. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval The clock division can be one of the following values: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT @@ -1297,14 +1297,14 @@ mode. /** * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__: specifies the Input Capture4 prescaler new value. + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events @@ -1320,8 +1320,8 @@ mode. /** * @brief Get the TIM Input Capture prescaler on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value * @arg TIM_CHANNEL_2: get input capture 2 prescaler value @@ -1341,8 +1341,8 @@ mode. /** * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1350,7 +1350,7 @@ mode. * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param __COMPARE__: specifies the Capture Compare register new value. + * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ @@ -1363,8 +1363,8 @@ mode. /** * @brief Get the TIM Capture Compare Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channel associated with the capture compare register + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value * @arg TIM_CHANNEL_2: get capture/compare 2 register value @@ -1384,8 +1384,8 @@ mode. /** * @brief Set the TIM Output compare preload. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1405,8 +1405,8 @@ mode. /** * @brief Reset the TIM Output compare preload. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1426,7 +1426,7 @@ mode. /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @note When the USR bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) @@ -1437,7 +1437,7 @@ mode. /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @note When the USR bit of the TIMx_CR1 register is reset, any of the * following events generate an update interrupt or DMA request (if * enabled): @@ -1451,14 +1451,14 @@ mode. /** * @brief Set the TIM Capture x input polarity on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__: Polarity for TIx source + * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge @@ -1523,7 +1523,7 @@ mode. ((__BASE__) == TIM_DMABASE_OR3)) -#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000)) +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ @@ -1574,7 +1574,7 @@ mode. ((__MODE__) == TIM_ENCODERMODE_TI2) || \ ((__MODE__) == TIM_ENCODERMODE_TI12)) -#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000)) +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h index dd238edc3d..be53965b2d 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h @@ -4815,7 +4815,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * not available in differential mode. * @note When configuring a channel 'i' in differential mode, * the channel 'i+1' is not usable separately. - * @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available) + * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available) * are internally fixed to single-ended inputs configuration. * @note For ADC channels configured in differential mode, both inputs * should be biased at (Vref+)/2 +/-200mV. @@ -4825,7 +4825,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * ADC must be ADC disabled. * @note One or several values can be selected. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime + * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_1 @@ -4842,6 +4842,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 * @param SingleDiff This parameter can be a combination of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED @@ -4872,12 +4873,12 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha * not available in differential mode. * @note When configuring a channel 'i' in differential mode, * the channel 'i+1' is not usable separately. - * @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available) + * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available) * are internally fixed to single-ended inputs configuration. * @note One or several values can be selected. In this case, the value * returned is null if all channels are in single ended-mode. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime + * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: * @arg @ref LL_ADC_CHANNEL_1 @@ -4894,6 +4895,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 * @retval 0: channel in single-ended mode, else: channel in differential mode */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h index 79a73405e7..0a5ff00ec5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h @@ -134,7 +134,7 @@ extern "C" { * @param __VALUE__ Value to be written in the register * @retval None */ -#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) +#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__) /** * @brief Read a value in CRC register @@ -352,7 +352,10 @@ __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) */ __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData) { - *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData; + __IO uint16_t *pReg; + + pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); + *pReg = InData; } /** @@ -416,10 +419,11 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx) /** * @brief Return data stored in the Independent Data(IDR) register. - * @note This register can be used as a temporary storage location for one byte. + * @note This register can be used as a temporary storage location. + * @note Refer to the Reference Manual to get the authorized data length in bits. * @rmtoll IDR IDR LL_CRC_Read_IDR * @param CRCx CRC Instance - * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register). + * @retval Value stored in CRC_IDR register */ __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) { @@ -428,15 +432,20 @@ __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) /** * @brief Store data in the Independent Data(IDR) register. - * @note This register can be used as a temporary storage location for one byte. + * @note This register can be used as a temporary storage location. + * @note Refer to the Reference Manual to get the authorized data length in bits. * @rmtoll IDR IDR LL_CRC_Write_IDR * @param CRCx CRC Instance - * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF + * @param InData value to be stored in CRC_IDR register * @retval None */ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) { +#if (CRC_IDR_IDR == 0x0FFU) *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; +#else + WRITE_REG(CRCx->IDR, InData); +#endif } /** * @} diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h index 8e3dae5ed3..4501451d96 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h @@ -2080,6 +2080,16 @@ __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); } +/** + * @brief Check if HSI is enabled in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)); +} + /** * @brief Enable HSI oscillator * @rmtoll CR HSION LL_RCC_HSI_Enable @@ -3850,6 +3860,35 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); } +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + /** * @brief Get Main PLL multiplication factor for VCO * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN @@ -3946,20 +3985,6 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); } -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_NONE - * @arg @ref LL_RCC_PLLSOURCE_MSI - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); -} - /** * @brief Get Division factor for the main PLL and other PLL * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h index b147c20d2d..1f3565961e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h @@ -157,7 +157,7 @@ static const uint8_t SHIFT_TAB_OISx[] = #endif /* DFSDM1_Channel0 */ #define TIMx_OR3_BK2INP TIM1_OR3_BK2INP /*!< BRK2 BKIN2 input polarity */ #define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P /*!< BRK2 COMP1 input polarity */ -#define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P /*!< BRK2 COMP2 input polarity */ +#define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P /*!< BRK2 COMP2 input polarity */ /* Remap mask definitions */ #define TIMx_OR1_RMP_SHIFT 16U @@ -179,16 +179,16 @@ static const uint8_t SHIFT_TAB_OISx[] = #define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ -#define DT_DELAY_1 ((uint8_t)0x7FU) -#define DT_DELAY_2 ((uint8_t)0x3FU) -#define DT_DELAY_3 ((uint8_t)0x1FU) -#define DT_DELAY_4 ((uint8_t)0x1FU) +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ -#define DT_RANGE_1 ((uint8_t)0x00U) -#define DT_RANGE_2 ((uint8_t)0x80U) -#define DT_RANGE_3 ((uint8_t)0xC0U) -#define DT_RANGE_4 ((uint8_t)0xE0U) +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) /** Legacy definitions for compatibility purpose @cond 0 @@ -827,7 +827,7 @@ typedef struct * @{ */ #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ -#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/ +#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/ #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ /** * @} @@ -836,9 +836,9 @@ typedef struct /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode * @{ */ -#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ -#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ -#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */ +#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ +#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */ /** * @} */ @@ -896,14 +896,14 @@ typedef struct /** @defgroup TIM_LL_EC_TS Trigger Selection * @{ */ -#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ -#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ -#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ -#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ -#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ -#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ -#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ -#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ +#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ +#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ +#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ +#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ +#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ +#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ +#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ +#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ /** * @} */ @@ -1338,6 +1338,7 @@ typedef struct /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros * @{ */ + /** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); @@ -1362,9 +1363,9 @@ typedef struct */ #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\ + (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ 0U) /** @@ -1576,6 +1577,9 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * check whether or not the counter mode selection feature is supported * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n * CR1 CMS LL_TIM_SetCounterMode * @param TIMx Timer instance @@ -2518,7 +2522,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch } /** - * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals). + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter @@ -3651,7 +3655,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) * OR3 BK2INE LL_TIM_EnableBreakInputSource\n * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n - * OR3 BK2DF1BK0E LL_TIM_EnableBreakInputSource + * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN @@ -3680,7 +3684,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B * OR3 BK2INE LL_TIM_DisableBreakInputSource\n * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n - * OR3 BK2DF1BK0E LL_TIM_DisableBreakInputSource + * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h index 20bb2cbd72..c88120d090 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h @@ -246,7 +246,7 @@ __STATIC_INLINE uint32_t LL_GetUID_Word2(void) */ __STATIC_INLINE uint32_t LL_GetFlashSize(void) { - return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); } /** @@ -273,7 +273,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) */ __STATIC_INLINE uint32_t LL_GetPackageType(void) { - return (uint8_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); + return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); } /** @@ -287,7 +287,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void) /** * @brief This function configures the Cortex-M SysTick source of the time base. * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * @note When a RTOS is used, it is recommended to avoid changing the SysTick * configuration by calling this function, for a delay use rather osDelay RTOS service. * @param Ticks Number of ticks * @retval None diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html index 6032f348e6..241e2f0aa0 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html @@ -665,7 +665,38 @@

Update History

-

V1.8.1 +

V1.8.2 +/ 22-December-2017

+

Main +Changes

+
  • Maintenance Release of HAL and Low Layer drivers
+

   

HAL Drivers changes

+
  • HAL CAN driver
    • Rework of HAL CAN driver (compatibility break) 
      • A +new HAL CAN driver has been redesigned with new APIs, to bypass +limitations on CAN Tx/Rx FIFO management present with previous HAL CAN +driver version.
      • The +new HAL CAN driver is the recommended version. It is located as usual +in Drivers/STM32L4xx_HAL_Driver/Src and +Drivers/STM32L4xx_HAL_Driver/Inc folders. It can be enabled through +switch HAL_CAN_MODULE_ENABLED in stm32l4xx_hal_conf.h
      • The +legacy HAL CAN +driver is also present in the release in +Drivers/STM32L4xx_HAL_Driver/Src/Legacy and +Drivers/STM32L4xx_HAL_Driver/Inc/Legacy +folders for software compatibility reasons. Its usage is not +recommended as deprecated. It can however be enabled through +switch HAL_CAN_LEGACY_MODULE_ENABLED in +stm32l4xx_hal_conf.h
      • Short migration guide:
        • Fields of CAN_InitTypeDef structure are renamed : 
          • SJW +to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to +TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to +AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to +TransmitFifoPriority
        • HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start()
        • HAL_CAN_Transmit() +is replaced by HAL_CAN_AddTxMessage() to place Tx request, then +HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion
        • HAL_CAN_Transmit_IT() +is replaced by HAL_CAN_ActivateNotification() to enable transmission with interrupt mode, then HAL_CAN_AddTxMessage() to place Tx request
        • HAL_CAN_Receive() +is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until reception, then HAL_CAN_GetRxMessage() to get Rx message
        • HAL_CAN_Receive_IT() +is replaced by HAL_CAN_ActivateNotification() to enable reception with interrupt mode, then HAL_CAN_GetRxMessage() in the receive callback to get Rx message
        • HAL_CAN_Sleep() is renamed to HAL_CAN_RequestSleep()
        • HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback()
        • HAL_CAN_RxCpltCallback() is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback()
      • More complete "how to use the new driver" is detailed in the driver header section itself
  • HAL CORTEX driver
    • HAL_MPU_Enable() and HAL_MPU_Disable() functions moved to stm32l4xx_hal_cortex.c
  • HAL CRC driver
    • Fix GCC warning 
  • HAL FLASH driver
    • HAL_FLASH_Unlock() updated to not return HAL_ERROR if flash is already unlocked 
  • HAL OSPI driver
    • Cleanup IO Manager ports
  • HAL RCC driver
    • RCC_RTCCLKSOURCE_NO_CLK renamed to RCC_RTCCLKSOURCE_NONE
    • HAL_RCC_DeInit() updates
      • Clear of status flags
      • Wait for PLLs disable flags to clear PLLs configuration registers
    • Fix MISRA C-2004 rule 10.6 ('U' suffix)
  • HAL TIM driver
    • Fix MISRA C-2004 rule 10.6 ('U' suffix)

LL Drivers changes

+
  • LL CRC driver
    • Fix GCC warning
  • LL RCC driver
    • Add LL_RCC_PLL_SetMainSource() and LL_RCC_HSI_IsEnabledInStopMode() APIs
    • LL_RCC_DeInit() update
      • Clear of status flags
      • Wait for PLLs disable flags to clear PLLs configuration registers
    • Fix IS_LL_RCC_I2C_CLKSOURCE() assert macro

V1.8.1 / 13-October-2017

Main Changes

diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/Legacy/stm32l4xx_hal_can.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/Legacy/stm32l4xx_hal_can.c new file mode 100644 index 0000000000..7eb3cd6bc5 --- /dev/null +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/Legacy/stm32l4xx_hal_can.c @@ -0,0 +1,1480 @@ +/** + ****************************************************************************** + * @file stm32l4xx_hal_can.c + * @author MCD Application Team + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + @verbatim + ============================================================================== + ##### User NOTE ##### + ============================================================================== + [..] + (#) This HAL CAN driver is deprecated, it contains some CAN Tx/Rx FIFO management limitations. + Another HAL CAN driver version has been designed with new API's, to fix these limitations. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the CAN controller interface clock using + __HAL_RCC_CAN1_CLK_ENABLE() for CAN1. + + (#) CAN pins configuration + (++) Enable the clock for the CAN GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (++) Connect and configure the involved CAN pins using the + following function HAL_GPIO_Init(); + + (#) Initialize and configure the CAN using HAL_CAN_Init() function. + + (#) Transmit the desired CAN frame using HAL_CAN_Transmit() or + HAL_CAN_Transmit_IT() function. + + (#) Receive a CAN frame using HAL_CAN_Receive() or HAL_CAN_Receive_IT() function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the CAN peripheral transmission and wait the end of this operation + using HAL_CAN_Transmit(), at this stage user can specify the value of timeout + according to his end application + (+) Start the CAN peripheral reception and wait the end of this operation + using HAL_CAN_Receive(), at this stage user can specify the value of timeout + according to his end application + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() + (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() + (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine + (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_TxCpltCallback + (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_ErrorCallback + + *** CAN HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in CAN HAL driver. + + (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts + (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts + (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled + (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags + (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status + + [..] + (@) You can refer to the CAN Legacy HAL driver header file for more useful macros + + @endverbatim + + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l4xx_hal.h" + +/** @addtogroup STM32L4xx_HAL_Driver + * @{ + */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED +#ifdef HAL_CAN_MODULE_ENABLED +/* Select HAL CAN module in stm32l4xx_hal_conf.h file: + (#) HAL_CAN_MODULE_ENABLED for new HAL CAN driver fixing FIFO limitations + (#) HAL_CAN_LEGACY_MODULE_ENABLED for legacy HAL CAN driver */ +#error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32l4xx_hal_conf.h file' +#endif /* HAL_CAN_MODULE_ENABLED */ + +#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver' + +#if defined(CAN1) + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TIMEOUT_VALUE 10 +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the CAN. + (+) De-initialize the CAN. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the CAN peripheral according to the specified parameters + * in the CAN_InitStruct structure and initialize the associated handle. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +{ + uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */ + uint32_t tickstart = 0; + + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SJW)); + assert_param(IS_CAN_BS1(hcan->Init.BS1)); + assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + + if(hcan->State == HAL_CAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcan->Lock = HAL_UNLOCKED; + + /* Init the low level hardware */ + HAL_CAN_MspInit(hcan); + } + + /* Initialize the CAN state*/ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Exit from sleep mode */ + hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + hcan->Instance->MCR |= CAN_MCR_INRQ ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Check acknowledge */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + /* Set the time triggered communication mode */ + if (hcan->Init.TTCM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TTCM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (hcan->Init.ABOM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_ABOM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AWUM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_AWUM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (hcan->Init.NART == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_NART; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.RFLM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_RFLM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TXFP == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TXFP; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ + ((uint32_t)hcan->Init.SJW) | \ + ((uint32_t)hcan->Init.BS1) | \ + ((uint32_t)hcan->Init.BS2) | \ + ((uint32_t)hcan->Init.Prescaler - 1); + + /* Request leave initialisation */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Check acknowledged */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + status = CAN_INITSTATUS_SUCCESS; + } + } + + if(status == CAN_INITSTATUS_SUCCESS) + { + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Configure the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) +{ + uint32_t filternbrbitpos = 0; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); + + filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber; + + /* Initialisation mode for the filter */ + CAN1->FMR |= (uint32_t)CAN_FMR_FINIT; + +#if defined(CAN2) + /* Select the start slave bank */ + CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); + CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8); +#endif + + /* Filter Deactivation */ + CAN1->FA1R &= ~(uint32_t)filternbrbitpos; + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + CAN1->FS1R &= ~(uint32_t)filternbrbitpos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + CAN1->FS1R |= filternbrbitpos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1R &= ~(uint32_t)filternbrbitpos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1R |= (uint32_t)filternbrbitpos; + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN1->FFA1R &= ~(uint32_t)filternbrbitpos; + } + + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN1->FFA1R |= (uint32_t)filternbrbitpos; + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) + { + CAN1->FA1R |= filternbrbitpos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the CAN peripheral registers to their default reset values. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +{ + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_CAN_MspDeInit(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the CAN MSP. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the CAN MSP. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Transmit a CAN frame message. + (+) Receive a CAN frame message. + (+) Enter CAN peripheral in sleep mode. + (+) Wake up the CAN peripheral from sleep mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initiate and transmit a CAN frame message. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + /* Process locked */ + __HAL_LOCK(hcan); + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + + /* Select one empty transmit mailbox */ + if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = 0; + } + else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = 1; + } + else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmitmailbox = 2; + } + + if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + { + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if (hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | + ((uint32_t)hcan->pTxMsg->Data[2] << 16) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8) | + ((uint32_t)hcan->pTxMsg->Data[0])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | + ((uint32_t)hcan->pTxMsg->Data[6] << 16) | + ((uint32_t)hcan->pTxMsg->Data[5] << 8) | + ((uint32_t)hcan->pTxMsg->Data[4])); + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check End of transmission flag */ + while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initiate and transmit a CAN frame message in Interrupt mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX)) + { + /* Process Locked */ + __HAL_LOCK(hcan); + + /* Select one empty transmit mailbox */ + if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = 0; + } + else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = 1; + } + else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmitmailbox = 2; + } + + if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + { + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if(hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | + ((uint32_t)hcan->pTxMsg->Data[2] << 16) | + ((uint32_t)hcan->pTxMsg->Data[1] << 8) | + ((uint32_t)hcan->pTxMsg->Data[0])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | + ((uint32_t)hcan->pTxMsg->Data[6] << 16) | + ((uint32_t)hcan->pTxMsg->Data[5] << 8) | + ((uint32_t)hcan->pTxMsg->Data[4])); + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcan); + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + /* - Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME ); + + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + } + } + else + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Receive a correct CAN frame. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber: FIFO number. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Process locked */ + __HAL_LOCK(hcan); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check pending message */ + while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + + /* Get the Id */ + hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (hcan->pRxMsg->IDE == CAN_ID_STD) + { + hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); + hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); + hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); + hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); + hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); + hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); + + /* Release the FIFO */ + if(FIFONumber == CAN_FIFO0) + { + /* Release FIFO0 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + } + else /* FIFONumber == CAN_FIFO1 */ + { + /* Release FIFO1 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Receive a correct CAN frame in Interrupt mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber: FIFO number. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX)) + { + /* Process locked */ + __HAL_LOCK(hcan); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + if(FIFONumber == CAN_FIFO0) + { + /* Enable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + else + { + /* Enable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + } + else + { + return HAL_BUSY; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enter the Sleep (low power) mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Request Sleep mode */ + hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Wake up the CAN peripheral from sleep mode (after that the CAN peripheral + * is in the normal mode). + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Wake up request */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Sleep mode status */ + while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handle CAN interrupt request. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + + /* Check Overrun flag for FIFO0 */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0))) + { + /* Set CAN error code to FOV0 error */ + errorcode |= HAL_CAN_ERROR_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + + /* Check Overrun flag for FIFO1 */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1))) + { + /* Set CAN error code to FOV1 error */ + errorcode |= HAL_CAN_ERROR_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + + /* Check End of transmission flag */ + if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) + { + if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) || + (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) || + (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))) + { + /* Call transmit function */ + CAN_Transmit_IT(hcan); + } + } + + /* Check End of reception flag for FIFO0 */ + if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0)) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO0); + } + + /* Check End of reception flag for FIFO1 */ + if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && + (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0)) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO1); + } + + /* Set error code in handle */ + hcan->ErrorCode |= errorcode; + + /* Check Error Warning Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to EWG error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EWG; + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to EPV error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EPV; + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-Off Flag */ + if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + /* Set CAN error code to BOF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BOF; + /* No need for clear of Bus-Off Flag as read-only */ + } + + /* Check Last error code Flag */ + if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) && + (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + { + switch(hcan->Instance->ESR & CAN_ESR_LEC) + { + case(CAN_ESR_LEC_0): + /* Set CAN error code to STF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_STF; + break; + case(CAN_ESR_LEC_1): + /* Set CAN error code to FOR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_FOR; + break; + case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to ACK error */ + hcan->ErrorCode |= HAL_CAN_ERROR_ACK; + break; + case(CAN_ESR_LEC_2): + /* Set CAN error code to BR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BR; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to BD error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BD; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + hcan->ErrorCode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + hcan->Instance->ESR &= ~(CAN_ESR_LEC); + } + + /* Call the Error call Back in case of Errors */ + if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) + { + /* Clear ERRI bit */ + SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI); + + /* Set the CAN state ready to be able to start again the process */ + hcan->State = HAL_CAN_STATE_READY; + + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + /* - Disable FIFO 0 message pending Interrupt */ + /* - Disable FIFO 0 Overrun Interrupt */ + /* - Disable FIFO 1 message pending Interrupt */ + /* - Disable FIFO 1 Overrun Interrupt */ + /* - Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_FMP0| + CAN_IT_FOV0| + CAN_IT_FMP1| + CAN_IT_FOV1| + CAN_IT_TME ); + + /* Call Error callback function */ + HAL_CAN_ErrorCallback(hcan); + } +} + +/** + * @brief Transmission complete callback in non-blocking mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Reception complete callback in non-blocking mode. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Check the CAN state. + (+) Check CAN Errors detected during interrupt process. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CAN handle state. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +{ + /* Return CAN handle state */ + return hcan->State; +} + +/** + * @brief Return the CAN error code. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +{ + return hcan->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ +/** + * @brief Initiate and transmit a CAN frame message. + * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + /* Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Transmission complete callback */ + HAL_CAN_TxCpltCallback(hcan); + + return HAL_OK; +} + +/** + * @brief Receive a correct CAN frame. + * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber: Specify the FIFO number + * @retval HAL status + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + /* Get the Id */ + hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (hcan->pRxMsg->IDE == CAN_ID_STD) + { + hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); + hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); + hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); + hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); + hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); + hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + + /* Disable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + + /* Disable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + } + + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + { + /* Disable CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + } + + /* Receive complete callback */ + HAL_CAN_RxCpltCallback(hcan); + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* CAN1 */ + +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c index aa8887a89e..92ba628bd0 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c @@ -69,7 +69,7 @@ */ #define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L4xx_HAL_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ -#define __STM32L4xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32L4xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\ |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c index 36431c8df3..e1d039daa1 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c @@ -268,12 +268,6 @@ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ - -#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR |\ - ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\ - ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion - (neither regular nor injected) is on-going */ - /* Delay to wait before setting ADEN once ADCAL has been reset must be at least 4 ADC clock cycles. @@ -286,7 +280,6 @@ #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /*!< ADC enable time-out value */ #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /*!< ADC disable time-out value */ - /* Timeout to wait for current conversion on going to be completed. */ /* Timeout fixed to longest ADC conversion possible, for 1 channel: */ @@ -1554,7 +1547,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) * HAL_ADCEx_MultiModeStart_DMA() function must be used. * @param hadc ADC handle * @param pData Destination Buffer address. - * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes) + * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c index 3277b4c2c4..b3d24b0a43 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c @@ -81,13 +81,6 @@ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */ -#define ADC_CFGR2_INJ_FIELDS ((uint32_t)(ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR |\ - ADC_CFGR2_OVSS )) /*!< ADC_CFGR2 injected oversampling parameters that can be updated - when no conversion is on-going (neither regular nor injected) */ - -#define ADC_OFR_INJ_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN)) /*!< ADC_OFR fields of parameters that can be updated when no conversion - (neither regular nor injected) is on-going */ - /* Fixed timeout value for ADC calibration. */ /* Values defined to be higher than worst cases: low clock frequency, */ /* maximum prescalers. */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c index 35ce172ba7..d628cef4cc 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c @@ -3,71 +3,130 @@ * @file stm32l4xx_hal_can.c * @author MCD Application Team * @brief CAN HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Controller Area Network (CAN) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions * + Peripheral State and Error functions * @verbatim - ============================================================================== + ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] - (#) Enable the CAN controller interface clock using - __HAL_RCC_CAN1_CLK_ENABLE() for CAN1. - - (#) CAN pins configuration - (++) Enable the clock for the CAN GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (++) Connect and configure the involved CAN pins using the - following function HAL_GPIO_Init(); - - (#) Initialize and configure the CAN using HAL_CAN_Init() function. - - (#) Transmit the desired CAN frame using HAL_CAN_Transmit() or - HAL_CAN_Transmit_IT() function. - - (#) Receive a CAN frame using HAL_CAN_Receive() or HAL_CAN_Receive_IT() function. - - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the CAN peripheral transmission and wait the end of this operation - using HAL_CAN_Transmit(), at this stage user can specify the value of timeout - according to his end application - (+) Start the CAN peripheral reception and wait the end of this operation - using HAL_CAN_Receive(), at this stage user can specify the value of timeout - according to his end application - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() - (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() - (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine - (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_TxCpltCallback - (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_ErrorCallback - - *** CAN HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in CAN HAL driver. - - (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts - (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts - (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled - (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags - (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status - - [..] - (@) You can refer to the CAN HAL driver header file for more useful macros - + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function open-drain + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. + + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be trigged by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. + @endverbatim - ****************************************************************************** * @attention * @@ -105,1150 +164,1679 @@ * @{ */ +#if defined(CAN1) + /** @defgroup CAN CAN * @brief CAN driver modules * @{ - */ - -#ifdef HAL_CAN_MODULE_ENABLED - + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TIMEOUT_VALUE 10 +#define CAN_TIMEOUT_VALUE 10U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); -/** - * @} - */ - /* Exported functions --------------------------------------------------------*/ /** @defgroup CAN_Exported_Functions CAN Exported Functions * @{ */ -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the CAN. - (+) De-initialize the CAN. - + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + @endverbatim * @{ */ - + /** - * @brief Initialize the CAN peripheral according to the specified parameters - * in the CAN_InitStruct structure and initialize the associated handle. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { - uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */ - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); assert_param(IS_CAN_MODE(hcan->Init.Mode)); - assert_param(IS_CAN_SJW(hcan->Init.SJW)); - assert_param(IS_CAN_BS1(hcan->Init.BS1)); - assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - - if(hcan->State == HAL_CAN_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcan->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); } - - /* Initialize the CAN state*/ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Exit from sleep mode */ - hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - /* Request initialisation */ - hcan->Instance->MCR |= CAN_MCR_INRQ ; + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Check acknowledge */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) { - /* Set the time triggered communication mode */ - if (hcan->Init.TTCM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TTCM; - } - else + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Set the automatic bus-off management */ - if (hcan->Init.ABOM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_ABOM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Set the automatic wake-up mode */ - if (hcan->Init.AWUM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_AWUM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; + return HAL_ERROR; } + } - /* Set the no automatic retransmission */ - if (hcan->Init.NART == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_NART; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; - } + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Set the receive FIFO locked mode */ - if (hcan->Init.RFLM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_RFLM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } + /* Get tick */ + tickstart = HAL_GetTick(); - /* Set the transmit FIFO priority */ - if (hcan->Init.TXFP == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TXFP; - } - else + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ - ((uint32_t)hcan->Init.SJW) | \ - ((uint32_t)hcan->Init.BS1) | \ - ((uint32_t)hcan->Init.BS2) | \ - ((uint32_t)hcan->Init.Prescaler - 1); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Request leave initialisation */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Check acknowledged */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - status = CAN_INITSTATUS_SUCCESS; + return HAL_ERROR; } } - - if(status == CAN_INITSTATUS_SUCCESS) + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) { - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } else { - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Return function status */ - return HAL_ERROR; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } -} - -/** - * @brief Configure the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that - * contains the filter configuration information. - * @retval None - */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) -{ - uint32_t filternbrbitpos = 0; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); - assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); - - filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= (uint32_t)CAN_FMR_FINIT; - -#if defined(CAN2) - /* Select the start slave bank */ - CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); - CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8); -#endif - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filternbrbitpos; - /* Filter Scale */ - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + else { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filternbrbitpos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + else { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filternbrbitpos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } - /* Filter Mode */ - if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + else { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); } - /* Filter FIFO assignment */ - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + else { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); } - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } - - /* Filter activation */ - if (sFilterConfig->FilterActivation == ENABLE) + else { - CAN1->FA1R |= filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT); - + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + /* Return function status */ return HAL_OK; } /** - * @brief DeInitialize the CAN peripheral registers to their default reset values. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) { /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* DeInit the low level hardware */ + + /* Stop the CAN module */ + HAL_CAN_Stop(hcan); + + /* DeInit the low level hardware: CLOCK, NVIC */ HAL_CAN_MspDeInit(hcan); - + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + /* Change CAN state */ hcan->State = HAL_CAN_STATE_RESET; - /* Release Lock */ - __HAL_UNLOCK(hcan); - /* Return function status */ return HAL_OK; } /** - * @brief Initialize the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Initializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspInit could be implemented in the user file - */ + */ } /** - * @brief DeInitialize the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief DeInitializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspDeInit could be implemented in the user file - */ + */ } + /** * @} */ -/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. * -@verbatim +@verbatim ============================================================================== - ##### IO operation functions ##### + ##### Configuration functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Transmit a CAN frame message. - (+) Receive a CAN frame message. - (+) Enter CAN peripheral in sleep mode. - (+) Wake up the CAN peripheral from sleep mode. - + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + @endverbatim * @{ */ /** - * @brief Initiate and transmit a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param Timeout: Timeout duration. - * @retval HAL status + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None */ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - uint32_t tickstart = 0; + uint32_t filternbrbitpos = 0U; + CAN_TypeDef *can_ip = hcan->Instance; - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - - /* Select one empty transmit mailbox */ - if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - transmitmailbox = 0; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = 1; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmitmailbox = 2; - } + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + +#if defined(CAN2) + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); +#else + /* CAN1 is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); +#endif - if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX) - { - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if (hcan->pTxMsg->IDE == CAN_ID_STD) + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + +#if defined(CAN2) + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + +#endif + /* Convert filter number into bit position */ + filternbrbitpos = (1U) << sFilterConfig->FilterBank; + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ - hcan->pTxMsg->RTR); + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); } - else + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8) | - ((uint32_t)hcan->pTxMsg->Data[4])); - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check End of transmission flag */ - while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); } - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) + { + SET_BIT(can_ip->FA1R, filternbrbitpos); } - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + /* Return function status */ return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Return function status */ return HAL_ERROR; } } /** - * @brief Initiate and transmit a CAN frame message in Interrupt mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + +@endverbatim + * @{ + */ + +/** + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + uint32_t tickstart = 0U; - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX)) + if (hcan->State == HAL_CAN_STATE_READY) { - /* Process Locked */ - __HAL_LOCK(hcan); - - /* Select one empty transmit mailbox */ - if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = 0; - } - else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = 1; - } - else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmitmailbox = 2; - } + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; + + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET) { - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if(hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \ - hcan->pTxMsg->RTR); - } - else + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | - ((uint32_t)hcan->pTxMsg->Data[2] << 16) | - ((uint32_t)hcan->pTxMsg->Data[1] << 8) | - ((uint32_t)hcan->pTxMsg->Data[0])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | - ((uint32_t)hcan->pTxMsg->Data[6] << 16) | - ((uint32_t)hcan->pTxMsg->Data[5] << 8) | - ((uint32_t)hcan->pTxMsg->Data[4])); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hcan); - - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - /* - Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME ); - - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; } + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Return function status */ + return HAL_OK; } else { - return HAL_BUSY; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + + return HAL_ERROR; } - - return HAL_OK; } /** - * @brief Receive a correct CAN frame. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: FIFO number. - * @param Timeout: Timeout duration. + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check pending message */ - while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0) + uint32_t tickstart = 0U; + + if (hcan->State == HAL_CAN_STATE_LISTENING) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; } } - } - - /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) - { - hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; } else { - hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + + return HAL_ERROR; } - - hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); - hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); - hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); - hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); - hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); - hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); - - /* Release the FIFO */ - if(FIFONumber == CAN_FIFO0) +} + +/** + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Release FIFO0 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; } - else /* FIFONumber == CAN_FIFO1 */ + else { - /* Release FIFO1 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + /* Return function status */ + return HAL_ERROR; } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) +} + +/** + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + uint32_t timeout = 1000000U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do + { + /* Check if timeout is reached */ + if (++count > timeout) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET); + + /* Return function status */ + return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + status = 1U; + } } - - /* Process unlocked */ - __HAL_UNLOCK(hcan); /* Return function status */ - return HAL_OK; + return status; } /** - * @brief Receive a correct CAN frame in Interrupt mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: FIFO number. + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) { + uint32_t transmitmailbox; + /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX)) + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) { - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) + assert_param(IS_CAN_STDID(pHeader->StdId)); + } + else + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + /* Select an empty transmit mailbox */ + transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Store the Tx mailbox */ + *pTxMailbox = 1U << transmitmailbox; + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - if(FIFONumber == CAN_FIFO0) + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET) { - /* Enable FIFO 0 overrun and message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); } - else + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET) + { + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + } + + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET) { - /* Enable FIFO 1 overrun and message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); } - + + /* Return function status */ + return HAL_OK; } else { - return HAL_BUSY; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; } - - /* Return function status */ - return HAL_OK; } /** - * @brief Enter the Sleep (low power) mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @retval HAL status. + * @retval Number of free Tx Mailboxes. */ -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) { - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Request Sleep mode */ - hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + uint32_t freelevel = 0U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) + { + freelevel++; + } - /* Return function status */ - return HAL_ERROR; + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) + { + freelevel++; + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET) + { + freelevel++; + } } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + status = 1U; } } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; + + /* Return status */ + return status; } /** - * @brief Wake up the CAN peripheral from sleep mode (after that the CAN peripheral - * is in the normal mode). - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @retval HAL status. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. */ -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) { - uint32_t tickstart = 0; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Wake up request */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + uint32_t timestamp = 0U; + uint32_t transmitmailbox; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Select the Tx mailbox */ + transmitmailbox = POSITION_VAL(TxMailbox); + + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; + } + + /* Return the timestamp */ + return timestamp; +} - /* Sleep mode status */ - while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos; + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos; + aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos; + aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos; + aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos; + aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos; + aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos; + aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos; + aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos; + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + } + + /* Return function status */ + return HAL_OK; } - if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + else { - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. + */ +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) +{ + uint32_t filllevel = 0U; + + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + if (RxFifo == CAN_RX_FIFO0) + { + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ + { + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; + } + } + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) +{ + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + return HAL_ERROR; } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; } /** - * @brief Handle CAN interrupt request. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) { uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET) + { + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != RESET) + { + /* Transmission Mailbox 0 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); + } + } + } - /* Check Overrun flag for FIFO0 */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0))) + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != RESET) + { + /* Transmission Mailbox 1 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + + if ((tsrflags & CAN_TSR_TXOK2) != RESET) + { + /* Transmission Mailbox 2 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); + } + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET) { - /* Set CAN error code to FOV0 error */ - errorcode |= HAL_CAN_ERROR_FOV0; + if ((rf0rflags & CAN_RF0R_FOVR0) != RESET) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; - /* Clear FIFO0 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } } - /* Check Overrun flag for FIFO1 */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1))) + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET) { - /* Set CAN error code to FOV1 error */ - errorcode |= HAL_CAN_ERROR_FOV1; + if ((rf0rflags & CAN_RF0R_FULL0) != RESET) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); - /* Clear FIFO1 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + /* Receive FIFO 0 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); + } } - /* Check End of transmission flag */ - if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET) { - if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) || - (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) || - (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))) + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET) { - /* Call transmit function */ - CAN_Transmit_IT(hcan); + /* Receive FIFO 0 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); } } - - /* Check End of reception flag for FIFO0 */ - if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0)) + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET) { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO0); + if ((rf1rflags & CAN_RF1R_FOVR1) != RESET) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } } - - /* Check End of reception flag for FIFO1 */ - if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0)) + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET) { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO1); + if ((rf1rflags & CAN_RF1R_FULL1) != RESET) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); + } } - - /* Set error code in handle */ - hcan->ErrorCode |= errorcode; - - /* Check Error Warning Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET) { - /* Set CAN error code to EWG error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EWG; - /* No need for clear of Error Warning Flag as read-only */ + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET) + { + /* Receive FIFO 1 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); + } } - - /* Check Error Passive Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != RESET) { - /* Set CAN error code to EPV error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EPV; - /* No need for clear of Error Passive Flag as read-only */ + if ((msrflags & CAN_MSR_SLAKI) != RESET) + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); + } } - - /* Check Bus-Off Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != RESET) { - /* Set CAN error code to BOF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BOF; - /* No need for clear of Bus-Off Flag as read-only */ + if ((msrflags & CAN_MSR_WKUI) != RESET) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + + /* WakeUp Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); + } } - - /* Check Last error code Flag */ - if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != RESET) { - switch(hcan->Instance->ESR & CAN_ESR_LEC) + if ((msrflags & CAN_MSR_ERRI) != RESET) { - case(CAN_ESR_LEC_0): - /* Set CAN error code to STF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_STF; - break; - case(CAN_ESR_LEC_1): - /* Set CAN error code to FOR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_FOR; - break; - case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): - /* Set CAN error code to ACK error */ - hcan->ErrorCode |= HAL_CAN_ERROR_ACK; - break; - case(CAN_ESR_LEC_2): - /* Set CAN error code to BR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BR; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): - /* Set CAN error code to BD error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BD; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): - /* Set CAN error code to CRC error */ - hcan->ErrorCode |= HAL_CAN_ERROR_CRC; - break; - default: - break; + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) && + ((esrflags & CAN_ESR_EWGF) != RESET)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) && + ((esrflags & CAN_ESR_EPVF) != RESET)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != RESET) && + ((esrflags & CAN_ESR_BOFF) != RESET)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) && + ((esrflags & CAN_ESR_LEC) != RESET)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } } - /* Clear Last error code Flag */ - hcan->Instance->ESR &= ~(CAN_ESR_LEC); + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); } /* Call the Error call Back in case of Errors */ - if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) + if (errorcode != HAL_CAN_ERROR_NONE) { - /* Clear ERRI bit */ - SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI); - - /* Set the CAN state ready to be able to start again the process */ - hcan->State = HAL_CAN_STATE_READY; + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - /* - Disable FIFO 0 message pending Interrupt */ - /* - Disable FIFO 0 Overrun Interrupt */ - /* - Disable FIFO 1 message pending Interrupt */ - /* - Disable FIFO 1 Overrun Interrupt */ - /* - Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_FMP0| - CAN_IT_FOV0| - CAN_IT_FMP1| - CAN_IT_FOV1| - CAN_IT_TME ); - /* Call Error callback function */ + /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); - } + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback + +@endverbatim + * @{ + */ + +/** + * @brief Transmission Mailbox 0 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ } /** - * @brief Transmission complete callback in non-blocking mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CAN_TxCpltCallback could be implemented in the user file + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file */ } /** - * @brief Reception complete callback in non-blocking mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CAN_RxCpltCallback could be implemented in the user file + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Sleep callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + +/** + * @brief WakeUp from Rx message callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file */ } /** * @brief Error CAN callback. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -1257,7 +1845,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ } @@ -1266,192 +1854,110 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) * @} */ -/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral State and Error functions ##### ============================================================================== [..] This subsection provides functions allowing to : - (+) Check the CAN state. - (+) Check CAN Errors detected during interrupt process. - + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + @endverbatim * @{ */ /** - * @brief Return the CAN handle state. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return the CAN state. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL state */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) { - /* Return CAN handle state */ - return hcan->State; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + } + + /* Return CAN state */ + return state; } /** * @brief Return the CAN error code. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval CAN Error Code */ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) { + /* Return CAN error code */ return hcan->ErrorCode; } /** - * @} - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ -/** - * @brief Initiate and transmit a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Reset the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) { - /* Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + HAL_StatusTypeDef status = HAL_OK; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + /* Reset CAN error code */ + hcan->ErrorCode = 0U; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + status = HAL_ERROR; } - - /* Transmission complete callback */ - HAL_CAN_TxCpltCallback(hcan); - - return HAL_OK; + + /* Return the status */ + return status; } /** - * @brief Receive a correct CAN frame. - * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number - * @retval HAL status + * @} */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) -{ - /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) - { - hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); - hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); - hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); - hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); - hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); - hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - - /* Disable FIFO 0 overrun and message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - - /* Disable FIFO 1 overrun and message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Disable CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - } - - /* Receive complete callback */ - HAL_CAN_RxCpltCallback(hcan); - /* Return function status */ - return HAL_OK; -} /** - * @} - */ + * @} + */ #endif /* HAL_CAN_MODULE_ENABLED */ + /** * @} */ +#endif /* CAN1 */ + /** * @} */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c index 46e379feaf..be93803abc 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c @@ -335,6 +335,9 @@ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPre */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); } @@ -350,6 +353,9 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Return 1 if pending else 0 */ return NVIC_GetPendingIRQ(IRQn); } @@ -363,6 +369,9 @@ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); } @@ -424,6 +433,46 @@ __weak void HAL_SYSTICK_Callback(void) } #if (__MPU_PRESENT == 1) +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0U; +} + +/** + * @brief Enable the MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged accessto the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU settings take effects */ + __DSB(); + __ISB(); +} + /** * @brief Initialize and configure the Region and the memory to be protected. * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c index 932d07fdf8..bc77a5efb0 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l4xx_hal_crc.c * @author MCD Application Team - * @brief CRC HAL module driver. - * This file provides firmware functions to manage the following + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following * functionalities of the CRC peripheral: * + Initialization and de-initialization functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim =============================================================================== ##### How to use this driver ##### @@ -20,11 +20,11 @@ (++) specify initialization value (IP default or non-default one) (++) specify input data format (++) specify input or output data inversion mode if any - (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the - input data buffer starting with the previously computed CRC as + (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the + input data buffer starting with the previously computed CRC as initialization value - (+) Use HAL_CRC_Calculate() function to compute the CRC value of the - input data buffer starting with the defined initialization value + (+) Use HAL_CRC_Calculate() function to compute the CRC value of the + input data buffer starting with the defined initialization value (default or non-default) to initiate CRC calculation @endverbatim @@ -92,20 +92,20 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 * @{ */ -/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initialize the CRC according to the specified parameters + (+) Initialize the CRC according to the specified parameters in the CRC_InitTypeDef and create the associated handle (+) DeInitialize the CRC peripheral (+) Initialize the CRC MSP (MCU Specific Package) (+) DeInitialize the CRC MSP - + @endverbatim * @{ */ @@ -123,28 +123,28 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if(hcrc->State == HAL_CRC_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); } - - hcrc->State = HAL_CRC_STATE_BUSY; - - /* check whether or not non-default generating polynomial has been + + hcrc->State = HAL_CRC_STATE_BUSY; + + /* check whether or not non-default generating polynomial has been * picked up by user */ - assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); + assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) { /* initialize IP with default generating polynomial */ - WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); + WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); } else @@ -155,67 +155,67 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) return HAL_ERROR; } } - - /* check whether or not non-default CRC initial value has been + + /* check whether or not non-default CRC initial value has been * picked up by user */ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) { - WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); + WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); } else { WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); } - + /* set input data inversion mode */ - assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); - + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); + /* set output data inversion mode */ - assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); - + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); + /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; - + /* Return function status */ return HAL_OK; } /** - * @brief DeInitialize the CRC peripheral. + * @brief DeInitialize the CRC peripheral. * @param hcrc: CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) -{ +{ /* Check the CRC handle allocation */ if(hcrc == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); - + /* Check the CRC peripheral state */ if(hcrc->State == HAL_CRC_STATE_BUSY) { return HAL_BUSY; } - + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; - + /* Reset CRC calculation unit */ __HAL_CRC_DR_RESET(hcrc); - + /* Reset IDR register content */ CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ; @@ -266,19 +266,19 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) * @} */ -/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions. +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions. * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer using the combination of the previous CRC value and the new one - + [..] or - + (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer independently of the previous CRC value. @@ -286,35 +286,35 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) * @{ */ -/** +/** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with the previously computed CRC as initialization value. * @param hcrc: CRC handle * @param pBuffer: pointer to the input data buffer, exact input data format is - * provided by hcrc->InputDataFormat. + * provided by hcrc->InputDataFormat. * @param BufferLength: input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the - * handle field hcrc->InputDataFormat. + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index = 0; /* CRC input data buffer index */ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ - + /* Process locked */ - __HAL_LOCK(hcrc); - - /* Change CRC peripheral state */ + __HAL_LOCK(hcrc); + + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; - + switch (hcrc->InputDataFormat) { - case CRC_INPUTDATA_FORMAT_WORDS: + case CRC_INPUTDATA_FORMAT_WORDS: /* Enter Data to the CRC calculator */ for(index = 0; index < BufferLength; index++) { @@ -322,63 +322,63 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ } temp = hcrc->Instance->DR; break; - - case CRC_INPUTDATA_FORMAT_BYTES: + + case CRC_INPUTDATA_FORMAT_BYTES: temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); break; - - case CRC_INPUTDATA_FORMAT_HALFWORDS: + + case CRC_INPUTDATA_FORMAT_HALFWORDS: temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); break; - + default: - break; + break; } - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + /* Process unlocked */ __HAL_UNLOCK(hcrc); - - /* Return the CRC computed value */ + + /* Return the CRC computed value */ return temp; } -/** +/** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with hcrc->Instance->INIT as initialization value. * @param hcrc: CRC handle * @param pBuffer: pointer to the input data buffer, exact input data format is - * provided by hcrc->InputDataFormat. + * provided by hcrc->InputDataFormat. * @param BufferLength: input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the - * handle field hcrc->InputDataFormat. + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ + */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index = 0; /* CRC input data buffer index */ uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ - + /* Process locked */ - __HAL_LOCK(hcrc); - - /* Change CRC peripheral state */ + __HAL_LOCK(hcrc); + + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; - - /* Reset CRC Calculation Unit (hcrc->Instance->INIT is + + /* Reset CRC Calculation Unit (hcrc->Instance->INIT is * written in hcrc->Instance->DR) */ __HAL_CRC_DR_RESET(hcrc); - + switch (hcrc->InputDataFormat) { - case CRC_INPUTDATA_FORMAT_WORDS: + case CRC_INPUTDATA_FORMAT_WORDS: /* Enter 32-bit input data to the CRC calculator */ for(index = 0; index < BufferLength; index++) { @@ -386,28 +386,28 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t } temp = hcrc->Instance->DR; break; - - case CRC_INPUTDATA_FORMAT_BYTES: + + case CRC_INPUTDATA_FORMAT_BYTES: /* Specific 8-bit input data handling */ temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength); break; - - case CRC_INPUTDATA_FORMAT_HALFWORDS: + + case CRC_INPUTDATA_FORMAT_HALFWORDS: /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength); break; - + default: - break; + break; } - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + /* Process unlocked */ __HAL_UNLOCK(hcrc); - - /* Return the CRC computed value */ + + /* Return the CRC computed value */ return temp; } @@ -416,12 +416,12 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t */ /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. + * @brief Peripheral State functions. * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] This subsection permits to get in run-time the status of the peripheral. @@ -452,9 +452,9 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) * @{ */ -/** +/** * @brief Enter 8-bit input data to the CRC calculator. - * Specific data handling to optimize processing time. + * Specific data handling to optimize processing time. * @param hcrc: CRC handle * @param pBuffer: pointer to the input data buffer * @param BufferLength: input data buffer length @@ -463,63 +463,72 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { uint32_t i = 0; /* input data buffer index */ - + uint16_t data; + __IO uint16_t *pReg; + /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the IP */ for(i = 0; i < (BufferLength/4); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3]; + hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3]; } /* last bytes specific handling */ if ((BufferLength%4) != 0) { if (BufferLength%4 == 1) { - *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i]; + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4*i]; } if (BufferLength%4 == 2) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; + data = (uint16_t)(pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + *pReg = data; } if (BufferLength%4 == 3) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; - *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; + data = (uint16_t)(pBuffer[4*i]<<8) | (uint16_t)pBuffer[4*i+1]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + *pReg = data; + + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4*i+2]; } } - - /* Return the CRC computed value */ + + /* Return the CRC computed value */ return hcrc->Instance->DR; } -/** +/** * @brief Enter 16-bit input data to the CRC calculator. - * Specific data handling to optimize processing time. + * Specific data handling to optimize processing time. * @param hcrc: CRC handle * @param pBuffer: pointer to the input data buffer * @param BufferLength: input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ + */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { uint32_t i = 0; /* input data buffer index */ - + __IO uint16_t *pReg; + /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, - * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure + * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the IP */ for(i = 0; i < (BufferLength/2); i++) { - hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1]; + hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1]; } if ((BufferLength%2) != 0) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); + *pReg = pBuffer[2*i]; } - - /* Return the CRC computed value */ + + /* Return the CRC computed value */ return hcrc->Instance->DR; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c index 991c59d32e..3ec430f2a7 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c @@ -504,18 +504,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { + HAL_StatusTypeDef status = HAL_OK; + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); WRITE_REG(FLASH->KEYR, FLASH_KEY2); - } - else - { - return HAL_ERROR; + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } } - return HAL_OK; + return status; } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c index 31536b6ed0..73aa95a0e4 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c @@ -85,12 +85,12 @@ * @{ */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define MSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define HSI48_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */ +#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define MSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ /** * @} */ @@ -104,7 +104,7 @@ #define MCO1_PIN GPIO_PIN_8 #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ - (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__))) + (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__))) /** * @} */ @@ -144,11 +144,11 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); [..] Internal/external clock and PLL configuration (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through the PLL as System clock source. - + (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ. It can be used to generate the clock for the USB OTG FS (48 MHz). - The number of flash wait states is automatically adjusted when MSI range is updated with - HAL_RCC_OscConfig() and the MSI is used as System clock source. + The number of flash wait states is automatically adjusted when MSI range is updated with + HAL_RCC_OscConfig() and the MSI is used as System clock source. (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC clock source. @@ -206,19 +206,19 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz - to work correctly, while the SDMMC1 and RNG peripherals require a frequency + to work correctly, while the SDMMC1 and RNG peripherals require a frequency equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1 - through PLLQ divider. You have to enable the peripheral clock and use + through PLLQ divider. You have to enable the peripheral clock and use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) IWDG clock which is always the LSI clock. - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz. + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz. The clock source frequency should be adapted depending on the device voltage range as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter. @endverbatim - + Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices +--------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | @@ -267,28 +267,63 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO1 OFF * - All interrupts disabled + * - All interrupt and reset flags cleared * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks - * @retval None + * @retval HAL status */ -void HAL_RCC_DeInit(void) +HAL_StatusTypeDef HAL_RCC_DeInit(void) { + uint32_t tickstart = 0; + /* Set MSION bit */ SET_BIT(RCC->CR, RCC_CR_MSION); /* Insure MSIRDY bit is set before writing default MSIRANGE value */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) { __NOP(); } - + /* Get start tick */ + tickstart = HAL_GetTick(); + + /* Wait till MSI is ready */ + while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Set MSIRANGE default value */ MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6); - + /* Reset CFGR register (MSI is selected as system clock source) */ CLEAR_REG(RCC->CFGR); + /* Update the SystemCoreClock global variable for MSI as system clock source */ + SystemCoreClock = MSI_VALUE; + + /* Configure the source of time base considering new system clock settings */ + if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + + /* Insure MSI selected as system clock source */ + /* Get start tick */ + tickstart = HAL_GetTick(); + + /* Wait till system clock source is ready */ + while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */ #if defined(RCC_PLLSAI2_SUPPORT) - + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON); #else @@ -296,7 +331,27 @@ void HAL_RCC_DeInit(void) CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON); #endif /* RCC_PLLSAI2_SUPPORT */ - + + /* Insure PLLRDY, PLLSAI1RDY and PLLSAI2RDY (if present) are reset */ + /* Get start tick */ + tickstart = HAL_GetTick(); + +#if defined(RCC_PLLSAI2_SUPPORT) + + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) + +#else + + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) + +#endif + { + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset PLLCFGR register */ CLEAR_REG(RCC->PLLCFGR); SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 ); @@ -306,11 +361,11 @@ void HAL_RCC_DeInit(void) SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N_4 ); #if defined(RCC_PLLSAI2_SUPPORT) - + /* Reset PLLSAI2CFGR register */ CLEAR_REG(RCC->PLLSAI2CFGR); SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N_4 ); - + #endif /* RCC_PLLSAI2_SUPPORT */ /* Reset HSEBYP bit */ @@ -319,8 +374,13 @@ void HAL_RCC_DeInit(void) /* Disable all interrupts */ CLEAR_REG(RCC->CIER); - /* Update the SystemCoreClock global variable */ - SystemCoreClock = MSI_VALUE; + /* Clear all interrupt flags */ + WRITE_REG(RCC->CICR, 0xFFFFFFFFU); + + /* Clear all reset flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + return HAL_OK; } /** @@ -392,12 +452,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) { return HAL_ERROR; - } + } } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; - + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); } @@ -453,7 +513,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) { if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) @@ -504,7 +564,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) { @@ -608,7 +668,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { FlagStatus pwrclkchanged = RESET; - + /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); @@ -619,12 +679,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } - + if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); - + /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); @@ -788,14 +848,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Disable all PLL outputs to save power if no PLLs on */ if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) #if defined(RCC_PLLSAI2_SUPPORT) - && + && (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) #endif /* RCC_PLLSAI2_SUPPORT */ ) - { + { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); } - + #if defined(RCC_PLLSAI2_SUPPORT) __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK); #else @@ -857,7 +917,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * the MSI frequency is set to its default value 4 MHz. * * @note The HSI can be selected as system clock source after - * from STOP modes or in case of failure of the HSE used directly or indirectly + * from STOP modes or in case of failure of the HSE used directly or indirectly * as system clock (if the Clock Security System CSS is enabled). * * @note A switch from one clock source to another occurs only if the target @@ -891,14 +951,14 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) + if(FLatency > READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) { return HAL_ERROR; } @@ -921,9 +981,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ /* Compute target PLL output frequency */ pllfreq = RCC_GetSysClockFreqFromPLLSource(); - + /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ - if((pllfreq > 80000000U) && + if((pllfreq > 80000000U) && (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)) || ((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)))) @@ -965,7 +1025,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ pllfreq = HAL_RCC_GetSysClockFreq(); - + /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ if(pllfreq > 80000000U) { @@ -973,7 +1033,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui hpre = RCC_SYSCLK_DIV2; } #endif - + } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); @@ -1025,7 +1085,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } } } - + /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { @@ -1044,19 +1104,19 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui #endif /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) + if(FLatency < READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) { return HAL_ERROR; } } - + /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { @@ -1072,7 +1132,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); @@ -1084,7 +1144,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @} */ -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions * @brief RCC clocks control functions * @verbatim @@ -1093,7 +1153,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui =============================================================================== [..] This subsection provides a set of functions allowing to: - + (+) Ouput clock to MCO pin. (+) Retrieve current clock frequencies. (+) Enable the Clock Security System. @@ -1198,11 +1258,11 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /* Get SYSCLK source */ if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) { /* MSISRANGE from RCC_CSR applies */ - msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; + msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; } else { /* MSIRANGE from RCC_CR applies */ - msirange = (RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; + msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; } /*MSI frequency range in HZ*/ msirange = MSIRangeTable[msirange]; @@ -1231,25 +1291,25 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ default: - pllvco = (msirange / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllvco = (msirange / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; } - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; + pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; sysclockfreq = pllvco/pllr; } @@ -1278,7 +1338,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); } /** @@ -1290,7 +1350,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); } /** @@ -1315,11 +1375,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) #endif /* RCC_HSI48_SUPPORT */ /* Get the HSE configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; } - else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON) { RCC_OscInitStruct->HSEState = RCC_HSE_ON; } @@ -1329,7 +1389,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Get the MSI configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION) + if(READ_BIT(RCC->CR, RCC_CR_MSION) == RCC_CR_MSION) { RCC_OscInitStruct->MSIState = RCC_MSI_ON; } @@ -1338,11 +1398,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->MSIState = RCC_MSI_OFF; } - RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos); - RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_CR_MSIRANGE) ); + RCC_OscInitStruct->MSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos; + RCC_OscInitStruct->MSIClockRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE); /* Get the HSI configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION) { RCC_OscInitStruct->HSIState = RCC_HSI_ON; } @@ -1351,14 +1411,14 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); + RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos; /* Get the LSE configuration -----------------------------------------------*/ - if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; } - else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { RCC_OscInitStruct->LSEState = RCC_LSE_ON; } @@ -1368,7 +1428,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Get the LSI configuration -----------------------------------------------*/ - if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION) { RCC_OscInitStruct->LSIState = RCC_LSI_ON; } @@ -1379,7 +1439,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) #if defined(RCC_HSI48_SUPPORT) /* Get the HSI48 configuration ---------------------------------------------*/ - if((RCC->CRRCR & RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) + if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) { RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; } @@ -1392,7 +1452,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) #endif /* RCC_HSI48_SUPPORT */ /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; } @@ -1400,15 +1460,15 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; } - RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U); - RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); - RCC_OscInitStruct->PLL.PLLR = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U); + RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); + RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U); #if defined(RCC_PLLP_DIV_2_31_SUPPORT) - RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos); + RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; #else - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) != RESET) + if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) { RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17; } @@ -1437,19 +1497,19 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW); /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE); /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1); /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); + RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U); /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + *pFLatency = READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY); } /** @@ -1509,7 +1569,7 @@ __weak void HAL_RCC_CSSCallback(void) * @{ */ /** - * @brief Update number of Flash wait states in line with MSI range and current + * @brief Update number of Flash wait states in line with MSI range and current voltage range. * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11 * @retval HAL status @@ -1518,7 +1578,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) { uint32_t vos = 0; uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ - + if(__HAL_RCC_PWR_IS_CLK_ENABLED()) { vos = HAL_PWREx_GetVoltageRange(); @@ -1529,7 +1589,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) vos = HAL_PWREx_GetVoltageRange(); __HAL_RCC_PWR_CLK_DISABLE(); } - + if(vos == PWR_REGULATOR_VOLTAGE_SCALE1) { if(msirange > RCC_MSIRANGE_8) @@ -1578,7 +1638,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) /* MSI 16Mhz */ latency = FLASH_LATENCY_2; /* 2WS */ } - else if(msirange == RCC_MSIRANGE_7) + else if(msirange == RCC_MSIRANGE_7) { /* MSI 8Mhz */ latency = FLASH_LATENCY_1; /* 1WS */ @@ -1587,16 +1647,16 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) } #endif } - + __HAL_FLASH_SET_LATENCY(latency); - + /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != latency) + if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != latency) { return HAL_ERROR; } - + return HAL_OK; } @@ -1615,11 +1675,11 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void) /* Get MSI range source */ if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) { /* MSISRANGE from RCC_CSR applies */ - msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; + msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; } else { /* MSIRANGE from RCC_CR applies */ - msirange = (RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; + msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; } /*MSI frequency range in HZ*/ msirange = MSIRangeTable[msirange]; @@ -1628,26 +1688,26 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void) /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ default: - pllvco = (msirange / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllvco = (msirange / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; } - - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; + + pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; sysclockfreq = pllvco/pllr; return sysclockfreq; diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c index ee5043a886..14c6f7279e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c @@ -58,9 +58,9 @@ /** @defgroup RCCEx_Private_Constants RCCEx Private Constants * @{ */ -#define PLLSAI1_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define PLLSAI2_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ +#define PLLSAI1_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLLSAI2_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define DIVIDER_P_UPDATE 0U #define DIVIDER_Q_UPDATE 1U @@ -342,7 +342,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - while((PWR->CR1 & PWR_CR1_DBP) == RESET) + while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == RESET) { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { @@ -356,7 +356,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); - if((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != PeriphClkInit->RTCClockSelection)) + if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); @@ -907,16 +907,16 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLLSAI1.PLLSAI1Source = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos); + PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos; #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - PeriphClkInit->PLLSAI1.PLLSAI1M = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U; + PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U; #else - PeriphClkInit->PLLSAI1.PLLSAI1M = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; + PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - PeriphClkInit->PLLSAI1.PLLSAI1N = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos); - PeriphClkInit->PLLSAI1.PLLSAI1P = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U; - PeriphClkInit->PLLSAI1.PLLSAI1Q = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)+1U) * 2U; - PeriphClkInit->PLLSAI1.PLLSAI1R = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos)+1U) * 2U; + PeriphClkInit->PLLSAI1.PLLSAI1N = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; + PeriphClkInit->PLLSAI1.PLLSAI1P = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U; + PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U; + PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U; #if defined(RCC_PLLSAI2_SUPPORT) @@ -924,16 +924,16 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source; #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - PeriphClkInit->PLLSAI2.PLLSAI2M = (uint32_t)((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U; + PeriphClkInit->PLLSAI2.PLLSAI2M = (READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U; #else PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M; #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - PeriphClkInit->PLLSAI2.PLLSAI2N = (uint32_t)((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos); - PeriphClkInit->PLLSAI2.PLLSAI2P = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U; + PeriphClkInit->PLLSAI2.PLLSAI2N = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; + PeriphClkInit->PLLSAI2.PLLSAI2P = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U; #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) - PeriphClkInit->PLLSAI2.PLLSAI2Q = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2Q) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)+1U) * 2U; + PeriphClkInit->PLLSAI2.PLLSAI2Q = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) * 2U; #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ - PeriphClkInit->PLLSAI2.PLLSAI2R = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos)+1U) * 2U; + PeriphClkInit->PLLSAI2.PLLSAI2R = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) * 2U; #endif /* RCC_PLLSAI2_SUPPORT */ @@ -1148,7 +1148,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) { - frequency = HSE_VALUE / 32; + frequency = HSE_VALUE / 32U; } /* Clock not enabled for RTC*/ else @@ -2698,16 +2698,16 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo assert_param(pSynchroInfo != NULL); /* Get the reload value */ - pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); /* Get HSI48 oscillator smooth trimming */ - pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); + pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); /* Get Frequency error capture */ - pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); + pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); /* Get Frequency error direction */ - pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); + pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); } /** diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c index b01f765d26..d48a0b855d 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c @@ -126,8 +126,6 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection)); #endif /* defined(RNG_CR_CED) */ - __HAL_LOCK(hrng); - if(hrng->State == HAL_RNG_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -151,8 +149,6 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; - __HAL_UNLOCK(hrng); - /* Return function status */ return HAL_OK; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c index 56c75be164..6966858816 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c @@ -280,12 +280,12 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); * @brief Initialize the structure FrameInit, SlotInit and the low part of * Init according to the specified parameters and call the function * HAL_SAI_Init to initialize the SAI block. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol @ref SAI_Protocol - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize + * @param protocol one of the supported protocol @ref SAI_Protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * the configuration information for SAI module. - * @param nbslot: Number of slot. + * @param nbslot Number of slot. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) @@ -323,7 +323,7 @@ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protoco /** * @brief Initialize the SAI according to the specified parameters. * in the SAI_InitTypeDef structure and initialize the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -623,7 +623,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) /** * @brief DeInitialize the SAI peripheral. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -676,7 +676,7 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) /** * @brief Initialize the SAI MSP. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -692,7 +692,7 @@ __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) /** * @brief DeInitialize the SAI MSP. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -754,11 +754,11 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) /** * @brief Transmit an amount of data in blocking mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout) @@ -854,11 +854,11 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint /** * @brief Receive an amount of data in blocking mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -952,10 +952,10 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -1014,10 +1014,10 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -1074,7 +1074,7 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui /** * @brief Pause the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1094,7 +1094,7 @@ HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) /** * @brief Resume the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1121,7 +1121,7 @@ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) /** * @brief Stop the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1166,7 +1166,7 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /** * @brief Abort the current transfer and disable the SAI. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1219,10 +1219,10 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /** * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -1306,10 +1306,10 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -1376,9 +1376,9 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Enable the Tx mute mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param val: value sent during the mute @ref SAI_Block_Mute_Value + * @param val value sent during the mute @ref SAI_Block_Mute_Value * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val) @@ -1396,7 +1396,7 @@ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val /** * @brief Disable the Tx mute mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1412,10 +1412,10 @@ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Enable the Rx mute detection. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param callback: function called when the mute is detected. - * @param counter: number a data before mute detection max 63. + * @param callback function called when the mute is detected. + * @param counter number a data before mute detection max 63. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter) @@ -1437,7 +1437,7 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback /** * @brief Disable the Rx mute detection. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1456,7 +1456,7 @@ HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Handle SAI interrupt request. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1632,7 +1632,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1648,7 +1648,7 @@ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer Half completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1664,7 +1664,7 @@ __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1680,7 +1680,7 @@ __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer half completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1696,7 +1696,7 @@ __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief SAI error callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1732,7 +1732,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) /** * @brief Return the SAI handle state. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL state */ @@ -1743,7 +1743,7 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) /** * @brief Return the SAI error code. -* @param hsai: pointer to a SAI_HandleTypeDef structure that contains +* @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for the specified SAI Block. * @retval SAI Error Code */ @@ -1767,12 +1767,12 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) /** * @brief Initialize the SAI I2S protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol. - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize + * @param protocol one of the supported protocol. + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * the configuration information for SAI module. - * @param nbslot: number of slot minimum value is 2 and max is 16. + * @param nbslot number of slot minimum value is 2 and max is 16. * the value must be a multiple of 2. * @retval HAL status */ @@ -1862,11 +1862,11 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, /** * @brief Initialize the SAI PCM protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize - * @param nbslot: number of slot minimum value is 1 and the max is 16. + * @param protocol one of the supported protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize + * @param nbslot number of slot minimum value is 1 and the max is 16. * @retval HAL status */ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) @@ -1932,7 +1932,7 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, /** * @brief Fill the fifo. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1961,9 +1961,9 @@ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) /** * @brief Return the interrupt flag to set according the SAI setup. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param mode: SAI_MODE_DMA or SAI_MODE_IT + * @param mode SAI_MODE_DMA or SAI_MODE_IT * @retval the list of the IT flag to enable */ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) @@ -1995,7 +1995,7 @@ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) /** * @brief Disable the SAI and wait for the disabling. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2021,7 +2021,7 @@ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2045,7 +2045,7 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2070,7 +2070,7 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2095,7 +2095,7 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) /** * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2121,7 +2121,7 @@ static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) /** * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2147,7 +2147,7 @@ static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) } /** * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2174,7 +2174,7 @@ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) /** * @brief DMA SAI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2199,7 +2199,7 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI transmit process half complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2212,7 +2212,7 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2235,7 +2235,7 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2247,7 +2247,7 @@ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) } /** * @brief DMA SAI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2276,7 +2276,7 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI Abort callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c index 2fbbee699a..3ef20a7feb 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c @@ -83,8 +83,8 @@ /** * @brief Configure PDM microphone delays. - * @param hsai: SAI handle. - * @param pdmMicDelay: Microphone delays configuration. + * @param hsai SAI handle. + * @param pdmMicDelay Microphone delays configuration. * @retval HAL status */ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c index 98310fa57f..d147f18e26 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c @@ -33,7 +33,7 @@ (+++) Enable the DMAx clock (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel - (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle + (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS @@ -52,17 +52,15 @@ the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks [..] Master Receive mode restriction: - (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or + (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI does not initiate a new transfer the following procedure has to be respected: (##) HAL_SPI_DeInit() (##) HAL_SPI_Init() [..] - The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI - modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the - maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on - the APBx peripheral clock frequency (fPCLK) used by the SPI instance. - + Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. @endverbatim @@ -265,7 +263,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ /** * @brief Initialize the SPI according to the specified parameters * in the SPI_InitTypeDef and initialize the associated handle. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -364,7 +362,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) } #endif /* USE_SPI_CRC */ - /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */ + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth); @@ -390,7 +388,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI peripheral. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -424,7 +422,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /** * @brief Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -440,7 +438,7 @@ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -493,11 +491,11 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) /** * @brief Transmit an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -505,7 +503,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint uint32_t tickstart = 0U; HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -673,11 +670,11 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /** * @brief Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -688,7 +685,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 uint32_t tickstart = 0U; HAL_StatusTypeDef errorcode = HAL_OK; - if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -741,12 +737,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Set the Rx Fifo threshold */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthresold according the reception data length: 16bit */ + /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8bit */ + /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -904,12 +900,12 @@ error : /** * @brief Transmit and Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received - * @param Timeout: Timeout duration + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, @@ -924,7 +920,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD uint32_t txallowed = 1U; HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -980,12 +975,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Set the Rx Fifo threshold */ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U)) { - /* set fiforxthreshold according the reception data length: 16bit */ + /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthreshold according the reception data length: 8bit */ + /* Set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -1065,7 +1060,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { - /* check TXE flag */ + /* Check TXE flag */ if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) { if (hspi->TxXferCount > 1U) @@ -1106,7 +1101,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->RxXferCount -= 2U; if (hspi->RxXferCount <= 1U) { - /* set fiforxthresold before to switch on 8 bit data size */ + /* Set RX Fifo threshold before to switch on 8 bit data size */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } } @@ -1180,13 +1175,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - } - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { errorcode = HAL_ERROR; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; } error : @@ -1197,17 +1188,16 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1281,17 +1271,16 @@ error : /** * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1330,13 +1319,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Check the data size to adapt Rx threshold and the set the function for IT treatment */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* Set fiforxthresold according the reception data length: 16 bit */ + /* Set RX Fifo threshold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_16BIT; } else { - /* Set fiforxthresold according the reception data length: 8 bit */ + /* Set RX Fifo threshold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_8BIT; } @@ -1386,11 +1375,11 @@ error : /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) @@ -1398,7 +1387,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p uint32_t tmp = 0U, tmp1 = 0U; HAL_StatusTypeDef errorcode = HAL_OK; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1468,12 +1456,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Check if packing mode is enabled and if there is more than 2 data to receive */ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U)) { - /* Set fiforxthresold according the reception data length: 16 bit */ + /* Set RX Fifo threshold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* Set fiforxthresold according the reception data length: 8 bit */ + /* Set RX Fifo threshold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -1495,17 +1483,17 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - /* check tx dma handle */ + /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); /* Check Direction parameter */ @@ -1608,25 +1596,25 @@ error : /** * @brief Receive an amount of data in non-blocking mode with DMA. * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer + * @param pData pointer to data buffer * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; - /* check rx dma handle */ + /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; - /* check tx dma handle */ + /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ @@ -1679,17 +1667,17 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* Set fiforxthresold according the reception data length: 16bit */ + /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* Set fiforxthresold according the reception data length: 8bit */ + /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - /* set fiforxthresold according the reception data length: 16bit */ + /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if ((hspi->RxXferCount & 0x1U) == 0x0U) @@ -1741,12 +1729,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, @@ -1755,7 +1743,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * uint32_t tmp = 0U, tmp1 = 0U; HAL_StatusTypeDef errorcode = HAL_OK; - /* check rx & tx dma handles */ + /* Check rx & tx dma handles */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); @@ -1807,8 +1795,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } #endif /* USE_SPI_CRC */ - - /* Reset the threshold bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); @@ -1820,7 +1806,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } else { - /* Set fiforxthresold according the reception data length: 8bit */ + /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) @@ -1839,7 +1825,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - /* Set fiforxthresold according the reception data length: 16bit */ + /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if ((hspi->RxXferCount & 0x1U) == 0x0U) @@ -2262,7 +2248,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /** * @brief Pause the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2282,7 +2268,7 @@ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) /** * @brief Resume the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2301,8 +2287,8 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) } /** - * @brief Stop the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Stop the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2333,7 +2319,7 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) /** * @brief Handle SPI interrupt request. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval None */ @@ -2428,8 +2414,8 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) } /** - * @brief Tx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Tx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2444,8 +2430,8 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2460,8 +2446,8 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Tx and Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Tx and Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2476,8 +2462,8 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Tx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Tx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2492,8 +2478,8 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Rx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Rx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2508,8 +2494,8 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief Tx and Rx Half Transfer callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Tx and Rx Half Transfer callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2524,8 +2510,8 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) } /** - * @brief SPI error callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief SPI error callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2578,7 +2564,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI handle state. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI state */ @@ -2590,7 +2576,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI error code. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI error code in bitmap format */ @@ -2614,8 +2600,8 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ /** - * @brief DMA SPI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA SPI transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2661,8 +2647,8 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA SPI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA SPI receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2753,7 +2739,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2838,7 +2824,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2851,7 +2837,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2864,7 +2850,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2877,7 +2863,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -3035,7 +3021,7 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3049,7 +3035,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) hspi->RxXferCount -= 2U; if (hspi->RxXferCount == 1U) { - /* set fiforxthresold according the reception data length: 8bit */ + /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } } @@ -3060,7 +3046,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) hspi->RxXferCount--; } - /* check end of the reception */ + /* Check end of the reception */ if (hspi->RxXferCount == 0U) { #if (USE_SPI_CRC != 0U) @@ -3085,7 +3071,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3101,7 +3087,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) hspi->CRCSize--; - /* check end of the reception */ + /* Check end of the reception */ if (hspi->CRCSize == 0U) { /* Disable RXNE and ERR interrupt */ @@ -3117,7 +3103,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3137,7 +3123,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) hspi->TxXferCount--; } - /* check the end of the transmission */ + /* Check the end of the transmission */ if (hspi->TxXferCount == 0U) { #if (USE_SPI_CRC != 0U) @@ -3163,7 +3149,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3197,7 +3183,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3221,7 +3207,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3259,7 +3245,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 8-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3284,7 +3270,7 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the receive 8-bit in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3317,7 +3303,7 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3340,7 +3326,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3373,7 +3359,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 8-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3397,7 +3383,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 16-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3422,13 +3408,13 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) } /** - * @brief Handle SPI Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Handle SPI Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Flag: SPI flag to check - * @param State: flag state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, @@ -3474,13 +3460,13 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, } /** - * @brief Handle SPI FIFO Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Handle SPI FIFO Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Fifo: Fifo to check - * @param State: Fifo state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Fifo Fifo to check + * @param State Fifo state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, @@ -3536,10 +3522,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, /** * @brief Handle the check of the RX transaction complete. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) @@ -3573,9 +3559,9 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t /** * @brief Handle the check of the RXTX or TX transaction complete. - * @param hspi: SPI handle - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param hspi SPI handle + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) @@ -3586,6 +3572,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } + /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) { @@ -3599,12 +3586,13 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } + return HAL_OK; } /** * @brief Handle the end of the RXTX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3661,7 +3649,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the RX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3703,7 +3691,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the TX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3742,7 +3730,7 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Rx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3786,7 +3774,7 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Tx or Rx/Tx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c index a3b7400ebd..8ec6570b0f 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c @@ -63,7 +63,7 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions * @{ @@ -88,8 +88,8 @@ */ /** - * @brief Flush the RX fifo. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @brief Flush the RX fifo. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c index bf6e038394..81368159df 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c @@ -190,7 +190,11 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM Base handle + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) @@ -230,7 +234,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitialize the TIM Base peripheral - * @param htim: TIM Base handle + * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) @@ -257,7 +261,7 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Base MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) @@ -272,7 +276,7 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Base MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) @@ -288,7 +292,7 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) @@ -311,7 +315,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) @@ -334,7 +338,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) @@ -354,7 +358,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) @@ -373,9 +377,9 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in DMA mode. - * @param htim : TIM handle - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to peripheral. + * @param htim TIM handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -419,7 +423,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /** * @brief Stops the TIM Base generation in DMA mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) @@ -468,7 +472,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM Output Compare handle + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) @@ -508,7 +516,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) /** * @brief DeInitialize the TIM peripheral - * @param htim: TIM Output Compare handle + * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) @@ -535,7 +543,7 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) @@ -550,7 +558,7 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Output Compare MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) @@ -565,8 +573,8 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -599,8 +607,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -633,8 +641,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM OC handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -701,8 +709,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -769,8 +777,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -778,8 +786,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -890,8 +898,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -987,7 +995,11 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM handle + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) @@ -1027,7 +1039,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitialize the TIM peripheral - * @param htim: TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) @@ -1054,7 +1066,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM PWM MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) @@ -1069,7 +1081,7 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM PWM MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) @@ -1084,8 +1096,8 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1118,8 +1130,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the PWM signal generation. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1155,8 +1167,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1221,8 +1233,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1287,15 +1299,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1406,8 +1418,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1501,7 +1513,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM Input Capture handle + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) @@ -1541,7 +1557,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitialize the TIM peripheral - * @param htim: TIM Input Capture handle + * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) @@ -1568,7 +1584,7 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM INput Capture MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) @@ -1583,7 +1599,7 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Input Capture MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) @@ -1598,8 +1614,8 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Input Capture measurement. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1624,8 +1640,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Input Capture measurement. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1650,8 +1666,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1709,8 +1725,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim : TIM handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1769,15 +1785,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement on in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1884,8 +1900,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in DMA mode. - * @param htim : TIM Input Capture handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1973,8 +1989,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @param htim: TIM OnePulse handle - * @param OnePulseMode: Select the One pulse mode. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @param htim TIM OnePulse handle + * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. @@ -2024,7 +2044,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /** * @brief DeInitialize the TIM One Pulse - * @param htim: TIM One Pulse handle + * @param htim TIM One Pulse handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) @@ -2051,7 +2071,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM One Pulse MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) @@ -2066,7 +2086,7 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM One Pulse MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) @@ -2081,8 +2101,8 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2117,8 +2137,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be disable + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2153,8 +2173,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2195,8 +2215,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2261,8 +2281,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ /** * @brief Initializes the TIM Encoder Interface and initialize the associated handle. - * @param htim: TIM Encoder Interface handle - * @param sConfig: TIM Encoder Interface configuration structure + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) @@ -2355,7 +2379,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /** * @brief DeInitialize the TIM Encoder interface - * @param htim: TIM Encoder handle + * @param htim TIM Encoder handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) @@ -2382,7 +2406,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Encoder Interface MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) @@ -2397,7 +2421,7 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Encoder Interface MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) @@ -2412,8 +2436,8 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2456,8 +2480,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM Encoder Interface. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2502,8 +2526,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2552,8 +2576,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be disabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2603,15 +2627,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1: The destination Buffer address for IC1. - * @param pData2: The destination Buffer address for IC2. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) @@ -2723,8 +2747,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /** * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim : TIM Encoder Interface handle - * @param Channel : TIM Channels to be enabled + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2790,7 +2814,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ /** * @brief This function handles TIM interrupts requests. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) @@ -2946,9 +2970,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM Output Compare handle - * @param sConfig: TIM Output Compare configuration structure - * @param Channel : TIM Channels to configure + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3048,9 +3072,9 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. - * @param htim: TIM IC handle - * @param sConfig: TIM Input Capture configuration structure - * @param Channel : TIM Channels to be enabled + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3145,9 +3169,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM PWM handle - * @param sConfig: TIM PWM configuration structure - * @param Channel : TIM Channels to be configured + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3290,13 +3314,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim: TIM One Pulse handle - * @param sConfig: TIM One Pulse configuration structure - * @param OutputChannel : TIM Channels to be enabled + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel : TIM Channels to be enabled + * @param InputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3404,8 +3428,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim: TIM handle - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3426,7 +3450,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources + * @param BurstRequestSrc TIM DMA Request sources * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3435,8 +3459,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. * @retval HAL status */ @@ -3567,8 +3591,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM DMA Burst mode - * @param htim: TIM handle - * @param BurstRequestSrc: TIM DMA Request sources to disable + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3627,8 +3651,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim: TIM handle - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3649,7 +3673,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources + * @param BurstRequestSrc TIM DMA Request sources * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3658,8 +3682,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. * @retval HAL status */ @@ -3791,8 +3815,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Stop the DMA burst reading - * @param htim: TIM handle - * @param BurstRequestSrc: TIM DMA Request sources to disable. + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3851,8 +3875,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu /** * @brief Generate a software event - * @param htim: TIM handle - * @param EventSource: specifies the event source. + * @param htim TIM handle + * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source @@ -3892,10 +3916,10 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS /** * @brief Configures the OCRef clear feature - * @param htim: TIM handle - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 @@ -4061,8 +4085,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /** * @brief Configures the clock source to be used - * @param htim: TIM handle - * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ @@ -4237,8 +4261,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim: TIM handle. - * @param TI1_Selection: Indicate whether or not channel 1 is connected to the + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input @@ -4271,8 +4295,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S /** * @brief Configures the TIM in Slave mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4306,8 +4330,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI /** * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4342,8 +4366,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, /** * @brief Read the captured value from Capture Compare unit - * @param htim: TIM handle. - * @param Channel : TIM Channels to be enabled + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -4435,7 +4459,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Period elapsed callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) @@ -4450,7 +4474,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Output Compare callback in non-blocking mode - * @param htim : TIM OC handle + * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) @@ -4464,7 +4488,7 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Input Capture callback in non-blocking mode - * @param htim : TIM IC handle + * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) @@ -4479,7 +4503,7 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) /** * @brief PWM Pulse finished callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) @@ -4494,7 +4518,7 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Trigger detection callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) @@ -4509,7 +4533,7 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) /** * @brief Timer error callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) @@ -4543,7 +4567,7 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Base handle state. - * @param htim: TIM Base handle + * @param htim TIM Base handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) @@ -4553,7 +4577,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM OC handle state. - * @param htim: TIM Ouput Compare handle + * @param htim TIM Ouput Compare handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) @@ -4563,7 +4587,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM PWM handle state. - * @param htim: TIM handle + * @param htim TIM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) @@ -4573,7 +4597,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Input Capture handle state. - * @param htim: TIM IC handle + * @param htim TIM IC handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) @@ -4583,7 +4607,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM One Pulse Mode handle state. - * @param htim: TIM OPM handle + * @param htim TIM OPM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) @@ -4593,7 +4617,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Encoder Mode handle state. - * @param htim: TIM Encoder handle + * @param htim TIM Encoder handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) @@ -4607,7 +4631,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA error callback - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMAError(DMA_HandleTypeDef *hdma) @@ -4621,7 +4645,7 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Delay Pulse complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) @@ -4653,7 +4677,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) } /** * @brief TIM DMA Capture complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) @@ -4686,7 +4710,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Period Elapse complete callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) @@ -4700,7 +4724,7 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Trigger callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) @@ -4714,8 +4738,8 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) /** * @brief Time Base configuration - * @param TIMx: TIM peripheral - * @param Structure: TIM Base configuration structure + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) @@ -4764,7 +4788,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Time Ouput Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4838,7 +4862,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4914,7 +4938,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4988,7 +5012,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Ouput Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -5046,7 +5070,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Ouput Compare 5 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, @@ -5099,7 +5123,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, /** * @brief Timer Ouput Compare 6 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The ouput configuration structure + * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, @@ -5277,17 +5301,17 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 @@ -5332,12 +5356,12 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5367,17 +5391,17 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 @@ -5415,12 +5439,12 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5450,17 +5474,17 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 @@ -5498,17 +5522,17 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be @@ -5546,7 +5570,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral - * @param InputTriggerSource: The Input Trigger source. + * @param InputTriggerSource The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 @@ -5574,17 +5598,17 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. + * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ @@ -5608,7 +5632,7 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c index 150f980c43..6f332d1441 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c @@ -148,8 +148,8 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. - * @param htim: TIM Encoder Interface handle - * @param sConfig: TIM Hall Sensor configuration structure + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) @@ -228,7 +228,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen /** * @brief DeInitialize the TIM Hall Sensor interface - * @param htim: TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) @@ -255,7 +255,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Hall Sensor MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) @@ -270,7 +270,7 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitialize TIM Hall Sensor MSP. - * @param htim: TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) @@ -285,7 +285,7 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) @@ -306,7 +306,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall sensor Interface. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) @@ -327,7 +327,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim : TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) @@ -351,7 +351,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) @@ -375,9 +375,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim : TIM Hall Sensor handle - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param htim TIM Hall Sensor handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -424,7 +424,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim : TIM handle + * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) @@ -474,8 +474,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -503,8 +503,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -532,8 +532,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim : TIM OC handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -598,8 +598,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -670,14 +670,14 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -786,8 +786,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim : TIM Output Compare handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -885,8 +885,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Starts the PWM signal generation on the complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -913,8 +913,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation on the complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -942,8 +942,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1008,8 +1008,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1081,14 +1081,14 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output - * @param htim : TIM handle - * @param Channel : TIM Channel to be enabled + * @param htim TIM handle + * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1197,8 +1197,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output - * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param htim TIM handle + * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1285,8 +1285,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1310,8 +1310,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be disabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1339,8 +1339,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be enabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1370,8 +1370,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim : TIM One Pulse handle - * @param OutputChannel : TIM Channel to be disabled + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1434,15 +1434,15 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1483,15 +1483,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1536,15 +1536,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim: TIM handle - * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource : the Commutation Event source + * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1588,8 +1588,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM in master mode. - * @param htim: TIM handle. - * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status @@ -1650,8 +1650,8 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). - * @param htim: TIM handle - * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @retval HAL status */ @@ -1711,12 +1711,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, /** * @brief Configures the break input source. - * @param htim: TIM handle. - * @param BreakInput: Break input to configure + * @param htim TIM handle. + * @param BreakInput Break input to configure * This parameter can be one of the following values: * @arg TIM_BREAKINPUT_BRK: Timer break input * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input - * @param sBreakInputConfig: Break input source configuration + * @param sBreakInputConfig Break input source configuration * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, @@ -1869,7 +1869,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, /** * @brief Configures the TIMx Remapping input capabilities. - * @param htim: TIM handle. + * @param htim TIM handle. * @param Remap: specifies the TIM remapping source. * @if STM32L486xx @@ -2072,8 +2072,8 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) /** * @brief Group channel 5 and channel 1, 2 or 3 - * @param htim: TIM handle. - * @param Channels: specifies the reference signal(s) the OC5REF is combined with. + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. * This parameter can be any combination of the following values: * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF @@ -2127,7 +2127,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Hall commutation changed callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) @@ -2142,7 +2142,7 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Break detection callback in non-blocking mode - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) @@ -2176,7 +2176,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Hall Sensor interface handle state. - * @param htim: TIM Hall Sensor handle + * @param htim TIM Hall Sensor handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) @@ -2190,7 +2190,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA Commutation callback. - * @param hdma : pointer to DMA handle. + * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) @@ -2205,12 +2205,12 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 - * @param ChannelNState: specifies the TIM Channel CCxNE bit new state. + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c index ab63845237..d8b0a8484c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c @@ -61,23 +61,23 @@ /** @addtogroup LPTIM_LL_Private_Macros * @{ */ -#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ - || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) - -#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) - -#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) - -#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) +#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ + || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) + +#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) + +#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ + || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) + +#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ + || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) /** * @} */ @@ -167,10 +167,10 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_In { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); - assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); - assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); - assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); + assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); + assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); + assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); + assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); /* Set CKSEL bitfield according to ClockSource value */ /* Set PRESC bitfield according to Prescaler value */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c index dc1f6e76a7..528875fea5 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c @@ -78,19 +78,24 @@ #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)) -#if defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL) +#if defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) && defined(RCC_CCIPR2_I2C4SEL) +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)) +#elif defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) -#elif !defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL) +#elif !defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) #else #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) -#endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL */ +#endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL && RCC_CCIPR2_I2C4SEL */ #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)) @@ -186,7 +191,7 @@ uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void); * @brief Reset the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - MSI ON and used as system clock source - * - HSE, HSI, PLL and PLLSAIxSource OFF + * - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO OFF * - All interrupts disabled @@ -207,11 +212,11 @@ ErrorStatus LL_RCC_DeInit(void) /* Insure MSIRDY bit is set before writing default MSIRANGE value */ while (LL_RCC_MSI_IsReady() == 0U) { - __NOP(); } /* Set MSIRANGE default value */ LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6); + /* Set MSITRIM bits to the reset value*/ LL_RCC_MSI_SetCalibTrimming(0); @@ -223,7 +228,7 @@ ErrorStatus LL_RCC_DeInit(void) vl_mask = 0xFFFFFFFFU; - /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLSYSON bits */ + /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON bits */ CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_PLLON)); @@ -238,6 +243,18 @@ ErrorStatus LL_RCC_DeInit(void) /* Write new mask in CR register */ LL_RCC_WriteReg(CR, vl_mask); +#if defined(RCC_PLLSAI2_SUPPORT) + /* Wait for PLLRDY, PLLSAI1RDY and PLLSAI2RDY bits to be reset */ + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) + { + } +#else + /* Wait for PLLRDY, PLLSAI1RDY bits to be reset */ + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) + { + } +#endif + /* Reset PLLCFGR register */ LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); @@ -255,6 +272,21 @@ ErrorStatus LL_RCC_DeInit(void) /* Disable all interrupts */ LL_RCC_WriteReg(CIER, 0x00000000U); + /* Clear all interrupt flags */ + vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \ + RCC_CICR_PLLSAI1RDYC | RCC_CICR_CSSC | RCC_CICR_LSECSSC; +#if defined(RCC_HSI48_SUPPORT) + vl_mask |= RCC_CICR_HSI48RDYC; +#endif +#if defined(RCC_PLLSAI2_SUPPORT) + vl_mask |= RCC_CICR_PLLSAI2RDYC; +#endif + + LL_RCC_WriteReg(CICR, vl_mask); + + /* Clear reset flags */ + LL_RCC_ClearResetFlags(); + return SUCCESS; } diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c index cb748dbb3d..a45451abcd 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c @@ -170,24 +170,24 @@ || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) + || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) @@ -321,11 +321,11 @@ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) { /* Set the default configuration */ - TIM_InitStruct->Prescaler = (uint16_t)0x0000U; + TIM_InitStruct->Prescaler = (uint16_t)0x0000; TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct->Autoreload = 0xFFFFFFFFU; TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; - TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U; + TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; } /** @@ -701,7 +701,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; - TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U; + TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c index 63c5884e05..c74e669125 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c @@ -335,7 +335,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS case LL_RCC_MSIRANGE_3: /* MSI = 800 KHz */ case LL_RCC_MSIRANGE_4: /* MSI = 1 MHz */ case LL_RCC_MSIRANGE_5: /* MSI = 2 MHz */ - /* PLLVCO input frequency can not in the range from 4 to 16 MHz*/ + /* PLLVCO input frequency is not in the range from 4 to 16 MHz*/ status = ERROR; break; diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index e7f4bc7931..7b88f655e2 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -8,7 +8,7 @@ * STM32F7: 1.2.3 * STM32L0: 1.8.2 * STM32L1: 1.3.1 - * STM32L4: 1.8.1 + * STM32L4: 1.8.2 Release notes of each STM32YYxx HAL Drivers available here: From d9bc3d487c0f6cf0cbab4edcb8dce0ce712c5969 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 24 Jan 2018 08:27:36 +0100 Subject: [PATCH 4/9] Updated stm32l4xx_hal_conf.h in variant Signed-off-by: Frederic Pillon --- .../DISCO_L475VG_IOT/stm32l4xx_hal_conf.h | 83 +++++++++++------- variants/NUCLEO_L432KC/stm32l4xx_hal_conf.h | 85 ++++++++++++------- variants/NUCLEO_L476RG/stm32l4xx_hal_conf.h | 85 ++++++++++++------- 3 files changed, 161 insertions(+), 92 deletions(-) diff --git a/variants/DISCO_L475VG_IOT/stm32l4xx_hal_conf.h b/variants/DISCO_L475VG_IOT/stm32l4xx_hal_conf.h index 580903f5d4..9d9c175ef7 100644 --- a/variants/DISCO_L475VG_IOT/stm32l4xx_hal_conf.h +++ b/variants/DISCO_L475VG_IOT/stm32l4xx_hal_conf.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_conf.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32l4xx_hal_conf.h. @@ -55,6 +53,7 @@ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED /* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ /* #define HAL_COMP_MODULE_ENABLED */ #define HAL_CORTEX_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED @@ -64,8 +63,10 @@ #define HAL_DFSDM_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED /* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ /* #define HAL_FIREWALL_MODULE_ENABLED */ #define HAL_FLASH_MODULE_ENABLED +/* #define HAL_GFXMMU_MODULE_ENABLED */ /* #define HAL_HASH_MODULE_ENABLED */ #define HAL_HCD_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ @@ -77,7 +78,9 @@ /* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LCD_MODULE_ENABLED */ /* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_OPAMP_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ #define HAL_PCD_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED #define HAL_QSPI_MODULE_ENABLED @@ -145,9 +148,9 @@ */ #if !defined (LSI_VALUE) #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ /** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency @@ -241,6 +244,10 @@ #include "stm32l4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "Legacy/stm32l4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_COMP_MODULE_ENABLED #include "stm32l4xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ @@ -265,6 +272,10 @@ #include "stm32l4xx_hal_dma2d.h" #endif /* HAL_DMA2D_MODULE_ENABLED */ +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32l4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + #ifdef HAL_FIREWALL_MODULE_ENABLED #include "stm32l4xx_hal_firewall.h" #endif /* HAL_FIREWALL_MODULE_ENABLED */ @@ -290,97 +301,109 @@ #endif /* HAL_NAND_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l4xx_hal_i2c.h" + #include "stm32l4xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ #ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l4xx_hal_iwdg.h" + #include "stm32l4xx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ #ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l4xx_hal_lcd.h" + #include "stm32l4xx_hal_lcd.h" #endif /* HAL_LCD_MODULE_ENABLED */ #ifdef HAL_LPTIM_MODULE_ENABLED -#include "stm32l4xx_hal_lptim.h" + #include "stm32l4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32l4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + #ifdef HAL_OPAMP_MODULE_ENABLED -#include "stm32l4xx_hal_opamp.h" + #include "stm32l4xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32l4xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + #ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l4xx_hal_pwr.h" + #include "stm32l4xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ #ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32l4xx_hal_qspi.h" + #include "stm32l4xx_hal_qspi.h" #endif /* HAL_QSPI_MODULE_ENABLED */ #ifdef HAL_RNG_MODULE_ENABLED - #include "stm32l4xx_hal_rng.h" + #include "stm32l4xx_hal_rng.h" #endif /* HAL_RNG_MODULE_ENABLED */ #ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l4xx_hal_rtc.h" + #include "stm32l4xx_hal_rtc.h" #endif /* HAL_RTC_MODULE_ENABLED */ #ifdef HAL_SAI_MODULE_ENABLED - #include "stm32l4xx_hal_sai.h" + #include "stm32l4xx_hal_sai.h" #endif /* HAL_SAI_MODULE_ENABLED */ #ifdef HAL_SD_MODULE_ENABLED - #include "stm32l4xx_hal_sd.h" + #include "stm32l4xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ #ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32l4xx_hal_smbus.h" + #include "stm32l4xx_hal_smbus.h" #endif /* HAL_SMBUS_MODULE_ENABLED */ #ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l4xx_hal_spi.h" + #include "stm32l4xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ #ifdef HAL_SWPMI_MODULE_ENABLED - #include "stm32l4xx_hal_swpmi.h" + #include "stm32l4xx_hal_swpmi.h" #endif /* HAL_SWPMI_MODULE_ENABLED */ #ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l4xx_hal_tim.h" + #include "stm32l4xx_hal_tim.h" #endif /* HAL_TIM_MODULE_ENABLED */ #ifdef HAL_TSC_MODULE_ENABLED - #include "stm32l4xx_hal_tsc.h" + #include "stm32l4xx_hal_tsc.h" #endif /* HAL_TSC_MODULE_ENABLED */ #ifdef HAL_UART_MODULE_ENABLED - #include "stm32l4xx_hal_uart.h" + #include "stm32l4xx_hal_uart.h" #endif /* HAL_UART_MODULE_ENABLED */ #ifdef HAL_USART_MODULE_ENABLED - #include "stm32l4xx_hal_usart.h" + #include "stm32l4xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ #ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l4xx_hal_irda.h" + #include "stm32l4xx_hal_irda.h" #endif /* HAL_IRDA_MODULE_ENABLED */ #ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l4xx_hal_smartcard.h" + #include "stm32l4xx_hal_smartcard.h" #endif /* HAL_SMARTCARD_MODULE_ENABLED */ #ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l4xx_hal_wwdg.h" + #include "stm32l4xx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ #ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l4xx_hal_pcd.h" + #include "stm32l4xx_hal_pcd.h" #endif /* HAL_PCD_MODULE_ENABLED */ #ifdef HAL_HCD_MODULE_ENABLED - #include "stm32l4xx_hal_hcd.h" + #include "stm32l4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32l4xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** @@ -391,9 +414,9 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); + void assert_failed(char *file, uint32_t line); #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ diff --git a/variants/NUCLEO_L432KC/stm32l4xx_hal_conf.h b/variants/NUCLEO_L432KC/stm32l4xx_hal_conf.h index eabbc65902..1adfa64bb6 100644 --- a/variants/NUCLEO_L432KC/stm32l4xx_hal_conf.h +++ b/variants/NUCLEO_L432KC/stm32l4xx_hal_conf.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_conf.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32l4xx_hal_conf.h. @@ -55,6 +53,7 @@ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED /* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ /* #define HAL_COMP_MODULE_ENABLED */ #define HAL_CORTEX_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED @@ -64,8 +63,10 @@ /* #define HAL_DFSDM_MODULE_ENABLED */ #define HAL_DMA_MODULE_ENABLED /* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ /* #define HAL_FIREWALL_MODULE_ENABLED */ #define HAL_FLASH_MODULE_ENABLED +/* #define HAL_GFXMMU_MODULE_ENABLED */ /* #define HAL_HASH_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_NAND_MODULE_ENABLED */ @@ -77,7 +78,9 @@ /* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LCD_MODULE_ENABLED */ /* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_OPAMP_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ /* #define HAL_PCD_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED /* #define HAL_QSPI_MODULE_ENABLED */ @@ -135,7 +138,7 @@ * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency * which is subject to manufacturing process variations. */ -#if !defined (HSI48_VALUE) +#if !defined (HSI48_VALUE) #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ @@ -145,9 +148,9 @@ */ #if !defined (LSI_VALUE) #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ /** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency @@ -241,6 +244,10 @@ #include "stm32l4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "Legacy/stm32l4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_COMP_MODULE_ENABLED #include "stm32l4xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ @@ -265,6 +272,10 @@ #include "stm32l4xx_hal_dma2d.h" #endif /* HAL_DMA2D_MODULE_ENABLED */ +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32l4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + #ifdef HAL_FIREWALL_MODULE_ENABLED #include "stm32l4xx_hal_firewall.h" #endif /* HAL_FIREWALL_MODULE_ENABLED */ @@ -290,97 +301,109 @@ #endif /* HAL_NAND_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l4xx_hal_i2c.h" + #include "stm32l4xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ #ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l4xx_hal_iwdg.h" + #include "stm32l4xx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ #ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l4xx_hal_lcd.h" + #include "stm32l4xx_hal_lcd.h" #endif /* HAL_LCD_MODULE_ENABLED */ #ifdef HAL_LPTIM_MODULE_ENABLED -#include "stm32l4xx_hal_lptim.h" + #include "stm32l4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32l4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + #ifdef HAL_OPAMP_MODULE_ENABLED -#include "stm32l4xx_hal_opamp.h" + #include "stm32l4xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32l4xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + #ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l4xx_hal_pwr.h" + #include "stm32l4xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ #ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32l4xx_hal_qspi.h" + #include "stm32l4xx_hal_qspi.h" #endif /* HAL_QSPI_MODULE_ENABLED */ #ifdef HAL_RNG_MODULE_ENABLED - #include "stm32l4xx_hal_rng.h" + #include "stm32l4xx_hal_rng.h" #endif /* HAL_RNG_MODULE_ENABLED */ #ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l4xx_hal_rtc.h" + #include "stm32l4xx_hal_rtc.h" #endif /* HAL_RTC_MODULE_ENABLED */ #ifdef HAL_SAI_MODULE_ENABLED - #include "stm32l4xx_hal_sai.h" + #include "stm32l4xx_hal_sai.h" #endif /* HAL_SAI_MODULE_ENABLED */ #ifdef HAL_SD_MODULE_ENABLED - #include "stm32l4xx_hal_sd.h" + #include "stm32l4xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ #ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32l4xx_hal_smbus.h" + #include "stm32l4xx_hal_smbus.h" #endif /* HAL_SMBUS_MODULE_ENABLED */ #ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l4xx_hal_spi.h" + #include "stm32l4xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ #ifdef HAL_SWPMI_MODULE_ENABLED - #include "stm32l4xx_hal_swpmi.h" + #include "stm32l4xx_hal_swpmi.h" #endif /* HAL_SWPMI_MODULE_ENABLED */ #ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l4xx_hal_tim.h" + #include "stm32l4xx_hal_tim.h" #endif /* HAL_TIM_MODULE_ENABLED */ #ifdef HAL_TSC_MODULE_ENABLED - #include "stm32l4xx_hal_tsc.h" + #include "stm32l4xx_hal_tsc.h" #endif /* HAL_TSC_MODULE_ENABLED */ #ifdef HAL_UART_MODULE_ENABLED - #include "stm32l4xx_hal_uart.h" + #include "stm32l4xx_hal_uart.h" #endif /* HAL_UART_MODULE_ENABLED */ #ifdef HAL_USART_MODULE_ENABLED - #include "stm32l4xx_hal_usart.h" + #include "stm32l4xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ #ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l4xx_hal_irda.h" + #include "stm32l4xx_hal_irda.h" #endif /* HAL_IRDA_MODULE_ENABLED */ #ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l4xx_hal_smartcard.h" + #include "stm32l4xx_hal_smartcard.h" #endif /* HAL_SMARTCARD_MODULE_ENABLED */ #ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l4xx_hal_wwdg.h" + #include "stm32l4xx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ #ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l4xx_hal_pcd.h" + #include "stm32l4xx_hal_pcd.h" #endif /* HAL_PCD_MODULE_ENABLED */ #ifdef HAL_HCD_MODULE_ENABLED - #include "stm32l4xx_hal_hcd.h" + #include "stm32l4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32l4xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** @@ -391,9 +414,9 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); + void assert_failed(char *file, uint32_t line); #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ diff --git a/variants/NUCLEO_L476RG/stm32l4xx_hal_conf.h b/variants/NUCLEO_L476RG/stm32l4xx_hal_conf.h index eabbc65902..1adfa64bb6 100644 --- a/variants/NUCLEO_L476RG/stm32l4xx_hal_conf.h +++ b/variants/NUCLEO_L476RG/stm32l4xx_hal_conf.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32l4xx_hal_conf.h * @author MCD Application Team - * @version V1.7.0 - * @date 17-February-2017 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32l4xx_hal_conf.h. @@ -55,6 +53,7 @@ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED /* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ /* #define HAL_COMP_MODULE_ENABLED */ #define HAL_CORTEX_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED @@ -64,8 +63,10 @@ /* #define HAL_DFSDM_MODULE_ENABLED */ #define HAL_DMA_MODULE_ENABLED /* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ /* #define HAL_FIREWALL_MODULE_ENABLED */ #define HAL_FLASH_MODULE_ENABLED +/* #define HAL_GFXMMU_MODULE_ENABLED */ /* #define HAL_HASH_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_NAND_MODULE_ENABLED */ @@ -77,7 +78,9 @@ /* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LCD_MODULE_ENABLED */ /* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ /* #define HAL_OPAMP_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ /* #define HAL_PCD_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED /* #define HAL_QSPI_MODULE_ENABLED */ @@ -135,7 +138,7 @@ * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency * which is subject to manufacturing process variations. */ -#if !defined (HSI48_VALUE) +#if !defined (HSI48_VALUE) #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ @@ -145,9 +148,9 @@ */ #if !defined (LSI_VALUE) #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ /** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency @@ -241,6 +244,10 @@ #include "stm32l4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "Legacy/stm32l4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_COMP_MODULE_ENABLED #include "stm32l4xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ @@ -265,6 +272,10 @@ #include "stm32l4xx_hal_dma2d.h" #endif /* HAL_DMA2D_MODULE_ENABLED */ +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32l4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + #ifdef HAL_FIREWALL_MODULE_ENABLED #include "stm32l4xx_hal_firewall.h" #endif /* HAL_FIREWALL_MODULE_ENABLED */ @@ -290,97 +301,109 @@ #endif /* HAL_NAND_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l4xx_hal_i2c.h" + #include "stm32l4xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ #ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l4xx_hal_iwdg.h" + #include "stm32l4xx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ #ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l4xx_hal_lcd.h" + #include "stm32l4xx_hal_lcd.h" #endif /* HAL_LCD_MODULE_ENABLED */ #ifdef HAL_LPTIM_MODULE_ENABLED -#include "stm32l4xx_hal_lptim.h" + #include "stm32l4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32l4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + #ifdef HAL_OPAMP_MODULE_ENABLED -#include "stm32l4xx_hal_opamp.h" + #include "stm32l4xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32l4xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + #ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l4xx_hal_pwr.h" + #include "stm32l4xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ #ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32l4xx_hal_qspi.h" + #include "stm32l4xx_hal_qspi.h" #endif /* HAL_QSPI_MODULE_ENABLED */ #ifdef HAL_RNG_MODULE_ENABLED - #include "stm32l4xx_hal_rng.h" + #include "stm32l4xx_hal_rng.h" #endif /* HAL_RNG_MODULE_ENABLED */ #ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l4xx_hal_rtc.h" + #include "stm32l4xx_hal_rtc.h" #endif /* HAL_RTC_MODULE_ENABLED */ #ifdef HAL_SAI_MODULE_ENABLED - #include "stm32l4xx_hal_sai.h" + #include "stm32l4xx_hal_sai.h" #endif /* HAL_SAI_MODULE_ENABLED */ #ifdef HAL_SD_MODULE_ENABLED - #include "stm32l4xx_hal_sd.h" + #include "stm32l4xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ #ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32l4xx_hal_smbus.h" + #include "stm32l4xx_hal_smbus.h" #endif /* HAL_SMBUS_MODULE_ENABLED */ #ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l4xx_hal_spi.h" + #include "stm32l4xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ #ifdef HAL_SWPMI_MODULE_ENABLED - #include "stm32l4xx_hal_swpmi.h" + #include "stm32l4xx_hal_swpmi.h" #endif /* HAL_SWPMI_MODULE_ENABLED */ #ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l4xx_hal_tim.h" + #include "stm32l4xx_hal_tim.h" #endif /* HAL_TIM_MODULE_ENABLED */ #ifdef HAL_TSC_MODULE_ENABLED - #include "stm32l4xx_hal_tsc.h" + #include "stm32l4xx_hal_tsc.h" #endif /* HAL_TSC_MODULE_ENABLED */ #ifdef HAL_UART_MODULE_ENABLED - #include "stm32l4xx_hal_uart.h" + #include "stm32l4xx_hal_uart.h" #endif /* HAL_UART_MODULE_ENABLED */ #ifdef HAL_USART_MODULE_ENABLED - #include "stm32l4xx_hal_usart.h" + #include "stm32l4xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ #ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l4xx_hal_irda.h" + #include "stm32l4xx_hal_irda.h" #endif /* HAL_IRDA_MODULE_ENABLED */ #ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l4xx_hal_smartcard.h" + #include "stm32l4xx_hal_smartcard.h" #endif /* HAL_SMARTCARD_MODULE_ENABLED */ #ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l4xx_hal_wwdg.h" + #include "stm32l4xx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ #ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l4xx_hal_pcd.h" + #include "stm32l4xx_hal_pcd.h" #endif /* HAL_PCD_MODULE_ENABLED */ #ifdef HAL_HCD_MODULE_ENABLED - #include "stm32l4xx_hal_hcd.h" + #include "stm32l4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32l4xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** @@ -391,9 +414,9 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); + void assert_failed(char *file, uint32_t line); #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ From 9cc074f3395f5593d506885dbcbe7777cdcd8205 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 24 Jan 2018 08:55:06 +0100 Subject: [PATCH 5/9] Updated STM32F4xx HAL Drivers to v1.7.3 Included in STM32CubeF4 FW V1.19.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 44 +- .../Inc/Legacy/stm32f4xx_hal_can_legacy.h | 785 +++++ .../STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h | 39 +- .../Inc/stm32f4xx_hal_can.h | 741 +++-- .../Inc/stm32f4xx_hal_conf_template.h | 5 + .../Inc/stm32f4xx_hal_fmpi2c.h | 4 +- .../Inc/stm32f4xx_hal_rcc.h | 28 +- .../Inc/stm32f4xx_hal_rcc_ex.h | 8 + .../Inc/stm32f4xx_ll_rcc.h | 37 +- .../STM32F4xx_HAL_Driver/Release_Notes.html | 36 +- .../Src/Legacy/stm32f4xx_hal_can.c | 1697 +++++++++++ .../STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c | 108 +- .../Src/stm32f4xx_hal_can.c | 2680 +++++++++-------- .../Src/stm32f4xx_hal_fmpi2c.c | 6 + .../Src/stm32f4xx_hal_rcc.c | 36 +- .../Src/stm32f4xx_hal_rcc_ex.c | 299 +- .../Src/stm32f4xx_ll_fmc.c | 2 +- .../Src/stm32f4xx_ll_fsmc.c | 2 +- .../Src/stm32f4xx_ll_rcc.c | 28 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 20 files changed, 4950 insertions(+), 1637 deletions(-) create mode 100644 system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h create mode 100644 system/Drivers/STM32F4xx_HAL_Driver/Src/Legacy/stm32f4xx_hal_can.c diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 6e64e55f96..c37602b2a3 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -431,12 +431,12 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -2119,6 +2119,21 @@ #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE @@ -2787,7 +2802,9 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32WB) || defined(STM32G0) +#if defined(STM32L4) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#elif defined(STM32WB) || defined(STM32G0) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3038,6 +3055,16 @@ #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif +#if defined(STM32H7) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#endif /** * @} */ @@ -3252,6 +3279,17 @@ * @} */ +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h new file mode 100644 index 0000000000..0a2a4e04c7 --- /dev/null +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h @@ -0,0 +1,785 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_can_legacy.h + * @author MCD Application Team + * @brief Header file of CAN HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CAN_LEGACY_H +#define __STM32F4xx_HAL_CAN_LEGACY_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ + HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ + +}HAL_CAN_StateTypeDef; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE */ +}CAN_InitTypeDef; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. + This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ + + uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint32_t FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + uint32_t FilterActivation; /*!< Enable or disable the filter. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t BankNumber; /*!< Select the start slave bank filter. + This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + +}CAN_FilterConfTypeDef; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_Identifier_Type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + +}CanTxMsgTypeDef; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. + This parameter can be a value of @ref CAN_Identifier_Type */ + + uint32_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t FIFONumber; /*!< Specifies the receive FIFO number. + This parameter can be CAN_FIFO0 or CAN_FIFO1 */ + +}CanRxMsgTypeDef; + +/** + * @brief CAN handle Structure definition + */ +typedef struct +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + + CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ + + CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ + + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + + HAL_LockTypeDef Lock; /*!< CAN locking object */ + + __IO uint32_t ErrorCode; /*!< CAN Error code */ + +}CAN_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CAN_Exported_Constants CAN Exported Constants + * @{ + */ + +/** @defgroup CAN_Error_Code CAN Error Code + * @{ + */ +#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */ +#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */ +#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */ +#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */ +#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */ +#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */ +#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */ +#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */ +/** + * @} + */ + +/** @defgroup CAN_InitStatus CAN InitStatus + * @{ + */ +#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */ +/** + * @} + */ + +/** @defgroup CAN_operating_mode CAN Operating Mode + * @{ + */ +#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */ +#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ +#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width + * @{ + */ +#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ +#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ +#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1 + * @{ + */ +#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ +#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ +#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ +#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ +#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ +#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ +#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ +#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ +#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ +#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ +#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ +#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ +#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ +#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ +#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2 + * @{ + */ +#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ +#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ +#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ +#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ +#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ +#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ +#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode CAN Filter Mode + * @{ + */ +#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +/** + * @} + */ + +/** @defgroup CAN_filter_scale CAN Filter Scale + * @{ + */ +#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO CAN Filter FIFO + * @{ + */ +#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +/** + * @} + */ + +/** @defgroup CAN_Identifier_Type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD 0x00000000U /*!< Standard Id */ +#define CAN_ID_EXT 0x00000004U /*!< Extended Id */ +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request + * @{ + */ +#define CAN_RTR_DATA 0x00000000U /*!< Data frame */ +#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants + * @{ + */ +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +/** + * @} + */ + +/** @defgroup CAN_flags CAN Flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with + CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */ +#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */ +#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */ +#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */ +#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */ +#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */ +#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */ + +/* Receive Flags */ +#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */ + +#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */ +#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */ +#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */ + +/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */ +#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */ +#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */ +/** + * @} + */ + +/** @defgroup CAN_Interrupts CAN Interrupts + * @{ + */ +#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ +/** + * @} + */ + +/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition + * @{ + */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Macros CAN Exported Macros + * @{ + */ + +/** @brief Reset CAN handle state + * @param __HANDLE__ specifies the CAN Handle. + * @retval None + */ +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) + +/** + * @brief Enable the specified CAN interrupts. + * @param __HANDLE__ CAN handle + * @param __INTERRUPT__ CAN Interrupt + * @retval None + */ +#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified CAN interrupts. + * @param __HANDLE__ CAN handle + * @param __INTERRUPT__ CAN Interrupt + * @retval None + */ +#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** + * @brief Return the number of pending received messages. + * @param __HANDLE__ CAN handle + * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval The number of pending message. + */ +#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U))) + +/** @brief Check whether the specified CAN flag is set or not. + * @param __HANDLE__ CAN Handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + +/** @brief Clear the specified CAN pending flag. + * @param __HANDLE__ CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK)))) + +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ CAN Handle + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable + * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable + * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Check the transmission status of a CAN Frame. + * @param __HANDLE__ CAN Handle + * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. + * @retval The new status of transmission (TRUE or FALSE). + */ +#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ + ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) + +/** + * @brief Release the specified receive FIFO. + * @param __HANDLE__ CAN handle + * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval None + */ +#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) + +/** + * @brief Cancel a transmit request. + * @param __HANDLE__ CAN Handle + * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. + * @retval None + */ +#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ + ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) + +/** + * @brief Enable or disable the DBG Freeze for CAN. + * @param __HANDLE__ CAN Handle + * @param __NEWSTATE__ new state of the CAN peripheral. + * This parameter can be: ENABLE (CAN reception/transmission is frozen + * during debug. Reception FIFOs can still be accessed/controlled normally) + * or DISABLE (CAN is working during debug). + * @retval None + */ +#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ +((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions + * @{ + */ + +/** @addtogroup CAN_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ***********************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ******************************************************/ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); +void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ***************************************************/ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup CAN_Private_Types CAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Variables CAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ +#define CAN_FLAG_MASK 0x000000FFU +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) +#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ + +/** + * @} + */ + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CAN_LEGACY_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h index a74d45452a..59d1e59d50 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h @@ -56,6 +56,28 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/** + * @} + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup HAL_Exported_Macros HAL Exported Macros * @{ @@ -181,6 +203,16 @@ * @} */ +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup HAL_Exported_Functions * @{ @@ -188,7 +220,7 @@ /** @addtogroup HAL_Exported_Functions_Group1 * @{ */ -/* Initialization and de-initialization functions ******************************/ +/* Initialization and Configuration functions ******************************/ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); void HAL_MspInit(void); @@ -203,8 +235,11 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); */ /* Peripheral Control functions ************************************************/ void HAL_IncTick(void); -void HAL_Delay(__IO uint32_t Delay); +void HAL_Delay(uint32_t Delay); uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); void HAL_SuspendTick(void); void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h index e2961829b9..e3752f4bf6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -34,18 +34,13 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CAN_H -#define __STM32F4xx_HAL_CAN_H +#ifndef STM32F4xx_HAL_CAN_H +#define STM32F4xx_HAL_CAN_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ - defined(STM32F423xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -53,6 +48,7 @@ * @{ */ +#if defined (CAN1) /** @addtogroup CAN * @{ */ @@ -61,7 +57,6 @@ /** @defgroup CAN_Exported_Types CAN Exported Types * @{ */ - /** * @brief HAL State structures definition */ @@ -69,59 +64,53 @@ typedef enum { HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ - HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ + HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ + HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ + HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ + HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ -}HAL_CAN_StateTypeDef; +} HAL_CAN_StateTypeDef; /** * @brief CAN init structure definition */ typedef struct { - uint32_t Prescaler; /*!< Specifies the length of a time quantum. - This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ - uint32_t Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ + uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ - uint32_t SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ + uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ - uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set to ENABLE or DISABLE. */ + FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set to ENABLE or DISABLE */ -}CAN_InitTypeDef; +} CAN_InitTypeDef; /** * @brief CAN filter configuration structure definition @@ -130,27 +119,30 @@ typedef struct { uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ - uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. - This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ + uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. + For single CAN instance(14 dedicated filter banks), + this parameter must be a number between Min_Data = 0 and Max_Data = 13. + For dual CAN instances(28 filter banks shared), + this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ @@ -161,95 +153,94 @@ typedef struct uint32_t FilterActivation; /*!< Enable or disable the filter. This parameter can be set to ENABLE or DISABLE. */ - uint32_t BankNumber; /*!< Select the start slave bank filter. - This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. + For single CAN instances, this parameter is meaningless. + For dual CAN instances, all filter banks with lower index are assigned to master + CAN instance, whereas all filter banks with greater index are assigned to slave + CAN instance. + This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ -}CAN_FilterConfTypeDef; +} CAN_FilterTypeDef; /** - * @brief CAN Tx message structure definition + * @brief CAN Tx message header structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. - This parameter can be a value of @ref CAN_Identifier_Type */ + This parameter can be a value of @ref CAN_identifier_type */ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref CAN_remote_transmission_request */ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start + of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. + @note: Time Triggered Communication Mode must be enabled. + @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. + This parameter can be set to ENABLE or DISABLE. */ -}CanTxMsgTypeDef; +} CAN_TxHeaderTypeDef; /** - * @brief CAN Rx message structure definition + * @brief CAN Rx message header structure definition */ typedef struct { - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. - This parameter can be a value of @ref CAN_Identifier_Type */ + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - uint32_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of @ref CAN_remote_transmission_request */ + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ - uint32_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ - uint8_t Data[8]; /*!< Contains the data to be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + @note: Time Triggered Communication Mode must be enabled. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ - uint32_t FIFONumber; /*!< Specifies the receive FIFO number. - This parameter can be CAN_FIFO0 or CAN_FIFO1 */ + uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ -}CanRxMsgTypeDef; +} CAN_RxHeaderTypeDef; /** * @brief CAN handle Structure definition */ -typedef struct +typedef struct __CAN_HandleTypeDef { - CAN_TypeDef *Instance; /*!< Register base address */ - - CAN_InitTypeDef Init; /*!< CAN required parameters */ - - CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + CAN_TypeDef *Instance; /*!< Register base address */ - CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ + CAN_InitTypeDef Init; /*!< CAN required parameters */ - CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + __IO uint32_t ErrorCode; /*!< CAN Error code. + This parameter can be a value of @ref CAN_Error_Code */ - HAL_LockTypeDef Lock; /*!< CAN locking object */ - - __IO uint32_t ErrorCode; /*!< CAN Error code */ - -}CAN_HandleTypeDef; +} CAN_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup CAN_Exported_Constants CAN Exported Constants * @{ */ @@ -257,19 +248,30 @@ typedef struct /** @defgroup CAN_Error_Code CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */ -#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */ -#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */ -#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */ -#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */ -#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */ -#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */ -#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ +#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ +#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ +#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ +#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ +#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ +#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ + /** * @} */ @@ -277,8 +279,8 @@ typedef struct /** @defgroup CAN_InitStatus CAN InitStatus * @{ */ -#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ /** * @} */ @@ -286,7 +288,7 @@ typedef struct /** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ -#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ @@ -294,10 +296,11 @@ typedef struct * @} */ -/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width * @{ */ -#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ @@ -305,10 +308,10 @@ typedef struct * @} */ -/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1 +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 * @{ */ -#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ @@ -328,10 +331,10 @@ typedef struct * @} */ -/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2 +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 * @{ */ -#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ @@ -343,11 +346,11 @@ typedef struct * @} */ -/** @defgroup CAN_filter_mode CAN Filter Mode +/** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ -#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ -#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ /** * @} */ @@ -355,8 +358,8 @@ typedef struct /** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ -#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ /** * @} */ @@ -364,17 +367,17 @@ typedef struct /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ -#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ /** * @} */ -/** @defgroup CAN_Identifier_Type CAN Identifier Type +/** @defgroup CAN_identifier_type CAN Identifier Type * @{ */ -#define CAN_ID_STD 0x00000000U /*!< Standard Id */ -#define CAN_ID_EXT 0x00000004U /*!< Extended Id */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ /** * @} */ @@ -382,98 +385,100 @@ typedef struct /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ -#define CAN_RTR_DATA 0x00000000U /*!< Data frame */ -#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ /** * @} */ -/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants +/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number * @{ */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ +#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ /** * @} */ -/** @defgroup CAN_flags CAN Flags +/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes * @{ */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ +#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ +#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ +#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ +/** + * @} + */ +/** @defgroup CAN_flags CAN Flags + * @{ + */ /* Transmit Flags */ -#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */ -#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */ -#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */ -#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */ -#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */ -#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */ -#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ +#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ +#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ +#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ +#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ +#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ +#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ +#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ +#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ +#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ /* Receive Flags */ -#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */ -#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */ - -#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */ -#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ /* Operating Mode Flags */ -#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */ -#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */ -#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */ -#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */ -#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */ - -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ /* Error Flags */ -#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */ -#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */ -#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ /** * @} */ + /** @defgroup CAN_Interrupts CAN Interrupts * @{ */ -#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ +/* Transmit Interrupt */ +#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ /* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ -#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ -#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ -#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ -#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ -#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ +#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ /* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ -#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ +#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ /* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ -#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ -#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ -#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ -#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ -/** - * @} - */ - -/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition - * @{ - */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) +#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ /** * @} */ @@ -482,213 +487,198 @@ typedef struct * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup CAN_Exported_Macros CAN Exported Macros * @{ */ -/** @brief Reset CAN handle state - * @param __HANDLE__ specifies the CAN Handle. +/** @brief Reset CAN handle state + * @param __HANDLE__ CAN handle. * @retval None */ #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) /** * @brief Enable the specified CAN interrupts. - * @param __HANDLE__ CAN handle - * @param __INTERRUPT__ CAN Interrupt + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to enable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) /** * @brief Disable the specified CAN interrupts. - * @param __HANDLE__ CAN handle - * @param __INTERRUPT__ CAN Interrupt + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to disable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) -/** - * @brief Return the number of pending received messages. - * @param __HANDLE__ CAN handle - * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval The number of pending message. +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be a value of @arg CAN_Interrupts + * @retval The state of __IT__ (TRUE or FALSE). */ -#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U))) +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) /** @brief Check whether the specified CAN flag is set or not. - * @param __HANDLE__ CAN Handle + * @param __HANDLE__ specifies the CAN Handle. * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * This parameter can be one of @arg CAN_flags + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** @brief Clear the specified CAN pending flag. - * @param __HANDLE__ CAN Handle. + * @param __HANDLE__ specifies the CAN Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag + * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag + * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag + * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag + * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag + * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag + * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag + * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag + * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag + * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag + * @retval None */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK)))) - -/** @brief Check if the specified CAN interrupt source is enabled or disabled. - * @param __HANDLE__ CAN Handle - * @param __INTERRUPT__ specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable - * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable - * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** - * @brief Check the transmission status of a CAN Frame. - * @param __HANDLE__ CAN Handle - * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. - * @retval The new status of transmission (TRUE or FALSE). - */ -#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ - ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) + * @} + */ -/** - * @brief Release the specified receive FIFO. - * @param __HANDLE__ CAN handle - * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval None +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ */ -#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) -/** - * @brief Cancel a transmit request. - * @param __HANDLE__ CAN Handle - * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. - * @retval None - */ -#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ - ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ -/** - * @brief Enable or disable the DBG Freeze for CAN. - * @param __HANDLE__ CAN Handle - * @param __NEWSTATE__ new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ -((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); /** - * @} - */ + * @} + */ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CAN_Exported_Functions - * @{ - */ +/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions + * @{ + */ + +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); -/** @addtogroup CAN_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions ***********************************/ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); /** - * @} - */ + * @} + */ -/** @addtogroup CAN_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); +/** @addtogroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ + +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); -void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); -void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group5 Callback functions + * @brief Callback functions + * @{ + */ +/* Callbacks functions ********************************************************/ + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); + /** - * @} - */ + * @} + */ -/** @addtogroup CAN_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ***************************************************/ +/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); + /** - * @} - */ + * @} + */ /** - * @} - */ + * @} + */ /* Private types -------------------------------------------------------------*/ /** @defgroup CAN_Private_Types CAN Private Types @@ -706,71 +696,80 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ -#define CAN_FLAG_MASK 0x000000FFU +#define CAN_FLAG_MASK (0x000000FFU) /** * @} */ -/* Private macros ------------------------------------------------------------*/ +/* Private Macros -----------------------------------------------------------*/ /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ + #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ ((MODE) == CAN_MODE_LOOPBACK)|| \ ((MODE) == CAN_MODE_SILENT) || \ ((MODE) == CAN_MODE_SILENT_LOOPBACK)) -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) +#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ + ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ + ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ + ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ + ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ + ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ + ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ + ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) +#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ + ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ + ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ + ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) +#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ ((SCALE) == CAN_FILTERSCALE_32BIT)) #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU)) +#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) #define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ ((IDTYPE) == CAN_ID_EXT)) #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) +#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) +#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ + CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ + CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ + CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ + CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ + CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) /** * @} */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ +/* End of private macros -----------------------------------------------------*/ /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -/** - * @} - */ +#endif /* CAN1 */ /** * @} */ @@ -779,7 +778,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); } #endif -#endif /* __STM32F4xx_CAN_H */ +#endif /* STM32F4xx_HAL_CAN_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h index 35a5ad51fb..934a946e63 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h @@ -53,6 +53,7 @@ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED #define HAL_CAN_MODULE_ENABLED +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ #define HAL_CRC_MODULE_ENABLED #define HAL_CEC_MODULE_ENABLED #define HAL_CRYP_MODULE_ENABLED @@ -273,6 +274,10 @@ #include "stm32f4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CRC_MODULE_ENABLED #include "stm32f4xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h index bafe73ba48..bfd0571234 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h @@ -251,6 +251,7 @@ typedef struct __FMPI2C_HandleTypeDef #define FMPI2C_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE)) #define FMPI2C_FIRST_AND_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE) #define FMPI2C_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE) +#define FMPI2C_LAST_FRAME_NO_STOP ((uint32_t)FMPI2C_SOFTEND_MODE) /** * @} */ @@ -662,7 +663,8 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); ((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \ ((REQUEST) == FMPI2C_NEXT_FRAME) || \ ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == FMPI2C_LAST_FRAME)) + ((REQUEST) == FMPI2C_LAST_FRAME) || \ + ((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP)) #define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN))) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h index a1e304c397..5f2afe6c5e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h @@ -268,8 +268,10 @@ typedef struct /** @defgroup RCC_RTC_Clock_Source RTC Clock Source * @{ */ +#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U #define RCC_RTCCLKSOURCE_LSE 0x00000100U #define RCC_RTCCLKSOURCE_LSI 0x00000200U +#define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U @@ -990,10 +992,11 @@ typedef struct * a Power On Reset (POR). * @param __RTCCLKSource__ specifies the RTC clock source. * This parameter can be one of the following values: - * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. - * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. - * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected - * as RTC clock, where x:[2,31] + @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wake-up source. * However, when the HSE clock is used as RTC clock source, the RTC @@ -1008,6 +1011,23 @@ typedef struct RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ } while(0U) +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** + * @brief Get the RTC and HSE clock divider (RTCPRE). + * @retval Returned value can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + */ +#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) + /** @brief Macros to force or release the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) * and the RTC clock source selection in RCC_CSR register. diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h index 3ee7e1b92b..72d39627bd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h @@ -6735,6 +6735,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); defined(STM32F423xx) void HAL_RCCEx_SelectLSEMode(uint8_t Mode); #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +#if defined(RCC_PLLI2S_SUPPORT) +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); +#endif /* RCC_PLLI2S_SUPPORT */ +#if defined(RCC_PLLSAI_SUPPORT) +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); +#endif /* RCC_PLLSAI_SUPPORT */ /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h index efc9eb00f7..253f0d3c7e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h @@ -4851,6 +4851,31 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, #endif /* SAI1 */ #endif /* RCC_PLLCFGR_PLLR */ +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + /** * @brief Get Main PLL multiplication factor for VCO * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN @@ -4965,18 +4990,6 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void) } #endif /* RCC_DCKCFGR_PLLDIVR */ -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); -} - /** * @brief Get Division factor for the main PLL and other PLL * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html index cb046d6cd2..c2231f8895 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html @@ -1,4 +1,4 @@ - + @@ -922,7 +922,39 @@

-

Update History

V1.7.2 / 06-October-2017

Main +

Update History

V1.7.3 / 22-December-2017

Main +Changes

  • General updates +to fix known defects and enhancements implementation
  • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
    • Rework of HAL CAN driver (compatibility break) 
      • A +new HAL CAN driver has been redesigned with new APIs, to bypass +limitations on CAN Tx/Rx FIFO management present with previous HAL CAN +driver version.
      • The +new HAL CAN driver is the recommended version. It is located as usual +in Drivers/STM32F4xx_HAL_Driver/Src and +Drivers/STM32f4xx_HAL_Driver/Inc folders. It can be enabled through +switch HAL_CAN_MODULE_ENABLED in stm32f4xx_hal_conf.h
      • The +legacy HAL CAN driver is also present in the release in +Drivers/STM32F4xx_HAL_Driver/Src/Legacy and +Drivers/STM32F4xx_HAL_Driver/Inc/Legacy folders for software +compatibility reasons. Its usage is not recommended as +deprecated. It can however be enabled through switch +HAL_CAN_LEGACY_MODULE_ENABLED in stm32f4xx_hal_conf.h
  • HAL update
    • Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms :
      • Add the following API's :  
        • HAL_GetTickPrio(): Returns a tick priority.
        • HAL_SetTickFreq(): Sets new tick frequency.
        • HAL_GetTickFreq(): Returns tick frequency.
      • Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and 1KHz (default).
  • HAL CAN update
    • Fields of CAN_InitTypeDef structure are reworked:
      • SJW +to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to +TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to +AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to +TransmitFifoPriority
    • HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() API's
    • HAL_CAN_Transmit() +is replaced by HAL_CAN_AddTxMessage() to place Tx Request, then +HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion.
    • HAL_CAN_Transmit_IT() +is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then +HAL_CAN_AddTxMessage() for place Tx request.
    • HAL_CAN_Receive() +is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until +reception, then HAL_CAN_GetRxMessage()
      to get Rx message.
    • HAL_CAN_Receive_IT() +is replaced by HAL_CAN_ActivateNotification() to enable receive IT, then +HAL_CAN_GetRxMessage()
       in the receivecallback to get Rx message
    • HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()
    • HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback().
    • HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback().
    • More complete "How to use the new driver" is detailed in the driver header section itself.
  • HAL FMPI2C update
    • Add new option FMPI2C_LAST_FRAME_NO_STOP for the sequential transfer management
      • This option allows to manage a restart condition after several call of the same master sequential interface. 
  • HAL RCC update
    • Add new HAL macros
      • __HAL_RCC_GET_RTC_SOURCE() + allowing to get the RTC clock source
      • __HAL_RCC_GET_RTC_HSE_PRESCALER() + allowing to get the HSE clock divider for RTC peripheral
    • Ensure reset of CIR and CSR + registers when issuing HAL_RCC_DeInit()/LL_RCC_DeInit functions
    • Update HAL_RCC_OscConfig() to keep backup domain enabled when configuring respectively LSE and RTC clock source
    • Add new HAL interfaces allowing to control the activation or deactivation of PLLI2S and PLLSAI:
      • HAL_RCCEx_EnablePLLI2S()
      • HAL_RCCEx_DisablePLLI2S()
      • HAL_RCCEx_EnablePLLSAI()
      • HAL_RCCEx_DisablePLLSAI()
  • LL RCC update 
    • Add new LL RCC macro
      • LL_RCC_PLL_SetMainSource() + allowing to configure PLL main clock source
  • LL FMC / LL FSMC update
    • Add clear of the PTYP bit to select the PCARD mode in FMC_PCCARD_Init() / FSMC_PCCARD_Init()
+

V1.7.2 / 06-October-2017

Main Changes

  • General updates to fix known defects and enhancements implementation
  • Fix compilation warning with GCC compiler
  • Remove Date and version from header files
  • Update HAL drivers to refer to the new CMSIS bit position defines instead of usage the POSITION_VAL() macro
  • HAL Generic update
    • stm32f4xx_hal_def.h file changes: 
      • Update __weak and __packed defined values for ARM compiler
      • Update __ALIGN_BEGIN and __ALIGN_END defined values for ARM compiler
    • stm32f4xx_ll_system.h file: add LL_SYSCFG_REMAP_SDRAM define
  • HAL ADC update
    • Fix wrong definition of ADC channel temperature sensor for STM32F413xx and STM32F423xx devices.
  • HAL DMA update
    • Update values for the following defines: DMA_FLAG_FEIF0_4 and DMA_FLAG_DMEIF0_4 
  • HAL DSI update
    • Fix Extra warning with SW4STM32 compiler
    • Fix DSI display issue when using EWARM w/ high level optimization 
    • Fix MISRAC errors
  • HAL FLASH update
    • HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked
  • HAL FMPI2C update
    • Update Interface APIs headers to remove confusing message about device address
    • Update diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/Legacy/stm32f4xx_hal_can.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/Legacy/stm32f4xx_hal_can.c new file mode 100644 index 0000000000..2cfb869a42 --- /dev/null +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/Legacy/stm32f4xx_hal_can.c @@ -0,0 +1,1697 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_can.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + @verbatim + ============================================================================== + ##### User NOTE ##### + ============================================================================== + [..] + (#) This HAL CAN driver is deprecated, it contains some CAN Tx/Rx FIFO management limitations. + Another HAL CAN driver version has been designed with new API's, to fix these limitations. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the CAN controller interface clock using + __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2 + and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3 + -@- In case you are using CAN2 only, you have to enable the CAN1 clock. + + (#) CAN pins configuration + (++) Enable the clock for the CAN GPIOs using the following function: + __GPIOx_CLK_ENABLE() + (++) Connect and configure the involved CAN pins to AF9 using the + following function HAL_GPIO_Init() + + (#) Initialize and configure the CAN using CAN_Init() function. + + (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. + + (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. + + (#) Receive a CAN frame using HAL_CAN_Receive() function. + + (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the CAN peripheral transmission and wait the end of this operation + using HAL_CAN_Transmit(), at this stage user can specify the value of timeout + according to his end application + (+) Start the CAN peripheral reception and wait the end of this operation + using HAL_CAN_Receive(), at this stage user can specify the value of timeout + according to his end application + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() + (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() + (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine + (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_TxCpltCallback + (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_ErrorCallback + + *** CAN HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in CAN HAL driver. + + (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts + (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts + (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled + (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags + (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status + + [..] + (@) You can refer to the CAN Legacy HAL driver header file for more useful macros + + @endverbatim + + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2017 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) + +#ifdef HAL_CAN_MODULE_ENABLED +/* Select HAL CAN module in stm32f4xx_hal_conf.h file: + (#) HAL_CAN_MODULE_ENABLED for new HAL CAN driver fixing FIFO limitations + (#) HAL_CAN_LEGACY_MODULE_ENABLED for legacy HAL CAN driver */ +#error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32f4xx_hal_conf.h file' +#endif /* HAL_CAN_MODULE_ENABLED */ + +#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver' + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup CAN_Private_Constants + * @{ + */ +#define CAN_TIMEOUT_VALUE 10U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup CAN_Private_Functions + * @{ + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the CAN. + (+) De-initialize the CAN. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +{ + uint32_t InitStatus = CAN_INITSTATUS_FAILED; + uint32_t tickstart = 0U; + + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SJW)); + assert_param(IS_CAN_BS1(hcan->Init.BS1)); + assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + + + if(hcan->State == HAL_CAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcan->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_CAN_MspInit(hcan); + } + + /* Initialize the CAN state*/ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Exit from sleep mode */ + hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + hcan->Instance->MCR |= CAN_MCR_INRQ ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Check acknowledge */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + /* Set the time triggered communication mode */ + if (hcan->Init.TTCM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TTCM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (hcan->Init.ABOM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_ABOM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AWUM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_AWUM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (hcan->Init.NART == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_NART; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.RFLM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_RFLM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TXFP == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TXFP; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ + ((uint32_t)hcan->Init.SJW) | \ + ((uint32_t)hcan->Init.BS1) | \ + ((uint32_t)hcan->Init.BS2) | \ + ((uint32_t)hcan->Init.Prescaler - 1U); + + /* Request leave initialisation */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Check acknowledged */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + InitStatus = CAN_INITSTATUS_SUCCESS; + } + } + + if(InitStatus == CAN_INITSTATUS_SUCCESS) + { + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) +{ + uint32_t filternbrbitpos = 0U; + CAN_TypeDef *can_ip; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); + + filternbrbitpos = 1U << sFilterConfig->FilterNumber; +#if defined (CAN3) + /* Check the CAN instance */ + if(hcan->Instance == CAN3) + { + can_ip = CAN3; + } + else + { + can_ip = CAN1; + } +#else + can_ip = CAN1; +#endif + + /* Initialisation mode for the filter */ + can_ip->FMR |= (uint32_t)CAN_FMR_FINIT; + +#if defined (CAN2) + /* Select the start slave bank */ + can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); + can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U); +#endif + + /* Filter Deactivation */ + can_ip->FA1R &= ~(uint32_t)filternbrbitpos; + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + can_ip->FS1R &= ~(uint32_t)filternbrbitpos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + can_ip->FS1R |= filternbrbitpos; + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /*Id/Mask mode for the filter*/ + can_ip->FM1R &= ~(uint32_t)filternbrbitpos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + can_ip->FM1R |= (uint32_t)filternbrbitpos; + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + can_ip->FFA1R &= ~(uint32_t)filternbrbitpos; + } + + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + { + /* FIFO 1 assignation for the filter */ + can_ip->FFA1R |= (uint32_t)filternbrbitpos; + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) + { + can_ip->FA1R |= filternbrbitpos; + } + + /* Leave the initialisation mode for the filter */ + can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the CANx peripheral registers to their default reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +{ + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_CAN_MspDeInit(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Transmit a CAN frame message. + (+) Receive a CAN frame message. + (+) Enter CAN peripheral in sleep mode. + (+) Wake up the CAN peripheral from sleep mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + { + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + } + + /* Select one empty transmit mailbox */ + if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = CAN_TXMAILBOX_0; + } + else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = CAN_TXMAILBOX_1; + } + else + { + transmitmailbox = CAN_TXMAILBOX_2; + } + + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if (hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[0U])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[4U])); + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check End of transmission flag */ + while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + + __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + { + /* Process Locked */ + __HAL_LOCK(hcan); + + /* Select one empty transmit mailbox */ + if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = CAN_TXMAILBOX_0; + } + else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = CAN_TXMAILBOX_1; + } + else + { + transmitmailbox = CAN_TXMAILBOX_2; + } + + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if(hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[0U])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[4U])); + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcan); + + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + + /* Enable Error warning, Error passive, Bus-off, + Last error and Error Interrupts */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME); + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber FIFO Number value + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + CanRxMsgTypeDef* pRxMsg = NULL; + + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Check if CAN state is not busy for RX FIFO0 */ + if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Check if CAN state is not busy for RX FIFO1 */ + if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + } + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check pending message */ + while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) + { + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + + /* Get the Id */ + pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) + { + pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + } + else + { + pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + } + + pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; + /* Get the data field */ + pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); + pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); + pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); + pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); + pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); + pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); + + /* Release the FIFO */ + if(FIFONumber == CAN_FIFO0) + { + /* Release FIFO0 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + } + else /* FIFONumber == CAN_FIFO1 */ + { + /* Release FIFO1 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + } + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan Pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber Specify the FIFO number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Check if CAN state is not busy for RX FIFO0 */ + if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Check if CAN state is not busy for RX FIFO1 */ + if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + if(FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + } + } + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + /* - Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + if(FIFONumber == CAN_FIFO0) + { + /* Enable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + else + { + /* Enable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enters the Sleep (low power) mode. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0U; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Request Sleep mode */ + hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral + * is in the normal mode. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0U; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Wake up request */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Sleep mode status */ + while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +{ + uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U; + uint32_t errorcode = HAL_CAN_ERROR_NONE; + + /* Check Overrun flag for FIFO0 */ + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0); + if(tmp1 && tmp2) + { + /* Set CAN error code to FOV0 error */ + errorcode |= HAL_CAN_ERROR_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + /* Check Overrun flag for FIFO1 */ + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1); + + if(tmp1 && tmp2) + { + /* Set CAN error code to FOV1 error */ + errorcode |= HAL_CAN_ERROR_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + + /* Check End of transmission flag */ + if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) + { + tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0); + tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1); + tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2); + if(tmp1 || tmp2 || tmp3) + { + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0); + tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1); + tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2); + /* Check Transmit success */ + if(tmp1 || tmp2 || tmp3) + { + /* Call transmit function */ + CAN_Transmit_IT(hcan); + } + else /* Transmit failure */ + { + /* Set CAN error code to TXFAIL error */ + errorcode |= HAL_CAN_ERROR_TXFAIL; + } + + /* Clear transmission status flags (RQCPx and TXOKx) */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \ + CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2); + } + } + + tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0); + /* Check End of reception flag for FIFO0 */ + if((tmp1 != 0U) && tmp2) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO0); + } + + tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1); + /* Check End of reception flag for FIFO1 */ + if((tmp1 != 0U) && tmp2) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO1); + } + + /* Set error code in handle */ + hcan->ErrorCode |= errorcode; + + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); + /* Check Error Warning Flag */ + if(tmp1 && tmp2 && tmp3) + { + /* Set CAN error code to EWG error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EWG; + } + + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); + /* Check Error Passive Flag */ + if(tmp1 && tmp2 && tmp3) + { + /* Set CAN error code to EPV error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EPV; + } + + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); + /* Check Bus-Off Flag */ + if(tmp1 && tmp2 && tmp3) + { + /* Set CAN error code to BOF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BOF; + } + + tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); + /* Check Last error code Flag */ + if((!tmp1) && tmp2 && tmp3) + { + tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC; + switch(tmp1) + { + case(CAN_ESR_LEC_0): + /* Set CAN error code to STF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_STF; + break; + case(CAN_ESR_LEC_1): + /* Set CAN error code to FOR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_FOR; + break; + case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to ACK error */ + hcan->ErrorCode |= HAL_CAN_ERROR_ACK; + break; + case(CAN_ESR_LEC_2): + /* Set CAN error code to BR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BR; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to BD error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BD; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + hcan->ErrorCode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + hcan->Instance->ESR &= ~(CAN_ESR_LEC); + } + + /* Call the Error call Back in case of Errors */ + if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) + { + /* Clear ERRI Flag */ + hcan->Instance->MSR = CAN_MSR_ERRI; + /* Set the CAN state ready to be able to start again the process */ + hcan->State = HAL_CAN_STATE_READY; + + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + /* - Disable FIFO 0 message pending Interrupt */ + /* - Disable FIFO 0 Overrun Interrupt */ + /* - Disable FIFO 1 message pending Interrupt */ + /* - Disable FIFO 1 Overrun Interrupt */ + /* - Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_FMP0| + CAN_IT_FOV0| + CAN_IT_FMP1| + CAN_IT_FOV1| + CAN_IT_TME); + + /* Call Error callback function */ + HAL_CAN_ErrorCallback(hcan); + } +} + +/** + * @brief Transmission complete callback in non blocking mode + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Transmission complete callback in non blocking mode + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Check the CAN state. + (+) Check CAN Errors detected during interrupt process + +@endverbatim + * @{ + */ + +/** + * @brief return the CAN state + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +{ + /* Return CAN state */ + return hcan->State; +} + +/** + * @brief Return the CAN error code + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +{ + return hcan->ErrorCode; +} + +/** + * @} + */ +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + /* Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Disable Error warning, Error passive, Bus-off, Last error code + and Error Interrupts */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + } + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + + /* Transmission complete callback */ + HAL_CAN_TxCpltCallback(hcan); + + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan Pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber Specify the FIFO number + * @retval HAL status + * @retval None + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + uint32_t tmp1 = 0U; + CanRxMsgTypeDef* pRxMsg = NULL; + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) + { + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + + /* Get the Id */ + pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) + { + pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + } + else + { + pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + } + + pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; + /* Get the FMI */ + pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); + /* Get the data field */ + pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); + pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); + pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); + pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); + pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); + pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + + /* Disable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + + /* Disable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + tmp1 = hcan->State; + if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1)) + { + /* Disable Error warning, Error passive, Bus-off, Last error code + and Error Interrupts */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR); + } + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + + /* Receive complete callback */ + HAL_CAN_RxCpltCallback(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c index d88f321b0a..7ceb2f79c2 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -66,11 +66,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.7.2 + * @brief STM32F4xx HAL Driver version number V1.7.3 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ @@ -108,6 +108,8 @@ * @{ */ __IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ @@ -123,16 +125,16 @@ __IO uint32_t uwTick; * @verbatim =============================================================================== - ##### Initialization and de-initialization functions ##### + ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initializes the Flash interface the NVIC allocation and initial clock configuration. It initializes the systick also when timeout is needed and the backup domain when enabled. - (+) de-Initializes common part of the HAL - (+) Configure The time base source to have 1ms time base with a dedicated + (+) De-Initializes common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated Tick interrupt priority. - (++) Systick timer is used by default as source of time base, but user + (++) SysTick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose timer for example or other time source), keeping in mind that Time base duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and @@ -172,11 +174,11 @@ HAL_StatusTypeDef HAL_Init(void) { /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) - __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) - __HAL_FLASH_DATA_CACHE_ENABLE(); + __HAL_FLASH_DATA_CACHE_ENABLE(); #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) @@ -188,10 +190,10 @@ HAL_StatusTypeDef HAL_Init(void) /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); - + /* Init the low level hardware */ HAL_MspInit(); - + /* Return function status */ return HAL_OK; } @@ -227,12 +229,12 @@ HAL_StatusTypeDef HAL_DeInit(void) } /** - * @brief Initializes the MSP. + * @brief Initialize the MSP. * @retval None */ __weak void HAL_MspInit(void) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspInit could be implemented in the user file */ } @@ -243,7 +245,7 @@ __weak void HAL_MspInit(void) */ __weak void HAL_MspDeInit(void) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspDeInit could be implemented in the user file */ } @@ -257,7 +259,7 @@ __weak void HAL_MspDeInit(void) * @note In the default implementation, SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The the SysTick interrupt must have higher priority (numerically lower) + * The SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other * implementation in user file. @@ -266,11 +268,22 @@ __weak void HAL_MspDeInit(void) */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(SystemCoreClock/1000U); + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } - /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } /* Return function status */ return HAL_OK; @@ -307,14 +320,14 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. + * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - uwTick++; + uwTick += uwTickFreq; } /** @@ -328,6 +341,44 @@ __weak uint32_t HAL_GetTick(void) return uwTick; } +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + /** * @brief This function provides minimum delay (in milliseconds) based * on variable incremented. @@ -339,17 +390,17 @@ __weak uint32_t HAL_GetTick(void) * @param Delay specifies the delay time length, in milliseconds. * @retval None */ -__weak void HAL_Delay(__IO uint32_t Delay) +__weak void HAL_Delay(uint32_t Delay) { uint32_t tickstart = HAL_GetTick(); uint32_t wait = Delay; - - /* Add a period to guarantee minimum wait */ + + /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) { - wait++; + wait += (uint32_t)(uwTickFreq); } - + while((HAL_GetTick() - tickstart) < wait) { } @@ -393,7 +444,7 @@ __weak void HAL_ResumeTick(void) */ uint32_t HAL_GetHalVersion(void) { - return __STM32F4xx_HAL_VERSION; + return __STM32F4xx_HAL_VERSION; } /** @@ -402,7 +453,7 @@ uint32_t HAL_GetHalVersion(void) */ uint32_t HAL_GetREVID(void) { - return((DBGMCU->IDCODE) >> 16U); + return((DBGMCU->IDCODE) >> 16U); } /** @@ -411,7 +462,7 @@ uint32_t HAL_GetREVID(void) */ uint32_t HAL_GetDEVID(void) { - return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); } /** @@ -531,7 +582,6 @@ void HAL_EnableMemorySwappingBank(void) */ void HAL_DisableMemorySwappingBank(void) { - *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE; } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c index 50fee2c508..22a66b53ed 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c @@ -2,80 +2,135 @@ ****************************************************************************** * @file stm32f4xx_hal_can.c * @author MCD Application Team - * @brief This file provides firmware functions to manage the following + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions * + Peripheral State and Error functions * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] - (#) Enable the CAN controller interface clock using - __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2 - and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3 - -@- In case you are using CAN2 only, you have to enable the CAN1 clock. - - (#) CAN pins configuration - (++) Enable the clock for the CAN GPIOs using the following function: - __GPIOx_CLK_ENABLE() - (++) Connect and configure the involved CAN pins to AF9 using the - following function HAL_GPIO_Init() - - (#) Initialize and configure the CAN using CAN_Init() function. - - (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. - - (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. - - (#) Receive a CAN frame using HAL_CAN_Receive() function. - - (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. - - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the CAN peripheral transmission and wait the end of this operation - using HAL_CAN_Transmit(), at this stage user can specify the value of timeout - according to his end application - (+) Start the CAN peripheral reception and wait the end of this operation - using HAL_CAN_Receive(), at this stage user can specify the value of timeout - according to his end application - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() - (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() - (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine - (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_TxCpltCallback - (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_ErrorCallback - - *** CAN HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in CAN HAL driver. - - (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts - (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts - (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled - (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags - (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status - - [..] - (@) You can refer to the CAN HAL driver header file for more useful macros - + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function open-drain + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. + + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be trigged by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. + @endverbatim - ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2017 STMicroelectronics

      + *

      © COPYRIGHT(c) 2016 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -109,394 +164,243 @@ * @{ */ +#if defined(CAN1) + /** @defgroup CAN CAN * @brief CAN driver modules * @{ - */ - -#ifdef HAL_CAN_MODULE_ENABLED - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ - defined(STM32F423xx) - + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @addtogroup CAN_Private_Constants +/** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TIMEOUT_VALUE 10U +#define CAN_TIMEOUT_VALUE 10U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup CAN_Private_Functions - * @{ - */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); -/** - * @} - */ - /* Exported functions --------------------------------------------------------*/ + /** @defgroup CAN_Exported_Functions CAN Exported Functions * @{ */ -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the CAN. - (+) De-initialize the CAN. - + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + @endverbatim * @{ */ - + /** * @brief Initializes the CAN peripheral according to the specified * parameters in the CAN_InitStruct. * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { - uint32_t InitStatus = CAN_INITSTATUS_FAILED; uint32_t tickstart = 0U; - + /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); assert_param(IS_CAN_MODE(hcan->Init.Mode)); - assert_param(IS_CAN_SJW(hcan->Init.SJW)); - assert_param(IS_CAN_BS1(hcan->Init.BS1)); - assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - - if(hcan->State == HAL_CAN_STATE_RESET) + if (hcan->State == HAL_CAN_STATE_RESET) { - /* Allocate lock resource and initialize it */ - hcan->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ + /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); } - - /* Initialize the CAN state*/ - hcan->State = HAL_CAN_STATE_BUSY; - + /* Exit from sleep mode */ - hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - /* Request initialisation */ - hcan->Instance->MCR |= CAN_MCR_INRQ ; - /* Get tick */ tickstart = HAL_GetTick(); - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Check acknowledge */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) { - /* Set the time triggered communication mode */ - if (hcan->Init.TTCM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TTCM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (hcan->Init.ABOM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_ABOM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (hcan->Init.AWUM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_AWUM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (hcan->Init.NART == ENABLE) + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->Instance->MCR |= CAN_MCR_NART; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; - } + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Set the receive FIFO locked mode */ - if (hcan->Init.RFLM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_RFLM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Set the transmit FIFO priority */ - if (hcan->Init.TXFP == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TXFP; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; + return HAL_ERROR; } + } - /* Set the bit timing register */ - hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ - ((uint32_t)hcan->Init.SJW) | \ - ((uint32_t)hcan->Init.BS1) | \ - ((uint32_t)hcan->Init.BS2) | \ - ((uint32_t)hcan->Init.Prescaler - 1U); - - /* Request leave initialisation */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Check acknowledged */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - InitStatus = CAN_INITSTATUS_SUCCESS; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; } } - - if(InitStatus == CAN_INITSTATUS_SUCCESS) + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) { - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } else { - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Return function status */ - return HAL_ERROR; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } -} -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that - * contains the filter configuration information. - * @retval None - */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) -{ - uint32_t filternbrbitpos = 0U; - CAN_TypeDef *can_ip; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); - assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); - - filternbrbitpos = 1U << sFilterConfig->FilterNumber; -#if defined (CAN3) - /* Check the CAN instance */ - if(hcan->Instance == CAN3) - { - can_ip = CAN3; + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } else { - can_ip = CAN1; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } -#else - can_ip = CAN1; -#endif - - /* Initialisation mode for the filter */ - can_ip->FMR |= (uint32_t)CAN_FMR_FINIT; - -#if defined (CAN2) - /* Select the start slave bank */ - can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); - can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U); -#endif - - /* Filter Deactivation */ - can_ip->FA1R &= ~(uint32_t)filternbrbitpos; - /* Filter Scale */ - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) { - /* 16-bit scale for the filter */ - can_ip->FS1R &= ~(uint32_t)filternbrbitpos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } - - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + else { - /* 32-bit scale for the filter */ - can_ip->FS1R |= filternbrbitpos; - - /* 32-bit identifier or First 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } - /* Filter Mode */ - if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) { - /*Id/Mask mode for the filter*/ - can_ip->FM1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + else { - /*Identifier list mode for the filter*/ - can_ip->FM1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); } - /* Filter FIFO assignment */ - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + else { - /* FIFO 0 assignation for the filter */ - can_ip->FFA1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); } - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) { - /* FIFO 1 assignation for the filter */ - can_ip->FFA1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } - - /* Filter activation */ - if (sFilterConfig->FilterActivation == ENABLE) + else { - can_ip->FA1R |= filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } - /* Leave the initialisation mode for the filter */ - can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT); - + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + /* Return function status */ return HAL_OK; } /** - * @brief Deinitializes the CANx peripheral registers to their default reset values. + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) { /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* DeInit the low level hardware */ + + /* Stop the CAN module */ + HAL_CAN_Stop(hcan); + + /* DeInit the low level hardware: CLOCK, NVIC */ HAL_CAN_MspDeInit(hcan); - + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + /* Change CAN state */ hcan->State = HAL_CAN_STATE_RESET; - /* Release Lock */ - __HAL_UNLOCK(hcan); - /* Return function status */ return HAL_OK; } @@ -504,930 +408,1457 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) /** * @brief Initializes the CAN MSP. * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspInit could be implemented in the user file - */ + */ } /** * @brief DeInitializes the CAN MSP. * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspDeInit could be implemented in the user file - */ + */ } + /** * @} */ -/** @defgroup CAN_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. * -@verbatim +@verbatim ============================================================================== - ##### IO operation functions ##### + ##### Configuration functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Transmit a CAN frame message. - (+) Receive a CAN frame message. - (+) Enter CAN peripheral in sleep mode. - (+) Wake up the CAN peripheral from sleep mode. - + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + @endverbatim * @{ */ /** - * @brief Initiates and transmits a CAN frame message. + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param Timeout Specify Timeout value - * @retval HAL status + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None */ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - uint32_t tickstart = 0U; + uint32_t filternbrbitpos = 0U; + CAN_TypeDef *can_ip = hcan->Instance; - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ - ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ - ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) - { - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - switch(hcan->State) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + +#if defined(CAN3) + /* Check the CAN instance */ + if (hcan->Instance == CAN3) { - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; + /* CAN3 is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); } - - /* Select one empty transmit mailbox */ - if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + else { - transmitmailbox = CAN_TXMAILBOX_0; + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); } - else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) +#elif defined(CAN2) + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); +#else + /* CAN1 is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); +#endif + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + +#if defined(CAN3) + /* Check the CAN instance */ + if (can_ip == CAN1) { - transmitmailbox = CAN_TXMAILBOX_1; + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); } - else + +#elif defined(CAN2) + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + +#endif + /* Convert filter number into bit position */ + filternbrbitpos = (1U) << sFilterConfig->FilterBank; + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) { - transmitmailbox = CAN_TXMAILBOX_2; + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); } - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if (hcan->pTxMsg->IDE == CAN_ID_STD) + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ - hcan->pTxMsg->RTR); + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); } - else + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[0U])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[4U])); - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check End of transmission flag */ - while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - - __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + } - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); } - /* Change CAN state */ - switch(hcan->State) + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_TX */ - hcan->State = HAL_CAN_STATE_READY; - break; + SET_BIT(can_ip->FA1R, filternbrbitpos); } - /* Process unlocked */ - __HAL_UNLOCK(hcan); - + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + /* Return function status */ return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Return function status */ return HAL_ERROR; } } /** - * @brief Initiates and transmits a CAN frame message. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + +@endverbatim + * @{ + */ + +/** + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ - ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ - ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + uint32_t tickstart = 0U; + + if (hcan->State == HAL_CAN_STATE_READY) { - /* Process Locked */ - __HAL_LOCK(hcan); + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; - /* Select one empty transmit mailbox */ - if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = CAN_TXMAILBOX_0; - } - else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = CAN_TXMAILBOX_1; - } - else - { - transmitmailbox = CAN_TXMAILBOX_2; - } + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if(hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[0U])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[4U])); - - /* Change CAN state */ - switch(hcan->State) + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET) { - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - } + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hcan); + return HAL_ERROR; + } + } - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; - /* Enable Error warning, Error passive, Bus-off, - Last error and Error Interrupts */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME); + /* Return function status */ + return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; - /* Return function status */ return HAL_ERROR; } - - return HAL_OK; } /** - * @brief Receives a correct CAN frame. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber FIFO Number value - * @param Timeout Specify Timeout value + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { uint32_t tickstart = 0U; - CanRxMsgTypeDef* pRxMsg = NULL; - - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - /* Check if CAN state is not busy for RX FIFO0 */ - if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) - { - return HAL_BUSY; - } - /* Check if CAN state is not busy for RX FIFO1 */ - if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + if (hcan->State == HAL_CAN_STATE_LISTENING) { - return HAL_BUSY; - } + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Process locked */ - __HAL_LOCK(hcan); + /* Get tick */ + tickstart = HAL_GetTick(); - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) - { - switch(hcan->State) + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; } - else /* FIFONumber == CAN_FIFO1 */ + else { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - } + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + + return HAL_ERROR; } +} - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check pending message */ - while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U) +/** + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + uint32_t timeout = 1000000U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + /* Check if timeout is reached */ + if (++count > timeout) { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; } } - } + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET); - /* Set RxMsg pointer */ - if(FIFONumber == CAN_FIFO0) - { - pRxMsg = hcan->pRxMsg; + /* Return function status */ + return HAL_OK; } - else /* FIFONumber == CAN_FIFO1 */ + else { - pRxMsg = hcan->pRx1Msg; - } + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Get the Id */ - pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (pRxMsg->IDE == CAN_ID_STD) - { - pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + return HAL_ERROR; } - else +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + status = 1U; + } } - - pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); - /* Get the FIFONumber */ - pRxMsg->FIFONumber = FIFONumber; - /* Get the data field */ - pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); - - /* Release the FIFO */ - if(FIFONumber == CAN_FIFO0) + + /* Return function status */ + return status; +} + +/** + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) +{ + uint32_t transmitmailbox; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) { - /* Release FIFO0 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + assert_param(IS_CAN_STDID(pHeader->StdId)); } - else /* FIFONumber == CAN_FIFO1 */ + else { - /* Release FIFO1 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + assert_param(IS_CAN_EXTID(pHeader->ExtId)); } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - switch(hcan->State) + /* Check that all the Tx mailboxes are not full */ + if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)) { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_RX0 */ - hcan->State = HAL_CAN_STATE_READY; - break; + /* Select an empty transmit mailbox */ + transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Store the Tx mailbox */ + *pTxMailbox = 1U << transmitmailbox; + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) + else { - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - default: /* HAL_CAN_STATE_BUSY_RX1 */ - hcan->State = HAL_CAN_STATE_READY; - break; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; } } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; + return HAL_ERROR; + } } /** - * @brief Receives a correct CAN frame. - * @param hcan Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber Specify the FIFO number + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) { - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - /* Check if CAN state is not busy for RX FIFO0 */ - if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - return HAL_BUSY; - } + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET) + { + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); + } + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET) + { + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + } - /* Check if CAN state is not busy for RX FIFO1 */ - if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET) + { + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); + } + + /* Return function status */ + return HAL_OK; + } + else { - return HAL_BUSY; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; } +} - /* Process locked */ - __HAL_LOCK(hcan); +/** + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +{ + uint32_t freelevel = 0U; - /* Change CAN state */ - if(FIFONumber == CAN_FIFO0) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - switch(hcan->State) + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; + freelevel++; } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; + freelevel++; } - } - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - /* - Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME); - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - if(FIFONumber == CAN_FIFO0) - { - /* Enable FIFO 0 overrun and message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET) + { + freelevel++; + } } - else + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Enable FIFO 1 overrun and message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) + { + status = 1U; + } } - /* Return function status */ - return HAL_OK; + /* Return status */ + return status; } /** - * @brief Enters the Sleep (low power) mode. + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @retval HAL status. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. */ -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) { - uint32_t tickstart = 0U; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Request Sleep mode */ - hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + uint32_t timestamp = 0U; + uint32_t transmitmailbox; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); - /* Sleep mode status */ - if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Select the Tx mailbox */ + transmitmailbox = POSITION_VAL(TxMailbox); - /* Return function status */ - return HAL_ERROR; + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; } - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + /* Return the timestamp */ + return timestamp; +} + +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } } - } + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + return HAL_ERROR; + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos; + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos; + aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos; + aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos; + aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos; + aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos; + aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos; + aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos; + aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos; + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + } - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Return function status */ - return HAL_OK; + return HAL_ERROR; + } } /** - * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral - * is in the normal mode. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @retval HAL status. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. */ -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) { - uint32_t tickstart = 0U; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Wake up request */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + uint32_t filllevel = 0U; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); - /* Sleep mode status */ - while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + if (RxFifo == CAN_RX_FIFO0) { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ + { + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; } } - if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Process unlocked */ - __HAL_UNLOCK(hcan); - + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + return HAL_ERROR; } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; } /** - * @brief Handles CAN interrupt request - * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @retval None + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status */ -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) { - uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U; - uint32_t errorcode = HAL_CAN_ERROR_NONE; + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); - /* Check Overrun flag for FIFO0 */ - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0); - if(tmp1 && tmp2) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Set CAN error code to FOV0 error */ - errorcode |= HAL_CAN_ERROR_FOV0; + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); - /* Clear FIFO0 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + /* Return function status */ + return HAL_OK; } - /* Check Overrun flag for FIFO1 */ - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1); - - if(tmp1 && tmp2) + else { - /* Set CAN error code to FOV1 error */ - errorcode |= HAL_CAN_ERROR_FOV1; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Clear FIFO1 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + return HAL_ERROR; } +} - /* Check End of transmission flag */ - if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET) { - tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0); - tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1); - tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2); - if(tmp1 || tmp2 || tmp3) + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != RESET) + { + /* Transmission Mailbox 0 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != RESET) { - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0); - tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1); - tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2); - /* Check Transmit success */ - if(tmp1 || tmp2 || tmp3) + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != RESET) { - /* Call transmit function */ - CAN_Transmit_IT(hcan); + /* Transmission Mailbox 1 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); } - else /* Transmit failure */ + else { - /* Set CAN error code to TXFAIL error */ - errorcode |= HAL_CAN_ERROR_TXFAIL; + if ((tsrflags & CAN_TSR_ALST1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); + } } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); - /* Clear transmission status flags (RQCPx and TXOKx) */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \ - CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2); + if ((tsrflags & CAN_TSR_TXOK2) != RESET) + { + /* Transmission Mailbox 2 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); + } + } } } - tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0); - /* Check End of reception flag for FIFO0 */ - if((tmp1 != 0U) && tmp2) + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET) { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO0); + if ((rf0rflags & CAN_RF0R_FOVR0) != RESET) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } } - tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1); - /* Check End of reception flag for FIFO1 */ - if((tmp1 != 0U) && tmp2) + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET) { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO1); + if ((rf0rflags & CAN_RF0R_FULL0) != RESET) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + + /* Receive FIFO 0 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); + } } - /* Set error code in handle */ - hcan->ErrorCode |= errorcode; + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET) + { + /* Receive FIFO 0 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); + } + } - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Error Warning Flag */ - if(tmp1 && tmp2 && tmp3) + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET) { - /* Set CAN error code to EWG error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EWG; + if ((rf1rflags & CAN_RF1R_FOVR1) != RESET) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } } - - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Error Passive Flag */ - if(tmp1 && tmp2 && tmp3) + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET) { - /* Set CAN error code to EPV error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EPV; + if ((rf1rflags & CAN_RF1R_FULL1) != RESET) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); + } } - - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Bus-Off Flag */ - if(tmp1 && tmp2 && tmp3) + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET) { - /* Set CAN error code to BOF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BOF; + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET) + { + /* Receive FIFO 1 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); + } } - - tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Last error code Flag */ - if((!tmp1) && tmp2 && tmp3) + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != RESET) { - tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC; - switch(tmp1) + if ((msrflags & CAN_MSR_SLAKI) != RESET) { - case(CAN_ESR_LEC_0): - /* Set CAN error code to STF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_STF; - break; - case(CAN_ESR_LEC_1): - /* Set CAN error code to FOR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_FOR; - break; - case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): - /* Set CAN error code to ACK error */ - hcan->ErrorCode |= HAL_CAN_ERROR_ACK; - break; - case(CAN_ESR_LEC_2): - /* Set CAN error code to BR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BR; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): - /* Set CAN error code to BD error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BD; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): - /* Set CAN error code to CRC error */ - hcan->ErrorCode |= HAL_CAN_ERROR_CRC; - break; - default: - break; + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != RESET) + { + if ((msrflags & CAN_MSR_WKUI) != RESET) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); - /* Clear Last error code Flag */ - hcan->Instance->ESR &= ~(CAN_ESR_LEC); + /* WakeUp Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); + } } - - /* Call the Error call Back in case of Errors */ - if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != RESET) { - /* Clear ERRI Flag */ - hcan->Instance->MSR = CAN_MSR_ERRI; - /* Set the CAN state ready to be able to start again the process */ - hcan->State = HAL_CAN_STATE_READY; + if ((msrflags & CAN_MSR_ERRI) != RESET) + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) && + ((esrflags & CAN_ESR_EWGF) != RESET)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) && + ((esrflags & CAN_ESR_EPVF) != RESET)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != RESET) && + ((esrflags & CAN_ESR_BOFF) != RESET)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) && + ((esrflags & CAN_ESR_LEC) != RESET)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } + } + + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); + } - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - /* - Disable FIFO 0 message pending Interrupt */ - /* - Disable FIFO 0 Overrun Interrupt */ - /* - Disable FIFO 1 message pending Interrupt */ - /* - Disable FIFO 1 Overrun Interrupt */ - /* - Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_FMP0| - CAN_IT_FOV0| - CAN_IT_FMP1| - CAN_IT_FOV1| - CAN_IT_TME); + /* Call the Error call Back in case of Errors */ + if (errorcode != HAL_CAN_ERROR_NONE) + { + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; /* Call Error callback function */ + /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); - } + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback + +@endverbatim + * @{ + */ + +/** + * @brief Transmission Mailbox 0 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ } /** - * @brief Transmission complete callback in non blocking mode + * @brief Transmission Mailbox 1 complete callback. * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxCpltCallback could be implemented in the user file + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file */ } /** - * @brief Transmission complete callback in non blocking mode + * @brief Transmission Mailbox 2 complete callback. * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxCpltCallback could be implemented in the user file + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Sleep callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + +/** + * @brief WakeUp from Rx message callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file */ } @@ -1441,6 +1872,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ @@ -1450,230 +1882,110 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) * @} */ -/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * -@verbatim +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim ============================================================================== ##### Peripheral State and Error functions ##### ============================================================================== [..] This subsection provides functions allowing to : - (+) Check the CAN state. - (+) Check CAN Errors detected during interrupt process - + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + @endverbatim * @{ */ /** - * @brief return the CAN state + * @brief Return the CAN state. * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL state */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) { + HAL_CAN_StateTypeDef state = hcan->State; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + } + /* Return CAN state */ - return hcan->State; + return state; } /** - * @brief Return the CAN error code + * @brief Return the CAN error code. * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval CAN Error Code */ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) { + /* Return CAN error code */ return hcan->ErrorCode; } /** - * @} - */ -/** - * @brief Initiates and transmits a CAN frame message. + * @brief Reset the CAN error code. * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) -{ - /* Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Disable Error warning, Error passive, Bus-off, Last error code - and Error Interrupts */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - } - - /* Change CAN state */ - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_TX */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - - /* Transmission complete callback */ - HAL_CAN_TxCpltCallback(hcan); - - return HAL_OK; -} - -/** - * @brief Receives a correct CAN frame. - * @param hcan Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber Specify the FIFO number + * the configuration information for the specified CAN. * @retval HAL status - * @retval None */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) { - uint32_t tmp1 = 0U; - CanRxMsgTypeDef* pRxMsg = NULL; + HAL_StatusTypeDef status = HAL_OK; - /* Set RxMsg pointer */ - if(FIFONumber == CAN_FIFO0) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - pRxMsg = hcan->pRxMsg; - } - else /* FIFONumber == CAN_FIFO1 */ - { - pRxMsg = hcan->pRx1Msg; - } - - /* Get the Id */ - pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (pRxMsg->IDE == CAN_ID_STD) - { - pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + /* Reset CAN error code */ + hcan->ErrorCode = 0U; } else { - pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); - } - - pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FIFONumber */ - pRxMsg->FIFONumber = FIFONumber; - /* Get the FMI */ - pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); - /* Get the data field */ - pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - - /* Disable FIFO 0 overrun and message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - - /* Disable FIFO 1 overrun and message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); - } + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - tmp1 = hcan->State; - if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1)) - { - /* Disable Error warning, Error passive, Bus-off, Last error code - and Error Interrupts */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR); + status = HAL_ERROR; } - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_RX0 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - default: /* HAL_CAN_STATE_BUSY_RX1 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - } - - /* Receive complete callback */ - HAL_CAN_RxCpltCallback(hcan); - - /* Return function status */ - return HAL_OK; + /* Return the status */ + return status; } /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/** + * @} + */ #endif /* HAL_CAN_MODULE_ENABLED */ + /** * @} */ +#endif /* CAN1 */ + /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c index fc76f04c4f..72da49fa7e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c @@ -105,6 +105,12 @@ (++) FMPI2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer if no direction change and with a final stop condition in both cases + (++) FMPI2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential + interface several times (link with option FMPI2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using HAL_FMPI2C_Master_Sequential_Transmit_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME) + or HAL_FMPI2C_Master_Sequential_Receive_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME). + Then usage of this option FMPI2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. (+) Differents sequential FMPI2C interfaces are listed below: (++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Sequential_Transmit_IT() diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c index a09ebb9119..37e482cb56 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c @@ -406,23 +406,33 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { + FlagStatus pwrclkchanged = RESET; + /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - /* Enable Power Clock */ - __HAL_RCC_PWR_CLK_ENABLE(); + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } - /* Enable write access to Backup domain */ - PWR->CR |= PWR_CR_DBP; + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); - /* Wait for Backup domain Write protection enable */ - tickstart = HAL_GetTick(); + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); - while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { - return HAL_TIMEOUT; + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } } } @@ -457,6 +467,12 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc } } } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c index 7af5fdb22c..185c070733 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c @@ -2785,6 +2785,241 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode) #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of PLLI2S, PLLSAI. +@endverbatim + * @{ + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Enable PLLI2S. + * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that + * contains the configuration information for the PLLI2S + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR)); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM)); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ +#if defined(RCC_PLLI2SCFGR_PLLI2SP) + assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP)); +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ)); +#endif /* RCC_PLLI2SCFGR_PLLI2SQ */ + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLI2S division factors */ +#if defined(STM32F446xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SPCLK = PLLI2S_VCO / PLLI2SP */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ + PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ + PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F411xE) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); +#else + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); +#endif /* STM32F446xx */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Wait till PLLI2S is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLI2S. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +{ + uint32_t tickstart; + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Enable PLLSAI. + * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that + * contains the configuration information for the PLLSAI + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN)); + assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ)); +#if defined(RCC_PLLSAICFGR_PLLSAIM) + assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM)); +#endif /* RCC_PLLSAICFGR_PLLSAIM */ +#if defined(RCC_PLLSAICFGR_PLLSAIP) + assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP)); +#endif /* RCC_PLLSAICFGR_PLLSAIP */ +#if defined(RCC_PLLSAICFGR_PLLSAIR) + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR)); +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLSAI division factors */ +#if defined(STM32F446xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \ + PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U); +#elif defined(STM32F469xx) || defined(STM32F479xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ + PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#else + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#endif /* STM32F446xx */ + + /* Enable the PLLSAI */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Wait till PLLSAI is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLSAI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void) +{ + uint32_t tickstart; + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @} + */ + #if defined(STM32F446xx) /** * @brief Returns the SYSCLK frequency @@ -3042,10 +3277,32 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) #endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F469xx || STM32F479xx */ /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE); + +#if defined(RCC_CIR_PLLI2SRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +#endif /* RCC_CIR_PLLI2SRDYIE */ - /* Clear all flags */ - CLEAR_REG(RCC->CSR); +#if defined(RCC_CIR_PLLSAIRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +#endif /* RCC_CIR_PLLSAIRDYIE */ + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC); + +#if defined(RCC_CIR_PLLI2SRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); +#endif /* RCC_CIR_PLLI2SRDYC */ + +#if defined(RCC_CIR_PLLSAIRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); +#endif /* RCC_CIR_PLLSAIRDYC */ + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; @@ -3257,23 +3514,33 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { + FlagStatus pwrclkchanged = RESET; + /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } - /* Enable write access to Backup domain */ - PWR->CR |= PWR_CR_DBP; + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); - while((PWR->CR & PWR_CR_DBP) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { - return HAL_TIMEOUT; + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } } } @@ -3308,6 +3575,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c index c34e7a4b08..6325c9ad3a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c @@ -1155,7 +1155,7 @@ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTyp /* Clear TAR, TCLR, PWAITEN and PWID bits */ tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \ - FMC_PCR4_PWID)); + FMC_PCR4_PWID | FMC_PCR4_PTYP)); /* Set FMC_PCCARD device control parameters */ tmpr |= (uint32_t)(Init->Waitfeature |\ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c index 5d5aa48d75..3964bb69a4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c @@ -865,7 +865,7 @@ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_Init /* Clear TAR, TCLR, PWAITEN and PWID bits */ tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \ - FSMC_PCR4_PWID)); + FSMC_PCR4_PWID | FSMC_PCR4_PTYP)); /* Set FSMC_PCCARD device control parameters */ tmpr |= (uint32_t)(Init->Waitfeature |\ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c index 9393409f94..0747b0ed85 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c @@ -252,10 +252,32 @@ ErrorStatus LL_RCC_DeInit(void) #endif /* RCC_PLLSAI_SUPPORT */ /* Disable all interrupts */ - LL_RCC_WriteReg(CIR, 0x00000000U); + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE); - /* Clear all interrupts flags */ - LL_RCC_WriteReg(CSR, 0x00000000U); +#if defined(RCC_CIR_PLLI2SRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +#endif /* RCC_CIR_PLLI2SRDYIE */ + +#if defined(RCC_CIR_PLLSAIRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +#endif /* RCC_CIR_PLLSAIRDYIE */ + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC); + +#if defined(RCC_CIR_PLLI2SRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); +#endif /* RCC_CIR_PLLI2SRDYC */ + +#if defined(RCC_CIR_PLLSAIRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); +#endif /* RCC_CIR_PLLSAIRDYC */ + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); return SUCCESS; } diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 7b88f655e2..379be2a3e9 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -4,7 +4,7 @@ * STM32F1: 1.1.1 * STM32F2: 1.2.2 * STM32F3: 1.5.0 - * STM32F4: 1.7.2 + * STM32F4: 1.7.3 * STM32F7: 1.2.3 * STM32L0: 1.8.2 * STM32L1: 1.3.1 From 42d9759acba6e56c7db97d01f0221c0fdbc2fb64 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 24 Jan 2018 09:47:37 +0100 Subject: [PATCH 6/9] Updated stm32f4xx_hal_conf.h in variant Signed-off-by: Frederic Pillon --- variants/DISCO_F407VG/stm32f4xx_hal_conf.h | 174 ++++++++++---------- variants/NUCLEO_F401RE/stm32f4xx_hal_conf.h | 102 ++++++------ variants/NUCLEO_F411RE/stm32f4xx_hal_conf.h | 102 ++++++------ variants/NUCLEO_F429ZI/stm32f4xx_hal_conf.h | 81 +++++---- variants/NUCLEO_F446RE/stm32f4xx_hal_conf.h | 46 +++--- 5 files changed, 257 insertions(+), 248 deletions(-) diff --git a/variants/DISCO_F407VG/stm32f4xx_hal_conf.h b/variants/DISCO_F407VG/stm32f4xx_hal_conf.h index ce683494c7..10a4072b55 100644 --- a/variants/DISCO_F407VG/stm32f4xx_hal_conf.h +++ b/variants/DISCO_F407VG/stm32f4xx_hal_conf.h @@ -1,16 +1,11 @@ /** ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @version V1.5.1 - * @date 01-July-2016 - * @brief HAL configuration template file. - * This file should be copied to the application folder and renamed - * to stm32f4xx_hal_conf.h. + * @file stm32f4xx_hal_conf.h + * @brief HAL configuration file. ****************************************************************************** * @attention * - *

      © COPYRIGHT(c) 2016 STMicroelectronics

      + *

      © COPYRIGHT(c) 2017 STMicroelectronics

      * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -54,49 +49,51 @@ */ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED -// #define HAL_CAN_MODULE_ENABLED -// #define HAL_CRC_MODULE_ENABLED -// #define HAL_CEC_MODULE_ENABLED -// #define HAL_CRYP_MODULE_ENABLED +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ #define HAL_DAC_MODULE_ENABLED -// #define HAL_DCMI_MODULE_ENABLED +/* #define HAL_DCMI_MODULE_ENABLED */ #define HAL_DMA_MODULE_ENABLED -// #define HAL_DMA2D_MODULE_ENABLED -// #define HAL_ETH_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ #define HAL_FLASH_MODULE_ENABLED -// #define HAL_NAND_MODULE_ENABLED -// #define HAL_NOR_MODULE_ENABLED -// #define HAL_PCCARD_MODULE_ENABLED -// #define HAL_SRAM_MODULE_ENABLED -// #define HAL_SDRAM_MODULE_ENABLED -// #define HAL_HASH_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED -// #define HAL_I2S_MODULE_ENABLED -// #define HAL_IWDG_MODULE_ENABLED -// #define HAL_LTDC_MODULE_ENABLED -// #define HAL_DSI_MODULE_ENABLED +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED -// #define HAL_QSPI_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ #define HAL_RCC_MODULE_ENABLED -// #define HAL_RNG_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ #define HAL_RTC_MODULE_ENABLED -// #define HAL_SAI_MODULE_ENABLED -// #define HAL_SD_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED -// #define HAL_USART_MODULE_ENABLED -// #define HAL_IRDA_MODULE_ENABLED -// #define HAL_SMARTCARD_MODULE_ENABLED -// #define HAL_WWDG_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ #define HAL_CORTEX_MODULE_ENABLED #define HAL_PCD_MODULE_ENABLED #define HAL_HCD_MODULE_ENABLED -// #define HAL_FMPI2C_MODULE_ENABLED -// #define HAL_SPDIFRX_MODULE_ENABLED -// #define HAL_DFSDM_MODULE_ENABLED -// #define HAL_LPTIM_MODULE_ENABLED +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ /* ########################## HSE/HSI Values adaptation ##################### */ /** @@ -105,11 +102,11 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -118,26 +115,26 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */ #endif /* HSI_VALUE */ /** * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ /** * @brief External Low Speed oscillator (LSE) value. */ #if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ /** @@ -146,7 +143,7 @@ * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -156,8 +153,8 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ #define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U @@ -185,56 +182,56 @@ /* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ +#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ /* Section 2: PHY configuration section */ /* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U +#define DP83848_PHY_ADDRESS 0x01U /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +#define PHY_RESET_DELAY 0x000000FFU /* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) +#define PHY_CONFIG_DELAY 0x00000FFFU -#define PHY_READ_TO ((uint32_t)0x0000FFFFU) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) +#define PHY_READ_TO 0x0000FFFFU +#define PHY_WRITE_TO 0x0000FFFFU /* Section 3: Common PHY Registers */ -#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ +#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ /* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x0010U) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011U) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012U) /*!< MII Interrupt Status and Misc. Control Register */ +#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ -#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ +#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ -#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */ +#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ /* ################## SPI peripheral configuration ########################## */ @@ -274,6 +271,10 @@ #include "stm32f4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CRC_MODULE_ENABLED #include "stm32f4xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ @@ -426,24 +427,27 @@ #include "stm32f4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function + * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t* file, uint32_t line); #else - #define assert_param(expr) ((void)0) + #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ - #ifdef __cplusplus } #endif diff --git a/variants/NUCLEO_F401RE/stm32f4xx_hal_conf.h b/variants/NUCLEO_F401RE/stm32f4xx_hal_conf.h index 1a69a256e0..3dff96e9f6 100644 --- a/variants/NUCLEO_F401RE/stm32f4xx_hal_conf.h +++ b/variants/NUCLEO_F401RE/stm32f4xx_hal_conf.h @@ -1,7 +1,7 @@ /** ****************************************************************************** * @file stm32f4xx_hal_conf.h - * @brief HAL configuration file. + * @brief HAL configuration file. ****************************************************************************** * @attention * @@ -30,7 +30,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CONF_H @@ -45,34 +45,40 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED - +#define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED -/* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ /* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_DAC_MODULE_ENABLED */ /* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED /* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ +#define HAL_FLASH_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_PCCARD_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ /* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED /* #define HAL_I2S_MODULE_ENABLED */ /* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +#define HAL_PWR_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ /* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED @@ -80,30 +86,22 @@ /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED /* #define HAL_PCD_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */ /* #define HAL_SPDIFRX_MODULE_ENABLED */ /* #define HAL_DFSDM_MODULE_ENABLED */ /* #define HAL_LPTIM_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED +/* #define HAL_MMC_MODULE_ENABLED */ /* ########################## HSE/HSI Values adaptation ##################### */ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -114,7 +112,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */ @@ -123,11 +121,11 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ /** * @brief External Low Speed oscillator (LSE) value. */ @@ -141,8 +139,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/ @@ -157,14 +155,14 @@ */ #define VDD_VALUE 3300U /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ -#define USE_RTOS 0U +#define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U #define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -181,7 +179,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -190,8 +188,8 @@ /* Section 2: PHY configuration section */ /* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY 0x000000FFU /* PHY Configuration delay */ #define PHY_CONFIG_DELAY 0x00000FFFU @@ -203,7 +201,7 @@ #define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -218,7 +216,7 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ @@ -246,7 +244,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -260,7 +258,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -273,12 +271,16 @@ #include "stm32f4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CRC_MODULE_ENABLED #include "stm32f4xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED @@ -300,7 +302,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -315,11 +317,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -361,10 +363,6 @@ #include "stm32f4xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - #ifdef HAL_SPI_MODULE_ENABLED #include "stm32f4xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ @@ -400,7 +398,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -428,14 +426,18 @@ #ifdef HAL_LPTIM_MODULE_ENABLED #include "stm32f4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ - + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function + * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ @@ -444,13 +446,13 @@ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ +#endif /* USE_FULL_ASSERT */ #ifdef __cplusplus } #endif #endif /* __STM32F4xx_HAL_CONF_H */ - + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/NUCLEO_F411RE/stm32f4xx_hal_conf.h b/variants/NUCLEO_F411RE/stm32f4xx_hal_conf.h index 1a69a256e0..3dff96e9f6 100644 --- a/variants/NUCLEO_F411RE/stm32f4xx_hal_conf.h +++ b/variants/NUCLEO_F411RE/stm32f4xx_hal_conf.h @@ -1,7 +1,7 @@ /** ****************************************************************************** * @file stm32f4xx_hal_conf.h - * @brief HAL configuration file. + * @brief HAL configuration file. ****************************************************************************** * @attention * @@ -30,7 +30,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CONF_H @@ -45,34 +45,40 @@ /* ########################## Module Selection ############################## */ /** - * @brief This is the list of modules to be used in the HAL driver + * @brief This is the list of modules to be used in the HAL driver */ -#define HAL_MODULE_ENABLED - +#define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED -/* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ /* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_DAC_MODULE_ENABLED */ /* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED /* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ +#define HAL_FLASH_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_PCCARD_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ /* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED /* #define HAL_I2S_MODULE_ENABLED */ /* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +#define HAL_PWR_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ /* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED @@ -80,30 +86,22 @@ /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED /* #define HAL_PCD_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */ /* #define HAL_SPDIFRX_MODULE_ENABLED */ /* #define HAL_DFSDM_MODULE_ENABLED */ /* #define HAL_LPTIM_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED +/* #define HAL_MMC_MODULE_ENABLED */ /* ########################## HSE/HSI Values adaptation ##################### */ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). + * (when HSE is used as system clock source, directly or through the PLL). */ -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -114,7 +112,7 @@ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). + * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */ @@ -123,11 +121,11 @@ /** * @brief Internal Low Speed oscillator (LSI) value. */ -#if !defined (LSI_VALUE) +#if !defined (LSI_VALUE) #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ /** * @brief External Low Speed oscillator (LSE) value. */ @@ -141,8 +139,8 @@ /** * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/ @@ -157,14 +155,14 @@ */ #define VDD_VALUE 3300U /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ -#define USE_RTOS 0U +#define USE_RTOS 0U #define PREFETCH_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U #define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** - * @brief Uncomment the line below to expanse the "assert_param" macro in the + * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ @@ -181,7 +179,7 @@ #define MAC_ADDR4 0U #define MAC_ADDR5 0U -/* Definition of the Ethernet driver buffers size and count */ +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ @@ -190,8 +188,8 @@ /* Section 2: PHY configuration section */ /* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY 0x000000FFU /* PHY Configuration delay */ #define PHY_CONFIG_DELAY 0x00000FFFU @@ -203,7 +201,7 @@ #define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - + #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -218,7 +216,7 @@ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - + /* Section 4: Extended PHY Registers */ #define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ @@ -246,7 +244,7 @@ /* Includes ------------------------------------------------------------------*/ /** - * @brief Include module's header file + * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED @@ -260,7 +258,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -273,12 +271,16 @@ #include "stm32f4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CRC_MODULE_ENABLED #include "stm32f4xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" + #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DMA2D_MODULE_ENABLED @@ -300,7 +302,7 @@ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ - + #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ @@ -315,11 +317,11 @@ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - +#endif /* HAL_PCCARD_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED #include "stm32f4xx_hal_hash.h" @@ -361,10 +363,6 @@ #include "stm32f4xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - #ifdef HAL_SPI_MODULE_ENABLED #include "stm32f4xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ @@ -400,7 +398,7 @@ #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f4xx_hal_hcd.h" #endif /* HAL_HCD_MODULE_ENABLED */ - + #ifdef HAL_DSI_MODULE_ENABLED #include "stm32f4xx_hal_dsi.h" #endif /* HAL_DSI_MODULE_ENABLED */ @@ -428,14 +426,18 @@ #ifdef HAL_LPTIM_MODULE_ENABLED #include "stm32f4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ - + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function + * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source - * line number of the call that failed. + * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ @@ -444,13 +446,13 @@ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ +#endif /* USE_FULL_ASSERT */ #ifdef __cplusplus } #endif #endif /* __STM32F4xx_HAL_CONF_H */ - + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/NUCLEO_F429ZI/stm32f4xx_hal_conf.h b/variants/NUCLEO_F429ZI/stm32f4xx_hal_conf.h index a1b0ab3776..29a35eaed0 100644 --- a/variants/NUCLEO_F429ZI/stm32f4xx_hal_conf.h +++ b/variants/NUCLEO_F429ZI/stm32f4xx_hal_conf.h @@ -1,12 +1,7 @@ /** ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 - * @brief HAL configuration template file. - * This file should be copied to the application folder and renamed - * to stm32f4xx_hal_conf.h. + * @file stm32f4xx_hal_conf.h + * @brief HAL configuration file. ****************************************************************************** * @attention * @@ -54,50 +49,51 @@ */ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED -// #define HAL_CAN_MODULE_ENABLED -// #define HAL_CRC_MODULE_ENABLED -// #define HAL_CEC_MODULE_ENABLED -// #define HAL_CRYP_MODULE_ENABLED +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ #define HAL_DAC_MODULE_ENABLED -// #define HAL_DCMI_MODULE_ENABLED +/* #define HAL_DCMI_MODULE_ENABLED */ #define HAL_DMA_MODULE_ENABLED -// #define HAL_DMA2D_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ #define HAL_ETH_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED -// #define HAL_NAND_MODULE_ENABLED -// #define HAL_NOR_MODULE_ENABLED -// #define HAL_PCCARD_MODULE_ENABLED -// #define HAL_SRAM_MODULE_ENABLED -// #define HAL_SDRAM_MODULE_ENABLED -// #define HAL_HASH_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED -// #define HAL_I2S_MODULE_ENABLED -// #define HAL_IWDG_MODULE_ENABLED -// #define HAL_LTDC_MODULE_ENABLED -// #define HAL_DSI_MODULE_ENABLED +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED -// #define HAL_QSPI_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ #define HAL_RCC_MODULE_ENABLED -// #define HAL_RNG_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ #define HAL_RTC_MODULE_ENABLED -// #define HAL_SAI_MODULE_ENABLED -// #define HAL_SD_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED -// #define HAL_USART_MODULE_ENABLED -// #define HAL_IRDA_MODULE_ENABLED -// #define HAL_SMARTCARD_MODULE_ENABLED -// #define HAL_WWDG_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ #define HAL_CORTEX_MODULE_ENABLED #define HAL_PCD_MODULE_ENABLED #define HAL_HCD_MODULE_ENABLED -// #define HAL_FMPI2C_MODULE_ENABLED -// #define HAL_SPDIFRX_MODULE_ENABLED -// #define HAL_DFSDM_MODULE_ENABLED -// #define HAL_LPTIM_MODULE_ENABLED -//#define HAL_MMC_MODULE_ENABLED +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ /* ########################## HSE/HSI Values adaptation ##################### */ /** @@ -127,9 +123,9 @@ */ #if !defined (LSI_VALUE) #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ /** * @brief External Low Speed oscillator (LSE) value. */ @@ -270,6 +266,10 @@ #include "stm32f4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CRC_MODULE_ENABLED #include "stm32f4xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ @@ -430,7 +430,7 @@ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function + * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source * line number of the call that failed. * If expr is true, it returns no value. @@ -443,7 +443,6 @@ #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ - #ifdef __cplusplus } #endif diff --git a/variants/NUCLEO_F446RE/stm32f4xx_hal_conf.h b/variants/NUCLEO_F446RE/stm32f4xx_hal_conf.h index 739c00b669..e98ba0870d 100644 --- a/variants/NUCLEO_F446RE/stm32f4xx_hal_conf.h +++ b/variants/NUCLEO_F446RE/stm32f4xx_hal_conf.h @@ -48,31 +48,37 @@ * @brief This is the list of modules to be used in the HAL driver */ #define HAL_MODULE_ENABLED - #define HAL_ADC_MODULE_ENABLED -/* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ /* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */ #define HAL_DAC_MODULE_ENABLED /* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED /* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ +#define HAL_FLASH_MODULE_ENABLED /* #define HAL_NAND_MODULE_ENABLED */ /* #define HAL_NOR_MODULE_ENABLED */ /* #define HAL_PCCARD_MODULE_ENABLED */ /* #define HAL_SRAM_MODULE_ENABLED */ /* #define HAL_SDRAM_MODULE_ENABLED */ /* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED /* #define HAL_I2S_MODULE_ENABLED */ /* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +#define HAL_PWR_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RCC_MODULE_ENABLED /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ /* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED @@ -80,22 +86,14 @@ /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED /* #define HAL_PCD_MODULE_ENABLED */ /* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */ /* #define HAL_SPDIFRX_MODULE_ENABLED */ /* #define HAL_DFSDM_MODULE_ENABLED */ /* #define HAL_LPTIM_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED +/* #define HAL_MMC_MODULE_ENABLED */ /* ########################## HSE/HSI Values adaptation ##################### */ /** @@ -125,9 +123,9 @@ */ #if !defined (LSI_VALUE) #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ /** * @brief External Low Speed oscillator (LSE) value. */ @@ -190,7 +188,7 @@ /* Section 2: PHY configuration section */ /* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U +#define DP83848_PHY_ADDRESS 0x01U /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY 0x000000FFU /* PHY Configuration delay */ @@ -273,6 +271,10 @@ #include "stm32f4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CRC_MODULE_ENABLED #include "stm32f4xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ @@ -361,10 +363,6 @@ #include "stm32f4xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - #ifdef HAL_SPI_MODULE_ENABLED #include "stm32f4xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ @@ -429,11 +427,15 @@ #include "stm32f4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function + * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source * line number of the call that failed. * If expr is true, it returns no value. From b85eaadbb173e561102c909eca81c767e174efb0 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 24 Jan 2018 10:49:00 +0100 Subject: [PATCH 7/9] Updated STM32F7xx HAL Drivers to v1.2.4 Included in STM32CubeF7 FW V1.9.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 648 ++-- .../Inc/Legacy/stm32f7xx_hal_can_legacy.h | 777 +++++ .../Inc/stm32_assert_template.h | 2 +- .../STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h | 33 +- .../Inc/stm32f7xx_hal_adc.h | 68 +- .../Inc/stm32f7xx_hal_adc_ex.h | 6 +- .../Inc/stm32f7xx_hal_can.h | 739 ++--- .../Inc/stm32f7xx_hal_cec.h | 46 +- .../Inc/stm32f7xx_hal_conf_template.h | 11 +- .../Inc/stm32f7xx_hal_crc.h | 14 +- .../Inc/stm32f7xx_hal_crc_ex.h | 8 +- .../Inc/stm32f7xx_hal_cryp.h | 64 +- .../Inc/stm32f7xx_hal_cryp_ex.h | 4 +- .../Inc/stm32f7xx_hal_dac.h | 36 +- .../Inc/stm32f7xx_hal_dcmi.h | 26 +- .../Inc/stm32f7xx_hal_def.h | 25 +- .../Inc/stm32f7xx_hal_dfsdm.h | 4 +- .../Inc/stm32f7xx_hal_dma.h | 178 +- .../Inc/stm32f7xx_hal_dma2d.h | 24 +- .../Inc/stm32f7xx_hal_dma_ex.h | 32 +- .../Inc/stm32f7xx_hal_dsi.h | 36 +- .../Inc/stm32f7xx_hal_eth.h | 148 +- .../Inc/stm32f7xx_hal_flash.h | 10 +- .../Inc/stm32f7xx_hal_flash_ex.h | 2 +- .../Inc/stm32f7xx_hal_gpio.h | 10 +- .../Inc/stm32f7xx_hal_gpio_ex.h | 2 +- .../Inc/stm32f7xx_hal_hash.h | 6 +- .../Inc/stm32f7xx_hal_i2c.h | 64 +- .../Inc/stm32f7xx_hal_i2c_ex.h | 14 +- .../Inc/stm32f7xx_hal_i2s.h | 20 +- .../Inc/stm32f7xx_hal_irda.h | 54 +- .../Inc/stm32f7xx_hal_irda_ex.h | 6 +- .../Inc/stm32f7xx_hal_iwdg.h | 14 +- .../Inc/stm32f7xx_hal_jpeg.h | 26 +- .../Inc/stm32f7xx_hal_lptim.h | 96 +- .../Inc/stm32f7xx_hal_ltdc.h | 36 +- .../Inc/stm32f7xx_hal_mdios.h | 32 +- .../Inc/stm32f7xx_hal_mmc.h | 24 +- .../Inc/stm32f7xx_hal_nand.h | 10 +- .../Inc/stm32f7xx_hal_nor.h | 12 +- .../Inc/stm32f7xx_hal_pcd.h | 43 +- .../Inc/stm32f7xx_hal_pwr.h | 6 +- .../Inc/stm32f7xx_hal_pwr_ex.h | 6 +- .../Inc/stm32f7xx_hal_qspi.h | 26 +- .../Inc/stm32f7xx_hal_rcc.h | 72 +- .../Inc/stm32f7xx_hal_rcc_ex.h | 107 +- .../Inc/stm32f7xx_hal_rng.h | 26 +- .../Inc/stm32f7xx_hal_rtc.h | 38 +- .../Inc/stm32f7xx_hal_rtc_ex.h | 108 +- .../Inc/stm32f7xx_hal_sai.h | 18 +- .../Inc/stm32f7xx_hal_sd.h | 24 +- .../Inc/stm32f7xx_hal_sdram.h | 2 +- .../Inc/stm32f7xx_hal_smartcard.h | 54 +- .../Inc/stm32f7xx_hal_smartcard_ex.h | 10 +- .../Inc/stm32f7xx_hal_smbus.h | 32 +- .../Inc/stm32f7xx_hal_spdifrx.h | 24 +- .../Inc/stm32f7xx_hal_spi.h | 32 +- .../Inc/stm32f7xx_hal_sram.h | 2 +- .../Inc/stm32f7xx_hal_tim.h | 397 ++- .../Inc/stm32f7xx_hal_tim_ex.h | 18 +- .../Inc/stm32f7xx_hal_uart.h | 76 +- .../Inc/stm32f7xx_hal_uart_ex.h | 6 +- .../Inc/stm32f7xx_hal_usart.h | 38 +- .../Inc/stm32f7xx_hal_usart_ex.h | 2 +- .../Inc/stm32f7xx_hal_wwdg.h | 2 +- .../Inc/stm32f7xx_ll_adc.h | 22 +- .../Inc/stm32f7xx_ll_dac.h | 4 +- .../Inc/stm32f7xx_ll_fmc.h | 46 +- .../Inc/stm32f7xx_ll_i2c.h | 18 +- .../Inc/stm32f7xx_ll_rcc.h | 37 +- .../Inc/stm32f7xx_ll_sdmmc.h | 48 +- .../Inc/stm32f7xx_ll_utils.h | 4 +- .../STM32F7xx_HAL_Driver/Release_Notes.html | 42 +- .../Src/Legacy/stm32f7xx_hal_can.c | 1688 +++++++++++ .../STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c | 111 +- .../Src/stm32f7xx_hal_adc.c | 66 +- .../Src/stm32f7xx_hal_adc_ex.c | 42 +- .../Src/stm32f7xx_hal_can.c | 2695 +++++++++-------- .../Src/stm32f7xx_hal_cec.c | 42 +- .../Src/stm32f7xx_hal_cortex.c | 24 +- .../Src/stm32f7xx_hal_crc.c | 34 +- .../Src/stm32f7xx_hal_crc_ex.c | 14 +- .../Src/stm32f7xx_hal_cryp.c | 624 ++-- .../Src/stm32f7xx_hal_cryp_ex.c | 314 +- .../Src/stm32f7xx_hal_dac.c | 68 +- .../Src/stm32f7xx_hal_dac_ex.c | 36 +- .../Src/stm32f7xx_hal_dcmi.c | 54 +- .../Src/stm32f7xx_hal_dfsdm.c | 196 +- .../Src/stm32f7xx_hal_dma.c | 77 +- .../Src/stm32f7xx_hal_dma2d.c | 132 +- .../Src/stm32f7xx_hal_dma_ex.c | 34 +- .../Src/stm32f7xx_hal_dsi.c | 184 +- .../Src/stm32f7xx_hal_eth.c | 94 +- .../Src/stm32f7xx_hal_flash.c | 56 +- .../Src/stm32f7xx_hal_flash_ex.c | 70 +- .../Src/stm32f7xx_hal_gpio.c | 30 +- .../Src/stm32f7xx_hal_hash.c | 134 +- .../Src/stm32f7xx_hal_hash_ex.c | 118 +- .../Src/stm32f7xx_hal_hcd.c | 621 ++-- .../Src/stm32f7xx_hal_i2c.c | 879 +++--- .../Src/stm32f7xx_hal_i2c_ex.c | 13 +- .../Src/stm32f7xx_hal_i2s.c | 94 +- .../Src/stm32f7xx_hal_irda.c | 14 +- .../Src/stm32f7xx_hal_jpeg.c | 232 +- .../Src/stm32f7xx_hal_lptim.c | 436 ++- .../Src/stm32f7xx_hal_ltdc.c | 182 +- .../Src/stm32f7xx_hal_ltdc_ex.c | 8 +- .../Src/stm32f7xx_hal_mdios.c | 48 +- .../Src/stm32f7xx_hal_mmc.c | 128 +- .../Src/stm32f7xx_hal_nand.c | 144 +- .../Src/stm32f7xx_hal_nor.c | 76 +- .../Src/stm32f7xx_hal_pcd.c | 118 +- .../Src/stm32f7xx_hal_pcd_ex.c | 28 +- .../Src/stm32f7xx_hal_pwr.c | 14 +- .../Src/stm32f7xx_hal_pwr_ex.c | 6 +- .../Src/stm32f7xx_hal_qspi.c | 134 +- .../Src/stm32f7xx_hal_rcc.c | 382 ++- .../Src/stm32f7xx_hal_rcc_ex.c | 209 +- .../Src/stm32f7xx_hal_rng.c | 52 +- .../Src/stm32f7xx_hal_rtc.c | 152 +- .../Src/stm32f7xx_hal_rtc_ex.c | 224 +- .../Src/stm32f7xx_hal_sai.c | 142 +- .../Src/stm32f7xx_hal_sd.c | 144 +- .../Src/stm32f7xx_hal_sdram.c | 104 +- .../Src/stm32f7xx_hal_smartcard.c | 12 +- .../Src/stm32f7xx_hal_smartcard_ex.c | 12 +- .../Src/stm32f7xx_hal_smbus.c | 574 ++-- .../Src/stm32f7xx_hal_spdifrx.c | 94 +- .../Src/stm32f7xx_hal_spi.c | 180 +- .../Src/stm32f7xx_hal_sram.c | 86 +- .../Src/stm32f7xx_hal_tim.c | 1183 ++++++-- .../Src/stm32f7xx_hal_tim_ex.c | 231 +- ...tm32f7xx_hal_timebase_rtc_alarm_template.c | 4 +- ...m32f7xx_hal_timebase_rtc_wakeup_template.c | 4 +- .../Src/stm32f7xx_hal_timebase_tim_template.c | 4 +- .../Src/stm32f7xx_hal_uart.c | 134 +- .../Src/stm32f7xx_hal_usart.c | 128 +- .../Src/stm32f7xx_ll_dma2d.c | 12 +- .../Src/stm32f7xx_ll_fmc.c | 121 +- .../Src/stm32f7xx_ll_gpio.c | 4 +- .../Src/stm32f7xx_ll_rcc.c | 46 +- .../Src/stm32f7xx_ll_rtc.c | 2 +- .../Src/stm32f7xx_ll_sdmmc.c | 112 +- .../Src/stm32f7xx_ll_spi.c | 2 +- .../Src/stm32f7xx_ll_usart.c | 19 +- .../Src/stm32f7xx_ll_usb.c | 184 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 147 files changed, 12187 insertions(+), 7241 deletions(-) create mode 100644 system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32f7xx_hal_can_legacy.h create mode 100644 system/Drivers/STM32F7xx_HAL_Driver/Src/Legacy/stm32f7xx_hal_can.c diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 9604f205b7..24e0234348 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @brief This file contains aliases definition for the STM32Cube HAL constants + * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention @@ -58,7 +58,7 @@ /** * @} */ - + /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose * @{ */ @@ -90,10 +90,10 @@ #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 @@ -109,21 +109,21 @@ #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 /** * @} */ - + /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG /** * @} - */ - + */ + /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ @@ -136,7 +136,9 @@ #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 @@ -152,7 +154,7 @@ #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - + #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT @@ -224,7 +226,7 @@ /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ - + #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE @@ -253,28 +255,27 @@ /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose * @{ */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - - - + + + /** * @} */ @@ -282,7 +283,7 @@ /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose * @{ */ - + #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD @@ -358,11 +359,11 @@ /** * @} */ - + /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose * @{ */ - + #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 @@ -375,12 +376,12 @@ /** * @} */ - + /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ -#if defined(STM32L4) || defined(STM32F7) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 @@ -398,7 +399,7 @@ /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose * @{ */ - + #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef /** @@ -430,18 +431,18 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ - -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) @@ -455,6 +456,78 @@ * @} */ +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) + #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE + #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE + #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET + #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET + #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE + #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE + + #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 + #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + + #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX + #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT + #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT + #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT + #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 + #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT + #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT + #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT + #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP + #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 + #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 + #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT + #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT + #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT + #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT + #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + + #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT + #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING + #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING + #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + + +#endif /* STM32H7 */ + + +/** + * @} + */ + + /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ @@ -467,7 +540,7 @@ #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - + #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD @@ -540,7 +613,7 @@ #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS /* The following 3 definition have also been present in a temporary version of lptim.h */ /* They need to be renamed also to the right name, just in case */ @@ -570,7 +643,7 @@ /** * @} */ - + /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose * @{ */ @@ -594,11 +667,11 @@ #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - + #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 @@ -607,14 +680,14 @@ #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + /** * @} */ @@ -623,7 +696,7 @@ * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -#if defined(STM32F7) +#if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** @@ -635,18 +708,18 @@ */ /* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA /* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD @@ -659,31 +732,27 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ - + #define FORMAT_BIN RTC_FORMAT_BIN #define FORMAT_BCD RTC_FORMAT_BCD #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 @@ -691,15 +760,15 @@ #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 /** * @} */ - + /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose * @{ */ @@ -720,7 +789,7 @@ * @} */ - + /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ @@ -738,7 +807,7 @@ /** * @} */ - + /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ @@ -754,13 +823,13 @@ /** * @} */ - + /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose * @{ */ #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - + #define TIM_DMABase_CR1 TIM_DMABASE_CR1 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR @@ -861,7 +930,7 @@ * @} */ - + /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose * @{ */ @@ -901,7 +970,7 @@ /** * @} */ - + /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose * @{ */ @@ -926,7 +995,7 @@ #define ETH_MMCRFCECR 0x00000194U #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U - + #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ @@ -944,9 +1013,12 @@ #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ @@ -958,7 +1030,7 @@ /** * @} */ - + /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose * @{ */ @@ -973,39 +1045,39 @@ /** * @} - */ - -#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 /** * @} - */ -#endif /* STM32L4xx || STM32F7*/ + */ +#endif /* STM32L4 || STM32F7*/ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1018,11 +1090,11 @@ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback /** * @} - */ + */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish @@ -1032,12 +1104,12 @@ /*HASH Algorithm Selection*/ -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY @@ -1045,7 +1117,7 @@ /** * @} */ - + /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose * @{ */ @@ -1126,6 +1198,8 @@ #define CR_OFFSET_BB PWR_CR_OFFSET_BB #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB #define DBP_BitNumber DBP_BIT_NUMBER #define PVDE_BitNumber PVDE_BIT_NUMBER @@ -1139,17 +1213,17 @@ #define BRE_BitNumber BRE_BIT_NUMBER #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - + /** * @} - */ - + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback /** * @} */ @@ -1160,7 +1234,7 @@ #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo /** * @} - */ + */ /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose * @{ @@ -1172,28 +1246,31 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /** * @} */ - + /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose * @{ - */ + */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig /** * @} - */ - - + */ + + /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ - + /** * @} */ @@ -1208,8 +1285,8 @@ #define AES_FLAG_CCF CRYP_FLAG_CCF /** * @} - */ - + */ + /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ @@ -1218,7 +1295,7 @@ #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK @@ -1226,6 +1303,7 @@ #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 @@ -1237,7 +1315,7 @@ * @} */ - + /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose * @{ */ @@ -1307,7 +1385,6 @@ #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION #define __HAL_ADC_JSQR ADC_JSQR #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL @@ -1334,7 +1411,7 @@ /** * @} */ - + /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose * @{ */ @@ -1407,7 +1484,7 @@ #define COMP_START __HAL_COMP_ENABLE #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK - + #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -1594,7 +1671,7 @@ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ ((WAVE) == DAC_WAVE_NOISE)|| \ ((WAVE) == DAC_WAVE_TRIANGLE)) - + /** * @} */ @@ -1613,14 +1690,18 @@ /** * @} */ - + /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ #define __HAL_I2C_RISE_TIME I2C_RISE_TIME #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST @@ -1636,11 +1717,11 @@ /** * @} */ - + /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose * @{ */ - + #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT @@ -1651,7 +1732,7 @@ /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose * @{ */ - + #define __IRDA_DISABLE __HAL_IRDA_DISABLE #define __IRDA_ENABLE __HAL_IRDA_ENABLE @@ -1660,7 +1741,7 @@ #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE /** @@ -1689,8 +1770,8 @@ /** * @} */ - - + + /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose * @{ */ @@ -1755,7 +1836,7 @@ #if defined (STM32F4) #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #else @@ -1763,37 +1844,37 @@ #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG #endif /* STM32F4 */ -/** +/** * @} - */ - - + */ + + /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose * @{ */ - + #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE @@ -1810,7 +1891,7 @@ #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE @@ -2038,6 +2119,21 @@ #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE @@ -2229,13 +2325,13 @@ #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE @@ -2288,111 +2384,111 @@ #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE @@ -2400,29 +2496,28 @@ #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET @@ -2438,8 +2533,6 @@ #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE @@ -2461,8 +2554,6 @@ #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET @@ -2626,7 +2717,7 @@ #define SdioClockSelection Sdmmc1ClockSelection #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE #endif #if defined(STM32F7) @@ -2634,6 +2725,30 @@ #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #endif +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG @@ -2687,7 +2802,12 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32L4) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#elif defined(STM32WB) || defined(STM32G0) +#else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL @@ -2787,6 +2907,15 @@ #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 + /** * @} */ @@ -2794,17 +2923,19 @@ /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose * @{ */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ - +#if defined (STM32G0) +#else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT @@ -2840,7 +2971,7 @@ #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION @@ -2865,26 +2996,26 @@ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS -#if defined(STM32F4) +#if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn @@ -2893,8 +3024,8 @@ #if defined(STM32F7) || defined(STM32L4) #define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT @@ -2917,13 +3048,23 @@ #define SDIO_IRQHandler SDMMC1_IRQHandler #endif -#if defined(STM32F7) || defined(STM32F4) +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif +#if defined(STM32H7) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#endif /** * @} */ @@ -2942,7 +3083,7 @@ #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE /** * @} @@ -2974,7 +3115,7 @@ /** * @} */ - + /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose * @{ */ @@ -2986,8 +3127,8 @@ #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE /** * @} @@ -3092,7 +3233,7 @@ /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose * @{ */ - + #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG @@ -3101,7 +3242,7 @@ #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE /** @@ -3112,6 +3253,10 @@ * @{ */ #define __HAL_LTDC_LAYER LTDC_LAYER +#if defined(STM32F7) +#else +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +#endif /** * @} */ @@ -3137,11 +3282,22 @@ * @} */ +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ - + /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32f7xx_hal_can_legacy.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32f7xx_hal_can_legacy.h new file mode 100644 index 0000000000..a569e65eb3 --- /dev/null +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32f7xx_hal_can_legacy.h @@ -0,0 +1,777 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_can_legacy.h + * @author MCD Application Team + * @brief Header file of CAN HAL module. + ****************************************************************************** + * @attention + * + *

      © COPYRIGHT(c) 2017 STMicroelectronics

      + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CAN_LEGACY_H +#define __STM32F7xx_HAL_CAN_LEGACY_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ + HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ + +}HAL_CAN_StateTypeDef; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE */ +}CAN_InitTypeDef; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. + This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ + + uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint32_t FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + uint32_t FilterActivation; /*!< Enable or disable the filter. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t BankNumber; /*!< Select the start slave bank filter. + This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + +}CAN_FilterConfTypeDef; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_Identifier_Type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + +}CanTxMsgTypeDef; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. + This parameter can be a value of @ref CAN_Identifier_Type */ + + uint32_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t FIFONumber; /*!< Specifies the receive FIFO number. + This parameter can be CAN_FIFO0 or CAN_FIFO1 */ + +}CanRxMsgTypeDef; + +/** + * @brief CAN handle Structure definition + */ +typedef struct +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + + CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ + + CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ + + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + + HAL_LockTypeDef Lock; /*!< CAN locking object */ + + __IO uint32_t ErrorCode; /*!< CAN Error code + This parameter can be a value of @ref CAN_Error_Code */ +}CAN_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CAN_Exported_Constants CAN Exported Constants + * @{ + */ + +/** @defgroup CAN_Error_Code CAN Error Code + * @{ + */ +#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */ +#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */ +#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */ +#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */ +#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */ +#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */ +#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */ +#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */ +/** + * @} + */ + +/** @defgroup CAN_InitStatus CAN InitStatus + * @{ + */ +#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */ +/** + * @} + */ + +/** @defgroup CAN_operating_mode CAN Operating Mode + * @{ + */ +#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */ +#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ +#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width + * @{ + */ +#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ +#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ +#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1 + * @{ + */ +#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ +#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ +#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ +#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ +#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ +#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ +#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ +#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ +#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ +#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ +#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ +#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ +#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ +#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ +#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2 + * @{ + */ +#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ +#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ +#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ +#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ +#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ +#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ +#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode CAN Filter Mode + * @{ + */ +#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +/** + * @} + */ + +/** @defgroup CAN_filter_scale CAN Filter Scale + * @{ + */ +#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO CAN Filter FIFO + * @{ + */ +#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +/** + * @} + */ + +/** @defgroup CAN_Identifier_Type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD 0x00000000U /*!< Standard Id */ +#define CAN_ID_EXT 0x00000004U /*!< Extended Id */ +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request + * @{ + */ +#define CAN_RTR_DATA 0x00000000U /*!< Data frame */ +#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants + * @{ + */ +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +/** + * @} + */ + +/** @defgroup CAN_flags CAN Flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with + CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */ +#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */ +#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */ +#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */ +#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */ +#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */ +#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */ + +/* Receive Flags */ +#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */ + +#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */ +#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */ +#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */ + +/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */ +#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */ +#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */ +/** + * @} + */ + +/** @defgroup CAN_Interrupts CAN Interrupts + * @{ + */ +#define CAN_IT_TME CAN_IER_TMEIE /*!< Transmit mailbox empty interrupt */ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 CAN_IER_FMPIE0 /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_FF0 CAN_IER_FFIE0 /*!< FIFO 0 full interrupt */ +#define CAN_IT_FOV0 CAN_IER_FOVIE0 /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_FMP1 CAN_IER_FMPIE1 /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_FF1 CAN_IER_FFIE1 /*!< FIFO 1 full interrupt */ +#define CAN_IT_FOV1 CAN_IER_FOVIE1 /*!< FIFO 1 overrun interrupt */ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU CAN_IER_WKUIE /*!< Wake-up interrupt */ +#define CAN_IT_SLK CAN_IER_SLKIE /*!< Sleep acknowledge interrupt */ + +/* Error Interrupts */ +#define CAN_IT_EWG CAN_IER_EWGIE /*!< Error warning interrupt */ +#define CAN_IT_EPV CAN_IER_EPVIE /*!< Error passive interrupt */ +#define CAN_IT_BOF CAN_IER_BOFIE /*!< Bus-off interrupt */ +#define CAN_IT_LEC CAN_IER_LECIE /*!< Last error code interrupt */ +#define CAN_IT_ERR CAN_IER_ERRIE /*!< Error Interrupt */ +/** + * @} + */ + +/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition + * @{ + */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Macros CAN Exported Macros + * @{ + */ + +/** @brief Reset CAN handle state + * @param __HANDLE__ specifies the CAN Handle. + * @retval None + */ +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) + +/** + * @brief Enable the specified CAN interrupts. + * @param __HANDLE__ CAN handle + * @param __INTERRUPT__ CAN Interrupt + * @retval None + */ +#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified CAN interrupts. + * @param __HANDLE__ CAN handle + * @param __INTERRUPT__ CAN Interrupt + * @retval None + */ +#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** + * @brief Return the number of pending received messages. + * @param __HANDLE__ CAN handle + * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval The number of pending message. + */ +#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U))) + +/** @brief Check whether the specified CAN flag is set or not. + * @param __HANDLE__ CAN Handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @arg CAN_FLAG_EWG: Error Warning Flag + * @arg CAN_FLAG_EPV: Error Passive Flag + * @arg CAN_FLAG_BOF: Bus-Off Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + +/** @brief Clear the specified CAN pending flag. + * @param __HANDLE__ CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_TSR_RQCP0: Request MailBox0 Flag + * @arg CAN_TSR_RQCP1: Request MailBox1 Flag + * @arg CAN_TSR_RQCP2: Request MailBox2 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag + * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag + * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag + * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag + * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag + * @arg CAN_FLAG_FF0: FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag + * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag + * @arg CAN_FLAG_FF1: FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKU: Wake up Flag + * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ CAN Handle + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be one of the following values: + * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable + * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable + * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @brief Check the transmission status of a CAN Frame. + * @param __HANDLE__ CAN Handle + * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. + * @retval The new status of transmission (TRUE or FALSE). + */ +#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ + ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) + +/** + * @brief Release the specified receive FIFO. + * @param __HANDLE__ CAN handle + * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval None + */ +#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ +((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) + +/** + * @brief Cancel a transmit request. + * @param __HANDLE__ CAN Handle + * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. + * @retval None + */ +#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ + ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) + +/** + * @brief Enable or disable the DBG Freeze for CAN. + * @param __HANDLE__ CAN Handle + * @param __NEWSTATE__ new state of the CAN peripheral. + * This parameter can be: ENABLE (CAN reception/transmission is frozen + * during debug. Reception FIFOs can still be accessed/controlled normally) + * or DISABLE (CAN is working during debug). + * @retval None + */ +#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ +((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions + * @{ + */ + +/** @addtogroup CAN_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ***********************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ******************************************************/ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); +void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ***************************************************/ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup CAN_Private_Types CAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Variables CAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ +#define CAN_FLAG_MASK 0x000000FFU +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) +#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CAN_LEGACY_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32_assert_template.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32_assert_template.h index d6069d7ef7..012c118e9e 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32_assert_template.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32_assert_template.h @@ -50,7 +50,7 @@ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function + * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source * line number of the call that failed. * If expr is true, it returns no value. diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h index aa722c829a..62be5450ba 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h @@ -55,10 +55,25 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ + /** @defgroup HAL_Exported_Constants HAL Exported Constants * @{ */ +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + /** @defgroup SYSCFG_BootMode Boot Mode * @{ */ @@ -167,6 +182,15 @@ * @} */ +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup HAL_Exported_Functions * @{ @@ -174,12 +198,12 @@ /** @addtogroup HAL_Exported_Functions_Group1 * @{ */ -/* Initialization and de-initialization functions ******************************/ +/* Initialization and Configuration functions ******************************/ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); void HAL_MspInit(void); void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); /** * @} */ @@ -189,8 +213,11 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); */ /* Peripheral Control functions ************************************************/ void HAL_IncTick(void); -void HAL_Delay(__IO uint32_t Delay); +void HAL_Delay(uint32_t Delay); uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); void HAL_SuspendTick(void); void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h index c67d07ac7a..d69006bbfa 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h @@ -490,60 +490,60 @@ typedef struct */ /** @brief Reset ADC handle state - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) /** * @brief Enable the ADC peripheral. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) /** * @brief Disable the ADC peripheral. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) /** * @brief Enable the ADC end of conversion interrupt. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: ADC Interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC Interrupt. * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) /** * @brief Disable the ADC end of conversion interrupt. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: ADC interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC interrupt. * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) /** @brief Check if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: specifies the ADC interrupt source to check. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ specifies the ADC interrupt source to check. * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Clear the ADC's pending flags. - * @param __HANDLE__: specifies the ADC Handle. - * @param __FLAG__: ADC flag. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. * @retval None */ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) /** * @brief Get the selected ADC's flag status. - * @param __HANDLE__: specifies the ADC Handle. - * @param __FLAG__: ADC flag. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. * @retval None */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) @@ -651,7 +651,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Verification of ADC state: enabled or disabled - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_IS_ENABLE(__HANDLE__) \ @@ -661,7 +661,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Test if conversion trigger of regular group is software start * or external trigger. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ @@ -670,7 +670,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Test if conversion trigger of injected group is software start * or external trigger. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ @@ -687,7 +687,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Clear ADC error code (set it to error code: "no error") - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ @@ -795,89 +795,89 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Set ADC Regular channel sequence length. - * @param _NbrOfConversion_: Regular channel sequence length. + * @param _NbrOfConversion_ Regular channel sequence length. * @retval None */ #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20) /** * @brief Set the ADC's sample time for channel numbers between 10 and 18. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10))) /** * @brief Set the ADC's sample time for channel numbers between 0 and 9. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_))))) /** * @brief Set the selected regular channel rank for rank between 1 and 6. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1))) /** * @brief Set the selected regular channel rank for rank between 7 and 12. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7))) /** * @brief Set the selected regular channel rank for rank between 13 and 16. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13))) /** * @brief Enable ADC continuous conversion mode. - * @param _CONTINUOUS_MODE_: Continuous mode. + * @param _CONTINUOUS_MODE_ Continuous mode. * @retval None */ #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1) /** * @brief Configures the number of discontinuous conversions for the regular group channels. - * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions. + * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. * @retval None */ #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << ADC_CR1_DISCNUM_Pos) /** * @brief Enable ADC scan mode. - * @param _SCANCONV_MODE_: Scan conversion mode. + * @param _SCANCONV_MODE_ Scan conversion mode. * @retval None */ #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8) /** * @brief Enable the ADC end of conversion selection. - * @param _EOCSelection_MODE_: End of conversion selection mode. + * @param _EOCSelection_MODE_ End of conversion selection mode. * @retval None */ #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10) /** * @brief Enable the ADC DMA continuous request. - * @param _DMAContReq_MODE_: DMA continuous request mode. + * @param _DMAContReq_MODE_ DMA continuous request mode. * @retval None */ #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9) /** * @brief Return resolution bits in CR1 register. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h index 2c262ea41a..13cfa6152d 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h @@ -337,9 +337,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /** * @brief Set the selected injected Channel rank. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @param _JSQR_JL_: Sequence length. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @param _JSQR_JL_ Sequence length. * @retval None */ #define ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_)))) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_can.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_can.h index b16bf6b174..1af6b6f4c3 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_can.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_can.h @@ -34,11 +34,11 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_CAN_H -#define __STM32F7xx_HAL_CAN_H +#ifndef STM32F7xx_HAL_CAN_H +#define STM32F7xx_HAL_CAN_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -48,6 +48,7 @@ * @{ */ +#if defined (CAN1) /** @addtogroup CAN * @{ */ @@ -56,7 +57,6 @@ /** @defgroup CAN_Exported_Types CAN Exported Types * @{ */ - /** * @brief HAL State structures definition */ @@ -64,59 +64,53 @@ typedef enum { HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ - HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ + HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ + HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ + HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ + HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ -}HAL_CAN_StateTypeDef; +} HAL_CAN_StateTypeDef; /** * @brief CAN init structure definition */ typedef struct { - uint32_t Prescaler; /*!< Specifies the length of a time quantum. - This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ - uint32_t Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ + uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ - uint32_t SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ + uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ - uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set to ENABLE or DISABLE. */ + FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set to ENABLE or DISABLE */ -}CAN_InitTypeDef; +} CAN_InitTypeDef; /** * @brief CAN filter configuration structure definition @@ -125,27 +119,30 @@ typedef struct { uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ - uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. - This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ + uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. + For single CAN instance(14 dedicated filter banks), + this parameter must be a number between Min_Data = 0 and Max_Data = 13. + For dual CAN instances(28 filter banks shared), + this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ @@ -156,95 +153,94 @@ typedef struct uint32_t FilterActivation; /*!< Enable or disable the filter. This parameter can be set to ENABLE or DISABLE. */ - uint32_t BankNumber; /*!< Select the start slave bank filter. - This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. + For single CAN instances, this parameter is meaningless. + For dual CAN instances, all filter banks with lower index are assigned to master + CAN instance, whereas all filter banks with greater index are assigned to slave + CAN instance. + This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ -}CAN_FilterConfTypeDef; +} CAN_FilterTypeDef; /** - * @brief CAN Tx message structure definition + * @brief CAN Tx message header structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. - This parameter can be a value of @ref CAN_Identifier_Type */ + This parameter can be a value of @ref CAN_identifier_type */ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref CAN_remote_transmission_request */ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start + of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. + @note: Time Triggered Communication Mode must be enabled. + @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. + This parameter can be set to ENABLE or DISABLE. */ -}CanTxMsgTypeDef; +} CAN_TxHeaderTypeDef; /** - * @brief CAN Rx message structure definition + * @brief CAN Rx message header structure definition */ typedef struct { - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. - This parameter can be a value of @ref CAN_Identifier_Type */ + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - uint32_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of @ref CAN_remote_transmission_request */ + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ - uint32_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ - uint8_t Data[8]; /*!< Contains the data to be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + @note: Time Triggered Communication Mode must be enabled. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ - uint32_t FIFONumber; /*!< Specifies the receive FIFO number. - This parameter can be CAN_FIFO0 or CAN_FIFO1 */ + uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ -}CanRxMsgTypeDef; +} CAN_RxHeaderTypeDef; /** * @brief CAN handle Structure definition */ -typedef struct +typedef struct __CAN_HandleTypeDef { - CAN_TypeDef *Instance; /*!< Register base address */ - - CAN_InitTypeDef Init; /*!< CAN required parameters */ + CAN_TypeDef *Instance; /*!< Register base address */ - CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + CAN_InitTypeDef Init; /*!< CAN required parameters */ - CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ + __IO uint32_t ErrorCode; /*!< CAN Error code. + This parameter can be a value of @ref CAN_Error_Code */ - __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - - HAL_LockTypeDef Lock; /*!< CAN locking object */ - - __IO uint32_t ErrorCode; /*!< CAN Error code - This parameter can be a value of @ref CAN_Error_Code */ -}CAN_HandleTypeDef; +} CAN_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup CAN_Exported_Constants CAN Exported Constants * @{ */ @@ -252,19 +248,30 @@ typedef struct /** @defgroup CAN_Error_Code CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */ -#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */ -#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */ -#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */ -#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */ -#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */ -#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */ -#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ +#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ +#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ +#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ +#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ +#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ +#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ + /** * @} */ @@ -272,8 +279,8 @@ typedef struct /** @defgroup CAN_InitStatus CAN InitStatus * @{ */ -#define CAN_INITSTATUS_FAILED ((uint8_t)0x00U) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01U) /*!< CAN initialization OK */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ /** * @} */ @@ -281,7 +288,7 @@ typedef struct /** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ -#define CAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ @@ -289,10 +296,11 @@ typedef struct * @} */ -/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width * @{ */ -#define CAN_SJW_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ @@ -300,10 +308,10 @@ typedef struct * @} */ -/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1 +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 * @{ */ -#define CAN_BS1_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ @@ -323,10 +331,10 @@ typedef struct * @} */ -/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2 +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 * @{ */ -#define CAN_BS2_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ @@ -338,11 +346,11 @@ typedef struct * @} */ -/** @defgroup CAN_filter_mode CAN Filter Mode +/** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ -#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */ -#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */ +#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ /** * @} */ @@ -350,8 +358,8 @@ typedef struct /** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ -#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */ +#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ /** * @} */ @@ -359,17 +367,17 @@ typedef struct /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ -#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */ +#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ /** * @} */ -/** @defgroup CAN_Identifier_Type CAN Identifier Type +/** @defgroup CAN_identifier_type CAN Identifier Type * @{ */ -#define CAN_ID_STD ((uint32_t)0x00000000U) /*!< Standard Id */ -#define CAN_ID_EXT ((uint32_t)0x00000004U) /*!< Extended Id */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ /** * @} */ @@ -377,98 +385,100 @@ typedef struct /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ -#define CAN_RTR_DATA ((uint32_t)0x00000000U) /*!< Data frame */ -#define CAN_RTR_REMOTE ((uint32_t)0x00000002U) /*!< Remote frame */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ /** * @} */ -/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants +/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number * @{ */ -#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */ +#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ +#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ /** * @} */ -/** @defgroup CAN_flags CAN Flags +/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes * @{ */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ +#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ +#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ +#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ +/** + * @} + */ +/** @defgroup CAN_flags CAN Flags + * @{ + */ /* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500U) /*!< Request MailBox0 flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508U) /*!< Request MailBox1 flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510U) /*!< Request MailBox2 flag */ -#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501U) /*!< Transmission OK MailBox0 flag */ -#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509U) /*!< Transmission OK MailBox1 flag */ -#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511U) /*!< Transmission OK MailBox2 flag */ -#define CAN_FLAG_TME0 ((uint32_t)0x0000051AU) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME1 ((uint32_t)0x0000051BU) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME2 ((uint32_t)0x0000051CU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ +#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ +#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ +#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ +#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ +#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ +#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ +#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ +#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ +#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ /* Receive Flags */ -#define CAN_FLAG_FF0 ((uint32_t)0x00000203U) /*!< FIFO 0 Full flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x00000204U) /*!< FIFO 0 Overrun flag */ - -#define CAN_FLAG_FF1 ((uint32_t)0x00000403U) /*!< FIFO 1 Full flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x00000404U) /*!< FIFO 1 Overrun flag */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ /* Operating Mode Flags */ -#define CAN_FLAG_INAK ((uint32_t)0x00000100U) /*!< Initialization acknowledge flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x00000101U) /*!< Sleep acknowledge flag */ -#define CAN_FLAG_ERRI ((uint32_t)0x00000102U) /*!< Error flag */ -#define CAN_FLAG_WKU ((uint32_t)0x00000103U) /*!< Wake up flag */ -#define CAN_FLAG_SLAKI ((uint32_t)0x00000104U) /*!< Sleep acknowledge flag */ - -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ /* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x00000300U) /*!< Error warning flag */ -#define CAN_FLAG_EPV ((uint32_t)0x00000301U) /*!< Error passive flag */ -#define CAN_FLAG_BOF ((uint32_t)0x00000302U) /*!< Bus-Off flag */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ /** * @} */ + /** @defgroup CAN_Interrupts CAN Interrupts * @{ */ -#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ +/* Transmit Interrupt */ +#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ /* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ -#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ -#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ -#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ -#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ -#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ +#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ /* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ -#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ +#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ /* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ -#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ -#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ -#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ -#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ -/** - * @} - */ - -/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition - * @{ - */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00U) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01U) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02U) +#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ /** * @} */ @@ -477,213 +487,198 @@ typedef struct * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup CAN_Exported_Macros CAN Exported Macros * @{ */ -/** @brief Reset CAN handle state - * @param __HANDLE__: specifies the CAN Handle. +/** @brief Reset CAN handle state + * @param __HANDLE__ CAN handle. * @retval None */ #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) /** * @brief Enable the specified CAN interrupts. - * @param __HANDLE__: CAN handle - * @param __INTERRUPT__: CAN Interrupt + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to enable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) /** * @brief Disable the specified CAN interrupts. - * @param __HANDLE__: CAN handle - * @param __INTERRUPT__: CAN Interrupt + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to disable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) -/** - * @brief Return the number of pending received messages. - * @param __HANDLE__: CAN handle - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval The number of pending message. +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be a value of @arg CAN_Interrupts + * @retval The state of __IT__ (TRUE or FALSE). */ -#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03))) +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) /** @brief Check whether the specified CAN flag is set or not. - * @param __HANDLE__: CAN Handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @arg CAN_flags + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK)))) + ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** @brief Clear the specified CAN pending flag. - * @param __HANDLE__: CAN Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag + * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag + * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag + * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag + * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag + * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag + * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag + * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag + * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag + * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag + * @retval None */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__HANDLE__)->Instance->MSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK)))) - -/** @brief Check if the specified CAN interrupt source is enabled or disabled. - * @param __HANDLE__: CAN Handle - * @param __INTERRUPT__: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable - * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable - * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** - * @brief Check the transmission status of a CAN Frame. - * @param __HANDLE__: CAN Handle - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. - * @retval The new status of transmission (TRUE or FALSE). - */ -#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ - ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) + * @} + */ -/** - * @brief Release the specified receive FIFO. - * @param __HANDLE__: CAN handle - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval None +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ */ -#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) -/** - * @brief Cancel a transmit request. - * @param __HANDLE__: CAN Handle - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. - * @retval None - */ -#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ - ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ -/** - * @brief Enable or disable the DBG Freeze for CAN. - * @param __HANDLE__: CAN Handle - * @param __NEWSTATE__: new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ -((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); /** - * @} - */ + * @} + */ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CAN_Exported_Functions - * @{ - */ +/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions + * @{ + */ + +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); -/** @addtogroup CAN_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions ***********************************/ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); /** - * @} - */ + * @} + */ -/** @addtogroup CAN_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); +/** @addtogroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ + +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); -void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); -void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group5 Callback functions + * @brief Callback functions + * @{ + */ +/* Callbacks functions ********************************************************/ + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); + /** - * @} - */ + * @} + */ -/** @addtogroup CAN_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ***************************************************/ +/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); + /** - * @} - */ + * @} + */ /** - * @} - */ + * @} + */ /* Private types -------------------------------------------------------------*/ /** @defgroup CAN_Private_Types CAN Private Types @@ -701,66 +696,80 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ -#define CAN_FLAG_MASK ((uint32_t)0x000000FFU) +#define CAN_FLAG_MASK (0x000000FFU) /** * @} */ -/* Private macros ------------------------------------------------------------*/ +/* Private Macros -----------------------------------------------------------*/ /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ + #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ ((MODE) == CAN_MODE_LOOPBACK)|| \ ((MODE) == CAN_MODE_SILENT) || \ ((MODE) == CAN_MODE_SILENT_LOOPBACK)) -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ + ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ + ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ + ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ + ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ + ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ + ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ + ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) +#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ + ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ + ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ + ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) +#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ ((SCALE) == CAN_FILTERSCALE_32BIT)) #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - +#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ ((IDTYPE) == CAN_ID_EXT)) #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) +#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) +#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ + CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ + CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ + CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ + CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ + CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) /** * @} */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ +/* End of private macros -----------------------------------------------------*/ /** * @} */ -/** - * @} - */ + +#endif /* CAN1 */ /** * @} */ @@ -769,7 +778,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); } #endif -#endif /* __STM32F7xx_CAN_H */ +#endif /* STM32F7xx_HAL_CAN_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cec.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cec.h index 9af9b8f927..cfa137afbb 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cec.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cec.h @@ -427,7 +427,7 @@ typedef struct */ /** @brief Reset CEC handle gstate & RxState - * @param __HANDLE__: CEC handle. + * @param __HANDLE__ CEC handle. * @retval None */ #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -436,8 +436,8 @@ typedef struct } while(0) /** @brief Checks whether or not the specified CEC interrupt flag is set. - * @param __HANDLE__: specifies the CEC Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the CEC Handle. + * @param __FLAG__ specifies the flag to check. * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error * @arg CEC_FLAG_TXERR: Tx Error. * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. @@ -456,8 +456,8 @@ typedef struct #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) /** @brief Clears the interrupt or status flag when raised (write at 1) - * @param __HANDLE__: specifies the CEC Handle. - * @param __FLAG__: specifies the interrupt/status flag to clear. + * @param __HANDLE__ specifies the CEC Handle. + * @param __FLAG__ specifies the interrupt/status flag to clear. * This parameter can be one of the following values: * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error * @arg CEC_FLAG_TXERR: Tx Error. @@ -477,8 +477,8 @@ typedef struct #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) /** @brief Enables the specified CEC interrupt. - * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the CEC interrupt to enable. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to enable. * This parameter can be one of the following values: * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable @@ -498,8 +498,8 @@ typedef struct #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) /** @brief Disables the specified CEC interrupt. - * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the CEC interrupt to disable. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to disable. * This parameter can be one of the following values: * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable @@ -519,8 +519,8 @@ typedef struct #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) /** @brief Checks whether or not the specified CEC interrupt is enabled. - * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the CEC interrupt to check. + * @param __HANDLE__ specifies the CEC Handle. + * @param __INTERRUPT__ specifies the CEC interrupt to check. * This parameter can be one of the following values: * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable * @arg CEC_IT_TXERR: Tx Error IT Enable @@ -540,52 +540,52 @@ typedef struct #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) /** @brief Enables the CEC device - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) /** @brief Disables the CEC device - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) /** @brief Set Transmission Start flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) /** @brief Set Transmission End flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. */ #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) /** @brief Get Transmission Start flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval FlagStatus */ #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) /** @brief Get Transmission End flag - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval FlagStatus */ #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) /** @brief Clear OAR register - * @param __HANDLE__: specifies the CEC Handle. + * @param __HANDLE__ specifies the CEC Handle. * @retval none */ #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) /** @brief Set OAR register (without resetting previously set address in case of multi-address mode) * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand - * @param __HANDLE__: specifies the CEC Handle. - * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position) + * @param __HANDLE__ specifies the CEC Handle. + * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) * @retval none */ #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) @@ -700,21 +700,21 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); * The message size is the payload size: without counting the header, * it varies from 0 byte (ping operation, one header only, no payload) to * 15 bytes (1 opcode and up to 14 operands following the header). - * @param __SIZE__: CEC message size. + * @param __SIZE__ CEC message size. * @retval Test result (TRUE or FALSE). */ #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10) /** @brief Check CEC device Own Address Register (OAR) setting. * OAR address is written in a 15-bit field within CEC_CFGR register. - * @param __ADDRESS__: CEC own address. + * @param __ADDRESS__ CEC own address. * @retval Test result (TRUE or FALSE). */ #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF) /** @brief Check CEC initiator or destination logical address setting. * Initiator and destination addresses are coded over 4 bits. - * @param __ADDRESS__: CEC initiator or logical address. + * @param __ADDRESS__ CEC initiator or logical address. * @retval Test result (TRUE or FALSE). */ #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_conf_template.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_conf_template.h index 113d0d6568..8644e7d97f 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_conf_template.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_conf_template.h @@ -53,6 +53,7 @@ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED #define HAL_CAN_MODULE_ENABLED +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ #define HAL_CEC_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED #define HAL_CRYP_MODULE_ENABLED @@ -160,8 +161,8 @@ #define VDD_VALUE 3300U /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ #define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */ +#define PREFETCH_ENABLE 1U /* To enable prefetch */ +#define ART_ACCLERATOR_ENABLE 1U /* To enable ART Accelerator */ /* ########################## Assert Selection ############################## */ /** @@ -274,6 +275,10 @@ #include "stm32f7xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f7xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CEC_MODULE_ENABLED #include "stm32f7xx_hal_cec.h" #endif /* HAL_CEC_MODULE_ENABLED */ @@ -438,7 +443,7 @@ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function + * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source * line number of the call that failed. * If expr is true, it returns no value. diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h index 1e4670f2a7..4a7ee18295 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h @@ -241,37 +241,37 @@ typedef struct */ /** @brief Reset CRC handle state - * @param __HANDLE__: CRC handle. + * @param __HANDLE__ CRC handle. * @retval None */ #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) /** * @brief Reset CRC Data Register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None. */ #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) /** * @brief Set CRC INIT non-default value - * @param __HANDLE__ : CRC handle - * @param __INIT__ : 32-bit initial value + * @param __HANDLE__ CRC handle + * @param __INIT__ 32-bit initial value * @retval None. */ #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) /** * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle - * @param __VALUE__: 8-bit value to be stored in the ID register + * @param __HANDLE__ CRC handle + * @param __VALUE__ 8-bit value to be stored in the ID register * @retval None */ #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))) /** * @brief Returns the 8-bit data stored in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval 8-bit value of the ID register */ #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h index b33f598f12..7d37e28aad 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h @@ -99,22 +99,22 @@ /** * @brief Set CRC output reversal - * @param __HANDLE__ : CRC handle + * @param __HANDLE__ CRC handle * @retval None. */ #define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) /** * @brief Unset CRC output reversal - * @param __HANDLE__ : CRC handle + * @param __HANDLE__ CRC handle * @retval None. */ #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) /** * @brief Set CRC non-default polynomial - * @param __HANDLE__ : CRC handle - * @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial + * @param __HANDLE__ CRC handle + * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial * @retval None. */ #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h index 867b569c4e..2df13920e3 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h @@ -256,14 +256,14 @@ typedef struct */ /** @brief Reset CRYP handle state - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__ specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET) /** * @brief Enable/Disable the CRYP peripheral. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__ specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN) @@ -271,22 +271,22 @@ typedef struct /** * @brief Flush the data FIFO. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__ specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH) /** * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC. - * @param __HANDLE__: specifies the CRYP handle. - * @param MODE: The algorithm mode. + * @param __HANDLE__ specifies the CRYP handle. + * @param MODE The algorithm mode. * @retval None */ #define __HAL_CRYP_SET_MODE(__HANDLE__, MODE) ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE)) /** @brief Check whether the specified CRYP flag is set or not. - * @param __HANDLE__: specifies the CRYP handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the CRYP handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data * or a key preparation (for AES decryption). @@ -303,8 +303,8 @@ typedef struct ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) /** @brief Check whether the specified CRYP interrupt is set or not. - * @param __HANDLE__: specifies the CRYP handle. - * @param __INTERRUPT__: specifies the interrupt to check. + * @param __HANDLE__ specifies the CRYP handle. + * @param __INTERRUPT__ specifies the interrupt to check. * This parameter can be one of the following values: * @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending * @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending @@ -314,16 +314,16 @@ typedef struct /** * @brief Enable the CRYP interrupt. - * @param __HANDLE__: specifies the CRYP handle. - * @param __INTERRUPT__: CRYP Interrupt. + * @param __HANDLE__ specifies the CRYP handle. + * @param __INTERRUPT__ CRYP Interrupt. * @retval None */ #define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__)) /** * @brief Disable the CRYP interrupt. - * @param __HANDLE__: specifies the CRYP handle. - * @param __INTERRUPT__: CRYP interrupt. + * @param __HANDLE__ specifies the CRYP handle. + * @param __INTERRUPT__ CRYP interrupt. * @retval None */ #define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__)) @@ -825,7 +825,7 @@ typedef struct */ /** @brief Reset CRYP handle state. - * @param __HANDLE__: specifies the CRYP handle. + * @param __HANDLE__ specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET) @@ -844,7 +844,7 @@ typedef struct /** * @brief Set the algorithm operating mode. - * @param __OPERATING_MODE__: specifies the operating mode + * @param __OPERATING_MODE__ specifies the operating mode * This parameter can be one of the following values: * @arg @ref CRYP_ALGOMODE_ENCRYPT encryption * @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation @@ -857,7 +857,7 @@ typedef struct /** * @brief Set the algorithm chaining mode. - * @param __CHAINING_MODE__: specifies the chaining mode + * @param __CHAINING_MODE__ specifies the chaining mode * This parameter can be one of the following values: * @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook * @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining @@ -871,7 +871,7 @@ typedef struct /** @brief Check whether the specified CRYP status flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden * @arg @ref CRYP_IT_WRERR Write Error @@ -883,7 +883,7 @@ typedef struct /** @brief Clear the CRYP pending status flag. - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear @@ -894,7 +894,7 @@ typedef struct /** @brief Check whether the specified CRYP interrupt source is enabled or not. - * @param __INTERRUPT__: CRYP interrupt source to check + * @param __INTERRUPT__ CRYP interrupt source to check * This parameter can be one of the following values: * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt @@ -904,7 +904,7 @@ typedef struct /** @brief Check whether the specified CRYP interrupt is set or not. - * @param __INTERRUPT__: specifies the interrupt to check. + * @param __INTERRUPT__ specifies the interrupt to check. * This parameter can be one of the following values: * @arg @ref CRYP_IT_WRERR Write Error * @arg @ref CRYP_IT_RDERR Read Error @@ -916,7 +916,7 @@ typedef struct /** @brief Clear the CRYP pending interrupt. - * @param __INTERRUPT__: specifies the IT to clear. + * @param __INTERRUPT__ specifies the IT to clear. * This parameter can be one of the following values: * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear @@ -927,7 +927,7 @@ typedef struct /** * @brief Enable the CRYP interrupt. - * @param __INTERRUPT__: CRYP Interrupt. + * @param __INTERRUPT__ CRYP Interrupt. * This parameter can be one of the following values: * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt @@ -938,7 +938,7 @@ typedef struct /** * @brief Disable the CRYP interrupt. - * @param __INTERRUPT__: CRYP Interrupt. + * @param __INTERRUPT__ CRYP Interrupt. * This parameter can be one of the following values: * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt @@ -957,7 +957,7 @@ typedef struct /** * @brief Verify the key size length. - * @param __KEYSIZE__: Ciphering/deciphering algorithm key size. + * @param __KEYSIZE__ Ciphering/deciphering algorithm key size. * @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid) */ #define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \ @@ -965,7 +965,7 @@ typedef struct /** * @brief Verify the input data type. - * @param __DATATYPE__: Ciphering/deciphering algorithm input data type. + * @param __DATATYPE__ Ciphering/deciphering algorithm input data type. * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid) */ #define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \ @@ -975,7 +975,7 @@ typedef struct /** * @brief Verify the CRYP AES IP running mode. - * @param __MODE__: CRYP AES IP running mode. + * @param __MODE__ CRYP AES IP running mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \ @@ -983,7 +983,7 @@ typedef struct /** * @brief Verify the selected CRYP algorithm. - * @param __ALGOMODE__: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter). + * @param __ALGOMODE__ Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter). * @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid) */ #define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT) || \ @@ -994,7 +994,7 @@ typedef struct /** * @brief Verify the selected CRYP chaining algorithm. - * @param __CHAINMODE__: Selected CRYP chaining algorithm. + * @param __CHAINMODE__ Selected CRYP chaining algorithm. * @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid) */ #if defined(AES_CR_NPBLB) @@ -1013,7 +1013,7 @@ typedef struct /** * @brief Verify the deciphering key write option. - * @param __WRITE__: deciphering key write option. + * @param __WRITE__ deciphering key write option. * @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid) */ #define IS_CRYP_WRITE(__WRITE__) (((__WRITE__) == CRYP_KEY_WRITE_ENABLE) || \ @@ -1021,7 +1021,7 @@ typedef struct /** * @brief Verify the CRYP input data DMA mode. - * @param __MODE__: CRYP input data DMA mode. + * @param __MODE__ CRYP input data DMA mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \ @@ -1029,7 +1029,7 @@ typedef struct /** * @brief Verify the CRYP output data DMA mode. - * @param __MODE__: CRYP output data DMA mode. + * @param __MODE__ CRYP output data DMA mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \ @@ -1037,7 +1037,7 @@ typedef struct /** * @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase. - * @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase. + * @param __PHASE__ CRYP AES ciphering/deciphering/authentication algorithm phase. * @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid) */ #define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE) || \ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp_ex.h index 165f5e3361..0aa8365e11 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp_ex.h @@ -96,8 +96,8 @@ /** * @brief Set the phase: Init, header, payload, final. * This is relevant only for GCM and CCM modes. - * @param __HANDLE__: specifies the CRYP handle. - * @param __PHASE__: The phase. + * @param __HANDLE__ specifies the CRYP handle. + * @param __PHASE__ The phase. * @retval None */ #define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h index c22403807b..9a24422dce 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h @@ -194,22 +194,22 @@ typedef struct */ /** @brief Reset DAC handle state - * @param __HANDLE__: specifies the DAC handle. + * @param __HANDLE__ specifies the DAC handle. * @retval None */ #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) /** @brief Enable the DAC channel - * @param __HANDLE__: specifies the DAC handle. - * @param __DAC_CHANNEL__: specifies the DAC channel + * @param __HANDLE__ specifies the DAC handle. + * @param __DAC_CHANNEL__ specifies the DAC channel * @retval None */ #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \ ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_CHANNEL__))) /** @brief Disable the DAC channel - * @param __HANDLE__: specifies the DAC handle - * @param __DAC_CHANNEL__: specifies the DAC channel. + * @param __HANDLE__ specifies the DAC handle + * @param __DAC_CHANNEL__ specifies the DAC channel. * @retval None */ #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \ @@ -217,22 +217,22 @@ typedef struct /** @brief Enable the DAC interrupt - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. * @retval None */ #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) /** @brief Disable the DAC interrupt - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. * @retval None */ #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) /** @brief Checks if the specified DAC interrupt source is enabled or disabled. - * @param __HANDLE__: DAC handle - * @param __INTERRUPT__: DAC interrupt source to check + * @param __HANDLE__ DAC handle + * @param __INTERRUPT__ DAC interrupt source to check * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt @@ -241,8 +241,8 @@ typedef struct #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected DAC's flag status. - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag @@ -251,8 +251,8 @@ typedef struct #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the DAC's flag. - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag @@ -360,19 +360,19 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) /** @brief Set DHR12R1 alignment - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__)) /** @brief Set DHR12R2 alignment - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__)) /** @brief Set DHR12RD alignment - * @param __ALIGNMENT__: specifies the DAC alignment + * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__)) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h index 425e25b63a..767f74105c 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h @@ -370,21 +370,21 @@ typedef struct */ /** @brief Reset DCMI handle state - * @param __HANDLE__: specifies the DCMI handle. + * @param __HANDLE__ specifies the DCMI handle. * @retval None */ #define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET) /** * @brief Enable the DCMI. - * @param __HANDLE__: DCMI handle + * @param __HANDLE__ DCMI handle * @retval None */ #define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE) /** * @brief Disable the DCMI. - * @param __HANDLE__: DCMI handle + * @param __HANDLE__ DCMI handle * @retval None */ #define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE)) @@ -392,8 +392,8 @@ typedef struct /* Interrupt & Flag management */ /** * @brief Get the DCMI pending flag. - * @param __HANDLE__: DCMI handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DCMI handle + * @param __FLAG__ Get the specified flag. * This parameter can be one of the following values (no combination allowed) * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines) * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) @@ -416,8 +416,8 @@ typedef struct /** * @brief Clear the DCMI pending flags. - * @param __HANDLE__: DCMI handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DCMI handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask * @arg DCMI_FLAG_OVFRI: Overflow flag mask @@ -430,8 +430,8 @@ typedef struct /** * @brief Enable the specified DCMI interrupts. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVF: Overflow interrupt mask @@ -444,8 +444,8 @@ typedef struct /** * @brief Disable the specified DCMI interrupts. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVF: Overflow interrupt mask @@ -458,8 +458,8 @@ typedef struct /** * @brief Check whether the specified DCMI interrupt has occurred or not. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt source to check. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt source to check. * This parameter can be one of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVF: Overflow interrupt mask diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h index 51a94862f7..a0b8ddac94 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h @@ -46,6 +46,7 @@ #include "stm32f7xx.h" #include "Legacy/stm32_hal_legacy.h" #include + /* Exported types ------------------------------------------------------------*/ /** @@ -64,8 +65,8 @@ typedef enum */ typedef enum { - HAL_UNLOCKED = 0x00, - HAL_LOCKED = 0x01 + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ @@ -83,7 +84,7 @@ typedef enum #define UNUSED(x) ((void)(x)) /** @brief Reset the Handle's State field. - * @param __HANDLE__: specifies the Peripheral Handle. + * @param __HANDLE__ specifies the Peripheral Handle. * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter * to HAL_PPP_Init() for the first time, it is mandatory to use this macro @@ -99,7 +100,7 @@ typedef enum */ #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) -#if (USE_RTOS == 1) +#if (USE_RTOS == 1U) /* Reserved for future use */ #error "USE_RTOS should be 0 in the current HAL release" #else @@ -113,15 +114,15 @@ typedef enum { \ (__HANDLE__)->Lock = HAL_LOCKED; \ } \ - }while (0) + }while (0U) #define __HAL_UNLOCK(__HANDLE__) \ do{ \ (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0) + }while (0U) #endif /* USE_RTOS */ -#if defined ( __GNUC__ ) +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -132,7 +133,7 @@ typedef enum /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ @@ -145,7 +146,7 @@ typedef enum #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) + #define __ALIGN_BEGIN __align(4) #elif defined (__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN #endif /* __CC_ARM */ @@ -166,14 +167,14 @@ typedef enum Available memory areas are declared in the 'Target' tab of the 'Options for Target' dialog. */ -#define __RAM_FUNC HAL_StatusTypeDef +#define __RAM_FUNC #elif defined ( __ICCARM__ ) /* ICCARM Compiler --------------- RAM functions are defined using a specific toolchain keyword "__ramfunc". */ -#define __RAM_FUNC __ramfunc HAL_StatusTypeDef +#define __RAM_FUNC __ramfunc #elif defined ( __GNUC__ ) /* GNU Compiler @@ -181,7 +182,7 @@ typedef enum RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". */ -#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) +#define __RAM_FUNC __attribute__((section(".RamFunc"))) #endif diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dfsdm.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dfsdm.h index 01e772f574..ac767e3bdf 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dfsdm.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dfsdm.h @@ -460,13 +460,13 @@ typedef struct */ /** @brief Reset DFSDM channel handle state. - * @param __HANDLE__: DFSDM channel handle. + * @param __HANDLE__ DFSDM channel handle. * @retval None */ #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) /** @brief Reset DFSDM filter handle state. - * @param __HANDLE__: DFSDM filter handle. + * @param __HANDLE__ DFSDM filter handle. * @retval None */ #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h index 7592d8de97..6d9069052b 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h @@ -199,14 +199,14 @@ typedef struct __DMA_HandleTypeDef * @brief DMA Error Code * @{ */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ -#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */ -#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ -#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */ -#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */ -#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ +#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ /** * @} */ @@ -215,9 +215,9 @@ typedef struct __DMA_HandleTypeDef * @brief DMA data transfer direction * @{ */ -#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ /** * @} */ @@ -226,8 +226,8 @@ typedef struct __DMA_HandleTypeDef * @brief DMA peripheral incremented mode * @{ */ -#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ -#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */ +#define DMA_PINC_ENABLE DMA_SxCR_PINC /*!< Peripheral increment mode enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ /** * @} */ @@ -236,8 +236,8 @@ typedef struct __DMA_HandleTypeDef * @brief DMA memory incremented mode * @{ */ -#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ -#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */ +#define DMA_MINC_ENABLE DMA_SxCR_MINC /*!< Memory increment mode enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ /** * @} */ @@ -246,9 +246,9 @@ typedef struct __DMA_HandleTypeDef * @brief DMA peripheral data size * @{ */ -#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */ -#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ -#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment: Word */ /** * @} */ @@ -257,9 +257,9 @@ typedef struct __DMA_HandleTypeDef * @brief DMA memory data size * @{ */ -#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */ -#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ -#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment: Word */ /** * @} */ @@ -268,9 +268,9 @@ typedef struct __DMA_HandleTypeDef * @brief DMA mode * @{ */ -#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ -#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ -#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR DMA_SxCR_CIRC /*!< Circular mode */ +#define DMA_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ /** * @} */ @@ -279,10 +279,10 @@ typedef struct __DMA_HandleTypeDef * @brief DMA priority levels * @{ */ -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ -#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ -#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ -#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ +#define DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level: Medium */ +#define DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level: High */ +#define DMA_PRIORITY_VERY_HIGH DMA_SxCR_PL /*!< Priority level: Very High */ /** * @} */ @@ -291,8 +291,8 @@ typedef struct __DMA_HandleTypeDef * @brief DMA FIFO direct mode * @{ */ -#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */ -#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ +#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ /** * @} */ @@ -301,10 +301,10 @@ typedef struct __DMA_HandleTypeDef * @brief DMA FIFO level * @{ */ -#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */ -#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ -#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ -#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ +#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define DMA_FIFO_THRESHOLD_HALFFULL DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ +#define DMA_FIFO_THRESHOLD_3QUARTERSFULL DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ +#define DMA_FIFO_THRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ /** * @} */ @@ -313,10 +313,10 @@ typedef struct __DMA_HandleTypeDef * @brief DMA memory burst * @{ */ -#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) -#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) -#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) -#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) +#define DMA_MBURST_SINGLE 0x00000000U +#define DMA_MBURST_INC4 DMA_SxCR_MBURST_0 +#define DMA_MBURST_INC8 DMA_SxCR_MBURST_1 +#define DMA_MBURST_INC16 DMA_SxCR_MBURST /** * @} */ @@ -325,10 +325,10 @@ typedef struct __DMA_HandleTypeDef * @brief DMA peripheral burst * @{ */ -#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U) -#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) -#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) -#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) +#define DMA_PBURST_SINGLE 0x00000000U +#define DMA_PBURST_INC4 DMA_SxCR_PBURST_0 +#define DMA_PBURST_INC8 DMA_SxCR_PBURST_1 +#define DMA_PBURST_INC16 DMA_SxCR_PBURST /** * @} */ @@ -337,11 +337,11 @@ typedef struct __DMA_HandleTypeDef * @brief DMA interrupts definition * @{ */ -#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) -#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) -#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) -#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) -#define DMA_IT_FE ((uint32_t)0x00000080U) +#define DMA_IT_TC DMA_SxCR_TCIE +#define DMA_IT_HT DMA_SxCR_HTIE +#define DMA_IT_TE DMA_SxCR_TEIE +#define DMA_IT_DME DMA_SxCR_DMEIE +#define DMA_IT_FE 0x00000080U /** * @} */ @@ -350,26 +350,26 @@ typedef struct __DMA_HandleTypeDef * @brief DMA flag definitions * @{ */ -#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U) -#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U) -#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) -#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) -#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) -#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) -#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) -#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) -#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) -#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) -#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) -#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) -#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) -#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) -#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) -#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) -#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) -#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) -#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) -#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) +#define DMA_FLAG_FEIF0_4 0x00000001U +#define DMA_FLAG_DMEIF0_4 0x00000004U +#define DMA_FLAG_TEIF0_4 0x00000008U +#define DMA_FLAG_HTIF0_4 0x00000010U +#define DMA_FLAG_TCIF0_4 0x00000020U +#define DMA_FLAG_FEIF1_5 0x00000040U +#define DMA_FLAG_DMEIF1_5 0x00000100U +#define DMA_FLAG_TEIF1_5 0x00000200U +#define DMA_FLAG_HTIF1_5 0x00000400U +#define DMA_FLAG_TCIF1_5 0x00000800U +#define DMA_FLAG_FEIF2_6 0x00010000U +#define DMA_FLAG_DMEIF2_6 0x00040000U +#define DMA_FLAG_TEIF2_6 0x00080000U +#define DMA_FLAG_HTIF2_6 0x00100000U +#define DMA_FLAG_TCIF2_6 0x00200000U +#define DMA_FLAG_FEIF3_7 0x00400000U +#define DMA_FLAG_DMEIF3_7 0x01000000U +#define DMA_FLAG_TEIF3_7 0x02000000U +#define DMA_FLAG_HTIF3_7 0x04000000U +#define DMA_FLAG_TCIF3_7 0x08000000U /** * @} */ @@ -381,14 +381,14 @@ typedef struct __DMA_HandleTypeDef /* Exported macro ------------------------------------------------------------*/ /** @brief Reset DMA handle state - * @param __HANDLE__: specifies the DMA handle. + * @param __HANDLE__ specifies the DMA handle. * @retval None */ #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) /** * @brief Return the current DMA Stream FIFO filled level. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The FIFO filling state. * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full * and not empty. @@ -402,14 +402,14 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enable the specified DMA Stream. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) /** * @brief Disable the specified DMA Stream. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) @@ -418,7 +418,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ @@ -438,7 +438,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream half transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ @@ -458,7 +458,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream transfer error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ @@ -478,7 +478,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream FIFO error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified FIFO error flag index. */ #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ @@ -498,7 +498,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream direct mode error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified direct mode error flag index. */ #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ @@ -518,8 +518,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Get the DMA Stream pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCIFx: Transfer complete flag. * @arg DMA_FLAG_HTIFx: Half transfer complete flag. @@ -536,8 +536,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Clear the DMA Stream pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCIFx: Transfer complete flag. * @arg DMA_FLAG_HTIFx: Half transfer complete flag. @@ -554,8 +554,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enable the specified DMA Stream interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. @@ -569,8 +569,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Disable the specified DMA Stream interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. @@ -584,8 +584,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Check whether the specified DMA Stream interrupt is enabled or not. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. @@ -600,8 +600,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Writes the number of data units to be transferred on the DMA Stream. - * @param __HANDLE__: DMA handle - * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) + * @param __HANDLE__ DMA handle + * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) * Number of data items depends only on the Peripheral data format. * * @note If Peripheral data format is Bytes: number of data units is equal @@ -619,7 +619,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * * @retval The number of remaining data units in the current DMA Stream transfer. */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h index d4eb2e9294..c1fbc65e8c 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h @@ -341,14 +341,14 @@ typedef struct __DMA2D_HandleTypeDef */ /** @brief Reset DMA2D handle state - * @param __HANDLE__: specifies the DMA2D handle. + * @param __HANDLE__ specifies the DMA2D handle. * @retval None */ #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) /** * @brief Enable the DMA2D. - * @param __HANDLE__: DMA2D handle + * @param __HANDLE__ DMA2D handle * @retval None. */ #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) @@ -357,8 +357,8 @@ typedef struct __DMA2D_HandleTypeDef /* Interrupt & Flag management */ /** * @brief Get the DMA2D pending flags. - * @param __HANDLE__: DMA2D handle - * @param __FLAG__: flag to check. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ flag to check. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag @@ -372,8 +372,8 @@ typedef struct __DMA2D_HandleTypeDef /** * @brief Clear the DMA2D pending flags. - * @param __HANDLE__: DMA2D handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag @@ -387,8 +387,8 @@ typedef struct __DMA2D_HandleTypeDef /** * @brief Enable the specified DMA2D interrupts. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -402,8 +402,8 @@ typedef struct __DMA2D_HandleTypeDef /** * @brief Disable the specified DMA2D interrupts. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -417,8 +417,8 @@ typedef struct __DMA2D_HandleTypeDef /** * @brief Check whether the specified DMA2D interrupt source is enabled or not. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt source to check. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. * This parameter can be one of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h index 4c14dd7d1d..8eee9ae716 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h @@ -83,25 +83,25 @@ typedef enum * @brief DMAEx channel selection * @{ */ -#define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */ -#define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */ -#define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */ -#define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */ -#define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */ -#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */ -#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */ -#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */ +#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ +#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ +#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ +#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ +#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ +#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ +#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ +#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ defined (STM32F779xx) -#define DMA_CHANNEL_8 ((uint32_t)0x10000000U) /*!< DMA Channel 8 */ -#define DMA_CHANNEL_9 ((uint32_t)0x12000000U) /*!< DMA Channel 9 */ -#define DMA_CHANNEL_10 ((uint32_t)0x14000000U) /*!< DMA Channel 10*/ -#define DMA_CHANNEL_11 ((uint32_t)0x16000000U) /*!< DMA Channel 11*/ -#define DMA_CHANNEL_12 ((uint32_t)0x18000000U) /*!< DMA Channel 12*/ -#define DMA_CHANNEL_13 ((uint32_t)0x1A000000U) /*!< DMA Channel 13*/ -#define DMA_CHANNEL_14 ((uint32_t)0x1C000000U) /*!< DMA Channel 14*/ -#define DMA_CHANNEL_15 ((uint32_t)0x1E000000U) /*!< DMA Channel 15*/ +#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ +#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ +#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10*/ +#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11*/ +#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12*/ +#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13*/ +#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14*/ +#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15*/ #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h index d46e2ea418..af936bc516 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h @@ -887,64 +887,64 @@ typedef struct /* Exported macros -----------------------------------------------------------*/ /** * @brief Enables the DSI host. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DSI_CR_EN) /** * @brief Disables the DSI host. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN) /** * @brief Enables the DSI wrapper. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR |= DSI_WCR_DSIEN) /** * @brief Disable the DSI wrapper. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN) /** * @brief Enables the DSI PLL. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_PLLEN) /** * @brief Disables the DSI PLL. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN) /** * @brief Enables the DSI regulator. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_REGEN) /** * @brief Disables the DSI regulator. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN) /** * @brief Get the DSI pending flags. - * @param __HANDLE__: DSI handle. - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag @@ -960,8 +960,8 @@ typedef struct /** * @brief Clears the DSI pending flags. - * @param __HANDLE__: DSI handle. - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag @@ -974,8 +974,8 @@ typedef struct /** * @brief Enables the specified DSI interrupts. - * @param __HANDLE__: DSI handle. - * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled. + * @param __HANDLE__ DSI handle. + * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt @@ -988,8 +988,8 @@ typedef struct /** * @brief Disables the specified DSI interrupts. - * @param __HANDLE__: DSI handle - * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt @@ -1002,8 +1002,8 @@ typedef struct /** * @brief Checks whether the specified DSI interrupt has occurred or not. - * @param __HANDLE__: DSI handle - * @param __INTERRUPT__: specifies the DSI interrupt source to check. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt source to check. * This parameter can be one of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h index 6556ba74c6..574699031b 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h @@ -1591,80 +1591,80 @@ typedef struct */ /** @brief Reset ETH handle state - * @param __HANDLE__: specifies the ETH handle. + * @param __HANDLE__ specifies the ETH handle. * @retval None */ #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) /** * @brief Checks whether the specified Ethernet DMA Tx Desc flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag of TDES0 to check. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag of TDES0 to check. * @retval the ETH_DMATxDescFlag (SET or RESET). */ #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) /** * @brief Checks whether the specified Ethernet DMA Rx Desc flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag of RDES0 to check. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag of RDES0 to check. * @retval the ETH_DMATxDescFlag (SET or RESET). */ #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) /** * @brief Enables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) /** * @brief Disables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) /** * @brief Set the specified DMA Rx Desc Own bit. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) /** * @brief Returns the specified Ethernet DMA Tx Desc collision count. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval The Transmit descriptor collision counter value. */ #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) /** * @brief Set the specified DMA Tx Desc Own bit. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) /** * @brief Enables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) /** * @brief Disables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) /** * @brief Selects the specified Ethernet DMA Tx Desc Checksum Insertion. - * @param __HANDLE__: ETH Handle - * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion. + * @param __HANDLE__ ETH Handle + * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. * This parameter can be one of the following values: * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum @@ -1676,36 +1676,36 @@ typedef struct /** * @brief Enables the DMA Tx Desc CRC. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) /** * @brief Disables the DMA Tx Desc CRC. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) /** * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) /** * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) /** * @brief Enables the specified Ethernet MAC interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the Ethernet MAC interrupt sources to be * enabled or disabled. * This parameter can be any combination of the following values: * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt @@ -1716,8 +1716,8 @@ typedef struct /** * @brief Disables the specified Ethernet MAC interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the Ethernet MAC interrupt sources to be * enabled or disabled. * This parameter can be any combination of the following values: * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt @@ -1728,36 +1728,36 @@ typedef struct /** * @brief Initiate a Pause Control Frame (Full-duplex only). - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) /** * @brief Checks whether the Ethernet flow control busy bit is set or not. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval The new state of flow control busy status bit (SET or RESET). */ #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) /** * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) /** * @brief Disables the MAC BackPressure operation activation (Half-duplex only). - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) /** * @brief Checks whether the specified Ethernet MAC flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag @@ -1770,8 +1770,8 @@ typedef struct /** * @brief Enables the specified Ethernet DMA interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the Ethernet DMA interrupt sources to be * enabled @ref ETH_DMA_Interrupts * @retval None */ @@ -1779,8 +1779,8 @@ typedef struct /** * @brief Disables the specified Ethernet DMA interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the Ethernet DMA interrupt sources to be * disabled. @ref ETH_DMA_Interrupts * @retval None */ @@ -1788,32 +1788,32 @@ typedef struct /** * @brief Clears the Ethernet DMA IT pending bit. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts * @retval None */ #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) /** * @brief Checks whether the specified Ethernet DMA flag is set or not. -* @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags +* @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags * @retval The new state of ETH_DMA_FLAG (SET or RESET). */ #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) /** * @brief Checks whether the specified Ethernet DMA flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags * @retval The new state of ETH_DMA_FLAG (SET or RESET). */ #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) /** * @brief Checks whether the specified Ethernet DMA overflow flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __OVERFLOW__: specifies the DMA overflow flag to check. + * @param __HANDLE__ ETH Handle + * @param __OVERFLOW__ specifies the DMA overflow flag to check. * This parameter can be one of the following values: * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter @@ -1823,8 +1823,8 @@ typedef struct /** * @brief Set the DMA Receive status watchdog timer register value - * @param __HANDLE__: ETH Handle - * @param __VALUE__: DMA Receive status watchdog timer register value + * @param __HANDLE__ ETH Handle + * @param __VALUE__ DMA Receive status watchdog timer register value * @retval None */ #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) @@ -1832,7 +1832,7 @@ typedef struct /** * @brief Enables any unicast packet filtered by the MAC address * recognition to be a wake-up frame. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) @@ -1840,57 +1840,57 @@ typedef struct /** * @brief Disables any unicast packet filtered by the MAC address * recognition to be a wake-up frame. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) /** * @brief Enables the MAC Wake-Up Frame Detection. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) /** * @brief Disables the MAC Wake-Up Frame Detection. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) /** * @brief Enables the MAC Magic Packet Detection. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) /** * @brief Disables the MAC Magic Packet Detection. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) /** * @brief Enables the MAC Power Down. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) /** * @brief Disables the MAC Power Down. - * @param __HANDLE__: ETH Handle + * @param __HANDLE__ ETH Handle * @retval None */ #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) /** * @brief Checks whether the specified Ethernet PMT flag is set or not. - * @param __HANDLE__: ETH Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ ETH Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received @@ -1901,14 +1901,14 @@ typedef struct /** * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) /** * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ @@ -1916,57 +1916,57 @@ typedef struct /** * @brief Enables the MMC Counter Freeze. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) /** * @brief Disables the MMC Counter Freeze. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) /** * @brief Enables the MMC Reset On Read. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) /** * @brief Disables the MMC Reset On Read. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) /** * @brief Enables the MMC Counter Stop Rollover. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) /** * @brief Disables the MMC Counter Stop Rollover. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) /** * @brief Resets the MMC Counters. - * @param __HANDLE__: ETH Handle. + * @param __HANDLE__ ETH Handle. * @retval None */ #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) /** * @brief Enables the specified Ethernet MMC Rx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value @@ -1976,8 +1976,8 @@ typedef struct #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF) /** * @brief Disables the specified Ethernet MMC Rx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value @@ -1987,8 +1987,8 @@ typedef struct #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF) /** * @brief Enables the specified Ethernet MMC Tx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value @@ -1999,8 +1999,8 @@ typedef struct /** * @brief Disables the specified Ethernet MMC Tx interrupts. - * @param __HANDLE__: ETH Handle. - * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value @@ -2073,15 +2073,17 @@ typedef struct * @brief Enables rising/falling edge trigger to the ETH External interrupt line. * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ - EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ + EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ + }while(0) /** * @brief Disables rising/falling edge trigger to the ETH External interrupt line. * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ + EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ + }while(0) /** * @brief Generate a Software interrupt on selected EXTI line. diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h index 468da0c3ff..2923e66813 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h @@ -207,7 +207,7 @@ typedef struct */ /** * @brief Set the FLASH Latency. - * @param __LATENCY__: FLASH Latency + * @param __LATENCY__ FLASH Latency * The value of this parameter depend on device used within the same series * @retval none */ @@ -256,7 +256,7 @@ typedef struct /** * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ : FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt * @arg FLASH_IT_ERR: Error Interrupt @@ -266,7 +266,7 @@ typedef struct /** * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ : FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt * @arg FLASH_IT_ERR: Error Interrupt @@ -276,7 +276,7 @@ typedef struct /** * @brief Get the specified FLASH flag status. - * @param __FLAG__: specifies the FLASH flag to check. + * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg FLASH_FLAG_EOP : FLASH End of Operation flag * @arg FLASH_FLAG_OPERR : FLASH operation Error flag @@ -291,7 +291,7 @@ typedef struct /** * @brief Clear the specified FLASH flag. - * @param __FLAG__: specifies the FLASH flags to clear. + * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg FLASH_FLAG_EOP : FLASH End of Operation flag * @arg FLASH_FLAG_OPERR : FLASH operation Error flag diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h index 7d73a99af1..21ebcf0e74 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h @@ -478,7 +478,7 @@ typedef struct /** * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1) * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. - * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) + * @param __ADDRESS__ FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) * @retval The FLASH Boot Base Adress */ #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h index 8e5fb1cd98..b0c7ecdad3 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h @@ -185,7 +185,7 @@ typedef enum /** * @brief Checks whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -193,7 +193,7 @@ typedef enum /** * @brief Clears the EXTI's line pending flags. - * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -201,7 +201,7 @@ typedef enum /** * @brief Checks whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -209,7 +209,7 @@ typedef enum /** * @brief Clears the EXTI's line pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -217,7 +217,7 @@ typedef enum /** * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h index 43db18f5f4..4cd62e5e97 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h @@ -395,7 +395,7 @@ #define GPIOI_PIN_AVAILABLE GPIO_PIN_All #define GPIOJ_PIN_AVAILABLE GPIO_PIN_All #define GPIOH_PIN_AVAILABLE GPIO_PIN_All -#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \ +#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \ GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) /** diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h index 213ac44130..b79a5a5167 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h @@ -223,13 +223,13 @@ typedef struct */ /** @brief Reset HASH handle state - * @param __HANDLE__: specifies the HASH handle. + * @param __HANDLE__ specifies the HASH handle. * @retval None */ #define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET) /** @brief Check whether the specified HASH flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer. * @arg HASH_FLAG_DCIS: Digest calculation complete @@ -262,7 +262,7 @@ typedef struct /** * @brief Set the number of valid bits in last word written in Data register - * @param SIZE: size in byte of last data written in Data register. + * @param SIZE size in byte of last data written in Data register. * @retval None */ #define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBW);\ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h index 8c9432152b..702e023349 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h @@ -38,11 +38,11 @@ #define __STM32F7xx_HAL_I2C_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" +#include "stm32f7xx_hal_def.h" /** @addtogroup STM32F7xx_HAL_Driver * @{ @@ -50,7 +50,7 @@ /** @addtogroup I2C * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup I2C_Exported_Types I2C Exported Types @@ -58,13 +58,13 @@ */ /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition - * @brief I2C Configuration Structure definition + * @brief I2C Configuration Structure definition * @{ */ typedef struct { uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization + This parameter calculated by referring to I2C initialization section in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. @@ -88,9 +88,9 @@ typedef struct uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ -}I2C_InitTypeDef; +} I2C_InitTypeDef; -/** +/** * @} */ @@ -120,7 +120,7 @@ typedef struct * 0 : Ready (no Tx operation ongoing)\n * 1 : Busy (Tx operation ongoing) * @{ - */ + */ typedef enum { HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ @@ -137,7 +137,7 @@ typedef enum HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ -}HAL_I2C_StateTypeDef; +} HAL_I2C_StateTypeDef; /** * @} @@ -168,9 +168,9 @@ typedef enum HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ -}HAL_I2C_ModeTypeDef; +} HAL_I2C_ModeTypeDef; -/** +/** * @} */ @@ -211,7 +211,7 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ @@ -226,7 +226,7 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t ErrorCode; /*!< I2C Error code */ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ -}I2C_HandleTypeDef; +} I2C_HandleTypeDef; /** * @} */ @@ -248,6 +248,7 @@ typedef struct __I2C_HandleTypeDef #define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) #define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) #define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) /** * @} */ @@ -311,7 +312,7 @@ typedef struct __I2C_HandleTypeDef /** * @} */ - + /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View * @{ */ @@ -335,9 +336,9 @@ typedef struct __I2C_HandleTypeDef * @{ */ #define I2C_NO_STARTSTOP (0x00000000U) -#define I2C_GENERATE_STOP I2C_CR2_STOP -#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_GENERATE_START_WRITE I2C_CR2_START +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /** * @} */ @@ -429,7 +430,7 @@ typedef struct __I2C_HandleTypeDef * @retval None */ #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - + /** @brief Check whether the specified I2C interrupt source is enabled or not. * @param __HANDLE__ specifies the I2C Handle. * @param __INTERRUPT__ specifies the I2C interrupt source to check. @@ -504,7 +505,7 @@ typedef struct __I2C_HandleTypeDef #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. - * @param __HANDLE__: specifies the I2C Handle. + * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) @@ -525,7 +526,7 @@ typedef struct __I2C_HandleTypeDef */ /* Initialization and de-initialization functions******************************/ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /** @@ -536,7 +537,7 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); * @{ */ /* IO operation functions ****************************************************/ - /******* Blocking mode: Polling */ +/******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); @@ -545,7 +546,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - /******* Non-Blocking mode: Interrupt */ +/******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); @@ -561,7 +562,7 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); - /******* Non-Blocking mode: DMA */ +/******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); @@ -602,11 +603,11 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2C_Private_Constants I2C Private Constants @@ -615,7 +616,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup I2C_Private_Macro I2C Private Macros @@ -659,7 +660,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ ((REQUEST) == I2C_NEXT_FRAME) || \ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME)) + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP)) #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) @@ -679,7 +681,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup I2C_Private_Functions I2C Private Functions @@ -688,15 +690,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /* Private functions are defined in stm32f7xx_hal_i2c.c file */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h index ee5ae4e6a2..002380f2c1 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h @@ -38,7 +38,7 @@ #define __STM32F7xx_HAL_I2C_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -50,7 +50,7 @@ /** @addtogroup I2CEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -112,7 +112,7 @@ /** * @} - */ + */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -129,10 +129,10 @@ /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -#if defined(SYSCFG_PMC_I2C1_FMP) +#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP) void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); -#endif /* SYSCFG_PMC_I2C1_FMP */ +#endif /* Private constants ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants @@ -152,7 +152,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) -#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP) +#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP) #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ @@ -185,7 +185,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */ /** * @} - */ + */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2s.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2s.h index aac5f16819..d262bb52dd 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2s.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2s.h @@ -275,21 +275,21 @@ typedef struct */ /** @brief Reset I2S handle state - * @param __HANDLE__: specifies the I2S handle. + * @param __HANDLE__ specifies the I2S handle. * @retval None */ #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) /** @brief Enable or disable the specified SPI peripheral (in I2S mode). - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE) #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE) /** @brief Enable or disable the specified I2S interrupts. - * @param __HANDLE__: specifies the I2S Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the I2S Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable @@ -300,9 +300,9 @@ typedef struct #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__)) /** @brief Checks if the specified I2S interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. - * @param __INTERRUPT__: specifies the I2S interrupt source to check. + * @param __INTERRUPT__ specifies the I2S interrupt source to check. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable @@ -312,8 +312,8 @@ typedef struct #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified I2S flag is set or not. - * @param __HANDLE__: specifies the I2S Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the I2S Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg I2S_FLAG_RXNE: Receive buffer not empty flag * @arg I2S_FLAG_TXE: Transmit buffer empty flag @@ -327,7 +327,7 @@ typedef struct #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clears the I2S OVR pending flag. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \ @@ -339,7 +339,7 @@ typedef struct } while(0) /** @brief Clears the I2S UDR pending flag. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda.h index f3c96c8c0e..17d335510b 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda.h @@ -394,14 +394,14 @@ typedef struct */ /** @brief Reset IRDA handle state - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * The Handle Instance which can be USART1 or USART2. * @retval None */ #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET) /** @brief Flush the IRDA DR register. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ @@ -411,8 +411,8 @@ typedef struct } while(0) /** @brief Clear the specified IRDA pending flag. - * @param __HANDLE__: specifies the IRDA Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref IRDA_CLEAR_PEF * @arg @ref IRDA_CLEAR_FEF @@ -424,41 +424,41 @@ typedef struct #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the IRDA PE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF) /** @brief Clear the IRDA FE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF) /** @brief Clear the IRDA NE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF) /** @brief Clear the IRDA ORE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF) /** @brief Clear the IRDA IDLE pending flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF) /** @brief Check whether the specified IRDA flag is set or not. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * The Handle Instance which can be USART1 or USART2. * UART peripheral - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg IRDA_FLAG_REACK: Receive enable acknowledge flag * @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag @@ -478,10 +478,10 @@ typedef struct #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Enable the specified IRDA interrupt. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * The Handle Instance which can be USART1 or USART2. * UART peripheral - * @param __INTERRUPT__: specifies the IRDA interrupt source to enable. + * @param __INTERRUPT__ specifies the IRDA interrupt source to enable. * This parameter can be one of the following values: * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt * @arg IRDA_IT_TC: Transmission complete interrupt @@ -496,9 +496,9 @@ typedef struct ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * The Handle Instance which can be USART1 or USART2. - * @param __INTERRUPT__: specifies the IRDA interrupt source to disable. + * @param __INTERRUPT__ specifies the IRDA interrupt source to disable. * This parameter can be one of the following values: * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt * @arg IRDA_IT_TC: Transmission complete interrupt @@ -513,9 +513,9 @@ typedef struct ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Check whether the specified IRDA interrupt has occurred or not. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * The Handle Instance which can be USART1 or USART2. - * @param __IT__: specifies the IRDA interrupt source to check. + * @param __IT__ specifies the IRDA interrupt source to check. * This parameter can be one of the following values: * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt * @arg IRDA_IT_TC: Transmission complete interrupt @@ -530,9 +530,9 @@ typedef struct #define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) /** @brief Check whether the specified IRDA interrupt source is enabled. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * The Handle Instance which can be USART1 or USART2. - * @param __IT__: specifies the IRDA interrupt source to check. + * @param __IT__ specifies the IRDA interrupt source to check. * This parameter can be one of the following values: * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt * @arg IRDA_IT_TC: Transmission complete interrupt @@ -548,9 +548,9 @@ typedef struct (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK))) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * The Handle Instance which can be USART1 or USART2. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag @@ -563,9 +563,9 @@ typedef struct #define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific IRDA request flag. - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * The Handle Instance which can be USART1 or USART2. - * @param __REQ__: specifies the request flag to set + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request @@ -576,14 +576,14 @@ typedef struct #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable UART/USART associated to IRDA Handle - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * The Handle Instance which can be USART1 or USART2. * @retval None */ #define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART/USART associated to IRDA Handle - * @param __HANDLE__: specifies the IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. * The Handle Instance which can be USART1 or USART2. * @retval None */ @@ -688,13 +688,13 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); */ /** @brief Ensure that IRDA Baud rate is less or equal to maximum value - * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user. + * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user. * @retval True or False */ #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) /** @brief Ensure that IRDA prescaler value is strictly larger than 0 - * @param __PRESCALER__: specifies the IRDA prescaler value set by the user. + * @param __PRESCALER__ specifies the IRDA prescaler value set by the user. * @retval True or False */ #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda_ex.h index 79b78acfc6..c4cdbb1b83 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda_ex.h @@ -81,8 +81,8 @@ * @{ */ /** @brief Reports the IRDA clock source. - * @param __HANDLE__: specifies the IRDA Handle - * @param __CLOCKSOURCE__ : output variable + * @param __HANDLE__ specifies the IRDA Handle + * @param __CLOCKSOURCE__ output variable * @retval IRDA clocking source, written in __CLOCKSOURCE__. */ #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ @@ -171,7 +171,7 @@ /** @brief Reports the mask to apply to retrieve the received data * according to the word length and to the parity bits activation. - * @param __HANDLE__: specifies the IRDA Handle + * @param __HANDLE__ specifies the IRDA Handle * @retval mask to apply to USART RDR register value. */ #define IRDA_MASK_COMPUTATION(__HANDLE__) \ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_iwdg.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_iwdg.h index 52b0d6a11b..c65baeb824 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_iwdg.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_iwdg.h @@ -126,7 +126,7 @@ typedef struct /** * @brief Enable the IWDG peripheral. - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ IWDG handle * @retval None */ #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) @@ -134,7 +134,7 @@ typedef struct /** * @brief Reload IWDG counter with value defined in the reload register * (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled). - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ IWDG handle * @retval None */ #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) @@ -194,21 +194,21 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ IWDG handle * @retval None */ #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) /** * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ IWDG handle * @retval None */ #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) /** * @brief Check IWDG prescaler value. - * @param __PRESCALER__: IWDG prescaler value + * @param __PRESCALER__ IWDG prescaler value * @retval None */ #define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ @@ -221,14 +221,14 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** * @brief Check IWDG reload value. - * @param __RELOAD__: IWDG reload value + * @param __RELOAD__ IWDG reload value * @retval None */ #define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) /** * @brief Check IWDG window value. - * @param __WINDOW__: IWDG window value + * @param __WINDOW__ IWDG window value * @retval None */ #define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_jpeg.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_jpeg.h index db296cdcf4..6a560a1ec8 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_jpeg.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_jpeg.h @@ -274,7 +274,7 @@ typedef struct */ /** @brief Reset JPEG handle state - * @param __HANDLE__: specifies the JPEG handle. + * @param __HANDLE__ specifies the JPEG handle. * @retval None */ #define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET) @@ -282,14 +282,14 @@ typedef struct /** * @brief Enable the JPEG peripheral. - * @param __HANDLE__: specifies the JPEG handle. + * @param __HANDLE__ specifies the JPEG handle. * @retval None */ #define __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN) /** * @brief Disable the JPEG peripheral. - * @param __HANDLE__: specifies the JPEG handle. + * @param __HANDLE__ specifies the JPEG handle. * @retval None */ #define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN) @@ -297,8 +297,8 @@ typedef struct /** * @brief Check the specified JPEG status flag. - * @param __HANDLE__: specifies the JPEG handle. - * @param __FLAG__ : specifies the flag to check + * @param __HANDLE__ specifies the JPEG handle. + * @param __FLAG__ specifies the flag to check * This parameter can be one of the following values: * @arg JPEG_FLAG_IFTF : The input FIFO is not full and is bellow its threshold flag * @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written @@ -317,8 +317,8 @@ typedef struct /** * @brief Clear the specified JPEG status flag. - * @param __HANDLE__: specifies the JPEG handle. - * @param __FLAG__ : specifies the flag to clear + * @param __HANDLE__ specifies the JPEG handle. + * @param __FLAG__ specifies the flag to clear * This parameter can be one of the following values: * @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process * and than last data has been sent to the output FIFO @@ -331,8 +331,8 @@ typedef struct /** * @brief Enable Interrupt. - * @param __HANDLE__: specifies the JPEG handle. - * @param __INTERRUPT__ : specifies the interrupt to enable + * @param __HANDLE__ specifies the JPEG handle. + * @param __INTERRUPT__ specifies the interrupt to enable * This parameter can be one of the following values: * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt @@ -347,8 +347,8 @@ typedef struct /** * @brief Disable Interrupt. - * @param __HANDLE__: specifies the JPEG handle. - * @param __INTERRUPT__ : specifies the interrupt to disable + * @param __HANDLE__ specifies the JPEG handle. + * @param __INTERRUPT__ specifies the interrupt to disable * This parameter can be one of the following values: * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt @@ -366,8 +366,8 @@ typedef struct /** * @brief Get Interrupt state. - * @param __HANDLE__: specifies the JPEG handle. - * @param __INTERRUPT__ : specifies the interrupt to check + * @param __HANDLE__ specifies the JPEG handle. + * @param __INTERRUPT__ specifies the interrupt to check * This parameter can be one of the following values: * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_lptim.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_lptim.h index f08911fe62..d3b4a50c36 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_lptim.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_lptim.h @@ -153,20 +153,54 @@ typedef enum __HAL_LPTIM_StateTypeDef /** * @brief LPTIM handle Structure definition */ -typedef struct +typedef struct __LPTIM_HandleTypeDef { - LPTIM_TypeDef *Instance; /*!< Register base address */ - - LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */ - - HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ - - HAL_LockTypeDef Lock; /*!< LPTIM locking object */ - - __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ - + LPTIM_TypeDef *Instance; /*!< Register base address */ + LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */ + HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ + HAL_LockTypeDef Lock; /*!< LPTIM locking object */ + __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + void (* MspInitCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Msp Init Callback */ + void (* MspDeInitCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Msp DeInit Callback */ + + void (* CompareMatchCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Compare Match Callback */ + void (* AutoReloadMatchCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Auto Reload Match Callback */ + void (* TriggerCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Trigger Callback */ + void (* CompareWriteCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Compare Write Callback */ + void (* AutoReloadWriteCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Auto Reload Write Callback */ + void (* DirectionUpCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Direction Up Callback */ + void (* DirectionDownCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Direction Down Callback */ +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + }LPTIM_HandleTypeDef; +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL LPTIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM MspInit Callback ID */ + HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM MspDeInit Callback ID */ + + HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< LPTIM Compare Match Callback ID */ + HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID = 0x03U, /*!< LPTIM Auto Reload Match Callback ID */ + HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< LPTIM Trigger Callback ID */ + HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< LPTIM Compare Write Callback ID */ + HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID = 0x06U, /*!< LPTIM Auto Reload Write Callback ID */ + HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< LPTIM Direction Up Callback ID */ + HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< LPTIM Direction Down Callback ID */ +}HAL_LPTIM_CallbackIDTypeDef; + +/** + * @brief HAL LPTIM Callback pointer definition + */ +typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< pointer to the LPTIM callback function */ + +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + /** * @} */ @@ -327,14 +361,14 @@ typedef struct */ /** @brief Reset LPTIM handle state - * @param __HANDLE__: LPTIM handle + * @param __HANDLE__ LPTIM handle * @retval None */ #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) /** * @brief Enable/Disable the LPTIM peripheral. - * @param __HANDLE__: LPTIM handle + * @param __HANDLE__ LPTIM handle * @retval None */ #define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE)) @@ -342,7 +376,7 @@ typedef struct /** * @brief Starts the LPTIM peripheral in Continuous or in single mode. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT) @@ -351,24 +385,24 @@ typedef struct /** * @brief Writes the passed parameter in the Autoreload register. - * @param __HANDLE__: LPTIM handle - * @param __VALUE__ : Autoreload value + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Autoreload value * @retval None */ #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) /** * @brief Writes the passed parameter in the Compare register. - * @param __HANDLE__: LPTIM handle - * @param __VALUE__ : Compare value + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Compare value * @retval None */ #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) /** * @brief Checks whether the specified LPTIM flag is set or not. - * @param __HANDLE__: LPTIM handle - * @param __FLAG__ : LPTIM flag to check + * @param __HANDLE__ LPTIM handle + * @param __FLAG__ LPTIM flag to check * This parameter can be a value of: * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. @@ -383,8 +417,8 @@ typedef struct /** * @brief Clears the specified LPTIM flag. - * @param __HANDLE__: LPTIM handle. - * @param __FLAG__ : LPTIM flag to clear. + * @param __HANDLE__ LPTIM handle. + * @param __FLAG__ LPTIM flag to clear. * This parameter can be a value of: * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. @@ -399,8 +433,8 @@ typedef struct /** * @brief Enable the specified LPTIM interrupt. - * @param __HANDLE__ : LPTIM handle. - * @param __INTERRUPT__ : LPTIM interrupt to set. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. * This parameter can be a value of: * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. @@ -415,8 +449,8 @@ typedef struct /** * @brief Disable the specified LPTIM interrupt. - * @param __HANDLE__ : LPTIM handle. - * @param __INTERRUPT__ : LPTIM interrupt to set. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. * This parameter can be a value of: * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. @@ -431,8 +465,8 @@ typedef struct /** * @brief Checks whether the specified LPTIM interrupt is set or not. - * @param __HANDLE__ : LPTIM handle. - * @param __INTERRUPT__ : LPTIM interrupt to check. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to check. * This parameter can be a value of: * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. @@ -612,6 +646,12 @@ void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + /* Peripheral State functions ************************************************/ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h index cba7041e2b..8e048ecc3f 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h @@ -363,29 +363,29 @@ typedef struct */ /** @brief Reset LTDC handle state - * @param __HANDLE__: specifies the LTDC handle. + * @param __HANDLE__ specifies the LTDC handle. * @retval None */ #define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) /** * @brief Enable the LTDC. - * @param __HANDLE__: LTDC handle + * @param __HANDLE__ LTDC handle * @retval None. */ #define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN) /** * @brief Disable the LTDC. - * @param __HANDLE__: LTDC handle + * @param __HANDLE__ LTDC handle * @retval None. */ #define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN)) /** * @brief Enable the LTDC Layer. - * @param __HANDLE__: LTDC handle - * @param __LAYER__: Specify the layer to be enabled + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be enabled * This parameter can be 0 or 1 * @retval None. */ @@ -393,8 +393,8 @@ typedef struct /** * @brief Disable the LTDC Layer. - * @param __HANDLE__: LTDC handle - * @param __LAYER__: Specify the layer to be disabled + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be disabled * This parameter can be 0 or 1 * @retval None. */ @@ -402,7 +402,7 @@ typedef struct /** * @brief Reload Layer Configuration. - * @param __HANDLE__: LTDC handle + * @param __HANDLE__ LTDC handle * @retval None. */ #define __HAL_LTDC_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR) @@ -410,8 +410,8 @@ typedef struct /* Interrupt & Flag management */ /** * @brief Get the LTDC pending flags. - * @param __HANDLE__: LTDC handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg LTDC_FLAG_LI: Line Interrupt flag * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag @@ -423,8 +423,8 @@ typedef struct /** * @brief Clears the LTDC pending flags. - * @param __HANDLE__: LTDC handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg LTDC_FLAG_LI: Line Interrupt flag * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag @@ -436,8 +436,8 @@ typedef struct /** * @brief Enables the specified LTDC interrupts. - * @param __HANDLE__: LTDC handle - * @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ specifies the LTDC interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg LTDC_IT_LI: Line Interrupt flag * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag @@ -449,8 +449,8 @@ typedef struct /** * @brief Disables the specified LTDC interrupts. - * @param __HANDLE__: LTDC handle - * @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ specifies the LTDC interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg LTDC_IT_LI: Line Interrupt flag * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag @@ -462,8 +462,8 @@ typedef struct /** * @brief Checks whether the specified LTDC interrupt has occurred or not. - * @param __HANDLE__: LTDC handle - * @param __INTERRUPT__: specifies the LTDC interrupt source to check. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ specifies the LTDC interrupt source to check. * This parameter can be one of the following values: * @arg LTDC_IT_LI: Line Interrupt flag * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mdios.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mdios.h index 6f980992e4..50d3b51089 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mdios.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mdios.h @@ -244,14 +244,14 @@ typedef struct */ /** @brief Reset MDIOS handle state - * @param __HANDLE__: MDIOS handle. + * @param __HANDLE__ MDIOS handle. * @retval None */ #define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET) /** * @brief Enable/Disable the MDIOS peripheral. - * @param __HANDLE__: specifies the MDIOS handle. + * @param __HANDLE__ specifies the MDIOS handle. * @retval None */ #define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN) @@ -260,8 +260,8 @@ typedef struct /** * @brief Enable the MDIOS device interrupt. - * @param __HANDLE__: specifies the MDIOS handle. - * @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled. + * @param __HANDLE__ specifies the MDIOS handle. + * @param __INTERRUPT__ specifies the MDIOS interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg MDIOS_IT_WRITE: Register write interrupt * @arg MDIOS_IT_READ: Register read interrupt @@ -272,8 +272,8 @@ typedef struct /** * @brief Disable the MDIOS device interrupt. - * @param __HANDLE__: specifies the MDIOS handle. - * @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled. + * @param __HANDLE__ specifies the MDIOS handle. + * @param __INTERRUPT__ specifies the MDIOS interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg MDIOS_IT_WRITE: Register write interrupt * @arg MDIOS_IT_READ: Register read interrupt @@ -283,22 +283,22 @@ typedef struct #define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) /** @brief Set MDIOS slave get write register flag - * @param __HANDLE__: specifies the MDIOS handle. - * @param __FLAG__: specifies the write register flag + * @param __HANDLE__ specifies the MDIOS handle. + * @param __FLAG__ specifies the write register flag * @retval The state of write flag */ #define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__)) /** @brief MDIOS slave get read register flag - * @param __HANDLE__: specifies the MDIOS handle. - * @param __FLAG__: specifies the read register flag + * @param __HANDLE__ specifies the MDIOS handle. + * @param __FLAG__ specifies the read register flag * @retval The state of read flag */ #define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__)) /** @brief MDIOS slave get interrupt - * @param __HANDLE__: specifies the MDIOS handle. - * @param __FLAG__ : specifies the Error flag. + * @param __HANDLE__ specifies the MDIOS handle. + * @param __FLAG__ specifies the Error flag. * This parameter can be one or a combination of the following values: * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt * @arg MDIOS_START_ERROR_FLAG: Register read interrupt @@ -308,8 +308,8 @@ typedef struct #define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__)) /** @brief MDIOS slave clear interrupt - * @param __HANDLE__: specifies the MDIOS handle. - * @param __FLAG__ : specifies the Error flag. + * @param __HANDLE__ specifies the MDIOS handle. + * @param __FLAG__ specifies the Error flag. * This parameter can be one or a combination of the following values: * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt * @arg MDIOS_START_ERROR_FLAG: Register read interrupt @@ -320,8 +320,8 @@ typedef struct /** * @brief Checks whether the specified MDIOS interrupt is set or not. - * @param __HANDLE__: specifies the MDIOS handle. - * @param __INTERRUPT__ : specifies the MDIOS interrupt sources + * @param __HANDLE__ specifies the MDIOS handle. + * @param __INTERRUPT__ specifies the MDIOS interrupt sources * This parameter can be one or a combination of the following values: * @arg MDIOS_IT_WRITE: Register write interrupt * @arg MDIOS_IT_READ: Register read interrupt diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h index c88b22aec7..7c8425cacb 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h @@ -362,8 +362,8 @@ typedef struct /** * @brief Enable the MMC device interrupt. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -393,8 +393,8 @@ typedef struct /** * @brief Disable the MMC device interrupt. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -424,8 +424,8 @@ typedef struct /** * @brief Check whether the specified MMC flag is set or not. - * @param __HANDLE__: MMC Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ MMC Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -455,8 +455,8 @@ typedef struct /** * @brief Clear the MMC's pending flags. - * @param __HANDLE__: MMC Handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ MMC Handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -475,8 +475,8 @@ typedef struct /** * @brief Check whether the specified MMC interrupt has occurred or not. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -506,8 +506,8 @@ typedef struct /** * @brief Clear the MMC's interrupt pending bits. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h index 03556c5767..39ce52afa8 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h @@ -152,7 +152,7 @@ typedef struct */ /** @brief Reset NAND handle state - * @param __HANDLE__: specifies the NAND handle. + * @param __HANDLE__ specifies the NAND handle. * @retval None */ #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) @@ -283,8 +283,8 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); /** * @brief NAND memory address computation. - * @param __ADDRESS__: NAND memory address. - * @param __HANDLE__ : NAND handle. + * @param __ADDRESS__ NAND memory address. + * @param __HANDLE__ NAND handle. * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ @@ -294,7 +294,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); /** * @brief NAND memory address cycling. - * @param __ADDRESS__: NAND memory address. + * @param __ADDRESS__ NAND memory address. * @retval NAND address cycling value. */ #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ @@ -304,7 +304,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); /** * @brief NAND memory Columns cycling. - * @param __ADDRESS__: NAND memory address. + * @param __ADDRESS__ NAND memory address. * @retval NAND Column address cycling value. */ #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nor.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nor.h index 3a9d1723e2..b51a40b075 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nor.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nor.h @@ -142,7 +142,7 @@ typedef struct * @{ */ /** @brief Reset NOR handle state - * @param __HANDLE__: specifies the NOR handle. + * @param __HANDLE__ specifies the NOR handle. * @retval None */ #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) @@ -255,9 +255,9 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres */ /** * @brief NOR memory address shifting. - * @param __NOR_ADDRESS: NOR base address - * @param __NOR_MEMORY_WIDTH_: NOR memory width - * @param __ADDRESS__: NOR memory address + * @param __NOR_ADDRESS NOR base address + * @param __NOR_MEMORY_WIDTH_ NOR memory width + * @param __ADDRESS__ NOR memory address * @retval NOR shifted address value */ #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ @@ -267,8 +267,8 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /** * @brief NOR memory write data to specified address. - * @param __ADDRESS__: NOR memory address - * @param __DATA__: Data to write + * @param __ADDRESS__ NOR memory address + * @param __DATA__ Data to write * @retval None */ #define NOR_WRITE(__ADDRESS__, __DATA__) do{ \ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h index 05dcd35fa9..faf27ecb63 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h @@ -190,16 +190,18 @@ typedef struct #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ + EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\ + }while(0) -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) - -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ - EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\ - EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\ - EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\ + EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ + }while(0) +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ + EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\ + EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\ + EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\ + }while(0) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) @@ -208,18 +210,21 @@ typedef struct #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE - +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ + EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ + }while(0) -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\ + EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ + }while(0) + +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ + EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ + EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ + EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ + }while(0) + -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE - #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h index a9c056d973..168ac64b6d 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h @@ -169,7 +169,7 @@ typedef struct */ /** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__: specifies the regulator output voltage to achieve + * @param __REGULATOR__ specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption when the device does * not operate at the maximum frequency (refer to the datasheets for more details). * This parameter can be one of the following values: @@ -187,7 +187,7 @@ typedef struct } while(0) /** @brief Check PWR flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B), @@ -208,7 +208,7 @@ typedef struct #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) /** @brief Clear the PWR's pending flags. - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg PWR_FLAG_SB: StandBy flag */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h index 16d3de123e..924fe67d14 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h @@ -147,7 +147,7 @@ #define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN)) /** @brief Check PWR flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode * is ready @@ -164,7 +164,7 @@ #define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY) /** @brief Check Wake Up flag is set or not. - * @param __WUFLAG__: specifies the Wake Up flag to check. + * @param __WUFLAG__ specifies the Wake Up flag to check. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2 @@ -176,7 +176,7 @@ #define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__)) /** @brief Clear the WakeUp pins flags. - * @param __WUFLAG__: specifies the Wake Up pin flag to clear. + * @param __WUFLAG__ specifies the Wake Up pin flag to clear. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2 diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h index 217ebad080..955795a8f6 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h @@ -429,26 +429,26 @@ typedef struct */ /** @brief Reset QSPI handle state - * @param __HANDLE__: QSPI handle. + * @param __HANDLE__ QSPI handle. * @retval None */ #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) /** @brief Enable QSPI - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable QSPI - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enables the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to enable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Time out interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -461,8 +461,8 @@ typedef struct /** @brief Disables the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to disable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -474,8 +474,8 @@ typedef struct #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Checks whether the specified QSPI interrupt source is enabled. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Time out interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -488,8 +488,8 @@ typedef struct /** * @brief Get the selected QSPI's flag status. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI flag to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Time out flag @@ -502,8 +502,8 @@ typedef struct #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Time out flag * @arg QSPI_FLAG_SM: QSPI Status match flag diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h index be6f851b4a..d317437858 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h @@ -265,8 +265,10 @@ typedef struct /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source * @{ */ +#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U) #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U) +#define RCC_RTCCLKSOURCE_HSE_DIVX ((uint32_t)0x00000300U) #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U) #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U) #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U) @@ -692,7 +694,7 @@ typedef struct /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. - * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value. + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value. * (default is RCC_HSICALIBRATION_DEFAULT). */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\ @@ -737,7 +739,7 @@ typedef struct * @note This function reset the CSSON bit, so if the clock security system(CSS) * was previously enabled you have to enable it again after calling this * function. - * @param __STATE__: specifies the new state of the HSE. + * @param __STATE__ specifies the new state of the HSE. * This parameter can be one of the following values: * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. @@ -785,7 +787,7 @@ typedef struct * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. - * @param __STATE__: specifies the new state of the LSE. + * @param __STATE__ specifies the new state of the LSE. * This parameter can be one of the following values: * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. @@ -836,12 +838,13 @@ typedef struct * @note Once the RTC clock is configured it can't be changed unless the * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by * a Power On Reset (POR). - * @param __RTCCLKSource__: specifies the RTC clock source. + * @param __RTCCLKSource__ specifies the RTC clock source. * This parameter can be one of the following values: - * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. - * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. - * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected - * as RTC clock, where x:[2,31] + @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the HSE clock is used as RTC clock source, the RTC @@ -850,11 +853,28 @@ typedef struct * RTC clock source). */ #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \ - } while (0) + } while (0) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** + * @brief Get the RTC and HSE clock divider (RTCPRE). + * @retval Returned value can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + */ +#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) /** @brief Macros to force or release the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) @@ -883,7 +903,7 @@ typedef struct /** @brief Macro to configure the PLL clock source. * @note This function must be used only when the main PLL is disabled. - * @param __PLLSOURCE__: specifies the PLL entry clock source. + * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry @@ -893,7 +913,7 @@ typedef struct /** @brief Macro to configure the PLL multiplication factor. * @note This function must be used only when the main PLL is disabled. - * @param __PLLM__: specifies the division factor for PLL VCO input clock + * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency @@ -911,7 +931,7 @@ typedef struct /** @brief Macro to configure the I2S clock source (I2SCLK). * @note This function must be called before enabling the I2S APB clock. - * @param __SOURCE__: specifies the I2S clock source. + * @param __SOURCE__ specifies the I2S clock source. * This parameter can be one of the following values: * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin @@ -935,7 +955,7 @@ typedef struct */ /** * @brief Macro to configure the system clock source. - * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. + * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. * This parameter can be one of the following values: * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. @@ -958,7 +978,7 @@ typedef struct * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE * (to be done once after reset). - * @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability. + * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. * This parameter can be one of the following values: * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. @@ -1032,7 +1052,7 @@ typedef struct /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt. * @arg RCC_IT_LSERDY: LSE ready interrupt. @@ -1045,7 +1065,7 @@ typedef struct /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt. * @arg RCC_IT_LSERDY: LSE ready interrupt. @@ -1058,7 +1078,7 @@ typedef struct /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] * bits to clear the selected interrupt pending bits. - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt. * @arg RCC_IT_LSERDY: LSE ready interrupt. @@ -1071,7 +1091,7 @@ typedef struct #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) /** @brief Check the RCC's interrupt has occurred or not. - * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt. * @arg RCC_IT_LSERDY: LSE ready interrupt. @@ -1090,7 +1110,7 @@ typedef struct #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) /** @brief Check RCC flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. @@ -1130,7 +1150,7 @@ typedef struct * @{ */ /* Initialization and de-initialization functions ******************************/ -void HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** @@ -1171,10 +1191,12 @@ void HAL_RCC_CSSCallback(void); * @{ */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ -#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ -#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ -#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ +#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ +#define PLLI2S_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ +#define PLLSAI_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias * @brief RCC registers bit address alias diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h index fdb41ed517..8f79fc4eb0 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h @@ -2509,31 +2509,31 @@ typedef struct #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @brief Macro to configure the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__: specifies the PLL entry clock source. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__: specifies the division factor for PLL VCO input clock + * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLL jitter. - * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz. - * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) * This parameter must be a number in the range {2, 4, 6, or 8}. * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on * the System clock frequency. - * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks + * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work * correctly. - * @param __PLLR__: specifies the division factor for DSI clock + * @param __PLLR__ specifies the division factor for DSI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. */ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ @@ -2545,25 +2545,25 @@ typedef struct #else /** @brief Macro to configure the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__: specifies the PLL entry clock source. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__: specifies the division factor for PLL VCO input clock + * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLL jitter. - * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz. - * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) * This parameter must be a number in the range {2, 4, 6, or 8}. * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on * the System clock frequency. - * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks + * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, @@ -2579,7 +2579,7 @@ typedef struct /*---------------------------------------------------------------------------------------------*/ /** @brief Macro to configure the Timers clocks prescalers - * @param __PRESC__ : specifies the Timers clocks prescalers selection + * @param __PRESC__ specifies the Timers clocks prescalers selection * This parameter can be one of the following values: * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is * equal to HPRE if PPREx is corresponding to division by 1 or 2, @@ -2605,13 +2605,13 @@ typedef struct * @note This function must be used only when the PLLSAI is disabled. * @note PLLSAI clock source is common with the main PLL (configured in * RCC_PLLConfig function ) - * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks + * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. - * @param __PLLSAIQ__: specifies the division factor for SAI clock + * @param __PLLSAIQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. */ #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \ @@ -2623,13 +2623,13 @@ typedef struct * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API) - * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock. + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * @param __PLLI2SQ__: specifies the division factor for SAI clock. + * @param __PLLI2SQ__ specifies the division factor for SAI clock. * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @param __PLLI2SR__: specifies the division factor for I2S clock + * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. @@ -2643,15 +2643,15 @@ typedef struct * @note This function must be used only when the PLLSAI is disabled. * @note PLLSAI clock source is common with the main PLL (configured in * RCC_PLLConfig function ) - * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks + * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. - * @param __PLLSAIQ__: specifies the division factor for SAI clock + * @param __PLLSAIQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @param __PLLSAIR__: specifies the division factor for LTDC clock + * @param __PLLSAIR__ specifies the division factor for LTDC clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. */ #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ @@ -2664,15 +2664,15 @@ typedef struct * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API) - * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock. + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock. + * @param __PLLI2SP__ specifies the division factor for SPDDIF-RX clock. * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. - * @param __PLLI2SQ__: specifies the division factor for SAI clock. + * @param __PLLI2SQ__ specifies the division factor for SAI clock. * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @param __PLLI2SR__: specifies the division factor for I2S clock + * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. @@ -2686,7 +2686,7 @@ typedef struct /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. * @note This function must be called before enabling the PLLI2S. - * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock . + * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock . * This parameter must be a number between 1 and 32. * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ */ @@ -2694,7 +2694,7 @@ typedef struct /** @brief Macro to configure the SAI clock Divider coming from PLLSAI. * @note This function must be called before enabling the PLLSAI. - * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock . + * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . * This parameter must be a number between Min_Data = 1 and Max_Data = 32. * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ */ @@ -2704,7 +2704,7 @@ typedef struct defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. * @note This function must be called before enabling the PLLSAI. - * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock . + * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ */ @@ -2715,7 +2715,7 @@ typedef struct /** @brief Macro to configure SAI1 clock source selection. * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI1 clock source. + * @param __SOURCE__ specifies the SAI1 clock source. * This parameter can be one of the following values: * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used * as SAI1 clock. @@ -2748,7 +2748,7 @@ typedef struct /** @brief Macro to configure SAI2 clock source selection. * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI2 clock source. + * @param __SOURCE__ specifies the SAI2 clock source. * This parameter can be one of the following values: * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used * as SAI2 clock. @@ -2810,7 +2810,7 @@ typedef struct /** @brief Macro to configure the I2C1 clock (I2C1CLK). * - * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source. + * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. * This parameter can be one of the following values: * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock @@ -2829,7 +2829,7 @@ typedef struct /** @brief Macro to configure the I2C2 clock (I2C2CLK). * - * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source. + * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. * This parameter can be one of the following values: * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock @@ -2848,7 +2848,7 @@ typedef struct /** @brief Macro to configure the I2C3 clock (I2C3CLK). * - * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source. + * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. * This parameter can be one of the following values: * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock @@ -2867,7 +2867,7 @@ typedef struct /** @brief Macro to configure the I2C4 clock (I2C4CLK). * - * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source. + * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. * This parameter can be one of the following values: * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock @@ -2886,7 +2886,7 @@ typedef struct /** @brief Macro to configure the USART1 clock (USART1CLK). * - * @param __USART1_CLKSOURCE__: specifies the USART1 clock source. + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. * This parameter can be one of the following values: * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock @@ -2907,7 +2907,7 @@ typedef struct /** @brief Macro to configure the USART2 clock (USART2CLK). * - * @param __USART2_CLKSOURCE__: specifies the USART2 clock source. + * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. * This parameter can be one of the following values: * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock @@ -2928,7 +2928,7 @@ typedef struct /** @brief Macro to configure the USART3 clock (USART3CLK). * - * @param __USART3_CLKSOURCE__: specifies the USART3 clock source. + * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. * This parameter can be one of the following values: * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock @@ -2949,7 +2949,7 @@ typedef struct /** @brief Macro to configure the UART4 clock (UART4CLK). * - * @param __UART4_CLKSOURCE__: specifies the UART4 clock source. + * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. * This parameter can be one of the following values: * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock @@ -2970,7 +2970,7 @@ typedef struct /** @brief Macro to configure the UART5 clock (UART5CLK). * - * @param __UART5_CLKSOURCE__: specifies the UART5 clock source. + * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. * This parameter can be one of the following values: * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock @@ -2991,7 +2991,7 @@ typedef struct /** @brief Macro to configure the USART6 clock (USART6CLK). * - * @param __USART6_CLKSOURCE__: specifies the USART6 clock source. + * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. * This parameter can be one of the following values: * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock @@ -3012,7 +3012,7 @@ typedef struct /** @brief Macro to configure the UART7 clock (UART7CLK). * - * @param __UART7_CLKSOURCE__: specifies the UART7 clock source. + * @param __UART7_CLKSOURCE__ specifies the UART7 clock source. * This parameter can be one of the following values: * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock @@ -3033,7 +3033,7 @@ typedef struct /** @brief Macro to configure the UART8 clock (UART8CLK). * - * @param __UART8_CLKSOURCE__: specifies the UART8 clock source. + * @param __UART8_CLKSOURCE__ specifies the UART8 clock source. * This parameter can be one of the following values: * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock @@ -3054,7 +3054,7 @@ typedef struct /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). * - * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source. + * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. * This parameter can be one of the following values: * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock @@ -3075,7 +3075,7 @@ typedef struct /** @brief Macro to configure the CEC clock (CECCLK). * - * @param __CEC_CLKSOURCE__: specifies the CEC clock source. + * @param __CEC_CLKSOURCE__ specifies the CEC clock source. * This parameter can be one of the following values: * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock @@ -3092,7 +3092,7 @@ typedef struct /** @brief Macro to configure the CLK48 source (CLK48CLK). * - * @param __CLK48_SOURCE__: specifies the CLK48 clock source. + * @param __CLK48_SOURCE__ specifies the CLK48 clock source. * This parameter can be one of the following values: * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source @@ -3109,7 +3109,7 @@ typedef struct /** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK). * - * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source. + * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. * This parameter can be one of the following values: * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock @@ -3127,7 +3127,7 @@ typedef struct #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). - * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source. + * @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source. * This parameter can be one of the following values: * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock @@ -3145,7 +3145,7 @@ typedef struct #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /** @brief Macro to configure the DFSDM1 clock - * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source. + * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. * This parameter can be one of the following values: * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock @@ -3161,7 +3161,7 @@ typedef struct #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) /** @brief Macro to configure the DFSDM1 Audio clock - * @param __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source. + * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 Audio clock source. * This parameter can be one of the following values: * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock @@ -3179,7 +3179,7 @@ typedef struct #if defined (STM32F769xx) || defined (STM32F779xx) /** @brief Macro to configure the DSI clock. - * @param __DSI_CLKSOURCE__: specifies the DSI clock source. + * @param __DSI_CLKSOURCE__ specifies the DSI clock source. * This parameter can be one of the following values: * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. @@ -3204,7 +3204,10 @@ typedef struct HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); - +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rng.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rng.h index 89ccbe2365..c51a3e7f98 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rng.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rng.h @@ -137,29 +137,29 @@ typedef struct */ /** @brief Reset RNG handle state - * @param __HANDLE__: RNG Handle + * @param __HANDLE__ RNG Handle * @retval None */ #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) /** * @brief Enables the RNG peripheral. - * @param __HANDLE__: RNG Handle + * @param __HANDLE__ RNG Handle * @retval None */ #define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN) /** * @brief Disables the RNG peripheral. - * @param __HANDLE__: RNG Handle + * @param __HANDLE__ RNG Handle * @retval None */ #define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN) /** * @brief Check the selected RNG flag status. - * @param __HANDLE__: RNG Handle - * @param __FLAG__: RNG flag + * @param __HANDLE__ RNG Handle + * @param __FLAG__ RNG flag * This parameter can be one of the following values: * @arg RNG_FLAG_DRDY: Data ready * @arg RNG_FLAG_CECS: Clock error current status @@ -170,8 +170,8 @@ typedef struct /** * @brief Clears the selected RNG flag status. - * @param __HANDLE__: RNG handle - * @param __FLAG__: RNG flag to clear + * @param __HANDLE__ RNG handle + * @param __FLAG__ RNG flag to clear * @note WARNING: This is a dummy macro for HAL code alignment, * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only. * @retval None @@ -182,22 +182,22 @@ typedef struct /** * @brief Enables the RNG interrupts. - * @param __HANDLE__: RNG Handle + * @param __HANDLE__ RNG Handle * @retval None */ #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE) /** * @brief Disables the RNG interrupts. - * @param __HANDLE__: RNG Handle + * @param __HANDLE__ RNG Handle * @retval None */ #define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE) /** * @brief Checks whether the specified RNG interrupt has occurred or not. - * @param __HANDLE__: RNG Handle - * @param __INTERRUPT__: specifies the RNG interrupt status flag to check. + * @param __HANDLE__ RNG Handle + * @param __INTERRUPT__ specifies the RNG interrupt status flag to check. * This parameter can be one of the following values: * @arg RNG_IT_DRDY: Data ready interrupt * @arg RNG_IT_CEI: Clock error interrupt @@ -208,8 +208,8 @@ typedef struct /** * @brief Clear the RNG interrupt status flags. - * @param __HANDLE__: RNG Handle - * @param __INTERRUPT__: specifies the RNG interrupt status flag to clear. + * @param __HANDLE__ RNG Handle + * @param __INTERRUPT__ specifies the RNG interrupt status flag to clear. * This parameter can be one of the following values: * @arg RNG_IT_CEI: Clock error interrupt * @arg RNG_IT_SEI: Seed error interrupt diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h index d9699f900a..a73e512a45 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h @@ -416,14 +416,14 @@ typedef struct */ /** @brief Reset RTC handle state - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) /** * @brief Disable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ @@ -434,7 +434,7 @@ typedef struct /** * @brief Enable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ @@ -444,36 +444,36 @@ typedef struct /** * @brief Enable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) /** * @brief Disable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) /** * @brief Enable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) /** * @brief Disable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) /** * @brief Enable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_ALRB: Alarm B interrupt @@ -483,8 +483,8 @@ typedef struct /** * @brief Disable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_ALRB: Alarm B interrupt @@ -494,8 +494,8 @@ typedef struct /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt to check. * This parameter can be: * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_ALRB: Alarm B interrupt @@ -505,8 +505,8 @@ typedef struct /** * @brief Get the selected RTC Alarm's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag to check. * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRBF @@ -518,8 +518,8 @@ typedef struct /** * @brief Clear the RTC Alarm's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled. * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRBF @@ -529,8 +529,8 @@ typedef struct /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. * This parameter can be: * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_ALRB: Alarm B interrupt diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h index 44dd9836f2..9e948ba99d 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h @@ -358,22 +358,22 @@ typedef struct /** * @brief Enable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) /** * @brief Disable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) /** * @brief Enable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -382,8 +382,8 @@ typedef struct /** * @brief Disable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -392,8 +392,8 @@ typedef struct /** * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to check. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -402,8 +402,8 @@ typedef struct /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -412,8 +412,8 @@ typedef struct /** * @brief Get the selected RTC WakeUpTimer's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_WUTF * @arg RTC_FLAG_WUTWF @@ -423,8 +423,8 @@ typedef struct /** * @brief Clear the RTC Wake Up timer's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear. * This parameter can be: * @arg RTC_FLAG_WUTF * @retval None @@ -433,50 +433,50 @@ typedef struct /** * @brief Enable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E)) /** * @brief Disable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E)) /** * @brief Enable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) /** * @brief Disable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) /** * @brief Enable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E)) /** * @brief Disable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E)) /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. * This parameter can be: * @arg RTC_IT_TAMP: All tampers interrupts * @arg RTC_IT_TAMP1: Tamper1 interrupt @@ -490,8 +490,8 @@ typedef struct /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. * This parameter can be: * @arg RTC_IT_TAMP: All tampers interrupts * @arg RTC_IT_TAMP1: Tamper1 interrupt @@ -503,8 +503,8 @@ typedef struct /** * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_TAMP1F: Tamper1 flag * @arg RTC_FLAG_TAMP2F: Tamper2 flag @@ -515,8 +515,8 @@ typedef struct /** * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag sources to clear. * This parameter can be: * @arg RTC_FLAG_TAMP1F: Tamper1 flag * @arg RTC_FLAG_TAMP2F: Tamper2 flag @@ -527,22 +527,22 @@ typedef struct /** * @brief Enable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) /** * @brief Disable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) /** * @brief Enable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -551,8 +551,8 @@ typedef struct /** * @brief Disable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -561,8 +561,8 @@ typedef struct /** * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -571,8 +571,8 @@ typedef struct /** * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -581,8 +581,8 @@ typedef struct /** * @brief Get the selected RTC TimeStamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_TSF * @arg RTC_FLAG_TSOVF @@ -592,8 +592,8 @@ typedef struct /** * @brief Clear the RTC Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to clear. * This parameter can be: * @arg RTC_FLAG_TSF * @arg RTC_FLAG_TSOVF @@ -603,22 +603,22 @@ typedef struct /** * @brief Enable the RTC internal TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE)) /** * @brief Disable the RTC internal TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE)) /** * @brief Get the selected RTC Internal Time Stamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_ITSF * @retval None @@ -627,8 +627,8 @@ typedef struct /** * @brief Clear the RTC Internal Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear. * This parameter can be: * @arg RTC_FLAG_ITSF * @retval None @@ -637,36 +637,36 @@ typedef struct /** * @brief Enable the RTC calibration output. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) /** * @brief Disable the calibration output. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) /** * @brief Enable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) /** * @brief Disable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) /** * @brief Get the selected RTC shift operation's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC shift operation Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_SHPF * @retval None diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai.h index 3c0e5a3614..f42068f859 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai.h @@ -563,14 +563,14 @@ typedef struct __SAI_HandleTypeDef */ /** @brief Reset SAI handle state. - * @param __HANDLE__: specifies the SAI Handle. + * @param __HANDLE__ specifies the SAI Handle. * @retval None */ #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) /** @brief Enable or disable the specified SAI interrupts. - * @param __HANDLE__: specifies the SAI Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -585,8 +585,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) /** @brief Check whether the specified SAI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SAI Handle. - * @param __INTERRUPT__: specifies the SAI interrupt source to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the SAI interrupt source to check. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -600,8 +600,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SAI flag is set or not. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SAI_FLAG_OVRUDR: Overrun underrun flag. * @arg SAI_FLAG_MUTEDET: Mute detection flag. @@ -615,8 +615,8 @@ typedef struct __SAI_HandleTypeDef #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified SAI pending flag. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun * @arg SAI_FLAG_MUTEDET: Clear Mute detection diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h index 588068010f..12f33e2b1f 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h @@ -381,8 +381,8 @@ typedef struct /** * @brief Enable the SD device interrupt. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -412,8 +412,8 @@ typedef struct /** * @brief Disable the SD device interrupt. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -443,8 +443,8 @@ typedef struct /** * @brief Check whether the specified SD flag is set or not. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ SD Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -474,8 +474,8 @@ typedef struct /** * @brief Clear the SD's pending flags. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ SD Handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -494,8 +494,8 @@ typedef struct /** * @brief Check whether the specified SD interrupt has occurred or not. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -525,8 +525,8 @@ typedef struct /** * @brief Clear the SD's interrupt pending bits. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h index 61139b37a1..d98e0e6b9e 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h @@ -100,7 +100,7 @@ typedef struct */ /** @brief Reset SDRAM handle state - * @param __HANDLE__: specifies the SDRAM handle. + * @param __HANDLE__ specifies the SDRAM handle. * @retval None */ #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard.h index 94484cedeb..e2a72f5a41 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard.h @@ -587,23 +587,23 @@ typedef struct */ /** @brief Reset SMARTCARD handle state - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2 * @retval None */ #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET) /** @brief Flush the Smartcard DR register - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. * @retval None */ #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) (__HAL_SMARTCARD_SEND_REQ((__HANDLE__), SMARTCARD_RXDATA_FLUSH_REQUEST)) /** @brief Checks whether the specified Smartcard flag is set or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SMARTCARD_FLAG_REACK: Receive enable acknowledge flag * @arg SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag @@ -622,8 +622,8 @@ typedef struct #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified SMARTCARD pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag @@ -641,40 +641,40 @@ typedef struct #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** @brief Clear the SMARTCARD PE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF) /** @brief Clear the SMARTCARD FE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF) /** @brief Clear the SMARTCARD NE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF) /** @brief Clear the SMARTCARD ORE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF) /** @brief Clear the SMARTCARD IDLE pending flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF) /** @brief Enables the specified SmartCard interrupt. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. - * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable. * This parameter can be one of the following values: * @arg SMARTCARD_IT_EOBF: End Of Block interrupt * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt @@ -689,9 +689,9 @@ typedef struct ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disables the specified SmartCard interrupt. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. - * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable. * This parameter can be one of the following values: * @arg SMARTCARD_IT_EOBF: End Of Block interrupt * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt @@ -707,9 +707,9 @@ typedef struct ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Checks whether the specified SmartCard interrupt has occurred or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. - * @param __IT__: specifies the SMARTCARD interrupt to check. + * @param __IT__ specifies the SMARTCARD interrupt to check. * This parameter can be one of the following values: * @arg SMARTCARD_IT_EOBF: End Of Block interrupt * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt @@ -725,9 +725,9 @@ typedef struct #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U))) /** @brief Checks whether the specified SmartCard interrupt interrupt source is enabled. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. - * @param __IT__: specifies the SMARTCARD interrupt source to check. + * @param __IT__ specifies the SMARTCARD interrupt source to check. * This parameter can be one of the following values: * @arg SMARTCARD_IT_EOBF: End Of Block interrupt * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt @@ -746,9 +746,9 @@ typedef struct /** @brief Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg USART_CLEAR_PEF: Parity Error Clear Flag @@ -763,9 +763,9 @@ typedef struct #define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific SMARTCARD request flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. - * @param __REQ__: specifies the request flag to set + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request * @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request @@ -775,23 +775,23 @@ typedef struct #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) /** @brief Enable the USART associated to the SMARTCARD Handle - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. * @retval None */ #define __HAL_SMARTCARD_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable the USART associated to the SMARTCARD Handle - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. * @retval None */ #define __HAL_SMARTCARD_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) /** @brief Macros to enable or disable the SmartCard DMA request. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. - * @param __REQUEST__: specifies the SmartCard DMA request. + * @param __REQUEST__ specifies the SmartCard DMA request. * This parameter can be one of the following values: * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard_ex.h index e0ffafa52f..6f08dbf5ff 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard_ex.h @@ -134,8 +134,8 @@ /* Exported macro ------------------------------------------------------------*/ /** @brief Reports the SMARTCARD clock source. - * @param __HANDLE__: specifies the USART Handle - * @param __CLOCKSOURCE__ : output variable + * @param __HANDLE__ specifies the USART Handle + * @param __CLOCKSOURCE__ output variable * @retval the USART clocking source, written in __CLOCKSOURCE__. */ #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ @@ -223,7 +223,7 @@ } while(0) /** @brief Set the Transmission Completion flag - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced * to SMARTCARD_TC (transmission completion indication when guard time has elapsed). @@ -249,7 +249,7 @@ #endif /** @brief Return the transmission completion flag. - * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. * When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is * reported. @@ -264,7 +264,7 @@ /** * @brief Ensure that SMARTCARD frame transmission completion used flag is valid. - * @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag. + * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag. * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid) */ #if defined(USART_TCBGT_SUPPORT) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smbus.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smbus.h index f874a15d63..83a50722ab 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smbus.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smbus.h @@ -38,7 +38,7 @@ #define __STM32F7xx_HAL_SMBUS_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -97,7 +97,7 @@ typedef struct This parameter can be a value of @ref SMBUS_peripheral_mode */ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. - (Enable bits and different timeout values) + (Enable bits and different timeout values) This parameter calculated by referring to SMBUS initialization section in Reference manual */ } SMBUS_InitTypeDef; @@ -166,7 +166,7 @@ typedef struct __IO uint32_t ErrorCode; /*!< SMBUS Error code */ -}SMBUS_HandleTypeDef; +} SMBUS_HandleTypeDef; /** * @} */ @@ -279,9 +279,9 @@ typedef struct */ #define SMBUS_NO_STARTSTOP (0x00000000U) -#define SMBUS_GENERATE_STOP I2C_CR2_STOP -#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) -#define SMBUS_GENERATE_START_WRITE I2C_CR2_START +#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /** * @} */ @@ -427,17 +427,17 @@ typedef struct * @param __HANDLE__ specifies the SMBUS Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref SMBUS_FLAG_TXE Transmit data register empty + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) - * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag - * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) - * @arg @ref SMBUS_FLAG_TCR Transfer complete reload + * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) + * @arg @ref SMBUS_FLAG_TCR Transfer complete reload * @arg @ref SMBUS_FLAG_BERR Bus error * @arg @ref SMBUS_FLAG_ARLO Arbitration lost - * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun * @arg @ref SMBUS_FLAG_PECERR PEC error in reception * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref SMBUS_FLAG_ALERT SMBus alert @@ -454,11 +454,11 @@ typedef struct * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) - * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag * @arg @ref SMBUS_FLAG_BERR Bus error * @arg @ref SMBUS_FLAG_ARLO Arbitration lost - * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun * @arg @ref SMBUS_FLAG_PECERR PEC error in reception * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref SMBUS_FLAG_ALERT SMBus alert @@ -500,6 +500,8 @@ typedef struct #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) +#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) @@ -590,9 +592,11 @@ typedef struct /* Initialization and de-initialization functions **********************************/ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); -HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spdifrx.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spdifrx.h index 6435fb87c4..cca2a596d1 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spdifrx.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spdifrx.h @@ -343,34 +343,34 @@ typedef struct */ /** @brief Reset SPDIFRX handle state - * @param __HANDLE__: SPDIFRX handle. + * @param __HANDLE__ SPDIFRX handle. * @retval None */ #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN) /** @brief Disable the specified SPDIFRX peripheral (IDLE State). - * @param __HANDLE__: specifies the SPDIFRX Handle. + * @param __HANDLE__ specifies the SPDIFRX Handle. * @retval None */ #define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE) /** @brief Enable the specified SPDIFRX peripheral (SYNC State). - * @param __HANDLE__: specifies the SPDIFRX Handle. + * @param __HANDLE__ specifies the SPDIFRX Handle. * @retval None */ #define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC) /** @brief Enable the specified SPDIFRX peripheral (RCV State). - * @param __HANDLE__: specifies the SPDIFRX Handle. + * @param __HANDLE__ specifies the SPDIFRX Handle. * @retval None */ #define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV) /** @brief Enable or disable the specified SPDIFRX interrupts. - * @param __HANDLE__: specifies the SPDIFRX Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SPDIFRX_IT_RXNE * @arg SPDIFRX_IT_CSRNE @@ -385,8 +385,8 @@ typedef struct #define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__))) /** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the SPDIFRX Handle. - * @param __INTERRUPT__: specifies the SPDIFRX interrupt source to check. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __INTERRUPT__ specifies the SPDIFRX interrupt source to check. * This parameter can be one of the following values: * @arg SPDIFRX_IT_RXNE * @arg SPDIFRX_IT_CSRNE @@ -400,8 +400,8 @@ typedef struct #define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified SPDIFRX flag is set or not. - * @param __HANDLE__: specifies the SPDIFRX Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPDIFRX_FLAG_RXNE * @arg SPDIFRX_FLAG_CSRNE @@ -417,8 +417,8 @@ typedef struct #define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg SPDIFRX_FLAG_PERR diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h index 5c53c362c0..5dfcc474bb 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h @@ -393,16 +393,16 @@ typedef struct __SPI_HandleTypeDef */ /** @brief Reset SPI handle state. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) /** @brief Enable or disable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -413,9 +413,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) /** @brief Check whether the specified SPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -425,9 +425,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag @@ -443,14 +443,14 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) /** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -463,7 +463,7 @@ typedef struct __SPI_HandleTypeDef } while(0) /** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -476,7 +476,7 @@ typedef struct __SPI_HandleTypeDef } while(0) /** @brief Clear the SPI FRE pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -488,14 +488,14 @@ typedef struct __SPI_HandleTypeDef }while(0) /** @brief Enable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) /** @brief Disable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -511,21 +511,21 @@ typedef struct __SPI_HandleTypeDef */ /** @brief Set the SPI transmit-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) /** @brief Set the SPI receive-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) /** @brief Reset the CRC calculation of the SPI. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sram.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sram.h index ce8cf0acb7..33ca683f6a 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sram.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sram.h @@ -100,7 +100,7 @@ typedef struct */ /** @brief Reset SRAM handle state - * @param __HANDLE__: SRAM handle + * @param __HANDLE__ SRAM handle * @retval None */ #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h index d55b20f6c0..5357f6b171 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h @@ -288,7 +288,7 @@ typedef enum /** * @brief TIM Time Base Handle Structure definition */ -typedef struct +typedef struct __TIM_HandleTypeDef { TIM_TypeDef *Instance; /*!< Register base address */ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ @@ -297,7 +297,74 @@ typedef struct This array is accessed by a @ref DMA_Handle_index */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + + void (* PeriodElapsedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* TriggerCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* IC_CaptureCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* OC_DelayElapsedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* ErrorCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* BreakCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + }TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, /*!< TIM Base MspInit Callback ID */ + HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, /*!< TIM Base MspDeInit Callback ID */ + HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, /*!< TIM IC MspInit Callback ID */ + HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U, /*!< TIM IC MspDeInit Callback ID */ + HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, /*!< TIM OC MspInit Callback ID */ + HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, /*!< TIM OC MspDeInit Callback ID */ + HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, /*!< TIM PWM MspInit Callback ID */ + HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U, /*!< TIM PWM MspDeInit Callback ID */ + HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, /*!< TIM One Pulse MspInit Callback ID */ + HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, /*!< TIM One Pulse MspDeInit Callback ID */ + HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, /*!< TIM Encoder MspInit Callback ID */ + HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU, /*!< TIM Encoder MspDeInit Callback ID */ + HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, /*!< TIM Encoder MspDeInit Callback ID */ + HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, /*!< TIM Encoder MspDeInit Callback ID */ + + HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, /*!< TIM Period Elapsed Callback ID */ + HAL_TIM_TRIGGER_CB_ID = 0x0FU, /*!< TIM Trigger Callback ID */ + HAL_TIM_IC_CAPTURE_CB_ID = 0x10U, /*!< TIM Input Capture Callback ID */ + HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x11U, /*!< TIM Output Compare Delay Elapsed Callback ID */ + HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x12U, /*!< TIM PWM Pulse Finished Callback ID */ + HAL_TIM_ERROR_CB_ID = 0x13U, /*!< TIM Error Callback ID */ + HAL_TIM_COMMUTATION_CB_ID = 0x14U, /*!< TIM Commutation Callback ID */ + HAL_TIM_BREAK_CB_ID = 0x15U /*!< TIM Break Callback ID */ + +}HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ @@ -835,41 +902,35 @@ typedef struct * @{ */ /** @brief Reset TIM handle state - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) /** * @brief Enable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** * @brief Enable the TIM update source request. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS)) /** * @brief Enable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) - -/* The counter of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) -#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) - /** * @brief Disable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ @@ -885,18 +946,16 @@ typedef struct /** * @brief Disable the TIM update source request. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None - */ + */ #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) - -/* The Main Output of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ /** * @brief Disable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ @@ -909,64 +968,181 @@ typedef struct } \ } while(0) +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__: specifies the TIM Handle. + * @param __INTERRUPT__: specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__: specifies the TIM Handle. + * @param __INTERRUPT__: specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__: specifies the TIM Handle. + * @param __DMA__: specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__: specifies the TIM Handle. + * @param __DMA__: specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__: specifies the TIM Handle. + * @param __FLAG__: specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__: specifies the TIM Handle. + * @param __FLAG__: specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__: TIM handle + * @param __INTERRUPT__: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__: TIM handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__: TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder +mode. + */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) -#define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) - -#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) - -#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) - -#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) -#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) - /** - * @brief Sets the TIM Counter Register value on runtime. + * @brief Set the TIM Prescaler on runtime. * @param __HANDLE__: TIM handle. - * @param __COUNTER__: specifies the Counter register new value. + * @param __PRESC__: specifies the Prescaler new value. * @retval None */ -#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) /** - * @brief Gets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. + * @brief Set the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. * @retval None */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register + */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) /** - * @brief Sets the TIM Autoreload Register value on runtime without calling + * @brief Set the TIM Autoreload Register value on runtime without calling * another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __AUTORELOAD__: specifies the Counter register new value. - * @retval None + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval 16-bit or 32-bit value of the timer auto-reload */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ do{ \ @@ -974,17 +1150,17 @@ typedef struct (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ } while(0) /** - * @brief Gets the TIM Autoreload Register value on runtime - * @param __HANDLE__: TIM handle. + * @brief Get the TIM Autoreload Register value on runtime + * @param __HANDLE__ TIM handle. * @retval None */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) /** - * @brief Sets the TIM Clock Division value on runtime without calling + * @brief Set the TIM Clock Division value on runtime without calling * another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __CKD__: specifies the clock division value. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. * This parameter can be one of the following value: * @arg TIM_CLOCKDIVISION_DIV1 * @arg TIM_CLOCKDIVISION_DIV2 @@ -998,23 +1174,26 @@ typedef struct (__HANDLE__)->Init.ClockDivision = (__CKD__); \ } while(0) /** - * @brief Gets the TIM Clock Division value on runtime - * @param __HANDLE__: TIM handle. - * @retval None + * @brief Get the TIM Clock Division value on runtime + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** - * @brief Sets the TIM Input Capture prescaler on runtime without calling + * @brief Set the TIM Input Capture prescaler on runtime without calling * another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__: specifies the Input Capture4 prescaler new value. + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events @@ -1029,15 +1208,19 @@ typedef struct } while(0) /** - * @brief Gets the TIM Input Capture prescaler on runtime - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. + * @brief Get the TIM Input Capture prescaler on runtime + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value * @arg TIM_CHANNEL_2: get input capture 2 prescaler value * @arg TIM_CHANNEL_3: get input capture 3 prescaler value * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval None + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ @@ -1046,15 +1229,15 @@ typedef struct (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) /** - * @brief Sets the TIM Capture x input polarity on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__: Polarity for TIx source + * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge @@ -1070,6 +1253,7 @@ typedef struct /** * @} */ +/* End of exported macros ----------------------------------------------------*/ /* Include TIM HAL Extension module */ #include "stm32f7xx_hal_tim_ex.h" @@ -1131,6 +1315,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); + /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -1256,6 +1441,12 @@ void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /** * @} */ @@ -1278,7 +1469,20 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); /** * @} */ - + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + /* Private macros ------------------------------------------------------------*/ /** @defgroup TIM_Private_Macros TIM Private Macros * @{ @@ -1514,16 +1718,51 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ +/** @defgroup TIM_ICPRESCALER TIM Private macros to SET/RESET TIM Input capture value + * @{ + */ +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) /** * @} */ - + +/** @defgroup TIM_CAPTUREPOLARITY TIM Private macros to SET/RESET TIM capture polarity value + * @{ + */ +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) /** * @} */ +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + /* Private functions ---------------------------------------------------------*/ /** @defgroup TIM_Private_Functions TIM Private Functions * @{ @@ -1540,10 +1779,16 @@ void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma); void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /** * @} */ - +/* End of private functions --------------------------------------------------*/ + /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h index 947155f858..6a81aad261 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h @@ -324,8 +324,8 @@ typedef struct { /** * @brief Sets the TIM Capture Compare Register value on runtime without * calling another time ConfigChannel function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -333,7 +333,7 @@ typedef struct { * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param __COMPARE__: specifies the Capture Compare register new value. + * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ @@ -346,8 +346,8 @@ typedef struct { /** * @brief Gets the TIM Capture Compare Register value on runtime - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channel associated with the capture compare register + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value * @arg TIM_CHANNEL_2: get capture/compare 2 register value @@ -367,8 +367,8 @@ typedef struct { /** * @brief Sets the TIM Output compare preload. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -388,8 +388,8 @@ typedef struct { /** * @brief Resets the TIM Output compare preload. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h index 8ef1de77af..12c35d8203 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h @@ -669,7 +669,7 @@ typedef struct */ /** @brief Reset UART handle state - * @param __HANDLE__: UART handle. + * @param __HANDLE__ UART handle. * @retval None */ #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ @@ -678,7 +678,7 @@ typedef struct } while(0) /** @brief Flush the UART Data registers - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ @@ -687,8 +687,8 @@ typedef struct } while(0) /** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __FLAG__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg UART_CLEAR_PEF: Parity Error Clear Flag @@ -707,38 +707,38 @@ typedef struct #define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__)) /** @brief Clear the UART PE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF) /** @brief Clear the UART FE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF) /** @brief Clear the UART NE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF) /** @brief Clear the UART ORE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF) /** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF) /** @brief Checks whether the specified UART flag is set or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg UART_FLAG_REACK: Receive enable acknowledge flag * @arg UART_FLAG_TEACK: Transmit enable acknowledge flag @@ -766,8 +766,8 @@ typedef struct #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Enables the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. - * @param __INTERRUPT__: specifies the UART interrupt source to enable. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. * This parameter can be one of the following values: * @arg UART_IT_WUF: Wakeup from stop mode interrupt * @arg UART_IT_CM: Character match interrupt @@ -787,8 +787,8 @@ typedef struct /** @brief Disables the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. - * @param __INTERRUPT__: specifies the UART interrupt source to disable. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. * This parameter can be one of the following values: * @arg UART_IT_CM: Character match interrupt * @arg UART_IT_CTS: CTS change interrupt @@ -806,8 +806,8 @@ typedef struct ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Checks whether the specified UART interrupt has occurred or not. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT__: specifies the UART interrupt to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT__ specifies the UART interrupt to check. * This parameter can be one of the following values: * @arg UART_IT_CM: Character match interrupt * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) @@ -825,8 +825,8 @@ typedef struct #define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) /** @brief Checks whether the specified UART interrupt source is enabled. - * @param __HANDLE__: specifies the UART Handle. - * @param __IT__: specifies the UART interrupt source to check. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT__ specifies the UART interrupt source to check. * This parameter can be one of the following values: * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) * @arg UART_IT_LBD: LIN Break detection interrupt @@ -844,8 +844,8 @@ typedef struct (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK))) /** @brief Set a specific UART request flag. - * @param __HANDLE__: specifies the UART Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request * @arg UART_SENDBREAK_REQUEST: Send Break Request @@ -857,25 +857,25 @@ typedef struct #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) /** @brief Enables the UART one bit sample method - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief Disables the UART one bit sample method - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -889,7 +889,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * The Handle Instance can be USART1, USART2 or LPUART. * @retval None */ @@ -908,7 +908,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * The Handle Instance can be USART1, USART2 or LPUART. * @retval None */ @@ -927,7 +927,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * The Handle Instance can be USART1, USART2 or LPUART. * @retval None */ @@ -946,7 +946,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * The Handle Instance can be USART1, USART2 or LPUART. * @retval None */ @@ -965,28 +965,28 @@ typedef struct * @{ */ /** @brief BRR division operation to set BRR register with LPUART - * @param _PCLK_: LPUART clock - * @param _BAUD_: Baud rate set by the user + * @param _PCLK_ LPUART clock + * @param _BAUD_ Baud rate set by the user * @retval Division result */ #define UART_DIV_LPUART(_PCLK_, _BAUD_) ((((_PCLK_)*256)+((_BAUD_)/2))/((_BAUD_))) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode - * @param _PCLK_: UART clock - * @param _BAUD_: Baud rate set by the user + * @param _PCLK_ UART clock + * @param _BAUD_ Baud rate set by the user * @retval Division result */ #define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((((_PCLK_)*2)+((_BAUD_)/2))/((_BAUD_))) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode - * @param _PCLK_: UART clock - * @param _BAUD_: Baud rate set by the user + * @param _PCLK_ UART clock + * @param _BAUD_ Baud rate set by the user * @retval Division result */ #define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((((_PCLK_))+((_BAUD_)/2))/((_BAUD_))) /** @brief Check UART Baud rate - * @param BAUDRATE: Baudrate specified by the user + * @param BAUDRATE Baudrate specified by the user * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval Test result (TRUE or FALSE). @@ -994,13 +994,13 @@ typedef struct #define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001) /** @brief Check UART assertion time - * @param TIME: 5-bit value assertion time + * @param TIME 5-bit value assertion time * @retval Test result (TRUE or FALSE). */ #define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F) /** @brief Check UART deassertion time - * @param TIME: 5-bit value deassertion time + * @param TIME 5-bit value deassertion time * @retval Test result (TRUE or FALSE). */ #define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h index 9d27617b46..ae5eb495f2 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h @@ -96,8 +96,8 @@ */ /** @brief Reports the UART clock source. - * @param __HANDLE__: specifies the UART Handle - * @param __CLOCKSOURCE__: output variable + * @param __HANDLE__ specifies the UART Handle + * @param __CLOCKSOURCE__ output variable * @retval UART clocking source, written in __CLOCKSOURCE__. */ #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ @@ -270,7 +270,7 @@ * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the UART Handle + * @param __HANDLE__ specifies the UART Handle * @retval mask to apply to UART RDR register value. */ #define UART_MASK_COMPUTATION(__HANDLE__) \ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h index a699a734e5..7e089123c3 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h @@ -338,14 +338,14 @@ typedef struct */ /** @brief Reset USART handle state - * @param __HANDLE__: USART handle. + * @param __HANDLE__ USART handle. * @retval None */ #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) /** @brief Checks whether the specified USART flag is set or not. - * @param __HANDLE__: specifies the USART Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the USART Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg USART_FLAG_REACK: Receive enable acknowledge flag * @arg USART_FLAG_TEACK: Transmit enable acknowledge flag @@ -365,8 +365,8 @@ typedef struct /** @brief Enables the specified USART interrupt. - * @param __HANDLE__: specifies the USART Handle - * @param __INTERRUPT__: specifies the USART interrupt source to enable. + * @param __HANDLE__ specifies the USART Handle + * @param __INTERRUPT__ specifies the USART interrupt source to enable. * This parameter can be one of the following values: * @arg USART_IT_TXE: Transmit Data Register empty interrupt * @arg USART_IT_TC: Transmission complete interrupt @@ -381,8 +381,8 @@ typedef struct ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disables the specified USART interrupt. - * @param __HANDLE__: specifies the USART Handle. - * @param __INTERRUPT__: specifies the USART interrupt source to disable. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to disable. * This parameter can be one of the following values: * @arg USART_IT_TXE: Transmit Data Register empty interrupt * @arg USART_IT_TC: Transmission complete interrupt @@ -398,8 +398,8 @@ typedef struct /** @brief Checks whether the specified USART interrupt has occurred or not. - * @param __HANDLE__: specifies the USART Handle - * @param __IT__: specifies the USART interrupt source to check. + * @param __HANDLE__ specifies the USART Handle + * @param __IT__ specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg USART_IT_TXE: Transmit Data Register empty interrupt * @arg USART_IT_TC: Transmission complete interrupt @@ -414,8 +414,8 @@ typedef struct #define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) /** @brief Checks whether the specified USART interrupt source is enabled. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT__: specifies the USART interrupt source to check. + * @param __HANDLE__ specifies the USART Handle. + * @param __IT__ specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg USART_IT_TXE: Transmit Data Register empty interrupt * @arg USART_IT_TC: Transmission complete interrupt @@ -433,8 +433,8 @@ typedef struct /** @brief Clears the specified USART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg USART_CLEAR_PEF: Parity Error Clear Flag @@ -449,8 +449,8 @@ typedef struct #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) /** @brief Set a specific USART request flag. - * @param __HANDLE__: specifies the USART Handle. - * @param __REQ__: specifies the request flag to set + * @param __HANDLE__ specifies the USART Handle. + * @param __REQ__ specifies the request flag to set * This parameter can be one of the following values: * @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request * @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request @@ -460,13 +460,13 @@ typedef struct #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) /** @brief Enable USART - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable USART - * @param __HANDLE__: specifies the USART Handle. + * @param __HANDLE__ specifies the USART Handle. * @retval None */ #define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) @@ -556,8 +556,8 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); * @{ */ /** @brief Reports the USART clock source. - * @param __HANDLE__: specifies the USART Handle - * @param __CLOCKSOURCE__ : output variable + * @param __HANDLE__ specifies the USART Handle + * @param __CLOCKSOURCE__ output variable * @retval the USART clocking source, written in __CLOCKSOURCE__. */ #define USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)\ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h index 506f7006af..843efaf1e3 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h @@ -85,7 +85,7 @@ * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the USART Handle + * @param __HANDLE__ specifies the USART Handle * @retval none */ #define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_wwdg.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_wwdg.h index 38670acd72..4b1ef86129 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_wwdg.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_wwdg.h @@ -174,7 +174,7 @@ typedef struct /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h index 0d53c572f3..55a73f6e7f 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h @@ -305,7 +305,7 @@ extern "C" { * a register from a register basis from which an offset * is applied. * @param __REG__ Register basis from which the offset is applied. - * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). * @retval Pointer to register address */ #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ @@ -1154,7 +1154,7 @@ typedef struct * @note Example: * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) * will return a data equivalent to "LL_ADC_CHANNEL_4". - * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 @@ -1624,7 +1624,7 @@ typedef struct * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) * (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: @@ -1657,7 +1657,7 @@ typedef struct * internal voltage reference VrefInt. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. - * @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits) + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) * of internal voltage reference VrefInt (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B @@ -1707,7 +1707,7 @@ typedef struct * temperature sensor. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal * temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature @@ -1762,13 +1762,13 @@ typedef struct * @note ADC measurement data must correspond to a resolution of 12bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius). * On STM32F7, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV). * On STM32F4, refer to device datasheet parameter "V25". - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) - * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B @@ -3558,7 +3558,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dac.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dac.h index 1d4b08d0db..8c03c6f3ba 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dac.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dac.h @@ -125,7 +125,7 @@ extern "C" { * a register from a register basis from which an offset * is applied. * @param __REG__ Register basis from which the offset is applied. - * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). * @retval Pointer to register address */ #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ @@ -454,7 +454,7 @@ typedef struct * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel * (unit: mVolt). * @param __DAC_RESOLUTION__ This parameter can be one of the following values: diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h index 5dc4b9cbc0..e33f282aae 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h @@ -1085,16 +1085,16 @@ typedef struct /** * @brief Enable the NORSRAM device access. - * @param __INSTANCE__: FMC_NORSRAM Instance - * @param __BANK__: FMC_NORSRAM Bank + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank * @retval None */ #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN) /** * @brief Disable the NORSRAM device access. - * @param __INSTANCE__: FMC_NORSRAM Instance - * @param __BANK__: FMC_NORSRAM Bank + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank * @retval None */ #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN) @@ -1110,14 +1110,14 @@ typedef struct /** * @brief Enable the NAND device access. - * @param __INSTANCE__: FMC_NAND Instance + * @param __INSTANCE__ FMC_NAND Instance * @retval None */ #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) /** * @brief Disable the NAND device access. - * @param __INSTANCE__: FMC_NAND Instance + * @param __INSTANCE__ FMC_NAND Instance * @retval None */ #define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN) @@ -1133,8 +1133,8 @@ typedef struct /** * @brief Enable the NAND device interrupt. - * @param __INSTANCE__: FMC_NAND instance - * @param __INTERRUPT__: FMC_NAND interrupt + * @param __INSTANCE__ FMC_NAND instance + * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. @@ -1145,8 +1145,8 @@ typedef struct /** * @brief Disable the NAND device interrupt. - * @param __INSTANCE__: FMC_NAND Instance - * @param __INTERRUPT__: FMC_NAND interrupt + * @param __INSTANCE__ FMC_NAND Instance + * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. @@ -1157,9 +1157,9 @@ typedef struct /** * @brief Get flag status of the NAND device. - * @param __INSTANCE__: FMC_NAND Instance - * @param __BANK__: FMC_NAND Bank - * @param __FLAG__: FMC_NAND flag + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @param __FLAG__ FMC_NAND flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. @@ -1171,8 +1171,8 @@ typedef struct /** * @brief Clear flag status of the NAND device. - * @param __INSTANCE__: FMC_NAND Instance - * @param __FLAG__: FMC_NAND flag + * @param __INSTANCE__ FMC_NAND Instance + * @param __FLAG__ FMC_NAND flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. @@ -1184,8 +1184,8 @@ typedef struct /** * @brief Enable the SDRAM device interrupt. - * @param __INSTANCE__: FMC_SDRAM instance - * @param __INTERRUPT__: FMC_SDRAM interrupt + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error * @retval None @@ -1194,8 +1194,8 @@ typedef struct /** * @brief Disable the SDRAM device interrupt. - * @param __INSTANCE__: FMC_SDRAM instance - * @param __INTERRUPT__: FMC_SDRAM interrupt + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error * @retval None @@ -1204,8 +1204,8 @@ typedef struct /** * @brief Get flag status of the SDRAM device. - * @param __INSTANCE__: FMC_SDRAM instance - * @param __FLAG__: FMC_SDRAM flag + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag * This parameter can be any combination of the following values: * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. @@ -1216,8 +1216,8 @@ typedef struct /** * @brief Clear flag status of the SDRAM device. - * @param __INSTANCE__: FMC_SDRAM instance - * @param __FLAG__: FMC_SDRAM flag + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag * This parameter can be any combination of the following values: * @arg FMC_SDRAM_FLAG_REFRESH_ERROR * @retval None diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_i2c.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_i2c.h index 7996f9274b..c4a0c26c84 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_i2c.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_i2c.h @@ -281,14 +281,14 @@ typedef struct /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation * @{ */ -#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ -#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */ -#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ -#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */ -#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 10Bit address.*/ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ /** * @} */ @@ -2067,7 +2067,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { - MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request); } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h index 06c8ccbc0e..9034f0cef9 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h @@ -3448,6 +3448,31 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, } #endif /* DSI */ +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + /** * @brief Get Main PLL multiplication factor for VCO * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN @@ -3516,18 +3541,6 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) } #endif /* RCC_PLLCFGR_PLLR */ -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); -} - /** * @brief Get Division factor for the main PLL and other PLL * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h index 4a8bdc2e09..aaeb484475 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h @@ -672,35 +672,35 @@ typedef struct /** * @brief Enable the SDMMC device. - * @param __INSTANCE__: SDMMC Instance + * @param __INSTANCE__ SDMMC Instance * @retval None */ #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) /** * @brief Disable the SDMMC device. - * @param __INSTANCE__: SDMMC Instance + * @param __INSTANCE__ SDMMC Instance * @retval None */ #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) /** * @brief Enable the SDMMC DMA transfer. - * @param __INSTANCE__: SDMMC Instance + * @param __INSTANCE__ SDMMC Instance * @retval None */ #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) /** * @brief Disable the SDMMC DMA transfer. - * @param __INSTANCE__: SDMMC Instance + * @param __INSTANCE__ SDMMC Instance * @retval None */ #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) /** * @brief Enable the SDMMC device interrupt. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -730,8 +730,8 @@ typedef struct /** * @brief Disable the SDMMC device interrupt. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -761,8 +761,8 @@ typedef struct /** * @brief Checks whether the specified SDMMC flag is set or not. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __FLAG__: specifies the flag to check. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -793,8 +793,8 @@ typedef struct /** * @brief Clears the SDMMC pending flags. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __FLAG__: specifies the flag to clear. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __FLAG__ specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -813,8 +813,8 @@ typedef struct /** * @brief Checks whether the specified SDMMC interrupt has occurred or not. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -844,8 +844,8 @@ typedef struct /** * @brief Clears the SDMMC's interrupt pending bits. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -863,56 +863,56 @@ typedef struct /** * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) /** * @brief Disable Start the SD I/O Read Wait operations. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) /** * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) /** * @brief Disable Stop the SD I/O Read Wait operations. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) /** * @brief Enable the SD I/O Mode Operation. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) /** * @brief Disable the SD I/O Mode Operation. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) /** * @brief Enable the SD I/O Suspend command sending. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) /** * @brief Disable the SD I/O Suspend command sending. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h index af3612deb2..154dbeba9a 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h @@ -236,7 +236,7 @@ __STATIC_INLINE uint32_t LL_GetUID_Word2(void) */ __STATIC_INLINE uint32_t LL_GetFlashSize(void) { - return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); } /** @@ -251,7 +251,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) */ __STATIC_INLINE uint32_t LL_GetPackageType(void) { - return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U); + return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U); } /** diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html index 65370101ea..d5c82ba803 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html @@ -1,4 +1,4 @@ - + @@ -680,7 +680,45 @@

      -

      Update History

      V1.2.3 / 25-Augustl-2017

      +

      Update History

      V1.2.4 / 22-December-2017

      +

      Main +Changes

      • General updates to fix known defects and enhancements implementation
      • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
        • Rework of HAL CAN driver (compatibility break) 
          • A +new HAL CAN driver has been redesigned with new APIs, to bypass +limitations on CAN Tx/Rx FIFO management present with previous HAL CAN +driver version.
          • The +new HAL CAN driver is the recommended version. It is located as usual +in Drivers/STM32F7xx_HAL_Driver/Src and +Drivers/STM32f7xx_HAL_Driver/Inc folders. It can be enabled through +switch HAL_CAN_MODULE_ENABLED in stm32f7xx_hal_conf.h
          • The +legacy HAL CAN driver is also present in the release in +Drivers/STM32F7xx_HAL_Driver/Src/Legacy and +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy folders for software +compatibility reasons. Its usage is not recommended as deprecated. It +can however be enabled through switch HAL_CAN_LEGACY_MODULE_ENABLED in +stm32f7xx_hal_conf.h
      • HAL update
        • Update HAL driver to allow user to change systick period to 1ms , 10 ms or 100 ms :
          • Add the following API's :  
            • HAL_GetTickPrio() : Returns a tick priority.
            • HAL_SetTickFreq() : Sets new tick frequency.
            • HAL_GetTickFreq() : Returns tick frequency.
          • Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies : 10 Hz , 100 Hz and 1KHz (default).
      • HAL CAN update
        • Fields of CAN_InitTypeDef structure are reworked:
          • SJW +to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to +TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to +AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to +TransmitFifoPriority
        • HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() API's
        • HAL_CAN_Transmit() +is replaced by HAL_CAN_AddTxMessage() to place Tx Request, then +HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion.
        • HAL_CAN_Transmit_IT() +is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then +HAL_CAN_AddTxMessage() for place Tx request.
        • HAL_CAN_Receive() +is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until +reception, then HAL_CAN_GetRxMessage()
          to get Rx message.
        • HAL_CAN_Receive_IT() +is replaced by HAL_CAN_ActivateNotification() to enable receive IT, then +HAL_CAN_GetRxMessage()
           in the receivecallback to get Rx message
        • HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()
        • HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback().
        • HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback().
        • More complete "How to use the new driver" is detailed in the driver header section itself.
      • HAL RCC update
          • Add new LL macro
            • LL_RCC_PLL_SetMainSource() + allowing to configure PLL clock source
          • Add new HAL macros
            • __HAL_RCC_GET_RTC_SOURCE() + allowing to get the RTC clock source
            • __HAL_RCC_GET_RTC_HSE_PRESCALER() + allowing to get the HSE clock divider for RTC peripheral
          • Ensure reset of CIR and CSR + registers when issuing HAL_RCC_DeInit()/LL_RCC_DeInit functions
          • Update HAL_RCC_GetSysClockFreq() + to avoid risk of rounding error which may leads to a wrong returned + value. 
          • Update HAL_RCC_DeInit() +  and LL_RCC_DeInit() APIs to
            • Be able to return HAL/LL + status
            • Add checks for HSI, PLL and + PLLI2S  ready before modifying RCC CFGR registers
            • Clear all interrupt flags
            • Initialize systick interrupt + period
      • HAL DMA update
        • Add clean of callbacks in HAL_DMA_DeInit() API
        • Fix wrong DMA_FLAG_FEIFO_4 and DMA_FLAGDMAEIFO_4 defines values 
      • HAL I2C update
        • Update Interface APIs headers to remove confusing message about device address
        • Update I2C_WaitOnRXNEFlagUntilTimeout() to resolve a race condition between STOPF and RXNE Flags
        • Update I2C_TransferConfig() to fix wrong bit management
      • LL USART update
        • Add assert macros to check USART BaudRate register
      • HAL ETH update
        • Do{..} While(0) insured in multi statement macros :
          • __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() 
          • __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()
      • HAL FLASH update
        • HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked
      • HAL GPIO update
        • Add missing define of GPIO_PIN_2 in GPIOK_PIN_AVAILABLE list
      • HAL PCD update
        • Do{..} While(0)  insured in multi statement macros
      • LL UTILS update
        • stm32f7xx_ll_utils.h : Update LL_GetPackageType command to return uint32_t instead of uint16_t
      • HAL TIM update
        • stm32f7xx_hal_tim_ex.c : Update HAL_TIMEx_ConfigBreakDeadTime API to avoid to block timer behavior when
          remains in the state HAL_TIM_STATE_BUSY.
        •  stm32f7xx_hal_tim.h : 
          • Fix __HAL_TIM_SET_PRESCALER() macro
          • Fix typos in some exported macros description 
      • LL FMC update
        • HAL_SDRAM_SendCommand() API: Remove the timeout check
      • HAL NAND update
        • Fix wrong check for NAND status
      +

      V1.2.3 / 25-August-2017

      Main Changes

      • General updates to fix known defects and enhancements implementation
      • Remove Date and Version from header files
      • Update HAL drivers to refer to the new CMSIS bit position defines instead of usage the POSITION_VAL() macro
      • HAL CAN update
        • Add missing unlock in HAL_CAN_Receive_IT() process
      • HAL DCMI update
        • HAL DCMI driver clean-up: remove non referenced callback APIs: HAL_DCMI_VsyncCallback() and HAL_DCMI_HsyncCallback()
      • HAL DFSDM update
        • Fix cast issue on APIs that return signed integer value (uint32_t) 
      • HAL DMA update
        • HAL DMA driver clean-up: remove non referenced callback APIs: HAL_DMA_CleanCallbacks()
      • HAL FLASH update
        • FLASH_Program_DoubleWord() API: Replace 64-bit accesses with 2 double words operations
      • HAL Generic update
        • Update assert_param() macro definition to be in line with stm32_ll_utils.c driver
      • HAL GPIO update
        • GPIOK_PIN_AVAILABLE() assert macro update to allow possibility to configure GPIO_PIN_2
      • HAL LTDC update
        • Rename HAL_LTDC_LineEvenCallback() API to HAL_LTDC_LineEventCallback()
      • HAL PCD update
        • Update HAL_PCD_IRQHandler() API to fix transfer issues when USB HS is used with DMA enabled
      • HAL RCC update
        • Update HAL_RCC_GetOscConfig() API to:
          • set PLLR in the RCC_OscInitStruct
          • check on null pointer
        • Update HAL_RCC_ClockConfig() API to:
          • check on null pointer
          • optimize code size by updating the handling method of the SWS bits
          • update diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/Legacy/stm32f7xx_hal_can.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/Legacy/stm32f7xx_hal_can.c new file mode 100644 index 0000000000..75c8f28bf1 --- /dev/null +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/Legacy/stm32f7xx_hal_can.c @@ -0,0 +1,1688 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_can.c + * @author MCD Application Team + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + @verbatim + ============================================================================== + ##### User NOTE ##### + ============================================================================== + [..] + (#) This HAL CAN driver is deprecated, it contains some CAN Tx/Rx FIFO management limitations. + Another HAL CAN driver version has been designed with new API's, to fix these limitations. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the CAN controller interface clock using + __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2 + and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3 + -@- In case you are using CAN2 only, you have to enable the CAN1 clock. + + (#) CAN pins configuration + (++) Enable the clock for the CAN GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE() + (++) Connect and configure the involved CAN pins to AF9 using the + following function HAL_GPIO_Init() + + (#) Initialize and configure the CAN using HAL_CAN_Init() function. + + (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. + + (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. + + (#) Receive a CAN frame using HAL_CAN_Receive() function. + + (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the CAN peripheral transmission and wait the end of this operation + using HAL_CAN_Transmit(), at this stage user can specify the value of timeout + according to his end application + (+) Start the CAN peripheral reception and wait the end of this operation + using HAL_CAN_Receive(), at this stage user can specify the value of timeout + according to his end application + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() + (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() + (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine + (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_TxCpltCallback + (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_CAN_ErrorCallback + + *** CAN HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in CAN HAL driver. + + (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts + (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts + (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled + (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags + (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status + + [..] + (@) You can refer to the CAN Legacy HAL driver header file for more useful macros + + @endverbatim + + ****************************************************************************** + * @attention + * + *

            © COPYRIGHT(c) 2017 STMicroelectronics

            + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED +#ifdef HAL_CAN_MODULE_ENABLED +/* Select HAL CAN module in stm32f7xx_hal_conf.h file: + (#) HAL_CAN_MODULE_ENABLED for new HAL CAN driver fixing FIFO limitations + (#) HAL_CAN_LEGACY_MODULE_ENABLED for legacy HAL CAN driver */ +#error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32f7xx_hal_conf.h file' +#endif /* HAL_CAN_MODULE_ENABLED */ + +#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver' + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup CAN_Private_Constants + * @{ + */ +#define CAN_TIMEOUT_VALUE 10U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup CAN_Private_Functions + * @{ + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the CAN. + (+) De-initialize the CAN. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +{ + uint32_t InitStatus = CAN_INITSTATUS_FAILED; + uint32_t tickstart = 0U; + + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SJW)); + assert_param(IS_CAN_BS1(hcan->Init.BS1)); + assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + + + if(hcan->State == HAL_CAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcan->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_CAN_MspInit(hcan); + } + + /* Initialize the CAN state*/ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Exit from sleep mode */ + hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + hcan->Instance->MCR |= CAN_MCR_INRQ ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Check acknowledge */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + /* Set the time triggered communication mode */ + if (hcan->Init.TTCM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TTCM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (hcan->Init.ABOM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_ABOM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AWUM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_AWUM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (hcan->Init.NART == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_NART; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.RFLM == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_RFLM; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TXFP == ENABLE) + { + hcan->Instance->MCR |= CAN_MCR_TXFP; + } + else + { + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ + ((uint32_t)hcan->Init.SJW) | \ + ((uint32_t)hcan->Init.BS1) | \ + ((uint32_t)hcan->Init.BS2) | \ + ((uint32_t)hcan->Init.Prescaler - 1U); + + /* Request leave initialisation */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Check acknowledged */ + if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + InitStatus = CAN_INITSTATUS_SUCCESS; + } + } + + if(InitStatus == CAN_INITSTATUS_SUCCESS) + { + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) +{ + uint32_t filternbrbitpos = 0U; + CAN_TypeDef *can_ip; + +#if !defined(CAN3) + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); +#endif /* CAN3 */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); + + filternbrbitpos = 1U << sFilterConfig->FilterNumber; +#if defined (CAN3) + /* Check the CAN instance */ + if(hcan->Instance == CAN3) + { + can_ip = CAN3; + } + else + { + can_ip = CAN1; + } +#else + can_ip = CAN1; +#endif + + /* Initialisation mode for the filter */ + can_ip->FMR |= (uint32_t)CAN_FMR_FINIT; + +#if defined (CAN2) + /* Select the start slave bank */ + can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); + can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U); +#endif + + /* Filter Deactivation */ + can_ip->FA1R &= ~(uint32_t)filternbrbitpos; + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + can_ip->FS1R &= ~(uint32_t)filternbrbitpos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + can_ip->FS1R |= filternbrbitpos; + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /*Id/Mask mode for the filter*/ + can_ip->FM1R &= ~(uint32_t)filternbrbitpos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + can_ip->FM1R |= (uint32_t)filternbrbitpos; + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + can_ip->FFA1R &= ~(uint32_t)filternbrbitpos; + } + + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + { + /* FIFO 1 assignation for the filter */ + can_ip->FFA1R |= (uint32_t)filternbrbitpos; + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) + { + can_ip->FA1R |= filternbrbitpos; + } + + /* Leave the initialisation mode for the filter */ + can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the CANx peripheral registers to their default reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +{ + /* Check CAN handle */ + if(hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* DeInit the low level hardware */ + HAL_CAN_MspDeInit(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Transmit a CAN frame message. + (+) Receive a CAN frame message. + (+) Enter CAN peripheral in sleep mode. + (+) Wake up the CAN peripheral from sleep mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + { + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + } + + /* Select one empty transmit mailbox */ + if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = CAN_TXMAILBOX_0; + } + else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = CAN_TXMAILBOX_1; + } + else + { + transmitmailbox = CAN_TXMAILBOX_2; + } + + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if (hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[0U])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[4U])); + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check End of transmission flag */ + while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); + assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); + assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + { + /* Process Locked */ + __HAL_LOCK(hcan); + + /* Select one empty transmit mailbox */ + if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmitmailbox = CAN_TXMAILBOX_0; + } + else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmitmailbox = CAN_TXMAILBOX_1; + } + else + { + transmitmailbox = CAN_TXMAILBOX_2; + } + + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if(hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ + hcan->pTxMsg->RTR); + } + else + { + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ + hcan->pTxMsg->IDE | \ + hcan->pTxMsg->RTR); + } + + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[0U])); + hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | + ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | + ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | + ((uint32_t)hcan->pTxMsg->Data[4U])); + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcan); + + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + + /* Enable Error warning, Error passive, Bus-off, + Last error and Error Interrupts */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME); + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber FIFO Number value + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + CanRxMsgTypeDef* pRxMsg = NULL; + + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Check if CAN state is not busy for RX FIFO0 */ + if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Check if CAN state is not busy for RX FIFO1 */ + if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + } + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check pending message */ + while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + } + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) + { + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + + /* Get the Id */ + pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) + { + pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + } + else + { + pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + } + + pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; + /* Get the data field */ + pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); + pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); + pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); + pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); + pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); + pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); + + /* Release the FIFO */ + if(FIFONumber == CAN_FIFO0) + { + /* Release FIFO0 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + } + else /* FIFONumber == CAN_FIFO1 */ + { + /* Release FIFO1 */ + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + } + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan Pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber Specify the FIFO number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_FIFO(FIFONumber)); + + /* Check if CAN state is not busy for RX FIFO0 */ + if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Check if CAN state is not busy for RX FIFO1 */ + if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + if(FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + } + } + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + /* - Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + if(FIFONumber == CAN_FIFO0) + { + /* Enable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + else + { + /* Enable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enters the Sleep (low power) mode. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0U; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Request Sleep mode */ + hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + { + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral + * is in the normal mode. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +{ + uint32_t tickstart = 0U; + + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY; + + /* Wake up request */ + hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Sleep mode status */ + while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + hcan->State= HAL_CAN_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hcan); + return HAL_TIMEOUT; + } + } + if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + { + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_ERROR; + } + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +{ + uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U; + uint32_t errorcode = HAL_CAN_ERROR_NONE; + + /* Check Overrun flag for FIFO0 */ + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0); + if(tmp1 && tmp2) + { + /* Set CAN error code to FOV0 error */ + errorcode |= HAL_CAN_ERROR_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + /* Check Overrun flag for FIFO1 */ + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1); + + if(tmp1 && tmp2) + { + /* Set CAN error code to FOV1 error */ + errorcode |= HAL_CAN_ERROR_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + + /* Check End of transmission flag */ + if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) + { + tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0); + tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1); + tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2); + if(tmp1 || tmp2 || tmp3) + { + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0); + tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1); + tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2); + /* Check Transmit success */ + if(tmp1 || tmp2 || tmp3) + { + /* Call transmit function */ + CAN_Transmit_IT(hcan); + } + else /* Transmit failure */ + { + /* Set CAN error code to TXFAIL error */ + errorcode |= HAL_CAN_ERROR_TXFAIL; + } + + /* Clear transmission status flags (RQCPx and TXOKx) */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \ + CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2); + } + } + + tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0); + /* Check End of reception flag for FIFO0 */ + if((tmp1 != 0U) && tmp2) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO0); + } + + tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1); + /* Check End of reception flag for FIFO1 */ + if((tmp1 != 0U) && tmp2) + { + /* Call receive function */ + CAN_Receive_IT(hcan, CAN_FIFO1); + } + + /* Set error code in handle */ + hcan->ErrorCode |= errorcode; + + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); + /* Check Error Warning Flag */ + if(tmp1 && tmp2 && tmp3) + { + /* Set CAN error code to EWG error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EWG; + } + + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); + /* Check Error Passive Flag */ + if(tmp1 && tmp2 && tmp3) + { + /* Set CAN error code to EPV error */ + hcan->ErrorCode |= HAL_CAN_ERROR_EPV; + } + + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); + /* Check Bus-Off Flag */ + if(tmp1 && tmp2 && tmp3) + { + /* Set CAN error code to BOF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BOF; + } + + tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); + /* Check Last error code Flag */ + if((!tmp1) && tmp2 && tmp3) + { + tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC; + switch(tmp1) + { + case(CAN_ESR_LEC_0): + /* Set CAN error code to STF error */ + hcan->ErrorCode |= HAL_CAN_ERROR_STF; + break; + case(CAN_ESR_LEC_1): + /* Set CAN error code to FOR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_FOR; + break; + case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to ACK error */ + hcan->ErrorCode |= HAL_CAN_ERROR_ACK; + break; + case(CAN_ESR_LEC_2): + /* Set CAN error code to BR error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BR; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to BD error */ + hcan->ErrorCode |= HAL_CAN_ERROR_BD; + break; + case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + hcan->ErrorCode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + hcan->Instance->ESR &= ~(CAN_ESR_LEC); + } + + /* Call the Error call Back in case of Errors */ + if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) + { + /* Clear ERRI Flag */ + hcan->Instance->MSR = CAN_MSR_ERRI; + /* Set the CAN state ready to be able to start again the process */ + hcan->State = HAL_CAN_STATE_READY; + + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + /* - Disable FIFO 0 message pending Interrupt */ + /* - Disable FIFO 0 Overrun Interrupt */ + /* - Disable FIFO 1 message pending Interrupt */ + /* - Disable FIFO 1 Overrun Interrupt */ + /* - Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_FMP0| + CAN_IT_FOV0| + CAN_IT_FMP1| + CAN_IT_FOV1| + CAN_IT_TME); + + /* Call Error callback function */ + HAL_CAN_ErrorCallback(hcan); + } +} + +/** + * @brief Transmission complete callback in non blocking mode + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Transmission complete callback in non blocking mode + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Check the CAN state. + (+) Check CAN Errors detected during interrupt process + +@endverbatim + * @{ + */ + +/** + * @brief return the CAN state + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +{ + /* Return CAN state */ + return hcan->State; +} + +/** + * @brief Return the CAN error code + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +{ + return hcan->ErrorCode; +} + +/** + * @} + */ +/** + * @brief Initiates and transmits a CAN frame message. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +{ + /* Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); + + if(hcan->State == HAL_CAN_STATE_BUSY_TX) + { + /* Disable Error warning, Error passive, Bus-off, Last error code + and Error Interrupts */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR ); + } + + /* Change CAN state */ + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + + /* Transmission complete callback */ + HAL_CAN_TxCpltCallback(hcan); + + return HAL_OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hcan Pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param FIFONumber Specify the FIFO number + * @retval HAL status + * @retval None + */ +static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +{ + uint32_t tmp1 = 0U; + CanRxMsgTypeDef* pRxMsg = NULL; + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) + { + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + + /* Get the Id */ + pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) + { + pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + } + else + { + pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + } + + pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; + /* Get the FMI */ + pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); + /* Get the data field */ + pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); + pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); + pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); + pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); + pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); + pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + + /* Disable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + + /* Disable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + } + + tmp1 = hcan->State; + if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1)) + { + /* Disable Error warning, Error passive, Bus-off, Last error code + and Error Interrupts */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR); + } + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } + } + + /* Receive complete callback */ + HAL_CAN_RxCpltCallback(hcan); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c index 9231fa61d2..a7ef6e5d60 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c @@ -66,11 +66,11 @@ * @{ */ /** - * @brief STM32F7xx HAL Driver version number V1.2.3 + * @brief STM32F7xx HAL Driver version number V1.2.4 */ #define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F7xx_HAL_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32F7xx_HAL_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */ #define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ @@ -88,6 +88,8 @@ * @{ */ __IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ @@ -104,16 +106,16 @@ __IO uint32_t uwTick; * @verbatim =============================================================================== - ##### Initialization and de-initialization functions ##### + ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initializes the Flash interface the NVIC allocation and initial clock configuration. It initializes the systick also when timeout is needed and the backup domain when enabled. - (+) de-Initializes common part of the HAL - (+) Configure The time base source to have 1ms time base with a dedicated + (+) De-Initializes common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated Tick interrupt priority. - (++) Systick timer is used by default as source of time base, but user + (++) SysTick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose timer for example or other time source), keeping in mind that Time base duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and @@ -151,11 +153,16 @@ __IO uint32_t uwTick; */ HAL_StatusTypeDef HAL_Init(void) { - /* Configure Flash prefetch and Instruction cache through ART accelerator */ + /* Configure Instruction cache through ART accelerator */ #if (ART_ACCLERATOR_ENABLE != 0) __HAL_FLASH_ART_ENABLE(); #endif /* ART_ACCLERATOR_ENABLE */ + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); @@ -200,12 +207,12 @@ HAL_StatusTypeDef HAL_DeInit(void) } /** - * @brief Initializes the MSP. + * @brief Initialize the MSP. * @retval None */ __weak void HAL_MspInit(void) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspInit could be implemented in the user file */ } @@ -216,7 +223,7 @@ __weak void HAL_MspInit(void) */ __weak void HAL_MspDeInit(void) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspDeInit could be implemented in the user file */ } @@ -230,20 +237,31 @@ __weak void HAL_MspDeInit(void) * @note In the default implementation, SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The the SysTick interrupt must have higher priority (numerically lower) + * The SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other * implementation in user file. - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(SystemCoreClock/1000); + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } - /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } /* Return function status */ return HAL_OK; @@ -280,14 +298,14 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. + * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - uwTick++; + uwTick += uwTickFreq; } /** @@ -302,21 +320,66 @@ __weak uint32_t HAL_GetTick(void) } /** - * @brief This function provides accurate delay (in milliseconds) based + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based * on variable incremented. * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick * is incremented. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. - * @param Delay: specifies the delay time length, in milliseconds. + * @param Delay specifies the delay time length, in milliseconds. * @retval None */ -__weak void HAL_Delay(__IO uint32_t Delay) +__weak void HAL_Delay(uint32_t Delay) { - uint32_t tickstart = 0; - tickstart = HAL_GetTick(); - while((HAL_GetTick() - tickstart) < Delay) + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) { } } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c index 244d688329..857580d139 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c @@ -250,7 +250,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); * External trigger source and edge, DMA continuous request after the * last transfer and End of conversion selection). * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -327,7 +327,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /** * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -374,7 +374,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /** * @brief Initializes the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -389,7 +389,7 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /** * @brief DeInitializes the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -428,7 +428,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /** * @brief Enables ADC and starts conversion of the regular channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -528,7 +528,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) * * @note Caution: This function will stop also injected channels. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * * @retval HAL status. @@ -571,9 +571,9 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) * In this case, DMA resets the flag EOC and polling cannot be * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) @@ -652,13 +652,13 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /** * @brief Poll for conversion event - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param EventType: the ADC event type. + * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. * @arg ADC_OVR_EVENT: ADC Overrun event. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) @@ -719,7 +719,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /** * @brief Enables the interrupt and starts ADC conversion of regular channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status. */ @@ -822,7 +822,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) * * @note Caution: This function will stop also injected channels. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status. */ @@ -859,7 +859,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) /** * @brief Handles ADC interrupt request - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1002,10 +1002,10 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /** * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -1123,7 +1123,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /** * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -1169,7 +1169,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) /** * @brief Gets the converted value from data register of regular channel. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval Converted value */ @@ -1181,7 +1181,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) /** * @brief Regular conversion complete callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1196,7 +1196,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Regular conversion half DMA transfer callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1211,7 +1211,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Analog watchdog callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1232,7 +1232,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" * (this function is also clearing overrun flag) - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1269,9 +1269,9 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) /** * @brief Configures for the selected ADC regular channel its corresponding * rank in the sequencer and its sample time. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param sConfig: ADC configuration structure. + * @param sConfig ADC configuration structure. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) @@ -1382,9 +1382,9 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf * Considering that registers write delay may happen due to * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure + * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure * that contains the configuration information of ADC analog watchdog. * @retval HAL status */ @@ -1466,7 +1466,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /** * @brief return the ADC state - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL state */ @@ -1478,7 +1478,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) /** * @brief Return the ADC error code - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval ADC Error Code */ @@ -1504,7 +1504,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) /** * @brief Initializes the ADCx peripheral according to the specified parameters * in the ADC_InitStruct without initializing the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1585,7 +1585,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1638,7 +1638,7 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1651,7 +1651,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c index 2530a4425e..14de03955c 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c @@ -168,7 +168,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); /** * @brief Enables the selected ADC software start conversion of the injected channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -256,7 +256,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /** * @brief Enables the interrupt and starts ADC conversion of injected channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * * @retval HAL status. @@ -355,7 +355,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note In case of auto-injection mode, HAL_ADC_Stop must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) @@ -407,9 +407,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) /** * @brief Poll for injected conversion complete - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) @@ -476,7 +476,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) @@ -531,9 +531,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) /** * @brief Gets the converted value from data register of injected channel. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param InjectedRank: the ADC injected rank. + * @param InjectedRank the ADC injected rank. * This parameter can be one of the following values: * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected @@ -586,10 +586,10 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa * * @note Caution: This function must be used only with the ADC master. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored. - * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored. + * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -701,7 +701,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /** * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -748,7 +748,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) /** * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results * data in the selected multi mode. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval The converted data value. */ @@ -760,7 +760,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) /** * @brief Injected conversion complete callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -776,9 +776,9 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Configures for the selected ADC injected channel its corresponding * rank in the sequencer and its sample time. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param sConfigInjected: ADC configuration structure for injected channel. + * @param sConfigInjected ADC configuration structure for injected channel. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) @@ -931,9 +931,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /** * @brief Configures the ADC multi-mode - * @param hadc : pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param multimode : pointer to an ADC_MultiModeTypeDef structure that contains + * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains * the configuration information for multimode. * @retval HAL status */ @@ -972,7 +972,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1025,7 +1025,7 @@ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1038,7 +1038,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c index cbf1f78641..1d48e58369 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c @@ -3,76 +3,130 @@ * @file stm32f7xx_hal_can.c * @author MCD Application Team * @brief CAN HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions * + Peripheral State and Error functions * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] - (#) Enable the CAN controller interface clock using - __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2 - and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3 - -@- In case you are using CAN2 only, you have to enable the CAN1 clock. - - (#) CAN pins configuration - (++) Enable the clock for the CAN GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE() - (++) Connect and configure the involved CAN pins to AF9 using the - following function HAL_GPIO_Init() - - (#) Initialize and configure the CAN using HAL_CAN_Init() function. - - (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. - - (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. - - (#) Receive a CAN frame using HAL_CAN_Receive() function. - - (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. - - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the CAN peripheral transmission and wait the end of this operation - using HAL_CAN_Transmit(), at this stage user can specify the value of timeout - according to his end application - (+) Start the CAN peripheral reception and wait the end of this operation - using HAL_CAN_Receive(), at this stage user can specify the value of timeout - according to his end application - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() - (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() - (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine - (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_TxCpltCallback - (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_ErrorCallback - - *** CAN HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in CAN HAL driver. - - (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts - (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts - (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled - (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags - (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status - - [..] - (@) You can refer to the CAN HAL driver header file for more useful macros - + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function open-drain + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. + + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be trigged by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. + @endverbatim - ****************************************************************************** * @attention * @@ -110,1328 +164,1707 @@ * @{ */ +#if defined(CAN1) + /** @defgroup CAN CAN * @brief CAN driver modules * @{ - */ - -#ifdef HAL_CAN_MODULE_ENABLED + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @addtogroup CAN_Private_Constants +/** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TIMEOUT_VALUE 10U +#define CAN_TIMEOUT_VALUE 10U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup CAN_Private_Functions - * @{ - */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); -/** - * @} - */ - /* Exported functions --------------------------------------------------------*/ + /** @defgroup CAN_Exported_Functions CAN Exported Functions * @{ */ -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the CAN. - (+) De-initialize the CAN. - + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + @endverbatim * @{ */ - + /** * @brief Initializes the CAN peripheral according to the specified * parameters in the CAN_InitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { - uint32_t InitStatus = CAN_INITSTATUS_FAILED; uint32_t tickstart = 0U; - + /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); assert_param(IS_CAN_MODE(hcan->Init.Mode)); - assert_param(IS_CAN_SJW(hcan->Init.SJW)); - assert_param(IS_CAN_BS1(hcan->Init.BS1)); - assert_param(IS_CAN_BS2(hcan->Init.BS2)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - - if(hcan->State == HAL_CAN_STATE_RESET) + if (hcan->State == HAL_CAN_STATE_RESET) { - /* Allocate lock resource and initialize it */ - hcan->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ + /* Init the low level hardware: CLOCK, NVIC */ HAL_CAN_MspInit(hcan); } - - /* Initialize the CAN state*/ - hcan->State = HAL_CAN_STATE_BUSY; - + /* Exit from sleep mode */ - hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - /* Request initialisation */ - hcan->Instance->MCR |= CAN_MCR_INRQ ; - /* Get tick */ tickstart = HAL_GetTick(); - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Check acknowledge */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) { - /* Set the time triggered communication mode */ - if (hcan->Init.TTCM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TTCM; - } - else + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Set the automatic bus-off management */ - if (hcan->Init.ABOM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_ABOM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Set the automatic wake-up mode */ - if (hcan->Init.AWUM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_AWUM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; + return HAL_ERROR; } + } - /* Set the no automatic retransmission */ - if (hcan->Init.NART == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_NART; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; - } + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Set the receive FIFO locked mode */ - if (hcan->Init.RFLM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_RFLM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } + /* Get tick */ + tickstart = HAL_GetTick(); - /* Set the transmit FIFO priority */ - if (hcan->Init.TXFP == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TXFP; - } - else + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ - ((uint32_t)hcan->Init.SJW) | \ - ((uint32_t)hcan->Init.BS1) | \ - ((uint32_t)hcan->Init.BS2) | \ - ((uint32_t)hcan->Init.Prescaler - 1U); - - /* Request leave initialisation */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Check acknowledged */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_INITSTATUS_SUCCESS; + return HAL_ERROR; } } - - if(InitStatus == CAN_INITSTATUS_SUCCESS) + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) { - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } else { - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Return function status */ - return HAL_ERROR; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } -} - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that - * contains the filter configuration information. - * @retval None - */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) -{ - uint32_t filternbrbitpos = 0U; - CAN_TypeDef *can_ip; - -#if !defined(CAN3) - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); -#endif /* CAN3 */ - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); - assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); - - filternbrbitpos = 1U << sFilterConfig->FilterNumber; -#if defined (CAN3) - /* Check the CAN instance */ - if(hcan->Instance == CAN3) - { - can_ip = CAN3; + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } else { - can_ip = CAN1; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } -#else - can_ip = CAN1; -#endif - - /* Initialisation mode for the filter */ - can_ip->FMR |= (uint32_t)CAN_FMR_FINIT; - -#if defined (CAN2) - /* Select the start slave bank */ - can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); - can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U); -#endif - - /* Filter Deactivation */ - can_ip->FA1R &= ~(uint32_t)filternbrbitpos; - /* Filter Scale */ - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) { - /* 16-bit scale for the filter */ - can_ip->FS1R &= ~(uint32_t)filternbrbitpos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } - - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + else { - /* 32-bit scale for the filter */ - can_ip->FS1R |= filternbrbitpos; - - /* 32-bit identifier or First 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } - /* Filter Mode */ - if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) { - /*Id/Mask mode for the filter*/ - can_ip->FM1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + else { - /*Identifier list mode for the filter*/ - can_ip->FM1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); } - /* Filter FIFO assignment */ - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + else { - /* FIFO 0 assignation for the filter */ - can_ip->FFA1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); } - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) { - /* FIFO 1 assignation for the filter */ - can_ip->FFA1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } - - /* Filter activation */ - if (sFilterConfig->FilterActivation == ENABLE) + else { - can_ip->FA1R |= filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); } - /* Leave the initialisation mode for the filter */ - can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT); - + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + /* Return function status */ return HAL_OK; } /** - * @brief Deinitializes the CANx peripheral registers to their default reset values. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) { /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* DeInit the low level hardware */ + + /* Stop the CAN module */ + HAL_CAN_Stop(hcan); + + /* DeInit the low level hardware: CLOCK, NVIC */ HAL_CAN_MspDeInit(hcan); - + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + /* Change CAN state */ hcan->State = HAL_CAN_STATE_RESET; - /* Release Lock */ - __HAL_UNLOCK(hcan); - /* Return function status */ return HAL_OK; } /** * @brief Initializes the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspInit could be implemented in the user file - */ + */ } /** * @brief DeInitializes the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspDeInit could be implemented in the user file - */ + */ } + /** * @} */ -/** @defgroup CAN_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. * -@verbatim +@verbatim ============================================================================== - ##### IO operation functions ##### + ##### Configuration functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Transmit a CAN frame message. - (+) Receive a CAN frame message. - (+) Enter CAN peripheral in sleep mode. - (+) Wake up the CAN peripheral from sleep mode. - + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + @endverbatim * @{ */ /** - * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param Timeout: Specify Timeout value - * @retval HAL status + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None */ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - uint32_t tickstart = 0U; + uint32_t filternbrbitpos = 0U; + CAN_TypeDef *can_ip = hcan->Instance; - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ - ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ - ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) - { - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - switch(hcan->State) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + +#if defined(CAN3) + /* Check the CAN instance */ + if (hcan->Instance == CAN3) { - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; + /* CAN3 is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); } - - /* Select one empty transmit mailbox */ - if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + else { - transmitmailbox = CAN_TXMAILBOX_0; + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); } - else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) +#elif defined(CAN2) + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); +#else + /* CAN1 is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); +#endif + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + +#if defined(CAN3) + /* Check the CAN instance */ + if (can_ip == CAN1) { - transmitmailbox = CAN_TXMAILBOX_1; + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); } - else + +#elif defined(CAN2) + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + +#endif + /* Convert filter number into bit position */ + filternbrbitpos = (1U) << sFilterConfig->FilterBank; + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) { - transmitmailbox = CAN_TXMAILBOX_2; + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); } - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if (hcan->pTxMsg->IDE == CAN_ID_STD) + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ - hcan->pTxMsg->RTR); + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); } - else + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[0U])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[4U])); - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check End of transmission flag */ - while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - - __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + } - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); } - /* Change CAN state */ - switch(hcan->State) + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_TX */ - hcan->State = HAL_CAN_STATE_READY; - break; + SET_BIT(can_ip->FA1R, filternbrbitpos); } - /* Process unlocked */ - __HAL_UNLOCK(hcan); - + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + /* Return function status */ return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Return function status */ return HAL_ERROR; } } /** - * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + +@endverbatim + * @{ + */ + +/** + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ - ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ - ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + uint32_t tickstart = 0U; + + if (hcan->State == HAL_CAN_STATE_READY) { - /* Process Locked */ - __HAL_LOCK(hcan); + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; - /* Select one empty transmit mailbox */ - if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = CAN_TXMAILBOX_0; - } - else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = CAN_TXMAILBOX_1; - } - else - { - transmitmailbox = CAN_TXMAILBOX_2; - } + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if(hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[0U])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[4U])); - - /* Change CAN state */ - switch(hcan->State) + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET) { - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - } + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hcan); + return HAL_ERROR; + } + } - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; - /* Enable Error warning, Error passive, Bus-off, - Last error and Error Interrupts */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME); + /* Return function status */ + return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; - /* Return function status */ return HAL_ERROR; } - - return HAL_OK; } /** - * @brief Receives a correct CAN frame. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: FIFO Number value - * @param Timeout: Specify Timeout value + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { uint32_t tickstart = 0U; - CanRxMsgTypeDef* pRxMsg = NULL; - - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - /* Check if CAN state is not busy for RX FIFO0 */ - if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) - { - return HAL_BUSY; - } - /* Check if CAN state is not busy for RX FIFO1 */ - if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + if (hcan->State == HAL_CAN_STATE_LISTENING) { - return HAL_BUSY; - } + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Process locked */ - __HAL_LOCK(hcan); + /* Get tick */ + tickstart = HAL_GetTick(); - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } } - } - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check pending message */ - while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - } + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - /* Set RxMsg pointer */ - if(FIFONumber == CAN_FIFO0) - { - pRxMsg = hcan->pRxMsg; - } - else /* FIFONumber == CAN_FIFO1 */ - { - pRxMsg = hcan->pRx1Msg; - } + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_READY; - /* Get the Id */ - pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (pRxMsg->IDE == CAN_ID_STD) - { - pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + /* Return function status */ + return HAL_OK; } else { - pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + + return HAL_ERROR; } - - pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); - /* Get the FIFONumber */ - pRxMsg->FIFONumber = FIFONumber; - /* Get the data field */ - pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); - - /* Release the FIFO */ - if(FIFONumber == CAN_FIFO0) +} + +/** + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Release FIFO0 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; } - else /* FIFONumber == CAN_FIFO1 */ + else { - /* Release FIFO1 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + /* Return function status */ + return HAL_ERROR; } +} - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) +/** + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + uint32_t timeout = 1000000U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - switch(hcan->State) + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_RX0 */ - hcan->State = HAL_CAN_STATE_READY; - break; + /* Check if timeout is reached */ + if (++count > timeout) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; + } } + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; } - else /* FIFONumber == CAN_FIFO1 */ +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - switch(hcan->State) + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) { - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - default: /* HAL_CAN_STATE_BUSY_RX1 */ - hcan->State = HAL_CAN_STATE_READY; - break; + status = 1U; } } - /* Process unlocked */ - __HAL_UNLOCK(hcan); - /* Return function status */ - return HAL_OK; + return status; } /** - * @brief Receives a correct CAN frame. - * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) { + uint32_t transmitmailbox; + /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - /* Check if CAN state is not busy for RX FIFO0 */ - if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) { - return HAL_BUSY; + assert_param(IS_CAN_STDID(pHeader->StdId)); } - - /* Check if CAN state is not busy for RX FIFO1 */ - if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + else { - return HAL_BUSY; + assert_param(IS_CAN_EXTID(pHeader->ExtId)); } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - if(FIFONumber == CAN_FIFO0) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - switch(hcan->State) + /* Check that all the Tx mailboxes are not full */ + if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)) + { + /* Select an empty transmit mailbox */ + transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Store the Tx mailbox */ + *pTxMailbox = 1U << transmitmailbox; + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; + } + else { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; } } - else /* FIFONumber == CAN_FIFO1 */ + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - switch(hcan->State) + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET) + { + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); + } + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET) { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); } + + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET) + { + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); + } + + /* Return function status */ + return HAL_OK; } - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - /* - Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME); - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - if(FIFONumber == CAN_FIFO0) +/** + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +{ + uint32_t freelevel = 0U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Enable FIFO 0 overrun and message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) + { + freelevel++; + } + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) + { + freelevel++; + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET) + { + freelevel++; + } } - else + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Enable FIFO 1 overrun and message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) + { + status = 1U; + } } - /* Return function status */ - return HAL_OK; + /* Return status */ + return status; } /** - * @brief Enters the Sleep (low power) mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @retval HAL status. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. */ -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) { - uint32_t tickstart = 0U; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Request Sleep mode */ - hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + uint32_t timestamp = 0U; + uint32_t transmitmailbox; - /* Sleep mode status */ - if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Select the Tx mailbox */ + transmitmailbox = POSITION_VAL(TxMailbox); - /* Return function status */ - return HAL_ERROR; + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; } - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) + /* Return the timestamp */ + return timestamp; +} + +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } } - } + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + return HAL_ERROR; + } + } - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos; + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos; + aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos; + aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos; + aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos; + aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos; + aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos; + aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos; + aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos; + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + } - /* Return function status */ - return HAL_OK; + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } } /** - * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral - * is in the normal mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @retval HAL status. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. */ -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) { - uint32_t tickstart = 0U; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Wake up request */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + uint32_t filllevel = 0U; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); - /* Sleep mode status */ - while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + if (RxFifo == CAN_RX_FIFO0) + { + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; } } - if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + return HAL_ERROR; } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; } /** - * @brief Handles CAN interrupt request - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. - * @retval None + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status */ -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) { - uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U; - uint32_t errorcode = HAL_CAN_ERROR_NONE; + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); - /* Check Overrun flag for FIFO0 */ - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0); - if(tmp1 && tmp2) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - /* Set CAN error code to FOV0 error */ - errorcode |= HAL_CAN_ERROR_FOV0; + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); - /* Clear FIFO0 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + /* Return function status */ + return HAL_OK; } - /* Check Overrun flag for FIFO1 */ - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1); - - if(tmp1 && tmp2) + else { - /* Set CAN error code to FOV1 error */ - errorcode |= HAL_CAN_ERROR_FOV1; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Clear FIFO1 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + return HAL_ERROR; } +} - /* Check End of transmission flag */ - if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET) { - tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0); - tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1); - tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2); - if(tmp1 || tmp2 || tmp3) + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != RESET) + { + /* Transmission Mailbox 0 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != RESET) + { + /* Transmission Mailbox 1 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != RESET) { - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0); - tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1); - tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2); - /* Check Transmit success */ - if(tmp1 || tmp2 || tmp3) + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + + if ((tsrflags & CAN_TSR_TXOK2) != RESET) { - /* Call transmit function */ - CAN_Transmit_IT(hcan); + /* Transmission Mailbox 2 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); } - else /* Transmit failure */ + else { - /* Set CAN error code to TXFAIL error */ - errorcode |= HAL_CAN_ERROR_TXFAIL; + if ((tsrflags & CAN_TSR_ALST2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); + } } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET) + { + if ((rf0rflags & CAN_RF0R_FOVR0) != RESET) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + } + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET) + { + if ((rf0rflags & CAN_RF0R_FULL0) != RESET) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); - /* Clear transmission status flags (RQCPx and TXOKx) */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \ - CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2); + /* Receive FIFO 0 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); } } - tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0); - /* Check End of reception flag for FIFO0 */ - if((tmp1 != 0U) && tmp2) + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET) { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO0); + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET) + { + /* Receive FIFO 0 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); + } } - tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1); - /* Check End of reception flag for FIFO1 */ - if((tmp1 != 0U) && tmp2) + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET) { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO1); + if ((rf1rflags & CAN_RF1R_FOVR1) != RESET) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } } - /* Set error code in handle */ - hcan->ErrorCode |= errorcode; + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET) + { + if ((rf1rflags & CAN_RF1R_FULL1) != RESET) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); + } + } - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Error Warning Flag */ - if(tmp1 && tmp2 && tmp3) + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET) { - /* Set CAN error code to EWG error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EWG; + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET) + { + /* Receive FIFO 1 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); + } } - - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Error Passive Flag */ - if(tmp1 && tmp2 && tmp3) + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != RESET) { - /* Set CAN error code to EPV error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EPV; + if ((msrflags & CAN_MSR_SLAKI) != RESET) + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); + } } - - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Bus-Off Flag */ - if(tmp1 && tmp2 && tmp3) + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != RESET) { - /* Set CAN error code to BOF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BOF; + if ((msrflags & CAN_MSR_WKUI) != RESET) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + + /* WakeUp Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); + } } - - tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Last error code Flag */ - if((!tmp1) && tmp2 && tmp3) + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != RESET) { - tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC; - switch(tmp1) + if ((msrflags & CAN_MSR_ERRI) != RESET) { - case(CAN_ESR_LEC_0): - /* Set CAN error code to STF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_STF; - break; - case(CAN_ESR_LEC_1): - /* Set CAN error code to FOR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_FOR; - break; - case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): - /* Set CAN error code to ACK error */ - hcan->ErrorCode |= HAL_CAN_ERROR_ACK; - break; - case(CAN_ESR_LEC_2): - /* Set CAN error code to BR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BR; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): - /* Set CAN error code to BD error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BD; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): - /* Set CAN error code to CRC error */ - hcan->ErrorCode |= HAL_CAN_ERROR_CRC; - break; - default: - break; + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) && + ((esrflags & CAN_ESR_EWGF) != RESET)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) && + ((esrflags & CAN_ESR_EPVF) != RESET)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != RESET) && + ((esrflags & CAN_ESR_BOFF) != RESET)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) && + ((esrflags & CAN_ESR_LEC) != RESET)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } } - /* Clear Last error code Flag */ - hcan->Instance->ESR &= ~(CAN_ESR_LEC); + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); } - + /* Call the Error call Back in case of Errors */ - if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) + if (errorcode != HAL_CAN_ERROR_NONE) { - /* Clear ERRI Flag */ - hcan->Instance->MSR = CAN_MSR_ERRI; - /* Set the CAN state ready to be able to start again the process */ - hcan->State = HAL_CAN_STATE_READY; - - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - /* - Disable FIFO 0 message pending Interrupt */ - /* - Disable FIFO 0 Overrun Interrupt */ - /* - Disable FIFO 1 message pending Interrupt */ - /* - Disable FIFO 1 Overrun Interrupt */ - /* - Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_FMP0| - CAN_IT_FOV0| - CAN_IT_FMP1| - CAN_IT_FOV1| - CAN_IT_TME); + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; /* Call Error callback function */ + /* Call weak (surcharged) callback */ HAL_CAN_ErrorCallback(hcan); - } + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback + +@endverbatim + * @{ + */ + +/** + * @brief Transmission Mailbox 0 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ } /** - * @brief Transmission complete callback in non blocking mode - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxCpltCallback could be implemented in the user file + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file */ } /** - * @brief Transmission complete callback in non blocking mode - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Sleep callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxCpltCallback could be implemented in the user file + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + +/** + * @brief WakeUp from Rx message callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file */ } /** * @brief Error CAN callback. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -1439,6 +1872,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ @@ -1448,227 +1882,110 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) * @} */ -/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * -@verbatim +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim ============================================================================== ##### Peripheral State and Error functions ##### ============================================================================== [..] This subsection provides functions allowing to : - (+) Check the CAN state. - (+) Check CAN Errors detected during interrupt process - + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + @endverbatim * @{ */ /** - * @brief return the CAN state - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return the CAN state. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL state */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) { + HAL_CAN_StateTypeDef state = hcan->State; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + } + /* Return CAN state */ - return hcan->State; + return state; } /** - * @brief Return the CAN error code - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval CAN Error Code */ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) { + /* Return CAN error code */ return hcan->ErrorCode; } /** - * @} - */ -/** - * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) -{ - /* Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Disable Error warning, Error passive, Bus-off, Last error code - and Error Interrupts */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - } - - /* Change CAN state */ - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_TX */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - - /* Transmission complete callback */ - HAL_CAN_TxCpltCallback(hcan); - - return HAL_OK; -} - -/** - * @brief Receives a correct CAN frame. - * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number + * @brief Reset the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status - * @retval None */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) { - uint32_t tmp1 = 0U; - CanRxMsgTypeDef* pRxMsg = NULL; + HAL_StatusTypeDef status = HAL_OK; - /* Set RxMsg pointer */ - if(FIFONumber == CAN_FIFO0) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - pRxMsg = hcan->pRxMsg; - } - else /* FIFONumber == CAN_FIFO1 */ - { - pRxMsg = hcan->pRx1Msg; - } - - /* Get the Id */ - pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (pRxMsg->IDE == CAN_ID_STD) - { - pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + /* Reset CAN error code */ + hcan->ErrorCode = 0U; } else { - pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); - } - - pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FIFONumber */ - pRxMsg->FIFONumber = FIFONumber; - /* Get the FMI */ - pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); - /* Get the data field */ - pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - - /* Disable FIFO 0 overrun and message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - - /* Disable FIFO 1 overrun and message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); - } + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - tmp1 = hcan->State; - if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1)) - { - /* Disable Error warning, Error passive, Bus-off, Last error code - and Error Interrupts */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR); + status = HAL_ERROR; } - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_RX0 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - default: /* HAL_CAN_STATE_BUSY_RX1 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - } - - /* Receive complete callback */ - HAL_CAN_RxCpltCallback(hcan); - - /* Return function status */ - return HAL_OK; + /* Return the status */ + return status; } +/** + * @} + */ + /** * @} */ #endif /* HAL_CAN_MODULE_ENABLED */ + /** * @} */ +#endif /* CAN1 */ + /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cec.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cec.c index bee1fe460a..202c013374 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cec.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cec.c @@ -140,7 +140,7 @@ /** * @brief Initializes the CEC mode according to the specified * parameters in the CEC_InitTypeDef and creates the associated handle . - * @param hcec: CEC handle + * @param hcec CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) @@ -210,7 +210,7 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) /** * @brief DeInitializes the CEC peripheral - * @param hcec: CEC handle + * @param hcec CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) @@ -264,8 +264,8 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) /** * @brief Initializes the Own Address of the CEC device - * @param hcec: CEC handle - * @param CEC_OwnAddress: The CEC own address. + * @param hcec CEC handle + * @param CEC_OwnAddress The CEC own address. * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress) @@ -311,7 +311,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC /** * @brief CEC MSP Init - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) @@ -325,7 +325,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC /** * @brief CEC MSP DeInit - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) @@ -377,11 +377,11 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC /** * @brief Send data in interrupt mode - * @param hcec: CEC handle - * @param InitiatorAddress: Initiator address - * @param DestinationAddress: destination logical address - * @param pData: pointer to input byte data buffer - * @param Size: amount of data to be sent in bytes (without counting the header). + * @param hcec CEC handle + * @param InitiatorAddress Initiator address + * @param DestinationAddress destination logical address + * @param pData pointer to input byte data buffer + * @param Size amount of data to be sent in bytes (without counting the header). * 0 means only the header is sent (ping operation). * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * @retval HAL status @@ -436,7 +436,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator /** * @brief Get size of the received frame. - * @param hcec: CEC handle + * @param hcec CEC handle * @retval Frame size */ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) @@ -446,8 +446,8 @@ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) /** * @brief Change Rx Buffer. - * @param hcec: CEC handle - * @param Rxbuffer: Rx Buffer + * @param hcec CEC handle + * @param Rxbuffer Rx Buffer * @note This function can be called only inside the HAL_CEC_RxCpltCallback() * @retval Frame size */ @@ -458,7 +458,7 @@ void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer) /** * @brief This function handles CEC interrupt requests. - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) @@ -563,7 +563,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /** * @brief Tx Transfer completed callback - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec) @@ -577,8 +577,8 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /** * @brief Rx Transfer completed callback - * @param hcec: CEC handle - * @param RxFrameSize: Size of frame + * @param hcec CEC handle + * @param RxFrameSize Size of frame * @retval None */ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize) @@ -593,7 +593,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize /** * @brief CEC error callbacks - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) @@ -624,7 +624,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize */ /** * @brief return the CEC state - * @param hcec: pointer to a CEC_HandleTypeDef structure that contains + * @param hcec pointer to a CEC_HandleTypeDef structure that contains * the configuration information for the specified CEC module. * @retval HAL state */ @@ -639,7 +639,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) /** * @brief Return the CEC error code -* @param hcec : pointer to a CEC_HandleTypeDef structure that contains +* @param hcec pointer to a CEC_HandleTypeDef structure that contains * the configuration information for the specified CEC. * @retval CEC Error Code */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c index a67b495da3..38410ffc4f 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c @@ -140,7 +140,7 @@ /** * @brief Sets the priority grouping field (preemption priority and subpriority) * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. + * @param PriorityGroup The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority @@ -167,13 +167,13 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) /** * @brief Sets the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @param PreemptPriority: The preemption priority for the IRQn channel. + * @param PreemptPriority The preemption priority for the IRQn channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. + * @param SubPriority the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None @@ -238,7 +238,7 @@ void HAL_NVIC_SystemReset(void) /** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ @@ -285,7 +285,7 @@ void HAL_MPU_Disable(void) /** * @brief Enables the MPU - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * @param MPU_Control Specifies the control mode of the MPU during hard fault, * NMI, FAULTMASK and privileged access to the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE @@ -309,7 +309,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control) /** * @brief Initializes and configures the Region and the memory to be protected. - * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ @@ -365,10 +365,10 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void) /** * @brief Gets the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @param PriorityGroup: the priority grouping bits length. + * @param PriorityGroup the priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority @@ -380,8 +380,8 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void) * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * 0 bits for subpriority - * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). * @retval None */ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) @@ -461,7 +461,7 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) /** * @brief Configures the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c index 816bb12f06..3f43b2c6d4 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c @@ -110,7 +110,7 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 /** * @brief Initialize the CRC according to the specified * parameters in the CRC_InitTypeDef and create the associated handle. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) @@ -187,7 +187,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) /** * @brief DeInitialize the CRC peripheral. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) @@ -231,7 +231,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) /** * @brief Initialize the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval None */ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) @@ -246,7 +246,7 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) /** * @brief DeInitialize the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval None */ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) @@ -286,10 +286,10 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) /** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with the previously computed CRC as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer + * @param BufferLength input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. @@ -344,10 +344,10 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ /** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with hcrc->Instance->INIT as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer + * @param BufferLength input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. @@ -408,9 +408,9 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /** * @brief Enter 8-bit input data to the CRC calculator. * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) @@ -449,9 +449,9 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ /** * @brief Enter 16-bit input data to the CRC calculator. * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) @@ -495,7 +495,7 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 /** * @brief Return the CRC state. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL state */ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c index 9cfd3b8b07..4fef104320 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c @@ -91,12 +91,12 @@ This subsection provides function allowing to: /** * @brief Initializes the CRC polynomial if different from default one. - * @param hcrc: CRC handle - * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long) + * @param hcrc CRC handle + * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long) * This parameter is written in normal representation, e.g. * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 - * @param PolyLength: CRC polynomial length + * @param PolyLength CRC polynomial length * This parameter can be one of the following values: * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7) * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8) @@ -161,8 +161,8 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol /** * @brief Set the Reverse Input data mode. - * @param hcrc: CRC handle - * @param InputReverseMode: Input Data inversion mode + * @param hcrc CRC handle + * @param InputReverseMode Input Data inversion mode * This parameter can be one of the following values: * @arg CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value) * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal @@ -189,8 +189,8 @@ HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t /** * @brief Set the Reverse Output data mode. - * @param hcrc: CRC handle - * @param OutputReverseMode: Output Data inversion mode + * @param hcrc CRC handle + * @param OutputReverseMode Output Data inversion mode * This parameter can be one of the following values: * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value) * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c index d6f7f35be4..577103322f 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c @@ -149,7 +149,7 @@ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction); /** * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -166,7 +166,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -189,7 +189,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) @@ -201,10 +201,10 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Writes the Key in Key registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Key: Pointer to Key buffer - * @param KeySize: Size of Key + * @param Key Pointer to Key buffer + * @param KeySize Size of Key * @retval None */ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize) @@ -260,10 +260,10 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySiz /** * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param InitVector: Pointer to InitVector/InitCounter buffer - * @param IVSize: Size of the InitVector/InitCounter + * @param InitVector Pointer to InitVector/InitCounter buffer + * @param IVSize Size of the InitVector/InitCounter * @retval None */ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize) @@ -299,12 +299,12 @@ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, u /** * @brief Process Data: Writes Input data in polling mode and read the output data - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer - * @param Ilength: Length of the Input buffer, must be a multiple of 16. - * @param Output: Pointer to the returned buffer - * @param Timeout: Timeout value + * @param Input Pointer to the Input buffer + * @param Ilength Length of the Input buffer, must be a multiple of 16. + * @param Output Pointer to the returned buffer + * @param Timeout Timeout value * @retval None */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) @@ -363,12 +363,12 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In /** * @brief Process Data: Write Input data in polling mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer - * @param Ilength: Length of the Input buffer, must be a multiple of 8 - * @param Output: Pointer to the returned buffer - * @param Timeout: Specify Timeout value + * @param Input Pointer to the Input buffer + * @param Ilength Length of the Input buffer, must be a multiple of 8 + * @param Output Pointer to the returned buffer + * @param Timeout Specify Timeout value * @retval None */ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) @@ -419,11 +419,11 @@ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief Set the DMA configuration and start the DMA transfer - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param inputaddr: address of the Input buffer - * @param Size: Size of the Input buffer, must be a multiple of 16. - * @param outputaddr: address of the Output buffer + * @param inputaddr address of the Input buffer + * @param Size Size of the Input buffer, must be a multiple of 16. + * @param outputaddr address of the Output buffer * @retval None */ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -457,9 +457,9 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin /** * @brief Sets the CRYP peripheral in DES ECB mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -484,9 +484,9 @@ static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) /** * @brief Sets the CRYP peripheral in DES CBC mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -514,9 +514,9 @@ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) /** * @brief Sets the CRYP peripheral in TDES ECB mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -540,9 +540,9 @@ static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) /** * @brief Sets the CRYP peripheral in TDES CBC mode - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -597,7 +597,7 @@ static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) /** * @brief Initializes the CRYP according to the specified * parameters in the CRYP_InitTypeDef and creates the associated handle. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -643,7 +643,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) /** * @brief DeInitializes the CRYP peripheral. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -683,7 +683,7 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) /** * @brief Initializes the CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -699,7 +699,7 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) /** * @brief DeInitializes CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -739,12 +739,12 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -793,12 +793,12 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -850,12 +850,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -909,12 +909,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -997,12 +997,12 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1086,12 +1086,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1142,11 +1142,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1243,11 +1243,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1346,11 +1346,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1450,11 +1450,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1579,11 +1579,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1716,11 +1716,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1821,11 +1821,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1876,11 +1876,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1934,11 +1934,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1993,11 +1993,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2077,11 +2077,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2164,11 +2164,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2247,12 +2247,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -2287,12 +2287,12 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -2327,12 +2327,12 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -2367,12 +2367,12 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -2407,11 +2407,11 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2492,11 +2492,11 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2578,11 +2578,11 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2663,11 +2663,11 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2748,11 +2748,11 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2791,11 +2791,11 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2834,11 +2834,11 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2877,11 +2877,11 @@ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2944,12 +2944,12 @@ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -2985,12 +2985,12 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -3026,12 +3026,12 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -3067,12 +3067,12 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -3107,11 +3107,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *p /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3192,11 +3192,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3276,11 +3276,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3360,11 +3360,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3444,11 +3444,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3487,11 +3487,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3530,11 +3530,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3573,11 +3573,11 @@ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3636,7 +3636,7 @@ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Input FIFO transfer completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3652,7 +3652,7 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief Output FIFO transfer completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3668,7 +3668,7 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief CRYP error callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3701,7 +3701,7 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief This function handles CRYP interrupt request. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3790,7 +3790,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) /** * @brief Returns the CRYP state. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL state */ @@ -4102,7 +4102,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) /** * @brief DeInitialize the CRYP peripheral. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -4142,7 +4142,7 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) /** * @brief Initialize the CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4158,7 +4158,7 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) /** * @brief DeInitialize CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4198,12 +4198,12 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) /** * @brief Encrypt pPlainData in AES ECB encryption mode. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4229,12 +4229,12 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Encrypt pPlainData in AES CBC encryption mode with key derivation. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4260,12 +4260,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Encrypt pPlainData in AES CTR encryption mode. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4291,12 +4291,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /** * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4322,12 +4322,12 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4353,12 +4353,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Decrypt pCypherData in AES CTR decryption mode, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4384,11 +4384,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /** * @brief Encrypt pPlainData in AES ECB encryption mode using Interrupt, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4414,11 +4414,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Encrypt pPlainData in AES CBC encryption mode using Interrupt, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4445,11 +4445,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Encrypt pPlainData in AES CTR encryption mode using Interrupt, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4475,11 +4475,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES ECB decryption mode using Interrupt, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer. + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4505,11 +4505,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES CBC decryption mode using Interrupt, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4535,11 +4535,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES CTR decryption mode using Interrupt, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4565,11 +4565,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Encrypt pPlainData in AES ECB encryption mode using DMA, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4598,11 +4598,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Encrypt pPlainData in AES CBC encryption mode using DMA, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4629,11 +4629,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Encrypt pPlainData in AES CTR encryption mode using DMA, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer. + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4660,11 +4660,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES ECB decryption mode using DMA, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4691,11 +4691,11 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES CBC decryption mode using DMA, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4722,11 +4722,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief Decrypt pCypherData in AES CTR decryption mode using DMA, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4773,7 +4773,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /** * @brief CRYP error callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4789,7 +4789,7 @@ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) /** * @brief Input DMA transfer complete callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4805,7 +4805,7 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief Output DMA transfer complete callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4838,7 +4838,7 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @brief Handle AES interrupt request. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4923,7 +4923,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) /** * @brief Return the CRYP handle state. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL state */ @@ -4935,7 +4935,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) /** * @brief Return the CRYP peripheral error. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @note The returned error is a bit-map combination of possible errors * @retval Error bit-map @@ -4960,7 +4960,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) /** * @brief Write the Key in KeyRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -5001,7 +5001,7 @@ static HAL_StatusTypeDef CRYP_SetKey(CRYP_HandleTypeDef *hcryp) /** * @brief Write the InitVector/InitCounter in IVRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -5044,7 +5044,7 @@ static HAL_StatusTypeDef CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp) * @brief Handle CRYP block input/output data handling under interruption. * @note The function is called under interruption only, once * interruptions have been enabled by HAL_CRYPEx_AES_IT(). - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @retval HAL status */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c index 1f05316e50..82080faaf3 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c @@ -145,7 +145,7 @@ static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t input /** * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -162,7 +162,7 @@ static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -185,7 +185,7 @@ static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma) @@ -197,10 +197,10 @@ static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Writes the Key in Key registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Key: Pointer to Key buffer - * @param KeySize: Size of Key + * @param Key Pointer to Key buffer + * @param KeySize Size of Key * @retval None */ static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize) @@ -256,9 +256,9 @@ static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32 /** * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param InitVector: Pointer to InitVector/InitCounter buffer + * @param InitVector Pointer to InitVector/InitCounter buffer * @retval None */ static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector) @@ -276,12 +276,12 @@ static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *Init /** * @brief Process Data: Writes Input data in polling mode and read the Output data. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer, must be a multiple of 16 - * @param Output: Pointer to the returned buffer - * @param Timeout: Timeout value + * @param Input Pointer to the Input buffer. + * @param Ilength Length of the Input buffer, must be a multiple of 16 + * @param Output Pointer to the returned buffer + * @param Timeout Timeout value * @retval None */ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout) @@ -339,11 +339,11 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, ui /** * @brief Sets the header phase - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer, must be a multiple of 16 - * @param Timeout: Timeout value + * @param Input Pointer to the Input buffer. + * @param Ilength Length of the Input buffer, must be a multiple of 16 + * @param Timeout Timeout value * @retval None */ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout) @@ -422,11 +422,11 @@ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, /** * @brief Sets the DMA configuration and start the DMA transfer. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param inputaddr: Address of the Input buffer - * @param Size: Size of the Input buffer, must be a multiple of 16 - * @param outputaddr: Address of the Output buffer + * @param inputaddr Address of the Input buffer + * @param Size Size of the Input buffer, must be a multiple of 16 + * @param outputaddr Address of the Output buffer * @retval None */ static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -490,12 +490,12 @@ static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t input /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode then * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -746,12 +746,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode then * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -844,12 +844,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode then * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Timeout duration + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the cyphertext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -937,11 +937,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /** * @brief Computes the authentication TAG. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Size: Total length of the plain/cyphertext buffer - * @param AuthTag: Pointer to the authentication buffer - * @param Timeout: Timeout duration + * @param Size Total length of the plain/cyphertext buffer + * @param AuthTag Pointer to the authentication buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout) @@ -1046,10 +1046,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t S /** * @brief Computes the authentication TAG for AES CCM mode. * @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt() - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param AuthTag: Pointer to the authentication buffer - * @param Timeout: Timeout duration + * @param AuthTag Pointer to the authentication buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout) @@ -1138,12 +1138,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *A /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode then * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1390,11 +1390,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t * /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1541,11 +1541,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1840,11 +1840,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the cyphertext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1988,11 +1988,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2278,11 +2278,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_ /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2375,11 +2375,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2629,11 +2629,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer. - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer. + * @param Size Length of the cyphertext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2719,11 +2719,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2990,7 +2990,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8 /** * @brief This function handles CRYPEx interrupt request. - * @param hcryp: pointer to a CRYPEx_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYPEx_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3097,7 +3097,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_ /** * @brief Computation completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3146,17 +3146,17 @@ __weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) * @brief Carry out in polling mode the ciphering or deciphering operation according to * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and * chaining modes ECB, CBC and CTR are managed by this function in polling mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. * Parameter is meaningless in case of key derivation. - * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. + * @param Size Length of the input data buffer in bytes, must be a multiple of 16. * Parameter is meaningless in case of key derivation. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption, or pointer to the derivative keys in * case of key derivation only. - * @param Timeout: Specify Timeout value + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout) @@ -3227,14 +3227,14 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, * @brief Carry out in interrupt mode the ciphering or deciphering operation according to * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and * chaining modes ECB, CBC and CTR are managed by this function in interrupt mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. * Parameter is meaningless in case of key derivation. - * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. + * @param Size Length of the input data buffer in bytes, must be a multiple of 16. * Parameter is meaningless in case of key derivation. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption, or pointer to the derivative keys in * case of key derivation only. * @retval HAL status @@ -3322,12 +3322,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputD /** * @brief Carry out in DMA mode the ciphering or deciphering operation according to * hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. - * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param Size Length of the input data buffer in bytes, must be a multiple of 16. + * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption. * @note Chaining modes ECB, CBC and CTR are managed by this function in DMA mode. * @note Supported operating modes are encryption, decryption and key derivation with decryption. @@ -3393,24 +3393,24 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /** * @brief Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering * operation according to hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: + * @param pInputData * - pointer to payload data in GCM payload phase, * - pointer to B0 block in CMAC header phase, * - pointer to C block in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init, header and final phases. - * @param Size: + * @param Size * - length of the input payload data buffer in bytes, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init and header phases. - * @param pOutputData: + * @param pOutputData * - pointer to plain or cipher text in GCM payload phase, * - pointer to authentication tag in GCM/GMAC and CMAC final phases. * - Parameter is meaningless in case of GCM/GMAC init and header phases * and in case of CMAC header phase. - * @param Timeout: Specify Timeout value + * @param Timeout Specify Timeout value * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC, CMAC and CCM when the latter is applicable. * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes * can be skipped by the user if so required. @@ -3878,19 +3878,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput /** * @brief Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering * operation according to hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: + * @param pInputData * - pointer to payload data in GCM payload phase, * - pointer to B0 block in CMAC header phase, * - pointer to C block in CMAC final phase. * Parameter is meaningless in case of GCM/GMAC init, header and final phases. - * @param Size: + * @param Size * - length of the input payload data buffer in bytes, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init and header phases. - * @param pOutputData: + * @param pOutputData * - pointer to plain or cipher text in GCM payload phase, * - pointer to authentication tag in GCM/GMAC and CMAC final phases. * - Parameter is meaningless in case of GCM/GMAC init and header phases @@ -4294,19 +4294,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn /** * @brief Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering * operation according to hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: + * @param pInputData * - pointer to payload data in GCM payload phase, * - pointer to B0 block in CMAC header phase, * - pointer to C block in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init, header and final phases. - * @param Size: + * @param Size * - length of the input payload data buffer in bytes, * - length of B block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init and header phases. - * @param pOutputData: + * @param pOutputData * - pointer to plain or cipher text in GCM payload phase, * - pointer to authentication tag in GCM/GMAC and CMAC final phases. * - Parameter is meaningless in case of GCM/GMAC init and header phases @@ -4721,9 +4721,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI /** * @brief In case of message processing suspension, read the Initialization Vector. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Initialization Vector. + * @param Output Pointer to the buffer containing the saved Initialization Vector. * @note This value has to be stored for reuse by writing the AES_IVRx registers * as soon as the interrupted processing has to be resumed. * Applicable to all chaining modes. @@ -4746,9 +4746,9 @@ void HAL_CRYPEx_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output) /** * @brief In case of message processing resumption, rewrite the Initialization * Vector in the AES_IVRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved Initialization Vector to + * @param Input Pointer to the buffer containing the saved Initialization Vector to * write back in the CRYP hardware block. * @note Applicable to all chaining modes. * @note AES must be disabled when reading or resetting the IV values. @@ -4770,9 +4770,9 @@ void HAL_CRYPEx_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input) /** * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Suspend Registers. + * @param Output Pointer to the buffer containing the saved Suspend Registers. * @note These values have to be stored for reuse by writing back the AES_SUSPxR registers * as soon as the interrupted processing has to be resumed. * @retval None @@ -4818,9 +4818,9 @@ void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output /** * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend * Registers in the AES_SUSPxR registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved suspend registers to + * @param Input Pointer to the buffer containing the saved suspend registers to * write back in the CRYP hardware block. * @retval None */ @@ -4848,10 +4848,10 @@ void HAL_CRYPEx_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input /** * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Key Registers. - * @param KeySize: Indicates the key size (128 or 256 bits). + * @param Output Pointer to the buffer containing the saved Key Registers. + * @param KeySize Indicates the key size (128 or 256 bits). * @note These values have to be stored for reuse by writing back the AES_KEYRx registers * as soon as the interrupted processing has to be resumed. * @retval None @@ -4884,11 +4884,11 @@ void HAL_CRYPEx_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output, ui /** * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key * Registers in the AES_KEYRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved key registers to + * @param Input Pointer to the buffer containing the saved key registers to * write back in the CRYP hardware block. - * @param KeySize: Indicates the key size (128 or 256 bits) + * @param KeySize Indicates the key size (128 or 256 bits) * @retval None */ void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize) @@ -4919,9 +4919,9 @@ void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, ui /** * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Control Register. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Control Register. + * @param Output Pointer to the buffer containing the saved Control Register. * @note This values has to be stored for reuse by writing back the AES_CR register * as soon as the interrupted processing has to be resumed. * @retval None @@ -4934,9 +4934,9 @@ void HAL_CRYPEx_Read_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Output) /** * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control * Registers in the AES_CR register. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved Control Register to + * @param Input Pointer to the buffer containing the saved Control Register to * write back in the CRYP hardware block. * @retval None */ @@ -4950,7 +4950,7 @@ void HAL_CRYPEx_Write_ControlRegister(CRYP_HandleTypeDef *hcryp, uint8_t* Input) /** * @brief Request CRYP processing suspension when in polling or interruption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @note Set the handle field SuspendRequest to the appropriate value so that * the on-going CRYP processing is suspended as soon as the required @@ -4984,7 +4984,7 @@ void HAL_CRYPEx_ProcessSuspend(CRYP_HandleTypeDef *hcryp) * in the case of header phase where no output data DMA * transfer is on-going (only input data transfer is enabled * in such a case). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -5025,7 +5025,7 @@ static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma) * @brief DMA CRYP Output Data process complete callback * for GCM, GMAC or CMAC chainging modes. * @note This callback is called only in the payload phase. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -5061,7 +5061,7 @@ static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP communication error callback * for GCM, GMAC or CMAC chainging modes. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma) @@ -5082,7 +5082,7 @@ static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma) * for GCM, GMAC or CMAC chaining modes. * @note The function is called under interruption only, once * interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT(). - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -5542,11 +5542,11 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp) /** * @brief Set the DMA configuration and start the DMA transfer * for GCM, GMAC or CMAC chainging modes. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param inputaddr: Address of the Input buffer. - * @param Size: Size of the Input buffer un bytes, must be a multiple of 16. - * @param outputaddr: Address of the Output buffer, null pointer when no output DMA stream + * @param inputaddr Address of the Input buffer. + * @param Size Size of the Input buffer un bytes, must be a multiple of 16. + * @param outputaddr Address of the Output buffer, null pointer when no output DMA stream * has to be configured. * @retval None */ @@ -5590,12 +5590,12 @@ static void CRYP_GCMCMAC_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputa /** * @brief Write/read input/output data in polling mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer in bytes, must be a multiple of 16. - * @param Output: Pointer to the returned buffer. - * @param Timeout: Specify Timeout value. + * @param Input Pointer to the Input buffer. + * @param Ilength Length of the Input buffer in bytes, must be a multiple of 16. + * @param Output Pointer to the returned buffer. + * @param Timeout Specify Timeout value. * @retval HAL status */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) @@ -5671,10 +5671,10 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In /** * @brief Read derivative key in polling mode when CRYP hardware block is set * in key derivation operating mode (mode 2). - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the returned buffer. - * @param Timeout: Specify Timeout value. + * @param Output Pointer to the returned buffer. + * @param Timeout Specify Timeout value. * @retval HAL status */ static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout) @@ -5719,11 +5719,11 @@ static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output /** * @brief Set the DMA configuration and start the DMA transfer. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param inputaddr: Address of the Input buffer. - * @param Size: Size of the Input buffer in bytes, must be a multiple of 16. - * @param outputaddr: Address of the Output buffer. + * @param inputaddr Address of the Input buffer. + * @param Size Size of the Input buffer in bytes, must be a multiple of 16. + * @param outputaddr Address of the Output buffer. * @retval None */ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -5754,9 +5754,9 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin /** * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Timeout: Timeout duration. + * @param Timeout Timeout duration. * @retval HAL status */ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) @@ -5782,9 +5782,9 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T /** * @brief Wait for Busy Flag to be reset during a GCM payload encryption process suspension. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Timeout: Timeout duration. + * @param Timeout Timeout duration. * @retval HAL status */ static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) @@ -5811,7 +5811,7 @@ static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uin /** * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -5827,7 +5827,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -5852,7 +5852,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) @@ -5868,10 +5868,10 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Last header or payload block padding when size is not a multiple of 128 bits. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param difflength: size remainder after having fed all complete 128-bit blocks. - * @param polling: specifies whether or not polling on CCF must be done after having + * @param difflength size remainder after having fed all complete 128-bit blocks. + * @param polling specifies whether or not polling on CCF must be done after having * entered a complete block. * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c index 69213b3e1d..c9a98dd665 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c @@ -221,7 +221,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); /** * @brief Initializes the DAC peripheral according to the specified parameters * in the DAC_InitStruct. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -258,7 +258,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) /** * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -294,7 +294,7 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) /** * @brief Initializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -310,7 +310,7 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) /** * @brief DeInitializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -348,9 +348,9 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -407,9 +407,9 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -432,15 +432,15 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The Source memory Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The Source memory Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected @@ -558,9 +558,9 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -608,9 +608,9 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -634,7 +634,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) /** * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -680,7 +680,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) /** * @brief Conversion complete callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -696,7 +696,7 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) /** * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -712,7 +712,7 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) /** * @brief Error DAC callback for Channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -728,7 +728,7 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) /** * @brief DMA underrun DAC callback for channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -763,10 +763,10 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) /** * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -814,18 +814,18 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf /** * @brief Set the specified data holding register value for DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Alignment: Specifies the data alignment. + * @param Alignment Specifies the data alignment. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. + * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) @@ -876,7 +876,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui /** * @brief return the DAC state - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL state */ @@ -889,7 +889,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) /** * @brief Return the DAC error code - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval DAC Error Code */ @@ -904,7 +904,7 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -919,7 +919,7 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -932,7 +932,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c index 72ccf1e424..5f389eac1c 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c @@ -97,7 +97,7 @@ /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ @@ -115,13 +115,13 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) /** * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Amplitude: Select max triangle amplitude. + * @param Amplitude Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 @@ -164,13 +164,13 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 /** * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. + * @param Amplitude Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation @@ -213,15 +213,15 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t /** * @brief Set the specified data holding register value for dual DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Alignment: Specifies the data alignment for dual channel DAC. + * @param Alignment Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * DAC_ALIGN_8B_R: 8bit right data alignment selected * DAC_ALIGN_12B_L: 12bit left data alignment selected * DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data1 Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data2 Data for DAC Channel1 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval HAL status @@ -261,7 +261,7 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align /** * @brief Conversion complete callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -277,7 +277,7 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) /** * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -293,7 +293,7 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) /** * @brief Error DAC callback for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -309,7 +309,7 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) /** * @brief DMA underrun DAC callback for channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -325,7 +325,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -340,7 +340,7 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -353,7 +353,7 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c index 1924611a38..a8514ea0e8 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c @@ -136,7 +136,7 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma); /** * @brief Initializes the DCMI according to the specified * parameters in the DCMI_InitTypeDef and create the associated handle. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -208,7 +208,7 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) /** * @brief Deinitializes the DCMI peripheral registers to their default reset * values. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -232,7 +232,7 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) /** * @brief Initializes the DCMI MSP. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -248,7 +248,7 @@ __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) /** * @brief DeInitializes the DCMI MSP. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -284,11 +284,11 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) /** * @brief Enables DCMI DMA request and enables DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. - * @param DCMI_Mode: DCMI capture mode snapshot or continuous grab. - * @param pData: The destination memory Buffer address (LCD Frame buffer). - * @param Length: The length of capture to be transferred. + * @param DCMI_Mode DCMI capture mode snapshot or continuous grab. + * @param pData The destination memory Buffer address (LCD Frame buffer). + * @param Length The length of capture to be transferred. * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length) @@ -370,7 +370,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo /** * @brief Disable DCMI DMA request and Disable DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -423,7 +423,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) /** * @brief Suspend DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -469,7 +469,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) /** * @brief Resume DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -495,7 +495,7 @@ HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi) /** * @brief Handles DCMI interrupt request. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for the DCMI. * @retval None */ @@ -580,7 +580,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) /** * @brief Error DCMI callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -596,7 +596,7 @@ __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief Line Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -609,7 +609,7 @@ __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief VSYNC Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -625,7 +625,7 @@ __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief Frame Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -661,12 +661,12 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) /** * @brief Configure the DCMI CROP coordinate. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. - * @param YSize: DCMI Line number - * @param XSize: DCMI Pixel per line - * @param X0: DCMI window X offset - * @param Y0: DCMI window Y offset + * @param YSize DCMI Line number + * @param XSize DCMI Pixel per line + * @param X0 DCMI window X offset + * @param Y0 DCMI window Y offset * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize) @@ -698,7 +698,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui /** * @brief Disable the Crop feature. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -724,7 +724,7 @@ HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi) /** * @brief Enable the Crop feature. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -770,7 +770,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) /** * @brief Return the DCMI state - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL state */ @@ -781,7 +781,7 @@ HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) /** * @brief Return the DCMI error code -* @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains +* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval DCMI Error Code */ @@ -799,7 +799,7 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) */ /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -856,7 +856,7 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c index d3c0755579..2c5600be37 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c @@ -267,7 +267,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma); /** * @brief Initialize the DFSDM channel according to the specified parameters * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -361,7 +361,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan /** * @brief De-initialize the DFSDM channel. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -407,7 +407,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch /** * @brief Initialize the DFSDM channel MSP. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -422,7 +422,7 @@ __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel /** * @brief De-initialize the DFSDM channel MSP. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -461,7 +461,7 @@ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chann * @note If clock is not available on this channel during 5 seconds, * clock absence detection will not be activated and function * will return HAL_TIMEOUT error. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -513,8 +513,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm /** * @brief This function allows to poll for the clock absence detection. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_channel DFSDM channel handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, @@ -564,7 +564,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs /** * @brief This function allows to stop clock absence detection in polling mode. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -600,7 +600,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ * @note If clock is not available on this channel during 5 seconds, * clock absence detection will not be activated and function * will return HAL_TIMEOUT error. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -655,7 +655,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf /** * @brief Clock absence detection callback. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -671,7 +671,7 @@ __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_ch /** * @brief This function allows to stop clock absence detection in interrupt mode. * @note Interrupt will be disabled for all channels - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -707,10 +707,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs /** * @brief This function allows to start short circuit detection in polling mode. * @note Same mode has to be used for all channels - * @param hdfsdm_channel : DFSDM channel handle. - * @param Threshold : Short circuit detector threshold. + * @param hdfsdm_channel DFSDM channel handle. + * @param Threshold Short circuit detector threshold. * This parameter must be a number between Min_Data = 0 and Max_Data = 255. - * @param BreakSignal : Break signals assigned to short circuit event. + * @param BreakSignal Break signals assigned to short circuit event. * This parameter can be a values combination of @ref DFSDM_BreakSignals. * @retval HAL status */ @@ -747,8 +747,8 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ /** * @brief This function allows to poll for the short circuit detection. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_channel DFSDM channel handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, @@ -798,7 +798,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd /** * @brief This function allows to stop short circuit detection in polling mode. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -831,10 +831,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c /** * @brief This function allows to start short circuit detection in interrupt mode. * @note Same mode has to be used for all channels - * @param hdfsdm_channel : DFSDM channel handle. - * @param Threshold : Short circuit detector threshold. + * @param hdfsdm_channel DFSDM channel handle. + * @param Threshold Short circuit detector threshold. * This parameter must be a number between Min_Data = 0 and Max_Data = 255. - * @param BreakSignal : Break signals assigned to short circuit event. + * @param BreakSignal Break signals assigned to short circuit event. * This parameter can be a values combination of @ref DFSDM_BreakSignals. * @retval HAL status */ @@ -874,7 +874,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs /** * @brief Short circuit detection callback. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval None */ __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -890,7 +890,7 @@ __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_cha /** * @brief This function allows to stop short circuit detection in interrupt mode. * @note Interrupt will be disabled for all channels - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -925,7 +925,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd /** * @brief This function allows to get channel analog watchdog value. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval Channel analog watchdog value. */ int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -935,8 +935,8 @@ int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel /** * @brief This function allows to modify channel offset value. - * @param hdfsdm_channel : DFSDM channel handle. - * @param Offset : DFSDM channel offset. + * @param hdfsdm_channel DFSDM channel handle. + * @param Offset DFSDM channel offset. * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607. * @retval HAL status. */ @@ -984,7 +984,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf /** * @brief This function allows to get the current DFSDM channel handle state. - * @param hdfsdm_channel : DFSDM channel handle. + * @param hdfsdm_channel DFSDM channel handle. * @retval DFSDM channel state. */ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) @@ -1014,7 +1014,7 @@ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTyp /** * @brief Initialize the DFSDM filter according to the specified parameters * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1124,7 +1124,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /** * @brief De-initializes the DFSDM filter. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1152,7 +1152,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filt /** * @brief Initializes the DFSDM filter MSP. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1167,7 +1167,7 @@ __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) /** * @brief De-initializes the DFSDM filter MSP. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1201,10 +1201,10 @@ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) /** * @brief This function allows to select channel and to enable/disable * continuous mode for regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channel for regular conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Channel for regular conversion. * This parameter can be a value of @ref DFSDM_Channel_Selection. - * @param ContinuousMode : Enable/disable continuous mode for regular conversion. + * @param ContinuousMode Enable/disable continuous mode for regular conversion. * This parameter can be a value of @ref DFSDM_ContinuousMode. * @retval HAL status */ @@ -1248,8 +1248,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to select channels for injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channels for injected conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Channels for injected conversion. * This parameter can be a values combination of @ref DFSDM_Channel_Selection. * @retval HAL status */ @@ -1320,7 +1320,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *h * @brief This function allows to start regular conversion in polling mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1348,8 +1348,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsd /** * @brief This function allows to poll for the end of regular conversion. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_filter DFSDM filter handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1410,7 +1410,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to stop regular conversion in polling mode. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1440,7 +1440,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm * @brief This function allows to start regular conversion in interrupt mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1471,7 +1471,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hd /** * @brief This function allows to stop regular conversion in interrupt mode. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1507,9 +1507,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf * Please note that data on buffer will contain signed regular conversion * value on 24 most significant bits and corresponding channel on 3 least * significant bits. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1584,9 +1584,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *h * in idle state or if injected conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1657,7 +1657,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef /** * @brief This function allows to stop regular conversion in DMA mode. * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1695,8 +1695,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd /** * @brief This function allows to get regular conversion value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel of regular conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel of regular conversion. * @retval Regular conversion value */ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1724,7 +1724,7 @@ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filte * @brief This function allows to start injected conversion in polling mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1752,8 +1752,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief This function allows to poll for the end of injected conversion. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Timeout : Timeout value in milliseconds. + * @param hdfsdm_filter DFSDM filter handle. + * @param Timeout Timeout value in milliseconds. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1824,7 +1824,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to stop injected conversion in polling mode. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1854,7 +1854,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd * @brief This function allows to start injected conversion in interrupt mode. * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1885,7 +1885,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to stop injected conversion in interrupt mode. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -1921,9 +1921,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd * Please note that data on buffer will contain signed injected conversion * value on 24 most significant bits and corresponding channel on 3 least * significant bits. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -1996,9 +1996,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef * * in idle state or if regular conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. - * @param pData : The destination buffer address. - * @param Length : The length of data to be transferred from DFSDM filter to memory. + * @param hdfsdm_filter DFSDM filter handle. + * @param pData The destination buffer address. + * @param Length The length of data to be transferred from DFSDM filter to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2067,7 +2067,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to stop injected conversion in DMA mode. * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2105,8 +2105,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to get injected conversion value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel of injected conversion. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel of injected conversion. * @retval Injected conversion value */ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2132,8 +2132,8 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt /** * @brief This function allows to start filter analog watchdog in interrupt mode. - * @param hdfsdm_filter : DFSDM filter handle. - * @param awdParam : DFSDM filter analog watchdog parameters. + * @param hdfsdm_filter DFSDM filter handle. + * @param awdParam DFSDM filter analog watchdog parameters. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2182,7 +2182,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief This function allows to stop filter analog watchdog in interrupt mode. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2220,8 +2220,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_ /** * @brief This function allows to start extreme detector feature. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Channels where extreme detector is enabled. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Channels where extreme detector is enabled. * This parameter can be a values combination of @ref DFSDM_Channel_Selection. * @retval HAL status */ @@ -2253,7 +2253,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi /** * @brief This function allows to stop extreme detector feature. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2289,8 +2289,8 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /** * @brief This function allows to get extreme detector maximum value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel. * @retval Extreme detector maximum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ @@ -2317,8 +2317,8 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /** * @brief This function allows to get extreme detector minimum value. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel. * @retval Extreme detector minimum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ @@ -2345,7 +2345,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter /** * @brief This function allows to get conversion time value. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval Conversion time value * @note To get time in second, this value has to be divided by DFSDM clock frequency. */ @@ -2369,7 +2369,7 @@ uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /** * @brief This function handles the DFSDM interrupts. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2530,7 +2530,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) * @brief Regular conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetRegularValue. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2545,7 +2545,7 @@ __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief Half regular conversion complete callback. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2562,7 +2562,7 @@ __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * * @brief Injected conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetInjectedValue. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2577,7 +2577,7 @@ __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs /** * @brief Half injected conversion complete callback. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2592,9 +2592,9 @@ __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * /** * @brief Filter analog watchdog callback. - * @param hdfsdm_filter : DFSDM filter handle. - * @param Channel : Corresponding channel. - * @param Threshold : Low or high threshold has been reached. + * @param hdfsdm_filter DFSDM filter handle. + * @param Channel Corresponding channel. + * @param Threshold Low or high threshold has been reached. * @retval None */ __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, @@ -2612,7 +2612,7 @@ __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filte /** * @brief Error callback. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2645,7 +2645,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /** * @brief This function allows to get the current DFSDM filter handle state. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter state. */ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2656,7 +2656,7 @@ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDe /** * @brief This function allows to get the current DFSDM filter error. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter error code. */ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) @@ -2680,7 +2680,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) /** * @brief DMA half transfer complete callback for regular conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -2694,7 +2694,7 @@ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete callback for regular conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) @@ -2708,7 +2708,7 @@ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback for injected conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) @@ -2722,7 +2722,7 @@ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete callback for injected conversion. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) @@ -2736,7 +2736,7 @@ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback. - * @param hdma : DMA handle. + * @param hdma DMA handle. * @retval None */ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) @@ -2753,7 +2753,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function allows to get the number of injected channels. - * @param Channels : bitfield of injected channels. + * @param Channels bitfield of injected channels. * @retval Number of injected channels. */ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) @@ -2776,7 +2776,7 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) /** * @brief This function allows to get the channel number from channel instance. - * @param Instance : DFSDM channel instance. + * @param Instance DFSDM channel instance. * @retval Channel number. */ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) @@ -2822,7 +2822,7 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) /** * @brief This function allows to really start regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -2863,7 +2863,7 @@ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @brief This function allows to really stop regular conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -2899,7 +2899,7 @@ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @brief This function allows to really start injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) @@ -2943,7 +2943,7 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @brief This function allows to really stop injected conversion. - * @param hdfsdm_filter : DFSDM filter handle. + * @param hdfsdm_filter DFSDM filter handle. * @retval None */ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c index 00b1c119ed..fadb46c5b3 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c @@ -41,7 +41,8 @@ =================================== [..] (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Select Callbacks functions using HAL_DMA_RegisterCallback() (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred. In this case the DMA interrupt is configured @@ -180,7 +181,7 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); /** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and create the associated handle. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ @@ -319,7 +320,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /** * @brief DeInitializes the DMA peripheral - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ @@ -369,11 +370,19 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Initialize the error code */ + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Reset the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; - /* Initialize the DMA state */ + /* Reset the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ @@ -406,11 +415,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /** * @brief Starts the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -450,11 +459,11 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui /** * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -510,7 +519,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /** * @brief Aborts the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * * @note After disabling a DMA Stream, a check for wait until the DMA Stream is @@ -583,7 +592,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /** * @brief Aborts the DMA Transfer in Interrupt mode. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ @@ -608,13 +617,13 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) /** * @brief Polling for transfer complete. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CompleteLevel: Specifies the DMA level complete. + * @param CompleteLevel Specifies the DMA level complete. * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. * This model could be used for debug purpose. * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). - * @param Timeout: Timeout duration. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) @@ -740,7 +749,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level } else { - /* Clear the half transfer and transfer complete flags */ + /* Clear the half transfer flag */ regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; } @@ -749,7 +758,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /** * @brief Handles DMA interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ @@ -966,11 +975,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /** * @brief Register callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a DMA_HandleTypeDef structure as parameter. - * @param pCallback: pointer to private callbacsk function which has pointer to + * @param pCallback pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ @@ -1028,9 +1037,9 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call /** * @brief UnRegister callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ @@ -1115,7 +1124,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca /** * @brief Returns the DMA state. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL state */ @@ -1126,7 +1135,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) /** * @brief Return the DMA error code - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval DMA Error Code */ @@ -1149,11 +1158,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) /** * @brief Sets the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -1186,7 +1195,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /** * @brief Returns the DMA Stream base address depending on stream number - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ @@ -1214,7 +1223,7 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) /** * @brief Check compatibility between FIFO threshold level and size of the memory burst - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c index ced61df5d9..ba5336760a 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c @@ -193,7 +193,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ /** * @brief Initialize the DMA2D according to the specified * parameters in the DMA2D_InitTypeDef and create the associated handle. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ @@ -253,7 +253,7 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) /** * @brief Deinitializes the DMA2D peripheral registers to their default reset * values. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -332,7 +332,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) /** * @brief Initializes the DMA2D MSP. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -348,7 +348,7 @@ __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) /** * @brief DeInitializes the DMA2D MSP. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -404,15 +404,15 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) /** * @brief Start the DMA2D Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param pdata: Configure the source memory Buffer address if + * @param pdata Configure the source memory Buffer address if * Memory-to-Memory or Memory-to-Memory with pixel format * conversion mode is selected, or configure * the color value if Register-to-Memory mode is selected. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -438,15 +438,15 @@ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, u /** * @brief Start the DMA2D Transfer with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param pdata: Configure the source memory Buffer address if + * @param pdata Configure the source memory Buffer address if * the Memory-to-Memory or Memory-to-Memory with pixel format * conversion mode is selected, or configure * the color value if Register-to-Memory mode is selected. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -475,13 +475,13 @@ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata /** * @brief Start the multi-source DMA2D Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param SrcAddress1: The source memory Buffer address for the foreground layer. - * @param SrcAddress2: The source memory Buffer address for the background layer. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param SrcAddress1 The source memory Buffer address for the foreground layer. + * @param SrcAddress2 The source memory Buffer address for the background layer. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -510,13 +510,13 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t /** * @brief Start the multi-source DMA2D Transfer with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param SrcAddress1: The source memory Buffer address for the foreground layer. - * @param SrcAddress2: The source memory Buffer address for the background layer. - * @param DstAddress: The destination memory Buffer address. - * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). - * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @param SrcAddress1 The source memory Buffer address for the foreground layer. + * @param SrcAddress2 The source memory Buffer address for the background layer. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) @@ -548,7 +548,7 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32 /** * @brief Abort the DMA2D Transfer. - * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ @@ -597,7 +597,7 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) /** * @brief Suspend the DMA2D Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ @@ -647,7 +647,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) /** * @brief Resume the DMA2D Transfer. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ @@ -672,9 +672,9 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) /** * @brief Enable the DMA2D CLUT Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -707,11 +707,11 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay /** * @brief Start DMA2D CLUT Loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT(). @@ -762,11 +762,11 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT /** * @brief Start DMA2D CLUT Loading with interrupt enabled. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -822,9 +822,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC /** * @brief Abort the DMA2D CLUT loading. - * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -879,9 +879,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint3 /** * @brief Suspend the DMA2D CLUT loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -936,9 +936,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin /** * @brief Resume the DMA2D CLUT loading. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -977,9 +977,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint /** * @brief Polling for transfer complete or CLUT loading. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) @@ -1104,7 +1104,7 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ } /** * @brief Handle DMA2D interrupt request. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ @@ -1265,7 +1265,7 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) /** * @brief Transfer watermark callback. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -1281,7 +1281,7 @@ __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) /** * @brief CLUT Transfer Complete callback. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ @@ -1321,9 +1321,9 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) /** * @brief Configure the DMA2D Layer according to the specified * parameters in the DMA2D_InitTypeDef and create the associated handle. - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -1418,11 +1418,11 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La /** * @brief Configure the DMA2D CLUT Transfer. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains * the configuration information for the color look up table. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval HAL status @@ -1473,9 +1473,9 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCf /** * @brief Configure the line watermark. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. - * @param Line: Line Watermark configuration (maximum 16-bit long value expected). + * @param Line Line Watermark configuration (maximum 16-bit long value expected). * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt. * @note The transfer watermark interrupt is disabled once it has occurred. * @retval HAL status @@ -1516,7 +1516,7 @@ HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32 /** * @brief Enable DMA2D dead time feature. - * @param hdma2d: DMA2D handle. + * @param hdma2d DMA2D handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) @@ -1539,7 +1539,7 @@ HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) /** * @brief Disable DMA2D dead time feature. - * @param hdma2d: DMA2D handle. + * @param hdma2d DMA2D handle. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) @@ -1564,8 +1564,8 @@ HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) * @brief Configure dead time. * @note The dead time value represents the guaranteed minimum number of cycles between * two consecutive transactions on the AHB bus. - * @param hdma2d: DMA2D handle. - * @param DeadTime: dead time value. + * @param hdma2d DMA2D handle. + * @param DeadTime dead time value. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime) @@ -1609,7 +1609,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t /** * @brief Return the DMA2D state - * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL state */ @@ -1620,7 +1620,7 @@ HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) /** * @brief Return the DMA2D error code - * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for DMA2D. * @retval DMA2D Error Code */ @@ -1644,12 +1644,12 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) /** * @brief Set the DMA2D transfer parameters. - * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the specified DMA2D. - * @param pdata: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param Width: The width of data to be transferred from source to destination. - * @param Height: The height of data to be transferred from source to destination. + * @param pdata The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param Width The width of data to be transferred from source to destination. + * @param Height The height of data to be transferred from source to destination. * @retval HAL status */ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c index 85dd515284..02d30900e7 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c @@ -108,12 +108,12 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres /** * @brief Starts the multi_buffer DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) @@ -162,12 +162,12 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S /** * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) @@ -236,10 +236,10 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_ /** * @brief Change the memory0 or memory1 address on the fly. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param Address: The new address - * @param memory: the memory to be changed, This parameter can be one of + * @param Address The new address + * @param memory the memory to be changed, This parameter can be one of * the following values: * MEMORY0 / * MEMORY1 @@ -278,11 +278,11 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre /** * @brief Set the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c index ed3a6248e1..8e08a4930b 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c @@ -86,16 +86,16 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32 /* Private functions ---------------------------------------------------------*/ /** * @brief Generic DSI packet header configuration - * @param DSIx: Pointer to DSI register base - * @param ChannelID: Virtual channel ID of the header packet - * @param DataType: Packet data type of the header packet + * @param DSIx Pointer to DSI register base + * @param ChannelID Virtual channel ID of the header packet + * @param DataType Packet data type of the header packet * This parameter can be any value of : * @ref DSI_SHORT_WRITE_PKT_Data_Type * or @ref DSI_LONG_WRITE_PKT_Data_Type * or @ref DSI_SHORT_READ_PKT_Data_Type * or DSI_MAX_RETURN_PKT_SIZE - * @param Data0: Word count LSB - * @param Data1: Word count MSB + * @param Data0 Word count LSB + * @param Data1 Word count MSB * @retval None */ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, @@ -131,9 +131,9 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, /** * @brief Initializes the DSI according to the specified * parameters in the DSI_InitTypeDef and create the associated handle. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains + * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains * the PLL Clock structure definition for the DSI. * @retval HAL status */ @@ -251,7 +251,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI /** * @brief De-initializes the DSI peripheral registers to their default reset * values. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -298,7 +298,7 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) /** * @brief Return the DSI error code - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval DSI Error Code */ @@ -310,9 +310,9 @@ uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) /** * @brief Enable the error monitor flags - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ActiveErrors: indicates which error interrupts will be enabled. + * @param ActiveErrors indicates which error interrupts will be enabled. * This parameter can be any combination of @ref DSI_Error_Data_Type. * @retval HAL status */ @@ -395,7 +395,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t A /** * @brief Initializes the DSI MSP. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -411,7 +411,7 @@ __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) /** * @brief De-initializes the DSI MSP. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -444,7 +444,7 @@ __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) */ /** * @brief Handles DSI interrupt request. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -547,7 +547,7 @@ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) /** * @brief Tearing Effect DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -563,7 +563,7 @@ __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) /** * @brief End of Refresh DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -579,7 +579,7 @@ __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) /** * @brief Operation Error DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -611,9 +611,9 @@ __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) /** * @brief Configure the Generic interface read-back Virtual Channel ID. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param VirtualChannelID: Virtual channel ID + * @param VirtualChannelID Virtual channel ID * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) @@ -633,9 +633,9 @@ HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t Virtu /** * @brief Select video mode and configure the corresponding parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains * the DSI video mode configuration parameters * @retval HAL status */ @@ -783,9 +783,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTyp /** * @brief Select adapted command mode and configure the corresponding parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains * the DSI command mode configuration parameters * @retval HAL status */ @@ -853,9 +853,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_ /** * @brief Configure command transmission mode: High-speed or Low-power * and enable/disable acknowledge request after packet transmission - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains + * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains * the DSI command transmission mode configuration parameters * @retval HAL status */ @@ -916,9 +916,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDe /** * @brief Configure the flow control parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param FlowControl: flow control feature(s) to be enabled. + * @param FlowControl flow control feature(s) to be enabled. * This parameter can be any combination of @ref DSI_FlowControl. * @retval HAL status */ @@ -942,9 +942,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t Fl /** * @brief Configure the DSI PHY timer parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains + * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains * the DSI PHY timing parameters * @retval HAL status */ @@ -986,9 +986,9 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT /** * @brief Configure the DSI HOST timeout parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains + * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains * the DSI host timeout parameters * @retval HAL status */ @@ -1041,7 +1041,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_T /** * @brief Start the DSI module - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1064,7 +1064,7 @@ HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) /** * @brief Stop the DSI module - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1087,7 +1087,7 @@ HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) /** * @brief Refresh the display in command mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1107,9 +1107,9 @@ HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) /** * @brief Controls the display color mode in Video mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ColorMode: Color mode (full or 8-colors). + * @param ColorMode Color mode (full or 8-colors). * This parameter can be any value of @ref DSI_Color_Mode * @retval HAL status */ @@ -1133,9 +1133,9 @@ HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) /** * @brief Control the display shutdown in Video mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Shutdown: Shut-down (Display-ON or Display-OFF). + * @param Shutdown Shut-down (Display-ON or Display-OFF). * This parameter can be any value of @ref DSI_ShutDown * @retval HAL status */ @@ -1159,15 +1159,15 @@ HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) /** * @brief DCS or Generic short write command - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelID: Virtual channel ID. - * @param Mode: DSI short packet data type. + * @param ChannelID Virtual channel ID. + * @param Mode DSI short packet data type. * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. - * @param Param1: DSC command or first generic parameter. + * @param Param1 DSC command or first generic parameter. * This parameter can be any value of @ref DSI_DCS_Command or a * generic command code. - * @param Param2: DSC parameter or second generic parameter. + * @param Param2 DSC parameter or second generic parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, @@ -1215,16 +1215,16 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, /** * @brief DCS or Generic long write command - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelID: Virtual channel ID. - * @param Mode: DSI long packet data type. + * @param ChannelID Virtual channel ID. + * @param Mode DSI long packet data type. * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. - * @param NbParams: Number of parameters. - * @param Param1: DSC command or first generic parameter. + * @param NbParams Number of parameters. + * @param Param1 DSC command or first generic parameter. * This parameter can be any value of @ref DSI_DCS_Command or a * generic command code - * @param ParametersTable: Pointer to parameter values table. + * @param ParametersTable Pointer to parameter values table. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, @@ -1295,15 +1295,15 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, /** * @brief Read command (DCS or generic) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelNbr: Virtual channel ID - * @param Array: pointer to a buffer to store the payload of a read back operation. - * @param Size: Data size to be read (in byte). - * @param Mode: DSI read packet data type. + * @param ChannelNbr Virtual channel ID + * @param Array pointer to a buffer to store the payload of a read back operation. + * @param Size Data size to be read (in byte). + * @param Mode DSI read packet data type. * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. - * @param DCSCmd: DCS get/read command. - * @param ParametersTable: Pointer to parameter values table. + * @param DCSCmd DCS get/read command. + * @param ParametersTable Pointer to parameter values table. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, @@ -1416,7 +1416,7 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, /** * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running * (only data lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1472,7 +1472,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) /** * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running * (only data lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1531,7 +1531,7 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) /** * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off * (both data and clock lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1596,7 +1596,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) /** * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off * (both data and clock lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1679,13 +1679,13 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) /** * @brief Start test pattern generation - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Mode: Pattern generator mode + * @param Mode Pattern generator mode * This parameter can be one of the following values: * 0 : Color bars (horizontal or vertical) * 1 : BER pattern (vertical only) - * @param Orientation: Pattern generator orientation + * @param Orientation Pattern generator orientation * This parameter can be one of the following values: * 0 : Vertical color bars * 1 : Horizontal color bars @@ -1711,7 +1711,7 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_ /** * @brief Stop test pattern generation - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1731,13 +1731,13 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) /** * @brief Set Slew-Rate And Delay Tuning - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CommDelay: Communication delay to be adjusted. + * @param CommDelay Communication delay to be adjusted. * This parameter can be any value of @ref DSI_Communication_Delay - * @param Lane: select between clock or data lanes. + * @param Lane select between clock or data lanes. * This parameter can be any value of @ref DSI_Lane_Group - * @param Value: Custom value of the slew-rate or delay + * @param Value Custom value of the slew-rate or delay * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value) @@ -1805,9 +1805,9 @@ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uin /** * @brief Low-Power Reception Filter Tuning - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX + * @param Frequency cutoff frequency of low-pass filter at the input of LPRX * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) @@ -1828,9 +1828,9 @@ HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t /** * @brief Activate an additional current path on all lanes to meet the SDDTx parameter * defined in the MIPI D-PHY specification - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -1853,13 +1853,13 @@ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) /** * @brief Custom lane pins configuration - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CustomLane: Function to be applyed on selected lane. + * @param CustomLane Function to be applyed on selected lane. * This parameter can be any value of @ref DSI_CustomLane - * @param Lane: select between clock or data lane 0 or data lane 1. + * @param Lane select between clock or data lane 0 or data lane 1. * This parameter can be any value of @ref DSI_Lane_Select - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State) @@ -1926,12 +1926,12 @@ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint /** * @brief Set custom timing for the PHY - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Timing: PHY timing to be adjusted. + * @param Timing PHY timing to be adjusted. * This parameter can be any value of @ref DSI_PHY_Timing - * @param State: ENABLE or DISABLE - * @param Value: Custom value of the timing + * @param State ENABLE or DISABLE + * @param Value Custom value of the timing * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) @@ -2074,11 +2074,11 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing /** * @brief Force the Clock/Data Lane in TX Stop Mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Lane: select between clock or data lanes. + * @param Lane select between clock or data lanes. * This parameter can be any value of @ref DSI_Lane_Group - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) @@ -2111,9 +2111,9 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane /** * @brief Forces LP Receiver in Low-Power Mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2136,9 +2136,9 @@ HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalSta /** * @brief Force Data Lanes in RX Mode after a BTA - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2161,9 +2161,9 @@ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, Functional /** * @brief Enable a pull-down on the lanes to prevent from floating states when unused - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2186,9 +2186,9 @@ HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState S /** * @brief Switch off the contention detection on data lanes - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2231,7 +2231,7 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun /** * @brief Return the DSI state - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL state */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c index fb8ffba829..514b1e0948 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c @@ -165,7 +165,7 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); /** * @brief Initializes the Ethernet MAC and DMA according to default * parameters. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -438,7 +438,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) /** * @brief De-Initializes the ETH peripheral. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -462,11 +462,11 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) /** * @brief Initializes the DMA Tx descriptors in chain mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param DMATxDescTab: Pointer to the first Tx desc list - * @param TxBuff: Pointer to the first TxBuffer list - * @param TxBuffCount: Number of the used Tx desc in the list + * @param DMATxDescTab Pointer to the first Tx desc list + * @param TxBuff Pointer to the first TxBuffer list + * @param TxBuffCount Number of the used Tx desc in the list * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) @@ -529,11 +529,11 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc /** * @brief Initializes the DMA Rx descriptors in chain mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param DMARxDescTab: Pointer to the first Rx desc list - * @param RxBuff: Pointer to the first RxBuffer list - * @param RxBuffCount: Number of the used Rx desc in the list + * @param DMARxDescTab Pointer to the first Rx desc list + * @param RxBuff Pointer to the first RxBuffer list + * @param RxBuffCount Number of the used Rx desc in the list * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) @@ -599,7 +599,7 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc /** * @brief Initializes the ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -615,7 +615,7 @@ __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) /** * @brief DeInitializes ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -658,9 +658,9 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) /** * @brief Sends an Ethernet frame. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param FrameLength: Amount of data to be sent + * @param FrameLength Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) @@ -772,7 +772,7 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL /** * @brief Checks for received frames. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -852,7 +852,7 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) /** * @brief Gets the Received frame in interrupt mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -937,7 +937,7 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) /** * @brief This function handles ETH interrupt request. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -997,7 +997,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) /** * @brief Tx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1013,7 +1013,7 @@ __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) /** * @brief Rx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1029,7 +1029,7 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) /** * @brief Ethernet transfer error callbacks - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1045,14 +1045,14 @@ __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) /** * @brief Reads a PHY register - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. * This parameter can be one of the following values: * PHY_BCR: Transceiver Basic Control Register, * PHY_BSR: Transceiver Basic Status Register. * More PHY register could be read depending on the used PHY - * @param RegValue: PHY register value + * @param RegValue PHY register value * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) @@ -1118,13 +1118,13 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR /** * @brief Writes to a PHY register. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. * This parameter can be one of the following values: * PHY_BCR: Transceiver Control Register. * More PHY register could be written depending on the used PHY - * @param RegValue: the value to write + * @param RegValue the value to write * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) @@ -1215,7 +1215,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY /** * @brief Enables Ethernet MAC and DMA reception/transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -1254,7 +1254,7 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) /** * @brief Stop Ethernet MAC and DMA reception/transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -1293,9 +1293,9 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) /** * @brief Set ETH MAC Configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param macconf: MAC Configuration structure + * @param macconf MAC Configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) @@ -1460,9 +1460,9 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef /** * @brief Sets ETH DMA Configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param dmaconf: DMA Configuration structure + * @param dmaconf DMA Configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) @@ -1568,7 +1568,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef /** * @brief Return the ETH HAL state - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL state */ @@ -1592,9 +1592,9 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) /** * @brief Configures Ethernet MAC and DMA with default parameters. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param err: Ethernet Init error + * @param err Ethernet Init error * @retval HAL status */ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) @@ -1849,15 +1849,15 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /** * @brief Configures the selected MAC address. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param MacAddr: The MAC address to configure + * @param MacAddr The MAC address to configure * This parameter can be one of the following values: * @arg ETH_MAC_Address0: MAC Address0 * @arg ETH_MAC_Address1: MAC Address1 * @arg ETH_MAC_Address2: MAC Address2 * @arg ETH_MAC_Address3: MAC Address3 - * @param Addr: Pointer to MAC address buffer data (6 bytes) + * @param Addr Pointer to MAC address buffer data (6 bytes) * @retval HAL status */ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) @@ -1880,7 +1880,7 @@ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint /** * @brief Enables the MAC transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1900,7 +1900,7 @@ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the MAC transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1920,7 +1920,7 @@ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the MAC reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1940,7 +1940,7 @@ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the MAC reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1960,7 +1960,7 @@ static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the DMA transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1972,7 +1972,7 @@ static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the DMA transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1984,7 +1984,7 @@ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the DMA reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1996,7 +1996,7 @@ static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the DMA reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -2008,7 +2008,7 @@ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) /** * @brief Clears the ETHERNET transmit FIFO. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c index 6e9da0f99c..242cd7d3fc 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c @@ -170,10 +170,10 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** * @brief Program byte, halfword, word or double word at a specified address - * @param TypeProgram: Indicate the way to program at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ @@ -239,10 +239,10 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /** * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled. - * @param TypeProgram: Indicate the way to program at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed * * @retval HAL Status */ @@ -436,7 +436,7 @@ void HAL_FLASH_IRQHandler(void) /** * @brief FLASH end of operation interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that * all the selected sectors have been erased) * - Program : Address which was selected for data program @@ -454,7 +454,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) /** * @brief FLASH operation error interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that * all the selected sectors have been erased) * - Program : Address which was selected for data program @@ -495,18 +495,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { - if((FLASH->CR & FLASH_CR_LOCK) != RESET) + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) { /* Authorize the FLASH Registers access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - } - else - { - return HAL_ERROR; + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } } - - return HAL_OK; + + return status; } /** @@ -604,7 +608,7 @@ uint32_t HAL_FLASH_GetError(void) /** * @brief Wait for a FLASH operation to complete. - * @param Timeout: maximum flash operationtimeout + * @param Timeout maximum flash operationtimeout * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) @@ -658,8 +662,8 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) @@ -690,8 +694,8 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_Word(uint32_t Address, uint32_t Data) @@ -719,8 +723,8 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data) * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) @@ -749,8 +753,8 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c index f16bf292f0..549bb1d68c 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c @@ -162,10 +162,10 @@ extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); */ /** * @brief Perform a mass erase or erase the specified FLASH memory sectors - * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * - * @param[out] SectorError: pointer to variable that + * @param[out] SectorError pointer to variable that * contains the configuration information on faulty sector in case of error * (0xFFFFFFFF means that all the sectors have been correctly erased) * @@ -239,7 +239,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /** * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled - * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * * @retval HAL Status @@ -295,7 +295,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /** * @brief Program option bytes - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval HAL Status @@ -394,7 +394,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) /** * @brief Get the Option byte configuration - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval None @@ -437,7 +437,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) #if defined (FLASH_OPTCR_nDBANK) /** * @brief Full erase of FLASH memory sectors - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -447,7 +447,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) * the operation will be done by word (32-bit) * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) - * @param Banks: Banks to be erased + * @param Banks Banks to be erased * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be erased * @arg FLASH_BANK_2: Bank2 to be erased @@ -486,9 +486,9 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) /** * @brief Erase the specified FLASH memory sector - * @param Sector: FLASH sector to erase + * @param Sector FLASH sector to erase * The value of this parameter depend on device used within the same series - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -556,35 +556,35 @@ static uint32_t FLASH_OB_GetWRP(void) /** * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param Wwdg: Selects the IWDG mode + * @param Wwdg Selects the IWDG mode * This parameter can be one of the following values: * @arg OB_WWDG_SW: Software WWDG selected * @arg OB_WWDG_HW: Hardware WWDG selected - * @param Iwdg: Selects the WWDG mode + * @param Iwdg Selects the WWDG mode * This parameter can be one of the following values: * @arg OB_IWDG_SW: Software IWDG selected * @arg OB_IWDG_HW: Hardware IWDG selected - * @param Stop: Reset event when entering STOP mode. + * @param Stop Reset event when entering STOP mode. * This parameter can be one of the following values: * @arg OB_STOP_NO_RST: No reset generated when entering in STOP * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param Stdby: Reset event when entering Standby mode. + * @param Stdby Reset event when entering Standby mode. * This parameter can be one of the following values: * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @param Iwdgstop: Independent watchdog counter freeze in Stop mode. + * @param Iwdgstop Independent watchdog counter freeze in Stop mode. * This parameter can be one of the following values: * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP - * @param Iwdgstdby: Independent watchdog counter freeze in standby mode. + * @param Iwdgstdby Independent watchdog counter freeze in standby mode. * This parameter can be one of the following values: * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY - * @param NDBank: Flash Single Bank mode enabled. + * @param NDBank Flash Single Bank mode enabled. * This parameter can be one of the following values: * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank) * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode) - * @param NDBoot: Flash Dual boot mode disable. + * @param NDBoot Flash Dual boot mode disable. * This parameter can be one of the following values: * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot @@ -641,7 +641,7 @@ static uint32_t FLASH_OB_GetUser(void) /** * @brief Full erase of FLASH memory sectors - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -670,9 +670,9 @@ static void FLASH_MassErase(uint8_t VoltageRange) /** * @brief Erase the specified FLASH memory sector - * @param Sector: FLASH sector to erase + * @param Sector FLASH sector to erase * The value of this parameter depend on device used within the same series - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -734,27 +734,27 @@ static uint32_t FLASH_OB_GetWRP(void) /** * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param Wwdg: Selects the IWDG mode + * @param Wwdg Selects the IWDG mode * This parameter can be one of the following values: * @arg OB_WWDG_SW: Software WWDG selected * @arg OB_WWDG_HW: Hardware WWDG selected - * @param Iwdg: Selects the WWDG mode + * @param Iwdg Selects the WWDG mode * This parameter can be one of the following values: * @arg OB_IWDG_SW: Software IWDG selected * @arg OB_IWDG_HW: Hardware IWDG selected - * @param Stop: Reset event when entering STOP mode. + * @param Stop Reset event when entering STOP mode. * This parameter can be one of the following values: * @arg OB_STOP_NO_RST: No reset generated when entering in STOP * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param Stdby: Reset event when entering Standby mode. + * @param Stdby Reset event when entering Standby mode. * This parameter can be one of the following values: * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @param Iwdgstop: Independent watchdog counter freeze in Stop mode. + * @param Iwdgstop Independent watchdog counter freeze in Stop mode. * This parameter can be one of the following values: * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP - * @param Iwdgstdby: Independent watchdog counter freeze in standby mode. + * @param Iwdgstdby Independent watchdog counter freeze in standby mode. * This parameter can be one of the following values: * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY @@ -812,7 +812,7 @@ static uint32_t FLASH_OB_GetUser(void) * it is not possible to program or erase the flash sector i if CortexM7 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * - * @param WRPSector: specifies the sector(s) to be write protected. + * @param WRPSector specifies the sector(s) to be write protected. * This parameter can be one of the following values: * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) @@ -847,7 +847,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector) * it is not possible to program or erase the flash sector i if CortexM4 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * - * @param WRPSector: specifies the sector(s) to be write protected. + * @param WRPSector specifies the sector(s) to be write protected. * This parameter can be one of the following values: * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) @@ -878,7 +878,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector) /** * @brief Set the read protection level. - * @param Level: specifies the read protection level. + * @param Level specifies the read protection level. * This parameter can be one of the following values: * @arg OB_RDP_LEVEL_0: No protection * @arg OB_RDP_LEVEL_1: Read protection of the memory @@ -908,7 +908,7 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) /** * @brief Set the BOR Level. - * @param Level: specifies the Option Bytes BOR Reset Level. + * @param Level specifies the Option Bytes BOR Reset Level. * This parameter can be one of the following values: * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V @@ -931,11 +931,11 @@ static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) /** * @brief Configure Boot base address. * - * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1 + * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 * This parameter can be one of the following values: * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 - * @param Address: specifies Boot base address + * @param Address specifies Boot base address * This parameter can be one of the following values: * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) @@ -1017,7 +1017,7 @@ static uint32_t FLASH_OB_GetBOR(void) /** * @brief Configure Boot base address. * - * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1 + * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 * This parameter can be one of the following values: * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 @@ -1051,7 +1051,7 @@ static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption) #if defined (FLASH_OPTCR2_PCROP) /** * @brief Set the PCROP protection for sectors. - * @param PCROPSector: specifies the sector(s) to be PCROP protected. + * @param PCROPSector specifies the sector(s) to be PCROP protected. * This parameter can be one of the following values: * @arg OB_PCROP_SECTOR_x: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_7 * @arg OB_PCROP_SECTOR_ALL @@ -1078,7 +1078,7 @@ static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector) /** * @brief Set the PCROP_RDP value - * @param Pcrop_Rdp: specifies the PCROP_RDP bit value. + * @param Pcrop_Rdp specifies the PCROP_RDP bit value. * * @retval HAL Status */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c index aabf17fa4a..01720c10da 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c @@ -177,8 +177,8 @@ /** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ @@ -302,8 +302,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /** * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None */ @@ -382,8 +382,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /** * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ @@ -412,10 +412,10 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. + * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin @@ -439,8 +439,8 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin /** * @brief Toggles the specified GPIO pins. - * @param GPIOx: Where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: Specifies the pins to be toggled. + * @param GPIOx Where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -457,8 +457,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F7 family - * @param GPIO_Pin: specifies the port bit to be locked. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F7 family + * @param GPIO_Pin specifies the port bit to be locked. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ @@ -492,7 +492,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief This function handles EXTI interrupt request. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @param GPIO_Pin Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) @@ -507,7 +507,7 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) /** * @brief EXTI line detection callbacks. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @param GPIO_Pin Specifies the pins connected EXTI line * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c index 5dd92171a1..d007ec39a8 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c @@ -131,7 +131,7 @@ static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size); /** * @brief DMA HASH Input Data complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) @@ -203,7 +203,7 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA HASH communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void HASH_DMAError(DMA_HandleTypeDef *hdma) @@ -215,8 +215,8 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Writes the input buffer in data register. - * @param pInBuffer: Pointer to input buffer - * @param Size: The size of input buffer + * @param pInBuffer Pointer to input buffer + * @param Size The size of input buffer * @retval None */ static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size) @@ -233,8 +233,8 @@ static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size) /** * @brief Provides the message digest result. - * @param pMsgDigest: Pointer to the message digest - * @param Size: The size of the message digest in bytes + * @param pMsgDigest Pointer to the message digest + * @param Size The size of the message digest in bytes * @retval None */ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) @@ -335,7 +335,7 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) /** * @brief Initializes the HASH according to the specified parameters in the HASH_HandleTypeDef and creates the associated handle. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval HAL status */ @@ -382,7 +382,7 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) /** * @brief DeInitializes the HASH peripheral. * @note This API must be called before starting a new processing. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval HAL status */ @@ -420,7 +420,7 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) /** * @brief Initializes the HASH MSP. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -436,7 +436,7 @@ __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash) /** * @brief DeInitializes HASH MSP. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -452,7 +452,7 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Input data transfer complete callback. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -468,7 +468,7 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Data transfer Error callback. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -485,7 +485,7 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Digest computation complete callback. It is used only with interrupt. * @note This callback is not relevant with DMA. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -522,15 +522,15 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is multiple of 64 bytes, appending the input buffer is possible. * If the Size is not multiple of 64 bytes, the padding is managed by hardware * and appending the input buffer is no more possible. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -599,10 +599,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff /** * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is multiple of 64 bytes, appending the input buffer is possible. * If the Size is not multiple of 64 bytes, the padding is managed by hardware * and appending the input buffer is no more possible. @@ -646,13 +646,13 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -721,10 +721,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf /** * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted. * @retval HAL status @@ -790,12 +790,12 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p /** * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer. * The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes. + * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -952,12 +952,12 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB /** * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer. * The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -1112,7 +1112,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn /** * @brief This function handles HASH interrupt request. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -1156,10 +1156,10 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) /** * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to control data transfer. Use HAL_HASH_MD5_Finish() to get the digest. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1207,10 +1207,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /** * @brief Returns the computed digest in MD5 mode - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1260,10 +1260,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu /** * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1312,10 +1312,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Returns the computed digest in SHA1 mode. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1385,13 +1385,13 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB /** * @brief Initializes the HASH peripheral in HMAC MD5 mode * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1530,13 +1530,13 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff /** * @brief Initializes the HASH peripheral in HMAC SHA1 mode * then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1694,10 +1694,10 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf /** * @brief Initializes the HASH peripheral in HMAC MD5 mode * then enables DMA to control data transfer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1761,10 +1761,10 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /** * @brief Initializes the HASH peripheral in HMAC SHA1 mode * then enables DMA to control data transfer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1845,7 +1845,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief return the HASH state - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval HAL state */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c index 2c891e5b23..a0a7b2b7be 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c @@ -129,8 +129,8 @@ static void HASHEx_DMAError(DMA_HandleTypeDef *hdma); /** * @brief Writes the input buffer in data register. - * @param pInBuffer: Pointer to input buffer - * @param Size: The size of input buffer + * @param pInBuffer Pointer to input buffer + * @param Size The size of input buffer * @retval None */ static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size) @@ -147,8 +147,8 @@ static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size) /** * @brief Provides the message digest result. - * @param pMsgDigest: Pointer to the message digest - * @param Size: The size of the message digest in bytes + * @param pMsgDigest Pointer to the message digest + * @param Size The size of the message digest in bytes * @retval None */ static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size) @@ -220,7 +220,7 @@ static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size) /** * @brief DMA HASH Input Data complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma) @@ -292,7 +292,7 @@ static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA HASH communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void HASHEx_DMAError(DMA_HandleTypeDef *hdma) @@ -330,13 +330,13 @@ static void HASHEx_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Initializes the HASH peripheral in SHA224 mode * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes. - * @param Timeout: Specify Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes. + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -406,13 +406,13 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes. - * @param Timeout: Specify Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes. + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -483,10 +483,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in SHA224 mode * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -529,10 +529,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_ /** * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -595,13 +595,13 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_ /** * @brief Initializes the HASH peripheral in HMAC SHA224 mode * then processes pInBuffer. The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -739,13 +739,13 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in HMAC SHA256 mode * then processes pInBuffer. The digest is available in pOutBuffer - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -906,12 +906,12 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer. * The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -1054,12 +1054,12 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer. * The digest is available in pOutBuffer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. - * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes. + * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -1205,7 +1205,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** * @brief This function handles HASH interrupt request. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module * @retval None */ @@ -1251,10 +1251,10 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash) /** * @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1302,10 +1302,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Returns the computed digest in SHA224 - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1355,10 +1355,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* p /** * @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1406,10 +1406,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Returns the computed digest in SHA256. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes. - * @param Timeout: Timeout value + * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1479,10 +1479,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p /** * @brief Initializes the HASH peripheral in HMAC SHA224 mode * then enables DMA to control data transfer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ @@ -1546,10 +1546,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Initializes the HASH peripheral in HMAC SHA256 mode * then enables DMA to control data transfer. - * @param hhash: pointer to a HASH_HandleTypeDef structure that contains + * @param hhash pointer to a HASH_HandleTypeDef structure that contains * the configuration information for HASH module - * @param pInBuffer: Pointer to the input buffer (buffer to be hashed). - * @param Size: Length of the input buffer in bytes. + * @param pInBuffer Pointer to the input buffer (buffer to be hashed). + * @param Size Length of the input buffer in bytes. * If the Size is not multiple of 64 bytes, the padding is managed by hardware. * @retval HAL status */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c index f3d69fdecc..d714384f53 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c @@ -3,13 +3,13 @@ * @file stm32f7xx_hal_hcd.c * @author MCD Application Team * @brief HCD HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -17,21 +17,21 @@ [..] (#)Declare a HCD_HandleTypeDef handle structure, for example: HCD_HandleTypeDef hhcd; - + (#)Fill parameters of Init structure in HCD handle - - (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) + + (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API: (##) Enable the HCD/USB Low Level interface clock using the following macros (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode) - + (##) Initialize the related GPIO clocks (##) Configure HCD pin-out (##) Configure HCD NVIC interrupt - + (#)Associate the Upper USB Host stack to the HAL HCD Driver: (##) hhcd.pData = phost; @@ -67,7 +67,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -76,7 +76,7 @@ * @{ */ -/** @defgroup HCD HCD +/** @defgroup HCD HCD * @brief HCD HAL module driver * @{ */ @@ -92,7 +92,7 @@ * @{ */ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); -static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd); static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); /** @@ -104,82 +104,82 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); * @{ */ -/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - + @endverbatim * @{ */ /** * @brief Initialize the host driver. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) -{ +{ /* Check the HCD handle allocation */ if(hhcd == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); hhcd->State = HAL_HCD_STATE_BUSY; - + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_HCD_MspInit(hhcd); /* Disable the Interrupts */ __HAL_HCD_DISABLE(hhcd); - + /*Init the Core (common init.) */ USB_CoreInit(hhcd->Instance, hhcd->Init); - + /* Force Host Mode*/ USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE); - + /* Init Host */ USB_HostInit(hhcd->Instance, hhcd->Init); - + hhcd->State= HAL_HCD_STATE_READY; - + return HAL_OK; } /** * @brief Initialize a host channel. - * @param hhcd: HCD handle - * @param ch_num: Channel number. + * @param hhcd HCD handle + * @param ch_num Channel number. * This parameter can be a value from 1 to 15 - * @param epnum: Endpoint number. + * @param epnum Endpoint number. * This parameter can be a value from 1 to 15 - * @param dev_address : Current device address + * @param dev_address Current device address * This parameter can be a value from 0 to 255 - * @param speed: Current device speed. + * @param speed Current device speed. * This parameter can be one of these values: * HCD_SPEED_HIGH: High speed mode, * HCD_SPEED_FULL: Full speed mode, * HCD_SPEED_LOW: Low speed mode - * @param ep_type: Endpoint Type. + * @param ep_type Endpoint Type. * This parameter can be one of these values: * EP_TYPE_CTRL: Control type, * EP_TYPE_ISOC: Isochronous type, * EP_TYPE_BULK: Bulk type, * EP_TYPE_INTR: Interrupt type - * @param mps: Max Packet Size. + * @param mps Max Packet Size. * This parameter can be a value from 0 to32K * @retval HAL status */ -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, @@ -188,9 +188,9 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint16_t mps) { HAL_StatusTypeDef status = HAL_OK; - - __HAL_LOCK(hhcd); - + + __HAL_LOCK(hhcd); + hhcd->hc[ch_num].do_ping = 0; hhcd->hc[ch_num].dev_addr = dev_address; hhcd->hc[ch_num].max_packet = mps; hhcd->hc[ch_num].ch_num = ch_num; @@ -199,39 +199,39 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80); hhcd->hc[ch_num].speed = speed; - status = USB_HC_Init(hhcd->Instance, + status = USB_HC_Init(hhcd->Instance, ch_num, epnum, dev_address, speed, ep_type, mps); - __HAL_UNLOCK(hhcd); - + __HAL_UNLOCK(hhcd); + return status; } /** * @brief Halt a host channel. - * @param hhcd: HCD handle - * @param ch_num: Channel number. + * @param hhcd HCD handle + * @param ch_num Channel number. * This parameter can be a value from 1 to 15 * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) { HAL_StatusTypeDef status = HAL_OK; - - __HAL_LOCK(hhcd); - USB_HC_Halt(hhcd->Instance, ch_num); + + __HAL_LOCK(hhcd); + USB_HC_Halt(hhcd->Instance, ch_num); __HAL_UNLOCK(hhcd); - + return status; } /** * @brief DeInitialize the host driver. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) @@ -241,29 +241,29 @@ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) { return HAL_ERROR; } - + hhcd->State = HAL_HCD_STATE_BUSY; - + /* DeInit the low level hardware */ HAL_HCD_MspDeInit(hhcd); - + __HAL_HCD_DISABLE(hhcd); - - hhcd->State = HAL_HCD_STATE_RESET; - + + hhcd->State = HAL_HCD_STATE_RESET; + return HAL_OK; } /** * @brief Initialize the HCD MSP. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_HCD_MspInit could be implemented in the user file */ @@ -271,14 +271,14 @@ __weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) /** * @brief DeInitialize the HCD MSP. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_HCD_MspDeInit could be implemented in the user file */ @@ -295,49 +295,49 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USB Host Data + [..] This subsection provides a set of functions allowing to manage the USB Host Data Transfer - + @endverbatim * @{ */ - -/** - * @brief Submit a new URB for processing. - * @param hhcd: HCD handle - * @param ch_num: Channel number. + +/** + * @brief Submit a new URB for processing. + * @param hhcd HCD handle + * @param ch_num Channel number. * This parameter can be a value from 1 to 15 - * @param direction: Channel number. + * @param direction Channel number. * This parameter can be one of these values: * 0 : Output / 1 : Input - * @param ep_type: Endpoint Type. + * @param ep_type Endpoint Type. * This parameter can be one of these values: * EP_TYPE_CTRL: Control type/ * EP_TYPE_ISOC: Isochronous type/ * EP_TYPE_BULK: Bulk type/ * EP_TYPE_INTR: Interrupt type/ - * @param token: Endpoint Type. + * @param token Endpoint Type. * This parameter can be one of these values: * 0: HC_PID_SETUP / 1: HC_PID_DATA1 - * @param pbuff: pointer to URB data - * @param length: Length of URB data - * @param do_ping: activate do ping protocol (for high speed only). + * @param pbuff pointer to URB data + * @param length Length of URB data + * @param do_ping activate do ping protocol (for high speed only). * This parameter can be one of these values: - * 0 : do ping inactive / 1 : do ping active + * 0 : do ping inactive / 1 : do ping active * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, + uint8_t ch_num, uint8_t direction , - uint8_t ep_type, - uint8_t token, - uint8_t* pbuff, + uint8_t ep_type, + uint8_t token, + uint8_t* pbuff, uint16_t length, - uint8_t do_ping) + uint8_t do_ping) { hhcd->hc[ch_num].ep_is_in = direction; - hhcd->hc[ch_num].ep_type = ep_type; - + hhcd->hc[ch_num].ep_type = ep_type; + if(token == 0) { hhcd->hc[ch_num].data_pid = HC_PID_SETUP; @@ -346,7 +346,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, { hhcd->hc[ch_num].data_pid = HC_PID_DATA1; } - + /* Manage Data Toggle */ switch(ep_type) { @@ -357,38 +357,30 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, { /* For Status OUT stage, Length==0, Status Out PID = 1 */ hhcd->hc[ch_num].toggle_out = 1; } - + /* Set the Data Toggle bit as per the Flag */ if ( hhcd->hc[ch_num].toggle_out == 0) { /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } else { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; - } - if(hhcd->hc[ch_num].urb_state != URB_NOTREADY) - { - hhcd->hc[ch_num].do_ping = do_ping; + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; } } break; - + case EP_TYPE_BULK: if(direction == 0) { /* Set the Data Toggle bit as per the Flag */ if ( hhcd->hc[ch_num].toggle_out == 0) { /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } else { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; - } - if(hhcd->hc[ch_num].urb_state != URB_NOTREADY) - { - hhcd->hc[ch_num].do_ping = do_ping; + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; } } else @@ -402,7 +394,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].data_pid = HC_PID_DATA1; } } - + break; case EP_TYPE_INTR: if(direction == 0) @@ -410,7 +402,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, /* Set the Data Toggle bit as per the Flag */ if ( hhcd->hc[ch_num].toggle_out == 0) { /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } else { /* Put the PID 1 */ @@ -429,47 +421,47 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, } } break; - - case EP_TYPE_ISOC: + + case EP_TYPE_ISOC: hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - break; + break; } - + hhcd->hc[ch_num].xfer_buff = pbuff; hhcd->hc[ch_num].xfer_len = length; - hhcd->hc[ch_num].urb_state = URB_IDLE; + hhcd->hc[ch_num].urb_state = URB_IDLE; hhcd->hc[ch_num].xfer_count = 0 ; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].state = HC_IDLE; - + return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable); } /** * @brief Handle HCD interrupt request. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t i = 0 , interrupt = 0; - + /* ensure that we are in device mode */ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) { /* avoid spurious interrupt */ - if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) + if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) { return; } - + if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { /* incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } - + if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) { /* incorrect mode, acknowledge the interrupt */ @@ -480,41 +472,41 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { /* incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); - } - + } + if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) { /* incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); - } - + } + /* Handle Host Disconnect Interrupts */ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) { - + /* Cleanup HPRT */ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - + /* Handle Host Port Interrupts */ HAL_HCD_Disconnect_Callback(hhcd); USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); } - + /* Handle Host Port Interrupts */ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) { HCD_Port_IRQHandler (hhcd); } - + /* Handle Host SOF Interrupts */ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) { HAL_HCD_SOF_Callback(hhcd); __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); } - + /* Handle Host channel Interrupts */ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) { @@ -534,15 +526,15 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) } } __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); - } - + } + /* Handle Rx Queue Level Interrupts */ if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) { USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - + HCD_RXQLVL_IRQHandler (hhcd); - + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); } } @@ -550,14 +542,14 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) /** * @brief SOF callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_HCD_SOF_Callback could be implemented in the user file */ @@ -565,14 +557,14 @@ __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) /** * @brief Connection Event callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_HCD_Connect_Callback could be implemented in the user file */ @@ -580,39 +572,39 @@ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) /** * @brief Disconnection Event callback. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_HCD_Disconnect_Callback could be implemented in the user file */ -} +} /** * @brief Notify URB state change callback. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @param urb_state: * This parameter can be one of these values: * URB_IDLE/ * URB_DONE/ * URB_NOTREADY/ - * URB_NYET/ - * URB_ERROR/ - * URB_STALL/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL/ * @retval None */ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) { /* Prevent unused argument(s) compilation warning */ UNUSED(hhcd); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file */ @@ -622,15 +614,15 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t * @} */ -/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions - * @brief Management functions +/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the HCD data + This subsection provides a set of functions allowing to control the HCD data transfers. @endverbatim @@ -639,35 +631,35 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t /** * @brief Start the host driver. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) -{ - __HAL_LOCK(hhcd); +{ + __HAL_LOCK(hhcd); __HAL_HCD_ENABLE(hhcd); - USB_DriveVbus(hhcd->Instance, 1); - __HAL_UNLOCK(hhcd); + USB_DriveVbus(hhcd->Instance, 1); + __HAL_UNLOCK(hhcd); return HAL_OK; } /** * @brief Stop the host driver. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) -{ - __HAL_LOCK(hhcd); +{ + __HAL_LOCK(hhcd); USB_StopHost(hhcd->Instance); - __HAL_UNLOCK(hhcd); + __HAL_UNLOCK(hhcd); return HAL_OK; } /** * @brief Reset the host port. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) @@ -679,15 +671,15 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) * @} */ -/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -696,7 +688,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) /** * @brief Return the HCD handle state. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval HAL state */ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) @@ -706,16 +698,16 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) /** * @brief Return URB state for a channel. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval URB state. * This parameter can be one of these values: * URB_IDLE/ * URB_DONE/ * URB_NOTREADY/ - * URB_NYET/ - * URB_ERROR/ + * URB_NYET/ + * URB_ERROR/ * URB_STALL */ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum) @@ -726,32 +718,32 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu /** * @brief Return the last host transfer size. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval last transfer size in byte */ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - return hhcd->hc[chnum].xfer_count; + return hhcd->hc[chnum].xfer_count; } - + /** * @brief Return the Host Channel state. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval Host channel state * This parameter can be one of these values: * HC_IDLE/ * HC_XFRC/ * HC_HALTED/ - * HC_NYET/ - * HC_NAK/ - * HC_STALL/ - * HC_XACTERR/ - * HC_BBLERR/ - * HC_DATATGLERR + * HC_NYET/ + * HC_NAK/ + * HC_STALL/ + * HC_XACTERR/ + * HC_BBLERR/ + * HC_DATATGLERR */ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) { @@ -760,7 +752,7 @@ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) /** * @brief Return the current Host frame number. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval Current Host frame number */ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) @@ -770,7 +762,7 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) /** * @brief Return the Host enumeration speed. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval Enumeration speed */ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) @@ -791,8 +783,8 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) */ /** * @brief Handle Host Channel IN interrupt requests. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval none */ @@ -800,91 +792,91 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t tmpreg = 0; - + if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - } + } else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); } - - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) + + else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) { __HAL_HCD_UNMASK_HALT_HC_INT(chnum); hhcd->hc[chnum].state = HC_STALL; __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); - USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + USB_HC_Halt(hhcd->Instance, chnum); } else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR) { __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); hhcd->hc[chnum].state = HC_DATATGLERR; __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); - } - + } + if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + USB_HC_Halt(hhcd->Instance, chnum); __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); } - + else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) { - + if (hhcd->Init.dma_enable) { hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \ (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); } - + hhcd->hc[chnum].state = HC_XFRC; hhcd->hc[chnum].ErrCnt = 0; __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - - + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + USB_HC_Halt(hhcd->Instance, chnum); __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - + } else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR) { USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; - hhcd->hc[chnum].urb_state = URB_DONE; + hhcd->hc[chnum].urb_state = URB_DONE; HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); } hhcd->hc[chnum].toggle_in ^= 1; - + } else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(chnum); - + __HAL_HCD_MASK_HALT_HC_INT(chnum); + if(hhcd->hc[chnum].state == HC_XFRC) { - hhcd->hc[chnum].urb_state = URB_DONE; + hhcd->hc[chnum].urb_state = URB_DONE; } - - else if (hhcd->hc[chnum].state == HC_STALL) + + else if (hhcd->hc[chnum].state == HC_STALL) { hhcd->hc[chnum].urb_state = URB_STALL; - } - + } + else if((hhcd->hc[chnum].state == HC_XACTERR) || (hhcd->hc[chnum].state == HC_DATATGLERR)) { if(hhcd->hc[chnum].ErrCnt++ > 3) - { + { hhcd->hc[chnum].ErrCnt = 0; hhcd->hc[chnum].urb_state = URB_ERROR; } @@ -892,50 +884,63 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) { hhcd->hc[chnum].urb_state = URB_NOTREADY; } - + /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); - } - + } + else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + __HAL_HCD_UNMASK_HALT_HC_INT(chnum); hhcd->hc[chnum].ErrCnt++; hhcd->hc[chnum].state = HC_XACTERR; - USB_HC_Halt(hhcd->Instance, chnum); + USB_HC_Halt(hhcd->Instance, chnum); __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); } else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) - { + { if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + hhcd->hc[chnum].ErrCnt = 0; + hhcd->hc[chnum].state = HC_NAK; + __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + USB_HC_Halt(hhcd->Instance, chnum); + } - else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) { - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; + hhcd->hc[chnum].ErrCnt = 0; + if (!hhcd->Init.dma_enable) + { + hhcd->hc[chnum].state = HC_NAK; + __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + USB_HC_Halt(hhcd->Instance, chnum); + } } - hhcd->hc[chnum].state = HC_NAK; __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } } /** * @brief Handle Host Channel OUT interrupt requests. - * @param hhcd: HCD handle - * @param chnum: Channel number. + * @param hhcd HCD handle + * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval none */ @@ -943,120 +948,126 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t tmpreg = 0; - + if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - } + } else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK) { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); - if( hhcd->hc[chnum].do_ping == 1) { - hhcd->hc[chnum].state = HC_NYET; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + hhcd->hc[chnum].do_ping = 0; hhcd->hc[chnum].urb_state = URB_NOTREADY; + __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + USB_HC_Halt(hhcd->Instance, chnum); } } - + else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET) { hhcd->hc[chnum].state = HC_NYET; - hhcd->hc[chnum].ErrCnt= 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + hhcd->hc[chnum].do_ping = 1; + hhcd->hc[chnum].ErrCnt= 0; + __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + USB_HC_Halt(hhcd->Instance, chnum); __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); - - } - + } + else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + USB_HC_Halt(hhcd->Instance, chnum); __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); } - + else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) { - hhcd->hc[chnum].ErrCnt = 0; + hhcd->hc[chnum].ErrCnt = 0; __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + USB_HC_Halt(hhcd->Instance, chnum); __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); hhcd->hc[chnum].state = HC_XFRC; - } + } - else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) + else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL) { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_STALL; + USB_HC_Halt(hhcd->Instance, chnum); + hhcd->hc[chnum].state = HC_STALL; } else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) - { - hhcd->hc[chnum].ErrCnt = 0; - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + { + hhcd->hc[chnum].ErrCnt = 0; hhcd->hc[chnum].state = HC_NAK; + + if ( hhcd->hc[chnum].do_ping == 0) + { + if (hhcd->hc[chnum].speed == HCD_SPEED_HIGH) + { + hhcd->hc[chnum].do_ping = 1; + } + } + + __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + USB_HC_Halt(hhcd->Instance, chnum); __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); - hhcd->hc[chnum].state = HC_XACTERR; + __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + USB_HC_Halt(hhcd->Instance, chnum); + hhcd->hc[chnum].state = HC_XACTERR; __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); } - + else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(chnum); - USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_UNMASK_HALT_HC_INT(chnum); + USB_HC_Halt(hhcd->Instance, chnum); __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); hhcd->hc[chnum].state = HC_DATATGLERR; } - - + else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(chnum); - + __HAL_HCD_MASK_HALT_HC_INT(chnum); + if(hhcd->hc[chnum].state == HC_XFRC) { hhcd->hc[chnum].urb_state = URB_DONE; if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK) { - hhcd->hc[chnum].toggle_out ^= 1; - } + hhcd->hc[chnum].toggle_out ^= 1; + } } - else if (hhcd->hc[chnum].state == HC_NAK) + else if (hhcd->hc[chnum].state == HC_NAK) { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - } - - else if (hhcd->hc[chnum].state == HC_NYET) + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + + else if (hhcd->hc[chnum].state == HC_NYET) { hhcd->hc[chnum].urb_state = URB_NOTREADY; - hhcd->hc[chnum].do_ping = 0; - } - - else if (hhcd->hc[chnum].state == HC_STALL) + } + + else if (hhcd->hc[chnum].state == HC_STALL) { hhcd->hc[chnum].urb_state = URB_STALL; - } - + } + else if((hhcd->hc[chnum].state == HC_XACTERR) || (hhcd->hc[chnum].state == HC_DATATGLERR)) { if(hhcd->hc[chnum].ErrCnt++ > 3) - { + { hhcd->hc[chnum].ErrCnt = 0; hhcd->hc[chnum].urb_state = URB_ERROR; } @@ -1064,51 +1075,51 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) { hhcd->hc[chnum].urb_state = URB_NOTREADY; } - + /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; + USBx_HC(chnum)->HCCHAR = tmpreg; } - + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); } -} +} /** * @brief Handle Rx Queue Level interrupt requests. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval none */ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint8_t channelnum =0; + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint8_t channelnum =0; uint32_t pktsts; - uint32_t pktcnt; + uint32_t pktcnt; uint32_t temp = 0; uint32_t tmpreg = 0; - + temp = hhcd->Instance->GRXSTSP ; - channelnum = temp & USB_OTG_GRXSTSP_EPNUM; + channelnum = temp & USB_OTG_GRXSTSP_EPNUM; pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - + switch (pktsts) { case GRXSTS_PKTSTS_IN: /* Read the data into the host buffer. */ if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0)) - { - + { + USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt); - + /*manage multiple Xfer */ - hhcd->hc[channelnum].xfer_buff += pktcnt; + hhcd->hc[channelnum].xfer_buff += pktcnt; hhcd->hc[channelnum].xfer_count += pktcnt; - + if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0) { /* re-activate the channel when more packets are expected */ @@ -1132,40 +1143,40 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) /** * @brief Handle Host Port interrupt requests. - * @param hhcd: HCD handle + * @param hhcd HCD handle * @retval None */ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; __IO uint32_t hprt0, hprt0_dup; - + /* Handle Host Port Interrupts */ hprt0 = USBx_HPRT0; hprt0_dup = USBx_HPRT0; - + hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - + /* Check whether Port Connect detected */ if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) - { + { if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) { USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); HAL_HCD_Connect_Callback(hhcd); } hprt0_dup |= USB_OTG_HPRT_PCDET; - + } - + /* Check whether Port Enable Changed */ if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) { hprt0_dup |= USB_OTG_HPRT_PENCHNG; - + if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) - { + { if(hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) { if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) @@ -1185,18 +1196,18 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) } } HAL_HCD_Connect_Callback(hhcd); - + } else { /* Cleanup HPRT */ USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); - } + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); + } } - + /* Check For an overcurrent */ if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) { @@ -1214,7 +1225,7 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) /** * @} */ - + #endif /* HAL_HCD_MODULE_ENABLED */ /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c index 2fa4874902..2489ad3615 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c @@ -105,6 +105,12 @@ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential + interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using HAL_I2C_Master_Sequential_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Sequential_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. (+) Differents sequential I2C interfaces are listed below: (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() @@ -236,7 +242,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -301,8 +307,8 @@ /* Private macro -------------------------------------------------------------*/ #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ - ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \ - ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR))) + ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmatx->Instance)->NDTR)) : \ + ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmarx->Instance)->NDTR))) /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -364,7 +370,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui */ /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== @@ -404,7 +410,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { /* Check the I2C handle allocation */ - if(hi2c == NULL) + if (hi2c == NULL) { return HAL_ERROR; } @@ -419,7 +425,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - if(hi2c->State == HAL_I2C_STATE_RESET) + if (hi2c->State == HAL_I2C_STATE_RESET) { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; @@ -442,7 +448,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; /* Configure I2Cx: Own Address1 and ack own address1 mode */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); } @@ -453,7 +459,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { hi2c->Instance->CR2 = (I2C_CR2_ADD10); } @@ -491,7 +497,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) { /* Check the I2C handle allocation */ - if(hi2c == NULL) + if (hi2c == NULL) { return HAL_ERROR; } @@ -555,7 +561,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions + * @brief Data transfers functions * @verbatim =============================================================================== @@ -567,7 +573,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) (#) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function + The status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode : The communication is performed using Interrupts or DMA. These functions return the status of the transfer startup. @@ -617,8 +623,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) * @brief Transmits in master mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -628,7 +634,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -636,7 +642,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -644,7 +650,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; @@ -652,7 +658,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); @@ -663,12 +669,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -682,15 +688,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->XferCount--; hi2c->XferSize--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -705,9 +711,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -741,8 +747,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @brief Receives in master mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -752,7 +758,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -760,7 +766,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -776,7 +782,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); @@ -787,12 +793,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -807,15 +813,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd hi2c->XferSize--; hi2c->XferCount--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -830,9 +836,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -863,7 +869,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } /** - * @brief Transmits in slave mode an amount of data in blocking mode. + * @brief Transmits in slave mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer @@ -875,9 +881,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -900,7 +906,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -908,13 +914,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* If 10bit addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -922,26 +928,26 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Wait until DIR flag is set Transmitter mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -957,12 +963,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Normal use case for Transmitter mode */ /* A NACK is generated to confirm the end of transfer */ @@ -975,10 +981,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1015,9 +1021,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { uint32_t tickstart = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1040,7 +1046,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1048,33 +1054,33 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Wait until DIR flag is reset Receiver mode */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_TIMEOUT; } - while(hi2c->XferCount > 0U) + while (hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; /* Store Last receive data if any */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferCount--; } - if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) + if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) { return HAL_TIMEOUT; } @@ -1090,12 +1096,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1106,10 +1112,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -1137,8 +1143,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1147,9 +1153,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1166,8 +1172,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1183,7 +1189,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current @@ -1206,8 +1212,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1216,9 +1222,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1235,8 +1241,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1250,7 +1256,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1281,7 +1287,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -1321,7 +1327,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD } /** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer @@ -1330,7 +1336,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -1373,8 +1379,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa * @brief Transmit in master mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1383,9 +1389,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1402,8 +1408,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1414,7 +1420,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t xfermode = I2C_AUTOEND_MODE; } - if(hi2c->XferSize > 0U) + if (hi2c->XferSize > 0U) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; @@ -1426,7 +1432,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->hdmatx->XferHalfCpltCallback = NULL; hi2c->hdmatx->XferAbortCallback = NULL; - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); /* Send Slave Address */ @@ -1452,7 +1458,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; - + /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); @@ -1481,8 +1487,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t * @brief Receive in master mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status @@ -1491,9 +1497,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D { uint32_t xfermode = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -1510,8 +1516,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -1522,7 +1528,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D xfermode = I2C_AUTOEND_MODE; } - if(hi2c->XferSize > 0U) + if (hi2c->XferSize > 0U) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; @@ -1534,12 +1540,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->hdmarx->XferHalfCpltCallback = NULL; hi2c->hdmarx->XferAbortCallback = NULL; - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); /* Send Slave Address */ /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -1560,7 +1566,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; - + /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); @@ -1594,12 +1600,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; - } + } /* Process Locked */ __HAL_LOCK(hi2c); @@ -1624,7 +1630,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->hdmatx->XferHalfCpltCallback = NULL; hi2c->hdmatx->XferAbortCallback = NULL; - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); /* Enable Address Acknowledge */ @@ -1640,7 +1646,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; return HAL_OK; } @@ -1660,9 +1666,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1690,7 +1696,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->hdmarx->XferHalfCpltCallback = NULL; hi2c->hdmarx->XferAbortCallback = NULL; - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); /* Enable Address Acknowledge */ @@ -1719,8 +1725,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD * @brief Write an amount of data in blocking mode to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -1735,9 +1741,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1748,7 +1754,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1763,9 +1769,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress hi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1780,7 +1786,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1794,9 +1800,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress do { /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1811,15 +1817,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress hi2c->XferCount--; hi2c->XferSize--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1831,13 +1837,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - }while(hi2c->XferCount > 0U); + } + while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -1871,8 +1878,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress * @brief Read an amount of data in blocking mode from a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -1887,9 +1894,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1900,7 +1907,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1915,9 +1922,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1933,7 +1940,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); @@ -1947,7 +1954,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, do { /* Wait until RXNE flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1957,15 +1964,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->XferSize--; hi2c->XferCount--; - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -1976,13 +1983,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - }while(hi2c->XferCount > 0U); + } + while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -2015,8 +2023,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2031,14 +2039,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2058,8 +2066,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2071,9 +2079,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2088,12 +2096,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ @@ -2114,8 +2122,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2130,14 +2138,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2157,8 +2165,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2170,9 +2178,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2187,7 +2195,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2212,8 +2220,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2228,14 +2236,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2255,8 +2263,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2268,9 +2276,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2294,7 +2302,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->hdmatx->XferHalfCpltCallback = NULL; hi2c->hdmatx->XferAbortCallback = NULL; - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); /* Send Slave Address */ @@ -2328,8 +2336,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer @@ -2344,14 +2352,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2372,7 +2380,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2384,9 +2392,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2410,11 +2418,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->hdmarx->XferHalfCpltCallback = NULL; hi2c->hdmarx->XferAbortCallback = NULL; - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -2444,8 +2452,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @note This function is used with Memory devices * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status @@ -2456,9 +2464,9 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0U; - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } @@ -2472,16 +2480,16 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd do { /* Generate Start */ - hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress); + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hi2c->State = HAL_I2C_STATE_READY; @@ -2489,14 +2497,14 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_UNLOCK(hi2c); return HAL_TIMEOUT; } - } + } } /* Check if the NACKF flag has not been set */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) { - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2515,7 +2523,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd else { /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2533,8 +2541,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2542,7 +2550,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - }while(I2C_Trials < Trials); + } + while (I2C_Trials < Trials); hi2c->State = HAL_I2C_STATE_READY; @@ -2562,8 +2571,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS @@ -2577,7 +2586,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2593,7 +2602,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, hi2c->XferISR = I2C_Master_ISR_IT; /* If size > MAX_NBYTE_SIZE, use reload mode */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2606,7 +2615,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) { xferrequest = I2C_NO_STARTSTOP; } @@ -2635,8 +2644,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS @@ -2650,7 +2659,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2666,7 +2675,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, hi2c->XferISR = I2C_Master_ISR_IT; /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -2679,13 +2688,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) { xferrequest = I2C_NO_STARTSTOP; } /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest); + I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2718,9 +2727,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2730,10 +2739,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, /* Process Locked */ __HAL_LOCK(hi2c); - + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave RX state to TX state */ - if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); @@ -2753,11 +2762,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ @@ -2792,9 +2801,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -2804,15 +2813,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u /* Process Locked */ __HAL_LOCK(hi2c); - + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave TX state to RX state */ - if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); } - + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2827,11 +2836,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ @@ -2859,7 +2868,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u */ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) { - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->XferISR = I2C_Slave_ISR_IT; @@ -2887,7 +2896,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) uint32_t tmp; /* Disable Address listen mode only if a transfer is not ongoing */ - if(hi2c->State == HAL_I2C_STATE_LISTEN) + if (hi2c->State == HAL_I2C_STATE_LISTEN) { tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); @@ -2910,13 +2919,13 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) * @brief Abort a master I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if(hi2c->Mode == HAL_I2C_MODE_MASTER) + if (hi2c->Mode == HAL_I2C_MODE_MASTER) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -2935,7 +2944,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -2956,7 +2965,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ - */ + */ /** * @brief This function handles I2C event interrupt request. @@ -2971,7 +2980,7 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t itsources = READ_REG(hi2c->Instance->CR1); /* I2C events treatment -------------------------------------*/ - if(hi2c->XferISR != NULL) + if (hi2c->XferISR != NULL) { hi2c->XferISR(hi2c, itflags, itsources); } @@ -2989,7 +2998,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t itsources = READ_REG(hi2c->Instance->CR1); /* I2C Bus error interrupt occurred ------------------------------------*/ - if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; @@ -2998,7 +3007,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; @@ -3007,7 +3016,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) + if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -3016,7 +3025,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* Call the Error Callback in case of Error detected */ - if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) { I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -3089,8 +3098,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) * @brief Slave Address Match callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION - * @param AddrMatchCode: Address Match Code + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) @@ -3228,7 +3237,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) } /** -* @brief Return the I2C error code. + * @brief Return the I2C error code. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval I2C Error Code @@ -3240,7 +3249,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) /** * @} - */ + */ /** * @} @@ -3258,14 +3267,14 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint16_t devaddress = 0U; /* Process Locked */ __HAL_LOCK(hi2c); - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3278,27 +3287,27 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; hi2c->XferSize--; hi2c->XferCount--; } - else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); hi2c->XferSize--; hi2c->XferCount--; } - else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) + if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) { devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - if(hi2c->XferCount > MAX_NBYTE_SIZE) + + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); @@ -3306,7 +3315,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin else { hi2c->XferSize = hi2c->XferCount; - if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); } @@ -3319,7 +3328,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin else { /* Call TxCpltCallback() if no stop mode is set */ - if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Call I2C Master Sequential complete process */ I2C_ITMasterSequentialCplt(hi2c); @@ -3332,14 +3341,14 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } } - else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { - if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Generate a stop condition in case of no transfer option */ - if(hi2c->XferOptions == I2C_NO_OPTION_FRAME) + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; @@ -3359,7 +3368,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } - if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -3379,26 +3388,26 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { - if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ - (hi2c->State == HAL_I2C_STATE_LISTEN)) + if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ + (hi2c->State == HAL_I2C_STATE_LISTEN)) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); } - else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) + else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3426,9 +3435,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } - else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) + else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) { - if(hi2c->XferCount > 0U) + if (hi2c->XferCount > 0U) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; @@ -3436,24 +3445,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint hi2c->XferCount--; } - if((hi2c->XferCount == 0U) && \ - (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) + if ((hi2c->XferCount == 0U) && \ + (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSequentialCplt(hi2c); - } + } } - else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, ITFlags); } - else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) + else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Datas have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hi2c->XferCount > 0U) + if (hi2c->XferCount > 0U) { /* Write data to TXDR */ hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); @@ -3462,7 +3471,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } else { - if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) + if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) { /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ @@ -3472,7 +3481,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } /* Check if STOPF is set */ - if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); @@ -3492,7 +3501,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint16_t devaddress = 0U; uint32_t xfermode = 0U; @@ -3500,14 +3509,14 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Process Locked */ __HAL_LOCK(hi2c); - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - + /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ @@ -3516,18 +3525,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) + else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); - - if(hi2c->XferCount != 0U) + + if (hi2c->XferCount != 0U) { /* Recover Slave address */ devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - + /* Prepare the new XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; @@ -3545,7 +3554,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui hi2c->XferCount -= hi2c->XferSize; /* Enable DMA Request */ - if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } @@ -3561,7 +3570,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -3581,18 +3590,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { /* Process locked */ __HAL_LOCK(hi2c); - - if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) + + if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ - if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3602,17 +3611,17 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } - else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) + else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } - else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); @@ -3628,8 +3637,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin * @brief Master sends target device address followed by internal memory address for write request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration @@ -3638,12 +3647,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3654,7 +3663,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ } /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); @@ -3666,9 +3675,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3677,26 +3686,26 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ return HAL_TIMEOUT; } } - + /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TCR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } -return HAL_OK; + return HAL_OK; } /** * @brief Master sends target device address followed by internal memory address for read request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 or 10 bits address value + * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration @@ -3705,12 +3714,12 @@ return HAL_OK; */ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { - I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3721,7 +3730,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /* If Memory address size is 8Bit */ - if(MemAddSize == I2C_MEMADD_SIZE_8BIT) + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); @@ -3733,9 +3742,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ - if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; } @@ -3744,17 +3753,17 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t return HAL_TIMEOUT; } } - + /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TC flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } - + return HAL_OK; } @@ -3775,7 +3784,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) UNUSED(ITFlags); /* In case of Listen state, need to inform upper layer of address match code event */ - if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) { transferdirection = I2C_GET_DIR(hi2c); slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); @@ -3783,19 +3792,19 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); /* If 10bits addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) { slaveaddrcode = ownadd1code; hi2c->AddrEventCount++; - if(hi2c->AddrEventCount == 2U) + if (hi2c->AddrEventCount == 2U) { /* Reset Address Event counter */ hi2c->AddrEventCount = 0U; /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3897,7 +3906,7 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; - if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; @@ -3913,7 +3922,7 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) HAL_I2C_SlaveTxCpltCallback(hi2c); } - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; @@ -3949,7 +3958,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if((ITFlags & I2C_FLAG_AF) != RESET) + if ((ITFlags & I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -3962,16 +3971,16 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Flush_TXDR(hi2c); /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT); + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); /* Call the corresponding callback to inform upper layer of End of Transfer */ - if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) + if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; @@ -3997,7 +4006,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } } /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; @@ -4034,7 +4043,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); @@ -4049,26 +4058,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Flush_TXDR(hi2c); /* If a DMA is ongoing, Update handle size context */ - if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || - ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) + if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || + ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) { hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); } /* All data are not transferred, so set error code accordingly */ - if(hi2c->XferCount != 0U) + if (hi2c->XferCount != 0U) { /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } /* Store Last receive data if any */ - if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - if((hi2c->XferSize > 0U)) + if ((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; @@ -4082,19 +4091,19 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - if(hi2c->State == HAL_I2C_STATE_LISTEN) + if (hi2c->State == HAL_I2C_STATE_LISTEN) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); } } - else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME) + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; @@ -4106,7 +4115,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) HAL_I2C_ListenCpltCallback(hi2c); } /* Call the corresponding callback to inform upper layer of End of Transfer */ - else if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; @@ -4144,12 +4153,12 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferISR = NULL; /* Store Last receive data if any */ - if(((ITFlags & I2C_FLAG_RXNE) != RESET)) + if (((ITFlags & I2C_FLAG_RXNE) != RESET)) { /* Read data from RXDR */ (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - if((hi2c->XferSize > 0U)) + if ((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; @@ -4189,9 +4198,9 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->ErrorCode |= ErrorCode; /* Disable Interrupts */ - if((hi2c->State == HAL_I2C_STATE_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + if ((hi2c->State == HAL_I2C_STATE_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); @@ -4205,10 +4214,10 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - + /* If state is an abort treatment on goind, don't change state */ /* This change will be do later */ - if(hi2c->State != HAL_I2C_STATE_ABORT) + if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; @@ -4218,7 +4227,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } /* Abort DMA TX transfer if any */ - if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -4230,14 +4239,14 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } /* Abort DMA RX transfer if any */ - else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -4249,16 +4258,16 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) __HAL_UNLOCK(hi2c); /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) { /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } - else if(hi2c->State == HAL_I2C_STATE_ABORT) + else if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4284,13 +4293,13 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) { - hi2c->Instance->TXDR = 0x00U; + hi2c->Instance->TXDR = 0x00U; } /* Flush TX register if not empty */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); } @@ -4303,13 +4312,13 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -4321,7 +4330,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) hi2c->pBuffPtr += hi2c->XferSize; /* Set the XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; } @@ -4330,7 +4339,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) hi2c->XferSize = hi2c->XferCount; } - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); /* Enable TC interrupts */ @@ -4360,13 +4369,13 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* If last transfer, enable STOP interrupt */ - if(hi2c->XferCount == 0U) + if (hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); @@ -4378,7 +4387,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) hi2c->pBuffPtr += hi2c->XferSize; /* Set the XferSize to transfer */ - if(hi2c->XferCount > MAX_NBYTE_SIZE) + if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; } @@ -4387,7 +4396,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) hi2c->XferSize = hi2c->XferCount; } - /* Enable the DMA channel */ + /* Enable the DMA stream */ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); /* Enable TC interrupts */ @@ -4417,7 +4426,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -4429,12 +4438,12 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA I2C communication abort callback * (To be called at end of DMA Abort procedure). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -4444,10 +4453,10 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) hi2c->hdmarx->XferAbortCallback = NULL; /* Check if come from abort from user */ - if(hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; - + /* Call the corresponding callback to inform upper layer of End of Transfer */ HAL_I2C_AbortCpltCallback(hi2c); } @@ -4470,14 +4479,14 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4499,21 +4508,21 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin */ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4536,19 +4545,19 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4570,38 +4579,49 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { /* Check if a NACK is detected */ - if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check if a STOPF is detected */ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) { - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + } + else + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State= HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } /* Check for the Timeout */ - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -4622,18 +4642,18 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, */ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { /* Wait until STOP Flag is reset */ /* AutoEnd should be initiate after AF */ - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4656,7 +4676,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_AF; - hi2c->State= HAL_I2C_STATE_READY; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ @@ -4688,25 +4708,14 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0U; - /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); - /* Get the CR2 register value */ - tmpreg = hi2c->Instance->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - /* update CR2 register */ - hi2c->Instance->CR2 = tmpreg; + MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** @@ -4720,28 +4729,28 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr { uint32_t tmpisr = 0U; - if((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - - if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -4749,31 +4758,31 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr } else { - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK, and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } - if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } } - + /* Enable interrupts only at the end */ /* to avoid the risk of I2C interrupt handle execution before */ /* all interrupts requested done */ @@ -4793,49 +4802,49 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter { uint32_t tmpisr = 0U; - if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } - if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) + if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } - if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Disable ADDR, NACK and STOP interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - - if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c index 96d7e57c3d..084de19c8e 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c @@ -3,7 +3,7 @@ * @file stm32f7xx_hal_i2c_ex.c * @author MCD Application Team * @brief I2C Extended HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: * + Extended features functions * @@ -91,7 +91,7 @@ ##### Extended features functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Configure Noise Filters + (+) Configure Noise Filters (+) Configure Fast Mode Plus @endverbatim @@ -111,7 +111,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -157,7 +157,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - if(hi2c->State == HAL_I2C_STATE_READY) + if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -194,7 +194,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ } } -#if defined(SYSCFG_PMC_I2C1_FMP) +#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP) /** * @brief Enable the I2C fast mode plus driving capability. * @param ConfigFastModePlus Selects the pin. @@ -252,7 +252,8 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /* Disable fast mode plus driving capability for selected pin */ CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); } -#endif /* SYSCFG_PMC_I2C1_FMP */ + +#endif /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2s.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2s.c index 6531e6280a..43f4c1c05a 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2s.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2s.c @@ -207,7 +207,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, /** * @brief Initializes the I2S according to the specified parameters * in the I2S_InitTypeDef and create the associated handle. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -340,7 +340,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) /** * @brief DeInitializes the I2S peripheral - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -371,7 +371,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief I2S MSP Init - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -387,7 +387,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief I2S MSP DeInit - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -449,15 +449,15 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** * @brief Transmit an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -554,15 +554,15 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin /** * @brief Receive an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate @@ -657,10 +657,10 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint /** * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -720,10 +720,10 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -784,10 +784,10 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u /** * @brief Transmit an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Transmit data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Transmit data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -862,10 +862,10 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Receive an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -947,7 +947,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /** * @brief Pauses the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -988,7 +988,7 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) /** * @brief Resumes the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1023,7 +1023,7 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) /** * @brief Stops the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1064,7 +1064,7 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) /** * @brief This function handles I2S interrupt request. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1131,11 +1131,11 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) */ /** * @brief This function handles I2S Communication Timeout. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param Timeout: Duration of the timeout + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, @@ -1200,7 +1200,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, */ /** * @brief Tx Transfer Half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1216,7 +1216,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, /** * @brief Tx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1232,7 +1232,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, /** * @brief Rx Transfer half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1248,7 +1248,7 @@ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief Rx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1264,7 +1264,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief I2S error callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1299,7 +1299,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) /** * @brief Return the I2S state - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL state */ @@ -1310,7 +1310,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) /** * @brief Return the I2S error code - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval I2S Error Code */ @@ -1328,7 +1328,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) /** * @brief Get I2S Input Clock based on I2S source clock selection - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module. * @retval I2S Clock Input */ @@ -1387,7 +1387,7 @@ static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s) */ /** * @brief DMA I2S transmit process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1419,7 +1419,7 @@ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S transmit process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1432,7 +1432,7 @@ static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1463,7 +1463,7 @@ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1476,7 +1476,7 @@ static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S communication error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1498,7 +1498,7 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1520,7 +1520,7 @@ static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) /** * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: I2S handle + * @param hi2s I2S handle * @retval None */ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c index be657a3e15..5436ee296c 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c @@ -227,7 +227,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); /** * @brief Initialize the IRDA mode according to the specified * parameters in the IRDA_InitTypeDef and initialize the associated handle. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -280,7 +280,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) /** * @brief DeInitialize the IRDA peripheral. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -314,7 +314,7 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) /** * @brief Initialize the IRDA MSP. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -330,7 +330,7 @@ __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) /** * @brief DeInitialize the IRDA MSP. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1528,7 +1528,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) /** * @brief Rx Half Transfer complete callback. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1883,7 +1883,7 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1913,7 +1913,7 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process half complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_jpeg.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_jpeg.c index 7a10ed78e4..e1cc5e1a07 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_jpeg.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_jpeg.c @@ -467,7 +467,7 @@ static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) ; /** * @brief Initializes the JPEG according to the specified * parameters in the JPEG_InitTypeDef and creates the associated handle. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval HAL status */ @@ -552,7 +552,7 @@ HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg) /** * @brief DeInitializes the JPEG peripheral. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval HAL status */ @@ -592,7 +592,7 @@ HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg) /** * @brief Initializes the JPEG MSP. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -608,7 +608,7 @@ __weak void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg) /** * @brief DeInitializes JPEG MSP. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -646,9 +646,9 @@ __weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg) /** * @brief Set the JPEG encoding configuration. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pConf: pointer to a JPEG_ConfTypeDef structure that contains + * @param pConf pointer to a JPEG_ConfTypeDef structure that contains * the encoding configuration * @retval HAL status */ @@ -827,9 +827,9 @@ HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTy /** * @brief Extract the image configuration from the JPEG header during the decoding - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pInfo: pointer to a JPEG_ConfTypeDef structure that contains + * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains * The JPEG decoded header informations * @retval HAL status */ @@ -896,7 +896,7 @@ HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef * /** * @brief Enable JPEG Header parsing for decoding - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for the JPEG. * @retval HAL status */ @@ -932,7 +932,7 @@ HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg) /** * @brief Disable JPEG Header parsing for decoding - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for the JPEG. * @retval HAL status */ @@ -968,15 +968,15 @@ HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg) /** * @brief Modify the default Quantization tables used for JPEG encoding. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param QTable0 : pointer to uint8_t , define the user quantification table for color component 1. + * @param QTable0 pointer to uint8_t , define the user quantification table for color component 1. * If NULL assume no need to update the table and no error return - * @param QTable1 : pointer to uint8_t , define the user quantification table for color component 2. + * @param QTable1 pointer to uint8_t , define the user quantification table for color component 2. * If NULL assume no need to update the table and no error return. - * @param QTable2 : pointer to uint8_t , define the user quantification table for color component 3, + * @param QTable2 pointer to uint8_t , define the user quantification table for color component 3, * If NULL assume no need to update the table and no error return. - * @param QTable3 : pointer to uint8_t , define the user quantification table for color component 4. + * @param QTable3 pointer to uint8_t , define the user quantification table for color component 4. * If NULL assume no need to update the table and no error return. * * @retval HAL status @@ -1048,13 +1048,13 @@ HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_ /** * @brief Starts JPEG encoding with polling processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataInMCU: Pointer to the Input buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOut: Pointer to the jpeg output data buffer - * @param OutDataLength: size in bytes of the Output buffer - * @param Timeout: Specify Timeout value + * @param pDataInMCU Pointer to the Input buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOut Pointer to the jpeg output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout) @@ -1154,13 +1154,13 @@ HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMC /** * @brief Starts JPEG decoding with polling processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataIn: Pointer to the input data buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOutMCU: Pointer to the Output data buffer - * @param OutDataLength: size in bytes of the Output buffer - * @param Timeout: Specify Timeout value + * @param pDataIn Pointer to the input data buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOutMCU Pointer to the Output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout) @@ -1252,12 +1252,12 @@ HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn , /** * @brief Starts JPEG encoding with interrupt processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataInMCU: Pointer to the Input buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOut: Pointer to the jpeg output data buffer - * @param OutDataLength: size in bytes of the Output buffer + * @param pDataInMCU Pointer to the Input buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOut Pointer to the jpeg output data buffer + * @param OutDataLength size in bytes of the Output buffer * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength) @@ -1326,12 +1326,12 @@ HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataI /** * @brief Starts JPEG decoding with interrupt processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataIn: Pointer to the input data buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOutMCU: Pointer to the Output data buffer - * @param OutDataLength: size in bytes of the Output buffer + * @param pDataIn Pointer to the input data buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOutMCU Pointer to the Output data buffer + * @param OutDataLength size in bytes of the Output buffer * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength) @@ -1390,12 +1390,12 @@ HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataI /** * @brief Starts JPEG encoding with DMA processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataInMCU: Pointer to the Input buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOut: Pointer to the jpeg output data buffer - * @param OutDataLength: size in bytes of the Output buffer + * @param pDataInMCU Pointer to the Input buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOut Pointer to the jpeg output data buffer + * @param OutDataLength size in bytes of the Output buffer * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength) @@ -1463,12 +1463,12 @@ HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pData /** * @brief Starts JPEG decoding with DMA processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataIn: Pointer to the input data buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOutMCU: Pointer to the Output data buffer - * @param OutDataLength: size in bytes of the Output buffer + * @param pDataIn Pointer to the input data buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOutMCU Pointer to the Output data buffer + * @param OutDataLength size in bytes of the Output buffer * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength) @@ -1526,9 +1526,9 @@ HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pData /** * @brief Pause the JPEG Input/Output processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param XferSelection: This parameter can be one of the following values : + * @param XferSelection This parameter can be one of the following values : * JPEG_PAUSE_RESUME_INPUT : Pause Input processing * JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing @@ -1578,9 +1578,9 @@ HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelect /** * @brief Resume the JPEG Input/Output processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param XferSelection: This parameter can be one of the following values : + * @param XferSelection This parameter can be one of the following values : * JPEG_PAUSE_RESUME_INPUT : Resume Input processing * JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing @@ -1659,10 +1659,10 @@ HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelec /** * @brief Config Encoding/Decoding Input Buffer. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module. - * @param pNewInputBuffer: Pointer to the new input data buffer - * @param InDataLength: Size in bytes of the new Input data buffer + * @param pNewInputBuffer Pointer to the new input data buffer + * @param InDataLength Size in bytes of the new Input data buffer * @retval HAL status */ void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength) @@ -1673,10 +1673,10 @@ void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuf /** * @brief Config Encoding/Decoding Output Buffer. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module. - * @param pNewOutputBuffer: Pointer to the new output data buffer - * @param OutDataLength: Size in bytes of the new Output data buffer + * @param pNewOutputBuffer Pointer to the new output data buffer + * @param OutDataLength Size in bytes of the new Output data buffer * @retval HAL status */ void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength) @@ -1687,7 +1687,7 @@ void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputB /** * @brief Aborts the JPEG Encoding/Decoding. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval HAL status */ @@ -1788,9 +1788,9 @@ HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg) /** * @brief Decoding JPEG Info ready callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pInfo: pointer to a JPEG_ConfTypeDef structure that contains + * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains * The JPEG decoded header informations * @retval None */ @@ -1807,7 +1807,7 @@ __weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDe /** * @brief Encoding complete callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -1823,7 +1823,7 @@ __weak void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg) /** * @brief Decoding complete callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -1839,7 +1839,7 @@ __weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg) /** * @brief JPEG error callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -1855,9 +1855,9 @@ __weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg) /** * @brief Get New Data chunk callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param NbDecodedData: Number of consummed data in the previous chunk in bytes + * @param NbDecodedData Number of consummed data in the previous chunk in bytes * @retval None */ __weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData) @@ -1873,10 +1873,10 @@ __weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg) /** * @brief Decoded/Encoded Data ready callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataOut: pointer to the output data buffer - * @param OutDataLength: number in bytes of data available in the specified output buffer + * @param pDataOut pointer to the output data buffer + * @param OutDataLength number in bytes of data available in the specified output buffer * @retval None */ __weak void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength) @@ -1912,7 +1912,7 @@ __weak void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDat /** * @brief This function handles JPEG interrupt request. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -1962,7 +1962,7 @@ void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg) /** * @brief Returns the JPEG state. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval JPEG state */ @@ -1973,7 +1973,7 @@ HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg) /** * @brief Return the JPEG error code -* @param hjpeg : pointer to a JPEG_HandleTypeDef structure that contains +* @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for the specified JPEG. * @retval JPEG Error Code */ @@ -1997,10 +1997,10 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg) /** * @brief Generates Huffman sizes/Codes Table from Bits/vals Table - * @param Bits: pointer to bits table - * @param Huffsize: pointer to sizes table - * @param Huffcode: pointer to codes table - * @param LastK: pointer to last Coeff (table dimmension) + * @param Bits pointer to bits table + * @param Huffsize pointer to sizes table + * @param Huffcode pointer to codes table + * @param LastK pointer to last Coeff (table dimmension) * @retval HAL status */ static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK) @@ -2051,8 +2051,8 @@ static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize /** * @brief Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table * that can programmed to the JPEG encoder registers - * @param AC_BitsValsTable: pointer to AC huffman bits/vals table - * @param AC_SizeCodesTable: pointer to AC huffman Sizes/Codes table + * @param AC_BitsValsTable pointer to AC huffman bits/vals table + * @param AC_SizeCodesTable pointer to AC huffman Sizes/Codes table * @retval HAL status */ static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable) @@ -2109,8 +2109,8 @@ static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeD /** * @brief Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table * that can programmed to the JPEG encoder registers - * @param DC_BitsValsTable: pointer to DC huffman bits/vals table - * @param DC_SizeCodesTable: pointer to DC huffman Sizes/Codes table + * @param DC_BitsValsTable pointer to DC huffman bits/vals table + * @param DC_SizeCodesTable pointer to DC huffman Sizes/Codes table * @retval HAL status */ static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable) @@ -2151,10 +2151,10 @@ static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeD /** * @brief Set the JPEG register with an DC huffman table at the given DC table address - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param HuffTableDC: pointer to DC huffman table - * @param DCTableAddress: Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1. + * @param HuffTableDC pointer to DC huffman table + * @param DCTableAddress Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1. * @retval HAL status */ static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, uint32_t *DCTableAddress) @@ -2208,10 +2208,10 @@ static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCH /** * @brief Set the JPEG register with an AC huffman table at the given AC table address - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param HuffTableAC: pointer to AC huffman table - * @param ACTableAddress: Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1. + * @param HuffTableAC pointer to AC huffman table + * @param ACTableAddress Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1. * @retval HAL status */ static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, uint32_t *ACTableAddress) @@ -2280,12 +2280,12 @@ static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACH /** * @brief Configure the JPEG encoder register huffman tables to used during * the encdoing operation - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param HuffTableAC0: AC0 huffman table - * @param HuffTableDC0: DC0 huffman table - * @param HuffTableAC1: AC1 huffman table - * @param HuffTableDC1: DC1 huffman table + * @param HuffTableAC0 AC0 huffman table + * @param HuffTableDC0 DC0 huffman table + * @param HuffTableAC1 AC1 huffman table + * @param HuffTableDC1 DC1 huffman table * @retval None */ static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1) @@ -2336,12 +2336,12 @@ static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_AC /** * @brief Configure the JPEG register huffman tables to be included in the JPEG * file header (used for encoding only) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param HuffTableAC0: AC0 huffman table - * @param HuffTableDC0: DC0 huffman table - * @param HuffTableAC1: AC1 huffman table - * @param HuffTableDC1: DC1 huffman table + * @param HuffTableAC0 AC0 huffman table + * @param HuffTableDC0 DC0 huffman table + * @param HuffTableAC1 AC1 huffman table + * @param HuffTableDC1 DC1 huffman table * @retval None */ static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1) @@ -2532,10 +2532,10 @@ static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableType /** * @brief Configure the JPEG registers with a given quantization table - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param QTable: pointer to an array of 64 bytes giving the quantization table - * @param QTableAddress: destination quantization address in the JPEG peripheral + * @param QTable pointer to an array of 64 bytes giving the quantization table + * @param QTableAddress destination quantization address in the JPEG peripheral * it could be QMEM0, QMEM1, QMEM2 or QMEM3 * @retval None */ @@ -2601,7 +2601,7 @@ static HAL_StatusTypeDef JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, u /** * @brief Configure the JPEG registers for YCbCr color space - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -2662,7 +2662,7 @@ static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg) /** * @brief Configure the JPEG registers for GrayScale color space - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -2682,7 +2682,7 @@ static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg) /** * @brief Configure the JPEG registers for CMYK color space - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -2741,7 +2741,7 @@ static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg) /** * @brief Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -2795,7 +2795,7 @@ static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg) /** * @brief JPEG encoding/decoding process in case of Polling or Interrupt - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING */ @@ -2912,9 +2912,9 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) * @brief Store some output data from the JPEG peripheral to the output buffer. * This function is used when the JPEG peripheral has new data to output * in case of Polling or Interrupt process - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param nbOutputWords: Number of output words (of 32 bits) ready from the JPEG peripheral + * @param nbOutputWords Number of output words (of 32 bits) ready from the JPEG peripheral * @retval None */ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords) @@ -2982,9 +2982,9 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor * @brief Read some input Data from the input buffer. * This function is used when the JPEG peripheral needs new data * in case of Polling or Interrupt process - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param nbRequestWords: Number of input words (of 32 bits) that the JPE peripheral request + * @param nbRequestWords Number of input words (of 32 bits) that the JPE peripheral request * @retval None */ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords) @@ -3051,7 +3051,7 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord /** * @brief Start the JPEG DMA process (encoding/decoding) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING */ @@ -3099,7 +3099,7 @@ static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg) /** * @brief Continue the current JPEG DMA process (encoding/decoding) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING */ @@ -3163,7 +3163,7 @@ static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg) /** * @brief Finalize the current JPEG DMA process (encoding/decoding) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval JPEG_PROCESS_DONE */ @@ -3217,7 +3217,7 @@ static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg) /** * @brief Poll residual output data when DMA process (encoding/decoding) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None. */ @@ -3275,7 +3275,7 @@ static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg) /** * @brief DMA input transfer complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure. + * @param hdma pointer to a DMA_HandleTypeDef structure. * @retval None */ static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma) @@ -3320,7 +3320,7 @@ static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma) /** * @brief DMA output transfer complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure. + * @param hdma pointer to a DMA_HandleTypeDef structure. * @retval None */ static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma) @@ -3355,7 +3355,7 @@ static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma) /** * @brief DMA Transfer error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure. + * @param hdma pointer to a DMA_HandleTypeDef structure. * @retval None */ static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma) @@ -3382,7 +3382,7 @@ static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma) /** * @brief DMA output Abort callback - * @param hdma: pointer to a DMA_HandleTypeDef structure. + * @param hdma pointer to a DMA_HandleTypeDef structure. * @retval None */ static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) @@ -3397,7 +3397,7 @@ static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Calculate the decoded image quality (from 1 to 100) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval JPEG image quality from 1 to 100. */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c index 54be43c07f..2af11b5fbf 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c @@ -87,6 +87,53 @@ (#) Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral. + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback. + @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + These functions allow to register/unregister following callbacks: + (+) MspInitCallback : LPTIM Msp Init Callback. + (+) MspDeInitCallback : LPTIM Msp DeInit Callback. + (+) CompareMatchCallback : LPTIM Compare Match Init Callback. + (+) AutoReloadMatchCallback : LPTIM Auto Reload Match Callback. + (+) TriggerCallback : LPTIM Trigger Callback. + (+) CompareWriteCallback : LPTIM Compare Write Callback. + (+) AutoReloadWriteCallback : LPTIM Auto Reload Write Callback. + (+) DirectionUpCallback : LPTIM Direction Up Callback. + (+) DirectionDownCallback : LPTIM Direction Down Callback. + + By default, after the @ref HAL_LPTIM_Init and when the state is HAL_LPTIM_STATE_RESET + all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_LPTIM_CompareMatchCallback(), @ref HAL_LPTIM_AutoReloadMatchCallback(). + + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit only when these + callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, + the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit keep and use the user MspInit/MspDeInit + callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit. + In that case first register the MspInit/MspDeInit user callbacks using + @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + + When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim ****************************************************************************** * @attention @@ -220,7 +267,7 @@ /** * @brief Initializes the LPTIM according to the specified parameters in the * LPTIM_InitTypeDef and creates the associated handle. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) @@ -252,15 +299,33 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); - + if(hlptim->State == HAL_LPTIM_STATE_RESET) { /* Allocate lock resource and initialize it */ hlptim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + /* Reset the LPTIM callback to the legacy weak callbacks */ + hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; + hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; + hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; + hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; + hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; + hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; + hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; + + if(hlptim->MspInitCallback == NULL) + { + hlptim->MspInitCallback = HAL_LPTIM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + hlptim->MspInitCallback(hlptim); +#else /* Init the low level hardware */ HAL_LPTIM_MspInit(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } - /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; @@ -313,7 +378,7 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /** * @brief DeInitializes the LPTIM peripheral. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) @@ -329,10 +394,19 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) /* Disable the LPTIM Peripheral Clock */ __HAL_LPTIM_DISABLE(hlptim); - + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + if(hlptim->MspDeInitCallback == NULL) + { + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; + } + /* DeInit the low level hardware */ + hlptim->MspDeInitCallback(hlptim); +#else /* DeInit the low level hardware: CLOCK, NVIC.*/ HAL_LPTIM_MspDeInit(hlptim); - +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_RESET; @@ -345,7 +419,7 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) /** * @brief Initializes the LPTIM MSP. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) @@ -360,7 +434,7 @@ __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) /** * @brief DeInitializes LPTIM MSP. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) @@ -405,10 +479,10 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the LPTIM PWM generation. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -446,7 +520,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri /** * @brief Stops the LPTIM PWM generation. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) @@ -469,10 +543,10 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the LPTIM PWM generation in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF * @retval HAL status */ @@ -529,7 +603,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P /** * @brief Stops the LPTIM PWM generation in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -571,10 +645,10 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the LPTIM One pulse generation. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -612,7 +686,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /** * @brief Stops the LPTIM One pulse generation. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) @@ -635,10 +709,10 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the LPTIM One pulse generation in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -695,7 +769,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /** * @brief Stops the LPTIM One pulse generation in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -737,10 +811,10 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the LPTIM in Set once mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -778,7 +852,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /** * @brief Stops the LPTIM Set once mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) @@ -801,10 +875,10 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the LPTIM Set once mode in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse : Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -861,7 +935,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /** * @brief Stops the LPTIM Set once mode in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -903,8 +977,8 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the Encoder interface. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -955,7 +1029,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /** * @brief Stops the Encoder interface. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) @@ -981,8 +1055,8 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the Encoder interface in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1040,7 +1114,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /** * @brief Stops the Encoder interface in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -1074,10 +1148,10 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Starts the Timeout function. The first trigger event will start the * timer, any successive trigger event will reset the counter and * the timer restarts. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Timeout : Specifies the TimeOut value to rest the counter. + * @param Timeout Specifies the TimeOut value to rest the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1115,7 +1189,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /** * @brief Stops the Timeout function. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) @@ -1143,10 +1217,10 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Starts the Timeout function in interrupt mode. The first trigger * event will start the timer, any successive trigger event will reset * the counter and the timer restarts. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Timeout : Specifies the TimeOut value to rest the counter. + * @param Timeout Specifies the TimeOut value to rest the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1193,7 +1267,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /** * @brief Stops the Timeout function in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -1228,8 +1302,8 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the Counter mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1269,7 +1343,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /** * @brief Stops the Counter mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) @@ -1292,8 +1366,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) /** * @brief Starts the Counter mode in interrupt mode. - * @param hlptim : LPTIM handle - * @param Period : Specifies the Autoreload value. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1345,7 +1419,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /** * @brief Stops the Counter mode in interrupt mode. - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -1399,7 +1473,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /** * @brief This function returns the current counter value. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval Counter value. */ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) @@ -1412,7 +1486,7 @@ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) /** * @brief This function return the current Autoreload (Period) value. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval Autoreload value. */ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) @@ -1425,7 +1499,7 @@ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) /** * @brief This function return the current Compare (Pulse) value. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval Compare value. */ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) @@ -1457,7 +1531,7 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) /** * @brief This function handles LPTIM interrupt request. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval None */ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) @@ -1470,7 +1544,11 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Clear Compare match flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM); /* Compare match Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareMatchCallback(hlptim); +#else HAL_LPTIM_CompareMatchCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } @@ -1482,7 +1560,11 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Clear Autoreload match flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM); /* Autoreload match Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->AutoReloadMatchCallback(hlptim); +#else HAL_LPTIM_AutoReloadMatchCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } @@ -1494,7 +1576,11 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Clear Trigger detected flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG); /* Trigger detected callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->TriggerCallback(hlptim); +#else HAL_LPTIM_TriggerCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } @@ -1506,7 +1592,11 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Clear Compare write flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); /* Compare write Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareWriteCallback(hlptim); +#else HAL_LPTIM_CompareWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } @@ -1518,7 +1608,11 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Clear Autoreload write flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); /* Autoreload write Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->AutoReloadWriteCallback(hlptim); +#else HAL_LPTIM_AutoReloadWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } @@ -1530,7 +1624,11 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Clear Direction counter changed from Down to Up flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP); /* Direction counter changed from Down to Up Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->DirectionUpCallback(hlptim); +#else HAL_LPTIM_DirectionUpCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } @@ -1542,7 +1640,11 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Clear Direction counter changed from Up to Down flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN); /* Direction counter changed from Up to Down Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->DirectionDownCallback(hlptim); +#else HAL_LPTIM_DirectionDownCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } @@ -1551,7 +1653,7 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /** * @brief Compare match callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) @@ -1566,7 +1668,7 @@ __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Autoreload match callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) @@ -1581,7 +1683,7 @@ __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Trigger detected callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) @@ -1596,7 +1698,7 @@ __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Compare write callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) @@ -1611,7 +1713,7 @@ __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Autoreload write callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) @@ -1626,7 +1728,7 @@ __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Direction counter changed from Down to Up callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) @@ -1641,7 +1743,7 @@ __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Direction counter changed from Up to Down callback in non blocking mode - * @param hlptim : LPTIM handle + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) @@ -1654,6 +1756,212 @@ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) */ } +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register user LPTIM callback to be used instead of the weak predefined callback + * @param hlptim lptim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_LPTIM_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID MspDeInit Callback ID + * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare Match Callback ID + * @arg @ref HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID Auto Reload Match Callback ID + * @arg @ref HAL_LPTIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare Write Callback ID + * @arg @ref HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID Auto Reload Write Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Direction UP Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Direction Down Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hlptim); + + if(hlptim->State == HAL_LPTIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = pCallback; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = pCallback; + break; + + case HAL_LPTIM_COMPARE_MATCH_CB_ID : + hlptim->CompareMatchCallback = pCallback; + break; + + case HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID : + hlptim->AutoReloadMatchCallback = pCallback; + break; + + case HAL_LPTIM_TRIGGER_CB_ID : + hlptim->TriggerCallback = pCallback; + break; + + case HAL_LPTIM_COMPARE_WRITE_CB_ID : + hlptim->CompareWriteCallback = pCallback; + break; + + case HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID : + hlptim->AutoReloadWriteCallback = pCallback; + break; + + case HAL_LPTIM_DIRECTION_UP_CB_ID : + hlptim->DirectionUpCallback = pCallback; + break; + + case HAL_LPTIM_DIRECTION_DOWN_CB_ID : + hlptim->DirectionDownCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(hlptim->State == HAL_LPTIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = pCallback; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hlptim); + + return status; +} + +/** + * @brief UnRegister user LPTIM callback + * LPTIM callback is redirected to the weak predefined callback + * @param hlptim lptim handle + * @param CallbackID ID of the callback to be unregistered ++ * This parameter can be one of the following values: ++ * @arg @ref HAL_LPTIM_MSPINIT_CB_ID MspInit Callback ID ++ * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID MspDeInit Callback ID ++ * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare Match Callback ID ++ * @arg @ref HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID Auto Reload Match Callback ID ++ * @arg @ref HAL_LPTIM_TRIGGER_CB_ID Trigger Callback ID ++ * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare Write Callback ID ++ * @arg @ref HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID Auto Reload Write Callback ID ++ * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Direction UP Callback ID ++ * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Direction Down Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hlptim); + + if(hlptim->State == HAL_LPTIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak MspDeInit Callback */ + break; + + case HAL_LPTIM_COMPARE_MATCH_CB_ID : + hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare Match Callback */ + break; + + case HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID : + hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto Reload Match Callback */ + break; + + case HAL_LPTIM_TRIGGER_CB_ID : + hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak Trigger Callback */ + break; + + case HAL_LPTIM_COMPARE_WRITE_CB_ID : + hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare Write Callback */ + break; + + case HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID : + hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto Reload Write Callback */ + break; + + case HAL_LPTIM_DIRECTION_UP_CB_ID : + hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Direction Up Callback */ + break; + + case HAL_LPTIM_DIRECTION_DOWN_CB_ID : + hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Direction Down Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(hlptim->State == HAL_LPTIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak MspDeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hlptim); + + return status; +} +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + /** * @} */ @@ -1674,7 +1982,7 @@ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) /** * @brief Returns the LPTIM state. - * @param hlptim: LPTIM handle + * @param hlptim LPTIM handle * @retval HAL state */ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c index 464c133279..e6236d3c62 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c @@ -152,7 +152,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay /** * @brief Initializes the LTDC according to the specified * parameters in the LTDC_InitTypeDef and create the associated handle. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval HAL status */ @@ -244,7 +244,7 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) /** * @brief Deinitializes the LTDC peripheral registers to their default reset * values. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval None */ @@ -268,7 +268,7 @@ HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) /** * @brief Initializes the LTDC MSP. - * @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval None */ @@ -284,7 +284,7 @@ __weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) /** * @brief DeInitializes the LTDC MSP. - * @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval None */ @@ -317,7 +317,7 @@ __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) */ /** * @brief Handles LTDC interrupt request. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval HAL status */ @@ -417,7 +417,7 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) /** * @brief Error LTDC callback. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval None */ @@ -433,7 +433,7 @@ __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) /** * @brief Line Event callback. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval None */ @@ -449,7 +449,7 @@ __weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) /** * @brief Reload Event callback. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval None */ @@ -494,11 +494,11 @@ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) /** * @brief Configure the LTDC Layer according to the specified * parameters in the LTDC_InitTypeDef and create the associated handle. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains * the configuration information for the Layer. - * @param LayerIdx: LTDC Layer index. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -544,10 +544,10 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgT /** * @brief Configure the color keying. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param RGBValue: the color key value - * @param LayerIdx: LTDC Layer index. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -581,11 +581,11 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t /** * @brief Load the color lookup table. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param pCLUT: pointer to the color lookup table address. - * @param CLUTSize: the color lookup table size. - * @param LayerIdx: LTDC Layer index. + * @param pCLUT pointer to the color lookup table address. + * @param CLUTSize the color lookup table size. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -633,9 +633,9 @@ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT /** * @brief Enable the color keying. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -668,9 +668,9 @@ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t /** * @brief Disable the color keying. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -703,9 +703,9 @@ HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_ /** * @brief Enable the color lookup table. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -739,9 +739,9 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerI /** * @brief Disable the color lookup table. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -775,7 +775,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t Layer /** * @brief Enables Dither. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval HAL status */ @@ -802,7 +802,7 @@ HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) /** * @brief Disables Dither. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval HAL status */ @@ -829,11 +829,11 @@ HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) /** * @brief Set the LTDC window size. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param XSize: LTDC Pixel per line - * @param YSize: LTDC Line number - * @param LayerIdx: LTDC Layer index. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -891,11 +891,11 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSi /** * @brief Set the LTDC window position. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param X0: LTDC window X offset - * @param Y0: LTDC window Y offset - * @param LayerIdx: LTDC Layer index. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -945,10 +945,10 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t /** * @brief Reconfigure the pixel format. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param Pixelformat: new pixel format value. - * @param LayerIdx: LTDC Layer index. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1. * @retval HAL status @@ -990,10 +990,10 @@ HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pi /** * @brief Reconfigure the layer alpha value. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param Alpha: new alpha value. - * @param LayerIdx: LTDC Layer index. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -1034,10 +1034,10 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, u } /** * @brief Reconfigure the frame buffer Address. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param Address: new address value. - * @param LayerIdx: LTDC Layer index. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1. * @retval HAL status @@ -1083,10 +1083,10 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). * Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'. - * @param LayerIdx: LTDC layer index concerned by the modification of line pitch. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) @@ -1152,9 +1152,9 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitc /** * @brief Define the position of the line interrupt. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param Line: Line Interrupt Position. + * @param Line Line Interrupt Position. * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line) @@ -1185,9 +1185,9 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t /** * @brief LTDC configuration reload. - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param ReloadType: This parameter can be one of the following values : + * @param ReloadType This parameter can be one of the following values : * LTDC_RELOAD_IMMEDIATE : Immediate Reload * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking * @retval HAL status @@ -1221,11 +1221,11 @@ HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadTyp * @brief Configure the LTDC Layer according to the specified without reloading * parameters in the LTDC_InitTypeDef and create the associated handle. * Variant of the function HAL_LTDC_ConfigLayer without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains * the configuration information for the Layer. - * @param LayerIdx: LTDC Layer index. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -1271,11 +1271,11 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_ /** * @brief Set the LTDC window size without reloading. * Variant of the function HAL_LTDC_SetWindowSize without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param XSize: LTDC Pixel per line - * @param YSize: LTDC Line number - * @param LayerIdx: LTDC Layer index. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -1333,11 +1333,11 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin /** * @brief Set the LTDC window position without reloading. * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param X0: LTDC window X offset - * @param Y0: LTDC window Y offset - * @param LayerIdx: LTDC Layer index. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -1387,10 +1387,10 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, /** * @brief Reconfigure the pixel format without reloading. * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDfef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains * the configuration information for the LTDC. - * @param Pixelformat: new pixel format value. - * @param LayerIdx: LTDC Layer index. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1. * @retval HAL status @@ -1432,10 +1432,10 @@ HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, ui /** * @brief Reconfigure the layer alpha value without reloading. * Variant of the function HAL_LTDC_SetAlpha without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param Alpha: new alpha value. - * @param LayerIdx: LTDC Layer index. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -1477,10 +1477,10 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t /** * @brief Reconfigure the frame buffer Address without reloading. * Variant of the function HAL_LTDC_SetAddress without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param Address: new address value. - * @param LayerIdx: LTDC Layer index. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1. * @retval HAL status @@ -1526,10 +1526,10 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32 * Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). * Variant of the function HAL_LTDC_SetPitch without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'. - * @param LayerIdx: LTDC layer index concerned by the modification of line pitch. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) @@ -1593,10 +1593,10 @@ HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t /** * @brief Configure the color keying without reloading. * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param RGBValue: the color key value - * @param LayerIdx: LTDC Layer index. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -1630,9 +1630,9 @@ HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, /** * @brief Enable the color keying without reloading. * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -1665,9 +1665,9 @@ HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, /** * @brief Disable the color keying without reloading. * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -1700,9 +1700,9 @@ HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc /** * @brief Enable the color lookup table without reloading. * Variant of the function HAL_LTDC_EnableCLUT without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -1736,9 +1736,9 @@ HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32 /** * @brief Disable the color lookup table without reloading. * Variant of the function HAL_LTDC_DisableCLUT without immediate reload - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param LayerIdx: LTDC Layer index. + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: * 0 or 1 * @retval HAL status @@ -1791,7 +1791,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 /** * @brief Return the LTDC state - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval HAL state */ @@ -1802,7 +1802,7 @@ HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) /** * @brief Return the LTDC error code -* @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains +* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval LTDC Error Code */ @@ -1817,10 +1817,10 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) /** * @brief Configures the LTDC peripheral - * @param hltdc : Pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param pLayerCfg: Pointer LTDC Layer Configuration structure - * @param LayerIdx: LTDC Layer index. + * @param pLayerCfg Pointer LTDC Layer Configuration structure + * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: 0 or 1 * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c index b431a40a64..5588edccc8 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c @@ -73,9 +73,9 @@ #if defined (STM32F769xx) || defined (STM32F779xx) /** * @brief Retrieve common parameters from DSI Video mode configuration structure - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains * the DSI video mode configuration parameters * @note The implementation of this function is taking into account the LTDC * polarities inversion as described in the current LTDC specification @@ -109,9 +109,9 @@ HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, /** * @brief Retrieve common parameters from DSI Adapted command mode configuration structure - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains * the DSI command mode configuration parameters * @note The implementation of this function is taking into account the LTDC * polarities inversion as described in the current LTDC specification diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mdios.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mdios.c index 4f398c2bc3..fa38d36722 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mdios.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mdios.c @@ -143,7 +143,7 @@ /** * @brief Initializes the MDIOS according to the specified parameters in * the MDIOS_InitTypeDef and creates the associated handle . - * @param hmdios: pointer to a MDIOS_HandleTypeDef structure that contains + * @param hmdios pointer to a MDIOS_HandleTypeDef structure that contains * the configuration information for MDIOS module * @retval HAL status */ @@ -201,7 +201,7 @@ HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios) /** * @brief DeInitializes the MDIOS peripheral. - * @param hmdios: MDIOS handle + * @param hmdios MDIOS handle * @retval HAL status */ HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios) @@ -236,7 +236,7 @@ HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios) /** * @brief MDIOS MSP Init - * @param hmdios: mdios handle + * @param hmdios mdios handle * @retval None */ __weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios) @@ -251,7 +251,7 @@ HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios) /** * @brief MDIOS MSP DeInit - * @param hmdios: mdios handle + * @param hmdios mdios handle * @retval None */ __weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios) @@ -302,9 +302,9 @@ HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios) /** * @brief Writes to an MDIOS output register - * @param hmdios: mdios handle - * @param RegNum: MDIOS input register number - * @param Data: Data to write + * @param hmdios mdios handle + * @param RegNum MDIOS input register number + * @param Data Data to write * @retval HAL status */ HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data) @@ -331,9 +331,9 @@ HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNu /** * @brief Reads an MDIOS input register - * @param hmdios: mdios handle - * @param RegNum: MDIOS input register number - * @param pData: pointer to Data + * @param hmdios mdios handle + * @param RegNum MDIOS input register number + * @param pData pointer to Data * @retval HAL status */ HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData) @@ -360,7 +360,7 @@ HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum /** * @brief Gets Written registers by MDIO master - * @param hmdios: mdios handle + * @param hmdios mdios handle * @retval bit map of written registers addresses */ uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios) @@ -370,7 +370,7 @@ uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios) /** * @brief Gets Read registers by MDIO master - * @param hmdios: mdios handle + * @param hmdios mdios handle * @retval bit map of read registers addresses */ uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios) @@ -380,8 +380,8 @@ uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios) /** * @brief Clears Write registers flag - * @param hmdios: mdios handle - * @param RegNum: registers addresses to be cleared + * @param hmdios mdios handle + * @param RegNum registers addresses to be cleared * @retval HAL status */ HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum) @@ -403,8 +403,8 @@ HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, ui /** * @brief Clears Read register flag - * @param hmdios: mdios handle - * @param RegNum: registers addresses to be cleared + * @param hmdios mdios handle + * @param RegNum registers addresses to be cleared * @retval HAL status */ HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum) @@ -426,7 +426,7 @@ HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uin /** * @brief Enables Events for MDIOS peripheral - * @param hmdios: mdios handle + * @param hmdios mdios handle * @retval HAL status */ HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios) @@ -445,7 +445,7 @@ HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios) /** * @brief This function handles MDIOS interrupt request. - * @param hmdios: MDIOS handle + * @param hmdios MDIOS handle * @retval None */ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios) @@ -505,7 +505,7 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios) /** * @brief Write Complete Callback - * @param hmdios: mdios handle + * @param hmdios mdios handle * @retval None */ __weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios) @@ -520,7 +520,7 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios) /** * @brief Read Complete Callback - * @param hmdios: mdios handle + * @param hmdios mdios handle * @retval None */ __weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios) @@ -535,7 +535,7 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios) /** * @brief Error Callback - * @param hmdios: mdios handle + * @param hmdios mdios handle * @retval None */ __weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios) @@ -550,7 +550,7 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios) /** * @brief MDIOS WAKEUP interrupt callback - * @param hmdios: mdios handle + * @param hmdios mdios handle * @retval None */ __weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios) @@ -585,7 +585,7 @@ __weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios) /** * @brief Gets MDIOS error flags - * @param hmdios: mdios handle + * @param hmdios mdios handle * @retval bit map of occured errors */ uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) @@ -596,7 +596,7 @@ uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) /** * @brief Return the MDIOS HAL state - * @param hmdios: mdios handle + * @param hmdios mdios handle * @retval MDIOS state */ HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c index fadb6c8c22..19f337eb42 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c @@ -286,7 +286,7 @@ static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma); /** * @brief Initializes the MMC according to the specified parameters in the MMC_HandleTypeDef and create the associated handle. - * @param hmmc: Pointer to the MMC handle + * @param hmmc Pointer to the MMC handle * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) @@ -333,7 +333,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) /** * @brief Initializes the MMC Card. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @note This function initializes the MMC card. It could be used when a card re-initialization is needed. * @retval HAL status @@ -389,7 +389,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /** * @brief De-Initializes the MMC card. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) @@ -420,7 +420,7 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) /** * @brief Initializes the MMC MSP. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval None */ __weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc) @@ -435,7 +435,7 @@ __weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc) /** * @brief De-Initialize MMC MSP. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval None */ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) @@ -472,11 +472,11 @@ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) * is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_MMC_GetCardState(). - * @param hmmc: Pointer to MMC handle - * @param pData: pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of MMC blocks to read - * @param Timeout: Specify timeout value + * @param hmmc Pointer to MMC handle + * @param pData pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of MMC blocks to read + * @param Timeout Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) @@ -656,11 +656,11 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui * transfer is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_MMC_GetCardState(). - * @param hmmc: Pointer to MMC handle - * @param pData: pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of MMC blocks to write - * @param Timeout: Specify timeout value + * @param hmmc Pointer to MMC handle + * @param pData pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of MMC blocks to write + * @param Timeout Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) @@ -827,10 +827,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u * HAL_MMC_GetCardState(). * @note You could also check the IT transfer process through the MMC Rx * interrupt event. - * @param hmmc: Pointer to MMC handle - * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of blocks to read. + * @param hmmc Pointer to MMC handle + * @param pData Pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -929,10 +929,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, * HAL_MMC_GetCardState(). * @note You could also check the IT transfer process through the MMC Tx * interrupt event. - * @param hmmc: Pointer to MMC handle - * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of blocks to write + * @param hmmc Pointer to MMC handle + * @param pData Pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -1032,10 +1032,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData * HAL_MMC_GetCardState(). * @note You could also check the DMA transfer process through the MMC Rx * interrupt event. - * @param hmmc: Pointer MMC handle - * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of blocks to read. + * @param hmmc Pointer MMC handle + * @param pData Pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -1146,10 +1146,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData * HAL_MMC_GetCardState(). * @note You could also check the DMA transfer process through the MMC Tx * interrupt event. - * @param hmmc: Pointer to MMC handle - * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of blocks to write + * @param hmmc Pointer to MMC handle + * @param pData Pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -1258,9 +1258,9 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat * @brief Erases the specified memory area of the given MMC card. * @note This API should be followed by a check on the card state through * HAL_MMC_GetCardState(). - * @param hmmc: Pointer to MMC handle - * @param BlockStartAdd: Start Block address - * @param BlockEndAdd: End Block address + * @param hmmc Pointer to MMC handle + * @param BlockStartAdd Start Block address + * @param BlockEndAdd End Block address * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd) @@ -1356,7 +1356,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, /** * @brief This function handles MMC card interrupt request. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval None */ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) @@ -1502,7 +1502,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) /** * @brief return the MMC state - * @param hmmc: Pointer to mmc handle + * @param hmmc Pointer to mmc handle * @retval HAL state */ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) @@ -1512,7 +1512,7 @@ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) /** * @brief Return the MMC error code -* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains +* @param hmmc Pointer to a MMC_HandleTypeDef structure that contains * the configuration information. * @retval MMC Error Code */ @@ -1523,7 +1523,7 @@ uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) /** * @brief Tx Transfer completed callbacks - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval None */ __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc) @@ -1538,7 +1538,7 @@ uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) /** * @brief Rx Transfer completed callbacks - * @param hmmc: Pointer MMC handle + * @param hmmc Pointer MMC handle * @retval None */ __weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) @@ -1553,7 +1553,7 @@ __weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) /** * @brief MMC error callbacks - * @param hmmc: Pointer MMC handle + * @param hmmc Pointer MMC handle * @retval None */ __weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc) @@ -1568,7 +1568,7 @@ __weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc) /** * @brief MMC Abort callbacks - * @param hmmc: Pointer MMC handle + * @param hmmc Pointer MMC handle * @retval None */ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) @@ -1604,8 +1604,8 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) /** * @brief Returns information the information of the card which are stored on * the CID register. - * @param hmmc: Pointer to MMC handle - * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that + * @param hmmc Pointer to MMC handle + * @param pCID Pointer to a HAL_MMC_CIDTypedef structure that * contains all CID register parameters * @retval HAL status */ @@ -1685,8 +1685,8 @@ HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTyp /** * @brief Returns information the information of the card which are stored on * the CSD register. - * @param hmmc: Pointer to MMC handle - * @param pCSD: Pointer to a HAL_MMC_CardInfoTypeDef structure that + * @param hmmc Pointer to MMC handle + * @param pCSD Pointer to a HAL_MMC_CardInfoTypeDef structure that * contains all CSD register parameters * @retval HAL status */ @@ -1799,8 +1799,8 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp /** * @brief Gets the MMC card info. - * @param hmmc: Pointer to MMC handle - * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that + * @param hmmc Pointer to MMC handle + * @param pCardInfo Pointer to the HAL_MMC_CardInfoTypeDef structure that * will contain the MMC card status information * @retval HAL status */ @@ -1820,8 +1820,8 @@ HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoT /** * @brief Enables wide bus operation for the requested card if supported by * card. - * @param hmmc: Pointer to MMC handle - * @param WideMode: Specifies the MMC card wide bus mode + * @param hmmc Pointer to MMC handle + * @param WideMode Specifies the MMC card wide bus mode * This parameter can be one of the following values: * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer @@ -1955,7 +1955,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 /** * @brief Gets the current mmc card data state. - * @param hmmc: pointer to MMC handle + * @param hmmc pointer to MMC handle * @retval Card state */ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) @@ -1977,7 +1977,7 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) /** * @brief Abort the current transfer and disable the MMC. - * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * @param hmmc pointer to a MMC_HandleTypeDef structure that contains * the configuration information for MMC module. * @retval HAL status */ @@ -2024,7 +2024,7 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) /** * @brief Abort the current transfer and disable the MMC (IT mode). - * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * @param hmmc pointer to a MMC_HandleTypeDef structure that contains * the configuration information for MMC module. * @retval HAL status */ @@ -2101,7 +2101,7 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) /** * @brief DMA MMC transmit process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -2114,7 +2114,7 @@ static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA MMC receive process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -2147,7 +2147,7 @@ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA MMC communication error callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void MMC_DMAError(DMA_HandleTypeDef *hdma) @@ -2183,7 +2183,7 @@ static void MMC_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA MMC Tx Abort callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma) @@ -2220,7 +2220,7 @@ static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma) /** * @brief DMA MMC Rx Abort callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma) @@ -2258,7 +2258,7 @@ static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma) /** * @brief Initializes the mmc card. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval MMC Card error state */ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) @@ -2339,7 +2339,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) * @brief Enquires cards about their operating voltage and configures clock * controls and stores MMC information that will be needed in future * in the MMC handle. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval error state */ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) @@ -2393,7 +2393,7 @@ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) /** * @brief Turns the SDMMC output signals off. - * @param hmmc: Pointer to MMC handle + * @param hmmc Pointer to MMC handle * @retval HAL status */ static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc) @@ -2406,8 +2406,8 @@ static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc) /** * @brief Returns the current card's status. - * @param hmmc: Pointer to MMC handle - * @param pCardStatus: pointer to the buffer that will contain the MMC card + * @param hmmc Pointer to MMC handle + * @param pCardStatus pointer to the buffer that will contain the MMC card * status (Card Status register) * @retval error state */ @@ -2435,7 +2435,7 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) /** * @brief Wrap up reading in non-blocking mode. - * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * @param hmmc pointer to a MMC_HandleTypeDef structure that contains * the configuration information. * @retval HAL status */ @@ -2459,7 +2459,7 @@ static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc) /** * @brief Wrap up writing in non-blocking mode. - * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * @param hmmc pointer to a MMC_HandleTypeDef structure that contains * the configuration information. * @retval HAL status */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nand.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nand.c index d01cd40c87..79b305f166 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nand.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nand.c @@ -126,10 +126,10 @@ /** * @brief Perform NAND memory Initialization sequence - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param ComSpace_Timing: pointer to Common space timing structure - * @param AttSpace_Timing: pointer to Attribute space timing structure + * @param ComSpace_Timing pointer to Common space timing structure + * @param AttSpace_Timing pointer to Attribute space timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) @@ -168,7 +168,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT /** * @brief Perform NAND memory De-Initialization sequence - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ @@ -191,7 +191,7 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) /** * @brief NAND MSP Init - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval None */ @@ -207,7 +207,7 @@ __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) /** * @brief NAND MSP DeInit - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval None */ @@ -224,7 +224,7 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) /** * @brief This function handles NAND device interrupt request. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ @@ -274,7 +274,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) /** * @brief NAND interrupt feature callback - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval None */ @@ -309,9 +309,9 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) /** * @brief Read the NAND memory electronic signature - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pNAND_ID: NAND ID structure + * @param pNAND_ID NAND ID structure * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) @@ -375,7 +375,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN /** * @brief NAND memory reset - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ @@ -413,9 +413,9 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) /** * @brief Configure the device: Enter the physical parameters of the device - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure + * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) @@ -434,11 +434,11 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC /** * @brief Read Page(s) from NAND memory block (8-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to destination read buffer - * @param NumPageToRead : number of pages to read from block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to destination read buffer + * @param NumPageToRead number of pages to read from block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) @@ -578,11 +578,11 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT /** * @brief Read Page(s) from NAND memory block (16-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned - * @param NumPageToRead : number of pages to read from block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned + * @param NumPageToRead number of pages to read from block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead) @@ -720,11 +720,11 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address /** * @brief Write Page(s) to NAND memory block (8-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write - * @param NumPageToWrite : number of pages to write to block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumPageToWrite number of pages to write to block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) @@ -825,12 +825,12 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - /* Get tick */ - tickstart = HAL_GetTick(); - + { if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) { return HAL_TIMEOUT; @@ -858,11 +858,11 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address /** * @brief Write Page(s) to NAND memory block (16-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned - * @param NumPageToWrite : number of pages to write to block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned + * @param NumPageToWrite number of pages to write to block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite) @@ -963,12 +963,12 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - /* Get tick */ - tickstart = HAL_GetTick(); - + { if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) { return HAL_TIMEOUT; @@ -996,11 +996,11 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres /** * @brief Read Spare area(s) from NAND memory (8-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer: pointer to source buffer to write - * @param NumSpareAreaToRead: Number of spare area to read + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) @@ -1145,11 +1145,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add /** * @brief Read Spare area(s) from NAND memory (16-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned. - * @param NumSpareAreaToRead: Number of spare area to read + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. + * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) @@ -1294,11 +1294,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad /** * @brief Write Spare area(s) to NAND memory (8-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write - * @param NumSpareAreaTowrite : number of spare areas to write to block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write + * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) @@ -1408,12 +1408,12 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - /* Get tick */ - tickstart = HAL_GetTick(); - + { if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) { return HAL_TIMEOUT; @@ -1441,11 +1441,11 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad /** * @brief Write Spare area(s) to NAND memory (16-bits addressing) - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure - * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned. - * @param NumSpareAreaTowrite : number of spare areas to write to block + * @param pAddress pointer to NAND address structure + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. + * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) @@ -1555,12 +1555,12 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - /* Get tick */ - tickstart = HAL_GetTick(); - + { if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) { return HAL_TIMEOUT; @@ -1588,9 +1588,9 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A /** * @brief NAND memory Block erase - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress : pointer to NAND address structure + * @param pAddress pointer to NAND address structure * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) @@ -1636,9 +1636,9 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy /** * @brief Increment the NAND memory address - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param pAddress: pointer to NAND address structure + * @param pAddress pointer to NAND address structure * @retval The new status of the increment address operation. It can be: * - NAND_VALID_ADDRESS: When the new address is valid address * - NAND_INVALID_ADDRESS: When the new address is invalid address @@ -1692,7 +1692,7 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA /** * @brief Enables dynamically NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ @@ -1718,7 +1718,7 @@ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) /** * @brief Disables dynamically FMC_NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status */ @@ -1744,10 +1744,10 @@ HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) /** * @brief Disables dynamically NAND ECC feature. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param ECCval: pointer to ECC value - * @param Timeout: maximum timeout to wait + * @param ECCval pointer to ECC value + * @param Timeout maximum timeout to wait * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout) @@ -1794,7 +1794,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, /** * @brief return the NAND state - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL state */ @@ -1805,7 +1805,7 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) /** * @brief NAND memory read status - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval NAND status */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nor.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nor.c index b67d7294d9..0373e6d256 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nor.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nor.c @@ -168,10 +168,10 @@ static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; /** * @brief Perform the NOR memory Initialization sequence - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Timing: pointer to NOR control timing structure - * @param ExtTiming: pointer to NOR extended mode timing structure + * @param Timing pointer to NOR control timing structure + * @param ExtTiming pointer to NOR extended mode timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) @@ -220,7 +220,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe /** * @brief Perform NOR memory De-Initialization sequence - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ @@ -243,7 +243,7 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) /** * @brief NOR MSP Init - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval None */ @@ -259,7 +259,7 @@ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) /** * @brief NOR MSP DeInit - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval None */ @@ -275,9 +275,9 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) /** * @brief NOR MSP Wait for Ready/Busy signal - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Timeout: Maximum timeout value + * @param Timeout Maximum timeout value * @retval None */ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) @@ -311,9 +311,9 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) /** * @brief Read NOR flash IDs - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pNOR_ID : pointer to NOR ID structure + * @param pNOR_ID pointer to NOR ID structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) @@ -372,7 +372,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I /** * @brief Returns the NOR memory to Read mode. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ @@ -420,10 +420,10 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) /** * @brief Read data from NOR memory - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pAddress: pointer to Device address - * @param pData : pointer to read data + * @param pAddress pointer to Device address + * @param pData pointer to read data * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) @@ -479,10 +479,10 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint /** * @brief Program data to NOR memory - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pAddress: Device address - * @param pData : pointer to the data to write + * @param pAddress Device address + * @param pData pointer to the data to write * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) @@ -538,11 +538,11 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u /** * @brief Reads a half-word buffer from the NOR memory. - * @param hnor: pointer to the NOR handle - * @param uwAddress: NOR memory internal address to read from. - * @param pData: pointer to the buffer that receives the data read from the + * @param hnor pointer to the NOR handle + * @param uwAddress NOR memory internal address to read from. + * @param pData pointer to the buffer that receives the data read from the * NOR memory. - * @param uwBufferSize : number of Half word to read. + * @param uwBufferSize number of Half word to read. * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) @@ -604,10 +604,10 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress /** * @brief Writes a half-word buffer to the NOR memory. This function must be used only with S29GL128P NOR memory. - * @param hnor: pointer to the NOR handle - * @param uwAddress: NOR memory internal start write address - * @param pData: pointer to source data buffer. - * @param uwBufferSize: Size of the buffer to write + * @param hnor pointer to the NOR handle + * @param uwAddress NOR memory internal start write address + * @param pData pointer to source data buffer. + * @param uwBufferSize Size of the buffer to write * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) @@ -684,10 +684,10 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr /** * @brief Erase the specified block of the NOR memory - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param BlockAddress : Block to erase address - * @param Address: Device address + * @param BlockAddress Block to erase address + * @param Address Device address * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) @@ -744,9 +744,9 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd /** * @brief Erase the entire NOR chip. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Address : Device address + * @param Address Device address * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) @@ -802,9 +802,9 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) /** * @brief Read NOR flash CFI IDs - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pNOR_CFI : pointer to NOR CFI IDs structure + * @param pNOR_CFI pointer to NOR CFI IDs structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) @@ -880,7 +880,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR /** * @brief Enables dynamically NOR write operation. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ @@ -903,7 +903,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) /** * @brief Disables dynamically NOR write operation. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval HAL status */ @@ -948,7 +948,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) /** * @brief return the NOR controller state - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @retval NOR controller state */ @@ -959,10 +959,10 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) /** * @brief Returns the NOR operation status. - * @param hnor: pointer to a NOR_HandleTypeDef structure that contains + * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Address: Device address - * @param Timeout: NOR programming Timeout + * @param Address Device address + * @param Timeout NOR programming Timeout * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR * or HAL_NOR_STATUS_TIMEOUT */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c index 8567b81756..2a9884fbbc 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c @@ -127,7 +127,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t /** * @brief Initializes the PCD according to the specified * parameters in the PCD_InitTypeDef and create the associated handle. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) @@ -209,7 +209,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /** * @brief DeInitializes the PCD peripheral. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) @@ -235,7 +235,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) /** * @brief Initializes the PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) @@ -250,7 +250,7 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) /** * @brief DeInitializes PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) @@ -284,7 +284,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) /** * @brief Start The USB OTG Device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) @@ -298,7 +298,7 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) /** * @brief Stop The USB OTG Device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) @@ -313,7 +313,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) /** * @brief Handle PCD interrupt request. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) @@ -530,7 +530,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) for (i = 0; i < hpcd->Init.dev_endpoints ; i++) { USBx_INEP(i)->DIEPINT = 0xFF; + USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; USBx_OUTEP(i)->DOEPINT = 0xFF; + USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; } USBx_DEVICE->DAINT = 0xFFFFFFFF; USBx_DEVICE->DAINTMSK |= 0x10001; @@ -714,8 +716,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Data OUT stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -730,8 +732,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Data IN stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -745,7 +747,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } /** * @brief Setup stage callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) @@ -760,7 +762,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief USB Start Of Frame callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) @@ -775,7 +777,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief USB Reset callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) @@ -790,7 +792,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Suspend event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) @@ -805,7 +807,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Resume event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) @@ -820,8 +822,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Incomplete ISO OUT callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -836,8 +838,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Incomplete ISO IN callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -852,7 +854,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Connection event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) @@ -867,7 +869,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Disconnection event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) @@ -901,7 +903,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Connect the USB device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) @@ -914,7 +916,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) /** * @brief Disconnect the USB device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) @@ -927,8 +929,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) /** * @brief Set the USB Device address. - * @param hpcd: PCD handle - * @param address: new device address + * @param hpcd PCD handle + * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) @@ -940,10 +942,10 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) } /** * @brief Open and configure an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param ep_mps: endpoint max packet size - * @param ep_type: endpoint type + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) @@ -984,8 +986,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint /** * @brief Deactivate an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1013,10 +1015,10 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Receive an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the reception buffer - * @param len: amount of data to be received + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) @@ -1051,8 +1053,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u /** * @brief Get Received Data Size. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval Data Size */ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1061,10 +1063,10 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } /** * @brief Send an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the transmission buffer - * @param len: amount of data to be sent + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) @@ -1099,14 +1101,19 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, /** * @brief Set a STALL condition over an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { USB_OTG_EPTypeDef *ep; + if ((ep_addr & 0x0F) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + if ((0x80 & ep_addr) == 0x80) { ep = &hpcd->IN_ep[ep_addr & 0x7F]; @@ -1134,14 +1141,19 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Clear a STALL condition over in an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { USB_OTG_EPTypeDef *ep; + if ((ep_addr & 0x0F) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + if ((0x80 & ep_addr) == 0x80) { ep = &hpcd->IN_ep[ep_addr & 0x7F]; @@ -1164,8 +1176,8 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Flush an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1188,7 +1200,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Activate remote wakeup signalling. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) @@ -1205,7 +1217,7 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief De-activate remote wakeup signalling. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) @@ -1237,7 +1249,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief Return the PCD handle state. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL state */ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) @@ -1259,8 +1271,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) /** * @brief Check FIFO for the next packet to be loaded. - * @param hpcd: PCD handle - * @param epnum : endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c index de26a9a459..2c241741ce 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c @@ -77,9 +77,9 @@ /** * @brief Set Tx FIFO - * @param hpcd: PCD handle - * @param fifo: The number of Tx fifo - * @param size: Fifo size + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) @@ -120,8 +120,8 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin /** * @brief Set Rx FIFO - * @param hpcd: PCD handle - * @param size: Size of Rx fifo + * @param hpcd PCD handle + * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) @@ -133,7 +133,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) /** * @brief Activate LPM Feature - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) @@ -150,7 +150,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) /** * @brief DeActivate LPM feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) @@ -167,7 +167,7 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) #if defined (USB_OTG_GCCFG_BCDEN) /** * @brief Handle BatteryCharging Process. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) @@ -238,7 +238,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /** * @brief Activate BatteryCharging feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) @@ -253,7 +253,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) /** * @brief Deactivate BatteryCharging feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) @@ -267,8 +267,8 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) /** * @brief Send BatteryCharging message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message + * @param hpcd PCD handle + * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) @@ -285,8 +285,8 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m #endif /* USB_OTG_GCCFG_BCDEN */ /** * @brief Send LPM message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message + * @param hpcd PCD handle + * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c index 2b4b19f17d..b20ad556cf 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c @@ -266,7 +266,7 @@ void HAL_PWR_DisableBkUpAccess(void) /** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration * information for the PVD. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage threshold corresponding to each @@ -334,7 +334,7 @@ void HAL_PWR_DisablePVD(void) /** * @brief Enable the WakeUp PINx functionality. - * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable. + * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. * This parameter can be one of the following legacy values, which sets the default polarity: * detection on high level (rising edge): * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 @@ -363,7 +363,7 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) /** * @brief Disables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 * @arg PWR_WAKEUP_PIN2 @@ -388,13 +388,13 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) * @note In Sleep mode, the systick is stopped to avoid exit from this mode with * systick interrupt when used as time base for Timeout * - * @param Regulator: Specifies the regulator state in SLEEP mode. + * @param Regulator Specifies the regulator state in SLEEP mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON * @note This parameter is not used for the STM32F7 family and is kept as parameter * just to maintain compatibility with the lower power families. - * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction. + * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction @@ -433,11 +433,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. - * @param Regulator: Specifies the regulator state in Stop mode. + * @param Regulator Specifies the regulator state in Stop mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON - * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. + * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c index ac2ace434d..37d2efd9a1 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c @@ -380,13 +380,13 @@ HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. * - * @param Regulator: specifies the regulator state in STOP mode. + * @param Regulator specifies the regulator state in STOP mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode * and Flash memory in power-down when the device is in Stop under-drive mode * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode * and Flash memory in power-down when the device is in Stop under-drive mode - * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction @@ -465,7 +465,7 @@ uint32_t HAL_PWREx_GetVoltageRange(void) /** * @brief Configures the main internal regulator output voltage. - * @param VoltageScaling: specifies the regulator output voltage to achieve + * @param VoltageScaling specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption. * This parameter can be one of the following values: * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c index 58d8b1e2b1..60910d04c2 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c @@ -243,7 +243,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /** * @brief Initializes the QSPI mode according to the specified parameters * in the QSPI_InitTypeDef and creates the associated handle. - * @param hqspi: qspi handle + * @param hqspi qspi handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) @@ -322,7 +322,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /** * @brief DeInitializes the QSPI peripheral - * @param hqspi: qspi handle + * @param hqspi qspi handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -356,7 +356,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief QSPI MSP Init - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) @@ -371,7 +371,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief QSPI MSP DeInit - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) @@ -410,7 +410,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief This function handles QSPI interrupt request. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None. */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) @@ -634,9 +634,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /** * @brief Sets the command configuration. - * @param hqspi: QSPI handle - * @param cmd : structure that contains the command configuration information - * @param Timeout : Time out duration + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information + * @param Timeout Time out duration * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -725,8 +725,8 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /** * @brief Sets the command configuration in interrupt mode. - * @param hqspi: QSPI handle - * @param cmd : structure that contains the command configuration information + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -824,9 +824,9 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer - * @param Timeout : Time out duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Time out duration * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -910,9 +910,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer - * @param Timeout : Time out duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Time out duration * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -998,8 +998,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1058,8 +1058,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Receive an amount of data in no-blocking mode with Interrupt - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1122,8 +1122,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) /** * @brief Sends an amount of data in non blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1256,8 +1256,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /** * @brief Receives an amount of data in non blocking mode with DMA. - * @param hqspi: QSPI handle - * @param pData: pointer to data buffer. + * @param hqspi QSPI handle + * @param pData pointer to data buffer. * @note This function is used only in Indirect Read Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1392,10 +1392,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. - * @param Timeout : Time out duration + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. + * @param Timeout Time out duration * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1493,9 +1493,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the polling configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1597,9 +1597,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information. - * @param cfg: structure that contains the memory mapped configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ @@ -1686,7 +1686,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT /** * @brief Transfer Error callbacks - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1701,7 +1701,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Abort completed callback. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1716,7 +1716,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1731,7 +1731,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Transfer completed callbacks. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1746,7 +1746,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Transfer completed callbacks. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1761,7 +1761,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Half Transfer completed callbacks. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1776,7 +1776,7 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Half Transfer completed callbacks. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1791,7 +1791,7 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief FIFO Threshold callbacks - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -1806,7 +1806,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Status Match callbacks - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -1821,7 +1821,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Timeout callbacks - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -1857,7 +1857,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI handle state. - * @param hqspi: QSPI handle + * @param hqspi QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) @@ -1868,7 +1868,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI error code -* @param hqspi: QSPI handle +* @param hqspi QSPI handle * @retval QSPI Error Code */ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) @@ -1878,7 +1878,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission -* @param hqspi: QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -1931,7 +1931,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi: QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -1976,8 +1976,8 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) } /** @brief Set QSPI timeout - * @param hqspi: QSPI handle. - * @param Timeout: Timeout for the QSPI memory access. + * @param hqspi QSPI handle. + * @param Timeout Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -1986,8 +1986,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi: QSPI handle. - * @param Threshold: Threshold of the Fifo (value between 1 and 16). + * @param hqspi QSPI handle. + * @param Threshold Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2019,7 +2019,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi: QSPI handle. + * @param hqspi QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) @@ -2035,7 +2035,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) /** * @brief DMA QSPI receive process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -2049,7 +2049,7 @@ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) @@ -2063,7 +2063,7 @@ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI receive process half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -2075,7 +2075,7 @@ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -2087,7 +2087,7 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) @@ -2111,7 +2111,7 @@ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI abort complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) @@ -2146,11 +2146,11 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) /** * @brief Wait for a flag state until timeout. - * @param hqspi: QSPI handle - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param tickstart: Start tick value - * @param Timeout: Duration of the time out + * @param hqspi QSPI handle + * @param Flag Flag checked + * @param State Value of the flag expected + * @param tickstart Start tick value + * @param Timeout Duration of the time out * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, @@ -2176,9 +2176,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp /** * @brief Configure the communication registers. - * @param hqspi: QSPI handle - * @param cmd: structure that contains the command configuration information - * @param FunctionalMode: functional mode to configured + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information + * @param FunctionalMode functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c index 8c3397d10e..8839ea319e 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c @@ -12,9 +12,9 @@ ============================================================================== ##### RCC specific features ##### ============================================================================== - [..] - After reset the device is running from Internal High Speed oscillator - (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache and I-Cache are disabled, and all peripherals are off except internal SRAM, Flash and JTAG. (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; @@ -22,12 +22,12 @@ (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in input floating state, except the JTAG pins which are assigned to be used for debug purpose. - - [..] - Once the device started from reset, the user application has to: + + [..] + Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings + (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB busses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals which clocks are not @@ -35,17 +35,17 @@ ##### RCC Limitations ##### ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write from/to registers. (+) This delay depends on the peripheral mapping. - (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle after the clock enable bit is set on the hardware register - (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle after the clock enable bit is set on the hardware register - [..] + [..] Implemented Workaround: (+) For AHB & APB peripherals, a dummy read to the peripheral register has been inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. @@ -79,7 +79,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -129,16 +129,16 @@ * @{ */ -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to configure the internal/external oscillators - (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 and APB2). [..] Internal/external clock and PLL configuration @@ -151,7 +151,7 @@ (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or through the PLL as System clock source. Can be used also as RTC clock source. - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. (#) PLL (clocked by HSI or HSE), featuring two different output clocks: (++) The first output is used to generate the high speed system clock (up to 216 MHz) @@ -159,10 +159,10 @@ the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS() - and if a HSE clock failure occurs(HSE used directly or through PLL as System + and if a HSE clock failure occurs(HSE used directly or through PLL as System clock source), the System clock is automatically switched to HSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M7 NMI - (Non-Maskable Interrupt) exception vector. + is generated if enabled. The interrupt is linked to the Cortex-M7 NMI + (Non-Maskable Interrupt) exception vector. (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL clock (through a configurable prescaler) on PA8 pin. @@ -170,26 +170,26 @@ (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S clock (through a configurable prescaler) on PC9 pin. - [..] System, AHB and APB busses clocks configuration + [..] System, AHB and APB busses clocks configuration (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or - from an external clock mapped on the I2S_CKIN pin. + from an external clock mapped on the I2S_CKIN pin. You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or - from an external clock mapped on the I2S_CKIN pin. - You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. + from an external clock mapped on the I2S_CKIN pin. + You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE() - macros to configure this clock. + macros to configure this clock. (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz to work correctly, while the SDIO require a frequency equal or lower than to 48. This clock is derived of the main PLL through PLLQ divider. @@ -202,48 +202,151 @@ * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source - * - HSE, PLL and PLLI2S OFF + * - HSE, PLL, PLLI2S and PLLSAI OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO1 and MCO2 OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks + * - Peripheral clocks + * - LSI, LSE and RTC clocks * @retval None */ -void HAL_RCC_DeInit(void) +HAL_StatusTypeDef HAL_RCC_DeInit(void) { - /* Set HSION bit */ - SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); - + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[4:0] bits to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); - - /* Reset HSEON, CSSON, PLLON, PLLI2S */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON); - - /* Reset PLLCFGR register */ - CLEAR_REG(RCC->PLLCFGR); - SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | ((uint32_t)0x20000000U)); - - /* Reset PLLI2SCFGR register */ - CLEAR_REG(RCC->PLLI2SCFGR); - SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1); - - /* Reset HSEBYP bit */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear HSEON, HSEBYP and CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLI2SON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); + + /* Wait till PLLI2S is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLSAI bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); + + /* Wait till PLLSAI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | 0x20000000U; + + /* Reset PLLI2SCFGR register to default value */ + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; + + /* Reset PLLSAICFGR register to default value */ + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | 0x20000000U; + /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); - + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE); + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC); + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } } /** * @brief Initializes the RCC Oscillators according to the specified parameters in the * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not @@ -551,25 +654,25 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -586,26 +689,26 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } return HAL_OK; } - + /** - * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * @brief Initializes the CPU, AHB and APB busses clocks according to the specified * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. - * @param FLatency: FLASH Latency, this parameter depend on device selected - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * @param FLatency FLASH Latency, this parameter depend on device selected + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated by HAL_RCC_GetHCLKFreq() function called within this function * * @note The HSI is used (enabled by hardware) as system clock source after * startup from Reset, wake-up from STOP and STANDBY mode, or in case * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). - * + * * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). + * clock source is ready (clock stable after startup delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. + * occur when the clock source will be ready. * You can use HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @note Depending on the device voltage range, the software has to set correctly @@ -648,6 +751,19 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + } + + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + } + + /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } @@ -746,11 +862,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui @verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the RCC Clocks + This subsection provides a set of functions allowing to control the RCC Clocks frequencies. - + @endverbatim * @{ */ @@ -758,11 +874,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /** * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). * @note PA8/PC9 should be configured in alternate function mode. - * @param RCC_MCOx: specifies the output direction for the clock source. + * @param RCC_MCOx specifies the output direction for the clock source. * This parameter can be one of the following values: * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). - * @param RCC_MCOSource: specifies the clock source to output. + * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source @@ -772,7 +888,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source - * @param RCC_MCODiv: specifies the MCOx prescaler. + * @param RCC_MCODiv specifies the MCOx prescaler. * This parameter can be one of the following values: * @arg RCC_MCODIV_1: no division applied to MCOx clock * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock @@ -791,28 +907,28 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M if(RCC_MCOx == RCC_MCO1) { assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - + /* MCO1 Clock Enable */ MCO1_CLK_ENABLE(); - - /* Configure the MCO1 pin in alternate function mode */ + + /* Configure the MCO1 pin in alternate function mode */ GPIO_InitStruct.Pin = MCO1_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Alternate = GPIO_AF0_MCO; HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); - + /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); } else { assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); - + /* MCO2 Clock Enable */ MCO2_CLK_ENABLE(); - + /* Configure the MCO2 pin in alternate function mode */ GPIO_InitStruct.Pin = MCO2_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -820,7 +936,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Alternate = GPIO_AF0_MCO; HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); - + /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3))); } @@ -831,8 +947,8 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector. + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector. * @retval None */ void HAL_RCC_EnableCSS(void) @@ -851,14 +967,14 @@ void HAL_RCC_DisableCSS(void) /** * @brief Returns the SYSCLK frequency - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. @@ -866,17 +982,17 @@ void HAL_RCC_DisableCSS(void) * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * @note The result of this function could be not correct when using fractional * value for HSE crystal. - * - * @note This function can be used by the user application to compute the + * + * @note This function can be used by the user application to compute the * baudrate for the communication peripherals or configure other parameters. - * + * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * + * + * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) @@ -905,15 +1021,15 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) { /* HSE used as PLL clock source */ - pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)); + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } else { /* HSI used as PLL clock source */ - pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)); + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2); - + sysclockfreq = pllvco/pllp; break; } @@ -927,9 +1043,9 @@ uint32_t HAL_RCC_GetSysClockFreq(void) } /** - * @brief Returns the HCLK frequency + * @brief Returns the HCLK frequency * @note Each time HCLK changes, this function must be called to update the - * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency */ @@ -939,19 +1055,19 @@ uint32_t HAL_RCC_GetHCLKFreq(void) } /** - * @brief Returns the PCLK1 frequency + * @brief Returns the PCLK1 frequency * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) -{ +{ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); } /** - * @brief Returns the PCLK2 frequency + * @brief Returns the PCLK2 frequency * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency @@ -960,12 +1076,12 @@ uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); -} +} /** - * @brief Configures the RCC_OscInitStruct according to the internal + * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * will be configured. * @retval None */ @@ -973,7 +1089,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; - + /* Get the HSE configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { @@ -987,7 +1103,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } - + /* Get the HSI configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) { @@ -997,9 +1113,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); - + /* Get the LSE configuration -----------------------------------------------*/ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { @@ -1013,7 +1129,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } - + /* Get the LSI configuration -----------------------------------------------*/ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) { @@ -1023,7 +1139,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } - + /* Get the PLL configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) { @@ -1044,32 +1160,32 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /** - * @brief Configures the RCC_ClkInitStruct according to the internal + * @brief Configures the RCC_ClkInitStruct according to the internal * RCC configuration registers. - * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that * will be configured. - * @param pFLatency: Pointer on the Flash Latency. + * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - /* Get the SYSCLK configuration --------------------------------------------*/ + + /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); - - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); } /** @@ -1098,7 +1214,7 @@ __weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RCC_CSSCallback could be implemented in the user file - */ + */ } /** diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c index bc8d51da3f..cfdc545795 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c @@ -56,10 +56,6 @@ /** @defgroup RCCEx_Private_Defines RCCEx Private Defines * @{ */ - -#define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */ -#define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */ - /** * @} */ @@ -112,7 +108,7 @@ /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). * @@ -680,7 +676,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /** * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure + * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @@ -820,7 +816,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). * @@ -1289,7 +1285,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /** * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure + * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @@ -1395,7 +1391,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /** * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier + * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock @@ -1580,6 +1576,201 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) return frequency; } +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of PLLI2S, PLLSAI. +@endverbatim + * @{ + */ + +/** + * @brief Enable PLLI2S. + * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that + * contains the configuration information for the PLLI2S + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ)); +#if defined(RCC_PLLI2SCFGR_PLLI2SP) + assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP)); +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLI2S division factors */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#else + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SPCLK = PLLI2S_VCO / PLLI2SP */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Wait till PLLI2S is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLI2S. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +{ + uint32_t tickstart; + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Enable PLLSAI. + * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that + * contains the configuration information for the PLLSAI + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN)); + assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ)); + assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP)); +#if defined(RCC_PLLSAICFGR_PLLSAIR) + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR)); +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLSAI division factors */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ); +#else + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ + PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */ + + /* Enable the PLLSAI */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Wait till PLLSAI is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLSAI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void) +{ + uint32_t tickstart; + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c index 6f37f35da6..47d9556427 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c @@ -74,7 +74,7 @@ /** @addtogroup RNG_Private_Constants * @{ */ -#define RNG_TIMEOUT_VALUE 2 +#define RNG_TIMEOUT_VALUE 2U /** * @} */ @@ -107,7 +107,7 @@ /** * @brief Initializes the RNG peripheral and creates the associated handle. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ @@ -118,14 +118,11 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { return HAL_ERROR; } - - __HAL_LOCK(hrng); - + if(hrng->State == HAL_RNG_STATE_RESET) { /* Allocate lock resource and initialize it */ hrng->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ HAL_RNG_MspInit(hrng); } @@ -138,16 +135,14 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; - - __HAL_UNLOCK(hrng); - + /* Return function status */ return HAL_OK; } /** * @brief DeInitializes the RNG peripheral. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ @@ -179,7 +174,7 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) /** * @brief Initializes the RNG MSP. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval None */ @@ -187,7 +182,6 @@ __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrng); - /* NOTE : This function should not be modified. When the callback is needed, function HAL_RNG_MspInit must be implemented in the user file. */ @@ -195,7 +189,7 @@ __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) /** * @brief DeInitializes the RNG MSP. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval None */ @@ -203,7 +197,6 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrng); - /* NOTE : This function should not be modified. When the callback is needed, function HAL_RNG_MspDeInit must be implemented in the user file. */ @@ -233,15 +226,15 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) * @brief Generates a 32-bit random number. * @note Each time the random number data is read the RNG_FLAG_DRDY flag * is automatically cleared. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. - * @param random32bit: pointer to generated random number variable if successful. + * @param random32bit pointer to generated random number variable if successful. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ @@ -289,7 +282,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /** * @brief Generates a 32-bit random number in interrupt mode. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ @@ -339,7 +332,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) * the RNG peripheral to reinitialize and restart the RNG. * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS * or CEIS are set. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval None @@ -382,7 +375,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) /** * @brief Returns generated random number in polling mode (Obsolete) * Use HAL_RNG_GenerateRandomNumber() API instead. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval Random value */ @@ -394,20 +387,20 @@ uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng) } else { - return 0; + return 0U; } } /** * @brief Returns a 32-bit random number with interrupt enabled (Obsolete), * Use HAL_RNG_GenerateRandomNumber_IT() API instead. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval 32-bit random number */ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) { - uint32_t random32bit = 0; + uint32_t random32bit = 0U; /* Process locked */ __HAL_LOCK(hrng); @@ -427,7 +420,7 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) /** * @brief Read latest generated random number. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval random value */ @@ -438,16 +431,16 @@ uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) /** * @brief Data Ready callback in non-blocking mode. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. - * @param random32bit: generated random number. + * @param random32bit generated random number. * @retval None */ __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrng); - + UNUSED(random32bit); /* NOTE : This function should not be modified. When the callback is needed, function HAL_RNG_ReadyDataCallback must be implemented in the user file. */ @@ -455,7 +448,7 @@ __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32 /** * @brief RNG error callbacks. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval None */ @@ -463,7 +456,6 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrng); - /* NOTE : This function should not be modified. When the callback is needed, function HAL_RNG_ErrorCallback must be implemented in the user file. */ @@ -490,7 +482,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) /** * @brief Returns the RNG state. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains + * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL state */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c index 71dcd73625..d27445b8b8 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c @@ -195,7 +195,7 @@ /** * @brief Initializes the RTC peripheral - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -270,7 +270,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /** * @brief DeInitializes the RTC peripheral - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @note This function doesn't reset the RTC Backup Data registers. * @retval HAL status @@ -376,7 +376,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /** * @brief Initializes the RTC MSP. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -392,7 +392,7 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) /** * @brief DeInitializes the RTC MSP. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -426,10 +426,10 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) /** * @brief Sets RTC current time. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. + * @param sTime Pointer to Time structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg FORMAT_BIN: Binary data format * @arg FORMAT_BCD: BCD data format @@ -551,12 +551,12 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Gets RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned + * @param hrtc RTC handle + * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned * with input format (BIN or BCD), also SubSeconds field returning the * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler * factor to be used for second fraction ratio computation. - * @param Format: Specifies the format of the entered parameters. + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -606,10 +606,10 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Sets RTC current date. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sDate: Pointer to date structure - * @param Format: specifies the format of the entered parameters. + * @param sDate Pointer to date structure + * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -648,10 +648,8 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat else { assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); - datetmpreg = RTC_Bcd2ToByte(sDate->Month); - assert_param(IS_RTC_MONTH(datetmpreg)); - datetmpreg = RTC_Bcd2ToByte(sDate->Date); - assert_param(IS_RTC_DATE(datetmpreg)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ (((uint32_t)sDate->Month) << 8) | \ @@ -715,10 +713,10 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat /** * @brief Gets RTC current date. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sDate: Pointer to Date structure - * @param Format: Specifies the format of the entered parameters. + * @param sDate Pointer to Date structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -773,10 +771,10 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ /** * @brief Sets the specified RTC Alarm. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg FORMAT_BIN: Binary data format * @arg FORMAT_BCD: BCD data format @@ -959,10 +957,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief Sets the specified RTC Alarm with Interrupt - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg FORMAT_BIN: Binary data format * @arg FORMAT_BCD: BCD data format @@ -973,8 +971,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA */ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; + uint32_t tmpreg = 0U, subsecondtmpreg = 0U; + __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U) ; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -998,7 +996,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); } assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); @@ -1012,11 +1010,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -1030,7 +1028,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } else { - sAlarm->AlarmTime.TimeFormat = 0x00; + sAlarm->AlarmTime.TimeFormat = 0x00U; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); } @@ -1047,11 +1045,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } @@ -1070,26 +1068,24 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* Clear flag alarm A */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + do { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if (count-- == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ __HAL_UNLOCK(hrtc); - + return HAL_TIMEOUT; - } - } - + } + } + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET); + hrtc->Instance->ALRMAR = (uint32_t)tmpreg; /* Configure the Alarm A Sub Second register */ hrtc->Instance->ALRMASSR = subsecondtmpreg; @@ -1106,26 +1102,24 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* Clear flag alarm B */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + do { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if (count-- == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } + return HAL_TIMEOUT; + } + } + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET); + hrtc->Instance->ALRMBR = (uint32_t)tmpreg; /* Configure the Alarm B Sub Second register */ hrtc->Instance->ALRMBSSR = subsecondtmpreg; @@ -1153,9 +1147,9 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /** * @brief Deactive the specified RTC Alarm - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Alarm: Specifies the Alarm. + * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA * @arg RTC_ALARM_B: AlarmB @@ -1245,14 +1239,14 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /** * @brief Gets the RTC Alarm value and masks. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sAlarm: Pointer to Date structure - * @param Alarm: Specifies the Alarm. + * @param sAlarm Pointer to Date structure + * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA * @arg RTC_ALARM_B: AlarmB - * @param Format: Specifies the format of the entered parameters. + * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format @@ -1305,7 +1299,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief This function handles Alarm interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -1346,7 +1340,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) /** * @brief Alarm A callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -1362,9 +1356,9 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief This function handles AlarmA Polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -1425,7 +1419,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * The software must then wait until it is set again before reading * the calendar, which means that the calendar registers have been * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -1471,7 +1465,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) */ /** * @brief Returns the RTC state. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL state */ @@ -1488,7 +1482,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) * @brief Enters the RTC Initialization mode. * @note The RTC Initialization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -1521,7 +1515,7 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) /** * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted + * @param Value Byte to be converted * @retval Converted byte */ uint8_t RTC_ByteToBcd2(uint8_t Value) @@ -1539,7 +1533,7 @@ uint8_t RTC_ByteToBcd2(uint8_t Value) /** * @brief Converts from 2 digit BCD to Binary. - * @param Value: BCD value to be converted + * @param Value BCD value to be converted * @retval Converted word */ uint8_t RTC_Bcd2ToByte(uint8_t Value) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c index e0d5e8b17f..1862f7c551 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c @@ -138,16 +138,16 @@ /** * @brief Sets TimeStamp. * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. + * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin. * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. @@ -197,17 +197,17 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS /** * @brief Sets TimeStamp with Interrupt. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @note This API must be called before enabling the TimeStamp feature. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the * rising edge of the related pin. * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the * falling edge of the related pin. - * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. + * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin. * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. @@ -267,13 +267,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /** * @brief Deactivates TimeStamp. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Process Locked */ __HAL_LOCK(hrtc); @@ -306,7 +306,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) /** * @brief Sets Internal TimeStamp. * @note This API must be called before enabling the internal TimeStamp feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -337,7 +337,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) /** * @brief Deactivates internal TimeStamp. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -367,11 +367,11 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) /** * @brief Gets the RTC TimeStamp value. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sTimeStamp: Pointer to Time structure - * @param sTimeStampDate: Pointer to Date structure - * @param Format: specifies the format of the entered parameters. + * @param sTimeStamp Pointer to Time structure + * @param sTimeStampDate Pointer to Date structure + * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: * FORMAT_BIN: Binary data format * FORMAT_BCD: BCD data format @@ -379,7 +379,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) */ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) { - uint32_t tmptime = 0, tmpdate = 0; + uint32_t tmptime = 0U, tmpdate = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -389,17 +389,17 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U); sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U); sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; /* Fill the Date structure fields with the read parameters */ - sTimeStampDate->Year = 0; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); + sTimeStampDate->Year = 0U; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U); sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U); /* Check the input parameters format */ if(Format == RTC_FORMAT_BIN) @@ -424,14 +424,14 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe /** * @brief Sets Tamper * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sTamper: Pointer to Tamper Structure. + * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_TAMPER(sTamper->Tamper)); @@ -451,21 +451,21 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); + sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); } if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) { sTamper->NoErase = 0; - if((sTamper->Tamper & RTC_TAMPER_1) != 0) + if((sTamper->Tamper & RTC_TAMPER_1) != 0U) { sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; } - if((sTamper->Tamper & RTC_TAMPER_2) != 0) + if((sTamper->Tamper & RTC_TAMPER_2) != 0U) { sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; } - if((sTamper->Tamper & RTC_TAMPER_3) != 0) + if((sTamper->Tamper & RTC_TAMPER_3) != 0U) { sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; } @@ -474,15 +474,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { sTamper->MaskFlag = 0; - if((sTamper->Tamper & RTC_TAMPER_1) != 0) + if((sTamper->Tamper & RTC_TAMPER_1) != 0U) { sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; } - if((sTamper->Tamper & RTC_TAMPER_2) != 0) + if((sTamper->Tamper & RTC_TAMPER_2) != 0U) { sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; } - if((sTamper->Tamper & RTC_TAMPER_3) != 0) + if((sTamper->Tamper & RTC_TAMPER_3) != 0U) { sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; } @@ -512,9 +512,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef /** * @brief Sets Tamper with interrupt. * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param sTamper: Pointer to RTC Tamper. + * @param sTamper Pointer to RTC Tamper. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) @@ -622,9 +622,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /** * @brief Deactivates Tamper. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Tamper: Selected tamper pin. + * @param Tamper Selected tamper pin. * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2. * @retval HAL status */ @@ -666,7 +666,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T /** * @brief This function handles TimeStamp interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -739,7 +739,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /** * @brief TimeStamp callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -755,7 +755,7 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Tamper 1 callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -771,7 +771,7 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Tamper 2 callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -787,7 +787,7 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) /** * @brief Tamper 3 callback. - * @param hrtc: RTC handle + * @param hrtc RTC handle * @retval None */ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) @@ -802,9 +802,9 @@ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) /** * @brief This function handles TimeStamp polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -845,14 +845,14 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /** * @brief This function handles Tamper1 Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Get tick */ tickstart = HAL_GetTick(); @@ -862,7 +862,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -881,9 +881,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ /** * @brief This function handles Tamper2 Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -917,8 +917,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ /** * @brief This function handles Tamper3 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @param hrtc RTC handle + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -967,10 +967,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_ /** * @brief Sets wake up timer. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) @@ -1040,16 +1040,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /** * @brief Sets wake up timer with interrupt - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { - uint32_t tickstart = 0; - + __IO uint32_t count; + /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); @@ -1064,31 +1064,51 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - /* Get tick */ - tickstart = HAL_GetTick(); - - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ + /* Check RTC WUTWF flag is reset only when wake up timer enabled */ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) { - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ + count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + do { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if(count-- == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ __HAL_UNLOCK(hrtc); - + return HAL_TIMEOUT; - } + } } + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET); } - - /* Configure the Wakeup Timer counter */ + + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + do + { + if(count-- == 0U) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET); + + /* Configure the Wake-up Timer counter */ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; /* Clear the Wakeup Timer clock source bits in CR register */ @@ -1124,13 +1144,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /** * @brief Deactivates wake up timer counter. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Process Locked */ __HAL_LOCK(hrtc); @@ -1179,7 +1199,7 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /** * @brief Gets wake up timer counter. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval Counter value */ @@ -1191,7 +1211,7 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) /** * @brief This function handles Wake Up Timer interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -1219,7 +1239,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) /** * @brief Wake Up Timer callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -1235,9 +1255,9 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief This function handles Wake Up Timer Polling. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) @@ -1302,12 +1322,12 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /** * @brief Writes a data in a specified RTC Backup data register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param BackupRegister: RTC Backup data Register number. + * @param BackupRegister RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. + * @param Data Data to be written in the specified RTC Backup data register. * @retval None */ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) @@ -1326,9 +1346,9 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 /** * @brief Reads data from the specified RTC Backup data Register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param BackupRegister: RTC Backup data Register number. + * @param BackupRegister RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to * specify the register. * @retval Read value @@ -1349,18 +1369,18 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) /** * @brief Sets the Smooth calibration parameters. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param SmoothCalibPeriod: Select the Smooth Calibration Period. + * @param SmoothCalibPeriod Select the Smooth Calibration Period. * This parameter can be can be one of the following values : * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. - * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. + * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit. * This parameter can be one of the following values: * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulses every 2*11 pulses. * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * @param SmouthCalibMinusPulsesValue Select the value of CALM[80] bits. * This parameter can be one any value from 0 to 0x000001FF. * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field @@ -1427,13 +1447,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo /** * @brief Configures the Synchronization Shift Control Settings. * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. + * @param ShiftAdd1S Select to add or not 1 second to the time calendar. * This parameter can be one of the following values : * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. * @arg RTC_SHIFTADD1S_RESET: No effect. - * @param ShiftSubFS: Select the number of Second Fractions to substitute. + * @param ShiftSubFS Select the number of Second Fractions to substitute. * This parameter can be one any value from 0 to 0x7FFF. * @retval HAL status */ @@ -1524,9 +1544,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh /** * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param CalibOutput: Select the Calibration output Selection . + * @param CalibOutput Select the Calibration output Selection . * This parameter can be one of the following values: * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. @@ -1567,7 +1587,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32 /** * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -1597,7 +1617,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) /** * @brief Enables the RTC reference clock detection. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -1647,7 +1667,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) /** * @brief Disable the RTC reference clock detection. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ @@ -1697,7 +1717,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) /** * @brief Enables the Bypass Shadow feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. @@ -1730,7 +1750,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) /** * @brief Disables the Bypass Shadow feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. @@ -1782,7 +1802,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) /** * @brief Alarm B callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ @@ -1798,9 +1818,9 @@ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief This function handles AlarmB Polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c index 948aeedd8f..000ab3b486 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c @@ -270,12 +270,12 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); * @brief Initialize the structure FrameInit, SlotInit and the low part of * Init according to the specified parameters and call the function * HAL_SAI_Init to initialize the SAI block. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol @ref SAI_Protocol - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize + * @param protocol one of the supported protocol @ref SAI_Protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * the configuration information for SAI module. - * @param nbslot: Number of slot. + * @param nbslot Number of slot. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) @@ -313,7 +313,7 @@ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protoco /** * @brief Initialize the SAI according to the specified parameters. * in the SAI_InitTypeDef structure and initialize the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -515,7 +515,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) /** * @brief DeInitialize the SAI peripheral. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -556,7 +556,7 @@ HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) /** * @brief Initialize the SAI MSP. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -572,7 +572,7 @@ __weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) /** * @brief DeInitialize the SAI MSP. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -634,11 +634,11 @@ __weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) /** * @brief Transmit an amount of data in blocking mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout) @@ -734,11 +734,11 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint /** * @brief Receive an amount of data in blocking mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -832,10 +832,10 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -894,10 +894,10 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -954,7 +954,7 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui /** * @brief Pause the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -974,7 +974,7 @@ HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) /** * @brief Resume the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1001,7 +1001,7 @@ HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) /** * @brief Stop the audio stream playing from the Media. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1046,7 +1046,7 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /** * @brief Abort the current transfer and disable the SAI. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1098,10 +1098,10 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /** * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -1167,10 +1167,10 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) @@ -1237,9 +1237,9 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u /** * @brief Enable the Tx mute mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param val: value sent during the mute @ref SAI_Block_Mute_Value + * @param val value sent during the mute @ref SAI_Block_Mute_Value * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val) @@ -1257,7 +1257,7 @@ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val /** * @brief Disable the Tx mute mode. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1273,10 +1273,10 @@ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Enable the Rx mute detection. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param callback: function called when the mute is detected. - * @param counter: number a data before mute detection max 63. + * @param callback function called when the mute is detected. + * @param counter number a data before mute detection max 63. * @retval HAL status */ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter) @@ -1298,7 +1298,7 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback /** * @brief Disable the Rx mute detection. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL status */ @@ -1317,7 +1317,7 @@ HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) /** * @brief Handle SAI interrupt request. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1483,7 +1483,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1499,7 +1499,7 @@ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Tx Transfer Half completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1515,7 +1515,7 @@ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1531,7 +1531,7 @@ __weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief Rx Transfer half completed callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1547,7 +1547,7 @@ __weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) /** * @brief SAI error callback. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1583,7 +1583,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) /** * @brief Return the SAI handle state. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval HAL state */ @@ -1594,7 +1594,7 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) /** * @brief Return the SAI error code. -* @param hsai: pointer to a SAI_HandleTypeDef structure that contains +* @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for the specified SAI Block. * @retval SAI Error Code */ @@ -1618,12 +1618,12 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) /** * @brief Initialize the SAI I2S protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol. - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize + * @param protocol one of the supported protocol. + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize * the configuration information for SAI module. - * @param nbslot: number of slot minimum value is 2 and max is 16. + * @param nbslot number of slot minimum value is 2 and max is 16. * the value must be a multiple of 2. * @retval HAL status */ @@ -1713,11 +1713,11 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, /** * @brief Initialize the SAI PCM protocol according to the specified parameters * in the SAI_InitTypeDef and create the associated handle. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param protocol: one of the supported protocol - * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize - * @param nbslot: number of slot minimum value is 1 and the max is 16. + * @param protocol one of the supported protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize + * @param nbslot number of slot minimum value is 1 and the max is 16. * @retval HAL status */ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) @@ -1783,7 +1783,7 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, /** * @brief Fill the fifo. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1812,9 +1812,9 @@ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) /** * @brief Return the interrupt flag to set according the SAI setup. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. - * @param mode: SAI_MODE_DMA or SAI_MODE_IT + * @param mode SAI_MODE_DMA or SAI_MODE_IT * @retval the list of the IT flag to enable */ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) @@ -1846,7 +1846,7 @@ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) /** * @brief Disable the SAI and wait for the disabling. - * @param hsai : pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1875,7 +1875,7 @@ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1899,7 +1899,7 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1924,7 +1924,7 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) /** * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1949,7 +1949,7 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) /** * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -1975,7 +1975,7 @@ static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) /** * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2001,7 +2001,7 @@ static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) } /** * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer. - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval None */ @@ -2028,7 +2028,7 @@ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) /** * @brief DMA SAI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2053,7 +2053,7 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI transmit process half complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2066,7 +2066,7 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2089,7 +2089,7 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2101,7 +2101,7 @@ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) } /** * @brief DMA SAI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2132,7 +2132,7 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA SAI Abort callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c index e0b26080a7..9f253439d4 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c @@ -295,7 +295,7 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma); /** * @brief Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle. - * @param hsd: Pointer to the SD handle + * @param hsd Pointer to the SD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) @@ -342,7 +342,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) /** * @brief Initializes the SD Card. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @note This function initializes the SD card. It could be used when a card re-initialization is needed. * @retval HAL status @@ -398,7 +398,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /** * @brief De-Initializes the SD card. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) @@ -429,7 +429,7 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) /** * @brief Initializes the SD MSP. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval None */ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) @@ -444,7 +444,7 @@ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) /** * @brief De-Initialize SD MSP. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval None */ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) @@ -481,11 +481,11 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) * is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @param hsd: Pointer to SD handle - * @param pData: pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of SD blocks to read - * @param Timeout: Specify timeout value + * @param hsd Pointer to SD handle + * @param pData pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of SD blocks to read + * @param Timeout Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) @@ -667,11 +667,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 * transfer is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @param hsd: Pointer to SD handle - * @param pData: pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of SD blocks to write - * @param Timeout: Specify timeout value + * @param hsd Pointer to SD handle + * @param pData pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of SD blocks to write + * @param Timeout Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) @@ -840,10 +840,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint * HAL_SD_GetCardState(). * @note You could also check the IT transfer process through the SD Rx * interrupt event. - * @param hsd: Pointer to SD handle - * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of blocks to read. + * @param hsd Pointer to SD handle + * @param pData Pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -941,10 +941,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui * HAL_SD_GetCardState(). * @note You could also check the IT transfer process through the SD Tx * interrupt event. - * @param hsd: Pointer to SD handle - * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of blocks to write + * @param hsd Pointer to SD handle + * @param pData Pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -1043,10 +1043,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u * HAL_SD_GetCardState(). * @note You could also check the DMA transfer process through the SD Rx * interrupt event. - * @param hsd: Pointer SD handle - * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of blocks to read. + * @param hsd Pointer SD handle + * @param pData Pointer to the buffer that will contain the received data + * @param BlockAdd Block Address from where data is to be read + * @param NumberOfBlocks Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -1156,10 +1156,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u * HAL_SD_GetCardState(). * @note You could also check the DMA transfer process through the SD Tx * interrupt event. - * @param hsd: Pointer to SD handle - * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of blocks to write + * @param hsd Pointer to SD handle + * @param pData Pointer to the buffer that will contain the data to transmit + * @param BlockAdd Block Address where data will be written + * @param NumberOfBlocks Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) @@ -1267,9 +1267,9 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, * @brief Erases the specified memory area of the given SD card. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @param hsd: Pointer to SD handle - * @param BlockStartAdd: Start Block address - * @param BlockEndAdd: End Block address + * @param hsd Pointer to SD handle + * @param BlockStartAdd Start Block address + * @param BlockEndAdd End Block address * @retval HAL status */ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd) @@ -1369,7 +1369,7 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui /** * @brief This function handles SD card interrupt request. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval None */ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) @@ -1515,7 +1515,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) /** * @brief return the SD state - * @param hsd: Pointer to sd handle + * @param hsd Pointer to sd handle * @retval HAL state */ HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) @@ -1525,7 +1525,7 @@ HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) /** * @brief Return the SD error code -* @param hsd : Pointer to a SD_HandleTypeDef structure that contains +* @param hsd Pointer to a SD_HandleTypeDef structure that contains * the configuration information. * @retval SD Error Code */ @@ -1536,7 +1536,7 @@ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) /** * @brief Tx Transfer completed callbacks - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval None */ __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) @@ -1551,7 +1551,7 @@ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) /** * @brief Rx Transfer completed callbacks - * @param hsd: Pointer SD handle + * @param hsd Pointer SD handle * @retval None */ __weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) @@ -1566,7 +1566,7 @@ __weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) /** * @brief SD error callbacks - * @param hsd: Pointer SD handle + * @param hsd Pointer SD handle * @retval None */ __weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) @@ -1581,7 +1581,7 @@ __weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) /** * @brief SD Abort callbacks - * @param hsd: Pointer SD handle + * @param hsd Pointer SD handle * @retval None */ __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) @@ -1617,8 +1617,8 @@ __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) /** * @brief Returns information the information of the card which are stored on * the CID register. - * @param hsd: Pointer to SD handle - * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that + * @param hsd Pointer to SD handle + * @param pCID Pointer to a HAL_SD_CardCIDTypeDef structure that * contains all CID register parameters * @retval HAL status */ @@ -1698,8 +1698,8 @@ HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef /** * @brief Returns information the information of the card which are stored on * the CSD register. - * @param hsd: Pointer to SD handle - * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that + * @param hsd Pointer to SD handle + * @param pCSD Pointer to a HAL_SD_CardCSDTypeDef structure that * contains all CSD register parameters * @retval HAL status */ @@ -1845,8 +1845,8 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef /** * @brief Gets the SD status info. - * @param hsd: Pointer to SD handle - * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that + * @param hsd Pointer to SD handle + * @param pStatus Pointer to the HAL_SD_CardStatusTypeDef structure that * will contain the SD card status information * @retval HAL status */ @@ -1933,8 +1933,8 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT /** * @brief Gets the SD card info. - * @param hsd: Pointer to SD handle - * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that + * @param hsd Pointer to SD handle + * @param pCardInfo Pointer to the HAL_SD_CardInfoTypeDef structure that * will contain the SD card status information * @retval HAL status */ @@ -1955,8 +1955,8 @@ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeD /** * @brief Enables wide bus operation for the requested card if supported by * card. - * @param hsd: Pointer to SD handle - * @param WideMode: Specifies the SD card wide bus mode + * @param hsd Pointer to SD handle + * @param WideMode Specifies the SD card wide bus mode * This parameter can be one of the following values: * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer @@ -2032,7 +2032,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t /** * @brief Gets the current sd card data state. - * @param hsd: pointer to SD handle + * @param hsd pointer to SD handle * @retval Card state */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) @@ -2054,7 +2054,7 @@ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) /** * @brief Abort the current transfer and disable the SD. - * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * @param hsd pointer to a SD_HandleTypeDef structure that contains * the configuration information for SD module. * @retval HAL status */ @@ -2101,7 +2101,7 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) /** * @brief Abort the current transfer and disable the SD (IT mode). - * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * @param hsd pointer to a SD_HandleTypeDef structure that contains * the configuration information for SD module. * @retval HAL status */ @@ -2178,7 +2178,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) /** * @brief DMA SD transmit process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -2191,7 +2191,7 @@ static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SD receive process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -2224,7 +2224,7 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SD communication error callback -* @param hdma: DMA handle +* @param hdma DMA handle * @retval None */ static void SD_DMAError(DMA_HandleTypeDef *hdma) @@ -2259,7 +2259,7 @@ static void SD_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA SD Tx Abort callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) @@ -2296,7 +2296,7 @@ static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) /** * @brief DMA SD Rx Abort callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) @@ -2334,7 +2334,7 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) /** * @brief Initializes the sd card. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval SD Card error state */ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) @@ -2423,7 +2423,7 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) * @brief Enquires cards about their operating voltage and configures clock * controls and stores SD information that will be needed in future * in the SD handle. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval error state */ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) @@ -2524,7 +2524,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /** * @brief Turns the SDMMC output signals off. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval HAL status */ static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd) @@ -2537,8 +2537,8 @@ static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd) /** * @brief Send Status info command. - * @param hsd: pointer to SD handle - * @param pSDstatus: Pointer to the buffer that will contain the SD card status + * @param hsd pointer to SD handle + * @param pSDstatus Pointer to the buffer that will contain the SD card status * SD Status register) * @retval error state */ @@ -2639,8 +2639,8 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) /** * @brief Returns the current card's status. - * @param hsd: Pointer to SD handle - * @param pCardStatus: pointer to the buffer that will contain the SD card + * @param hsd Pointer to SD handle + * @param pCardStatus pointer to the buffer that will contain the SD card * status (Card Status register) * @retval error state */ @@ -2668,7 +2668,7 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) /** * @brief Enables the SDMMC wide bus mode. - * @param hsd: pointer to SD handle + * @param hsd pointer to SD handle * @retval error state */ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) @@ -2715,7 +2715,7 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) /** * @brief Disables the SDMMC wide bus mode. - * @param hsd: Pointer to SD handle + * @param hsd Pointer to SD handle * @retval error state */ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) @@ -2763,8 +2763,8 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) /** * @brief Finds the SD card SCR register value. - * @param hsd: Pointer to SD handle - * @param pSCR: pointer to the buffer that will contain the SCR value + * @param hsd Pointer to SD handle + * @param pSCR pointer to the buffer that will contain the SCR value * @retval error state */ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) @@ -2854,7 +2854,7 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /** * @brief Wrap up reading in non-blocking mode. - * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * @param hsd pointer to a SD_HandleTypeDef structure that contains * the configuration information. * @retval HAL status */ @@ -2878,7 +2878,7 @@ static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd) /** * @brief Wrap up writing in non-blocking mode. - * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * @param hsd pointer to a SD_HandleTypeDef structure that contains * the configuration information. * @retval HAL status */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c index 93c972e919..0af75da0cb 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c @@ -128,9 +128,9 @@ /** * @brief Performs the SDRAM device initialization sequence. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param Timing: Pointer to SDRAM control timing structure + * @param Timing Pointer to SDRAM control timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) @@ -166,7 +166,7 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy /** * @brief Perform the SDRAM device initialization sequence. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval HAL status */ @@ -189,7 +189,7 @@ HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) /** * @brief SDRAM MSP Init. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval None */ @@ -205,7 +205,7 @@ __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) /** * @brief SDRAM MSP DeInit. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval None */ @@ -221,7 +221,7 @@ __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) /** * @brief This function handles SDRAM refresh error interrupt request. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval HAL status */ @@ -240,7 +240,7 @@ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) /** * @brief SDRAM Refresh error callback. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval None */ @@ -256,7 +256,7 @@ __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -272,7 +272,7 @@ __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) @@ -305,11 +305,11 @@ __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) /** * @brief Reads 8-bit data buffer from the SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) @@ -346,11 +346,11 @@ HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddr /** * @brief Writes 8-bit data buffer to SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) @@ -390,11 +390,11 @@ HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /** * @brief Reads 16-bit data buffer from the SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) @@ -430,11 +430,11 @@ HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /** * @brief Writes 16-bit data buffer to SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) @@ -473,11 +473,11 @@ HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd /** * @brief Reads 32-bit data buffer from the SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) @@ -513,11 +513,11 @@ HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /** * @brief Writes 32-bit data buffer to SDRAM memory. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) @@ -556,11 +556,11 @@ HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd /** * @brief Reads a Words data from the SDRAM memory using DMA transfer. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) @@ -597,11 +597,11 @@ HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /** * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) @@ -657,7 +657,7 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd /** * @brief Enables dynamically SDRAM write protection. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval HAL status */ @@ -683,7 +683,7 @@ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) /** * @brief Disables dynamically SDRAM write protection. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval HAL status */ @@ -709,10 +709,10 @@ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) /** * @brief Sends Command to the SDRAM bank. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param Command: SDRAM command structure - * @param Timeout: Timeout duration + * @param Command SDRAM command structure + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) @@ -744,9 +744,9 @@ HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_C /** * @brief Programs the SDRAM Memory Refresh rate. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param RefreshRate: The SDRAM refresh rate value + * @param RefreshRate The SDRAM refresh rate value * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) @@ -771,9 +771,9 @@ HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint /** * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param AutoRefreshNumber: The SDRAM auto Refresh number + * @param AutoRefreshNumber The SDRAM auto Refresh number * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) @@ -798,7 +798,7 @@ HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, ui /** * @brief Returns the SDRAM memory current mode. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval The SDRAM memory mode. */ @@ -829,7 +829,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) /** * @brief Returns the SDRAM state. - * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval HAL state */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c index df15ad7d41..b0f0246136 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c @@ -1293,7 +1293,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /** * @brief Handle SMARTCARD interrupt requests. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ @@ -1657,7 +1657,7 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Configure the SMARTCARD associated USART peripheral. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ @@ -1755,7 +1755,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /** * @brief Configure the SMARTCARD associated USART peripheral advanced features. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ @@ -1817,7 +1817,7 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Check the SMARTCARD Idle State. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -2146,7 +2146,7 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Send an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() @@ -2219,7 +2219,7 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar /** * @brief Receive an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Receive_IT(). diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c index c63a491f02..e255a550d3 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c @@ -94,8 +94,8 @@ /** * @brief Update on the fly the SMARTCARD block length in RTOR register - * @param hsc: SMARTCARD handle - * @param BlockLength: SMARTCARD block length (8-bit long at most) + * @param hsc SMARTCARD handle + * @param BlockLength SMARTCARD block length (8-bit long at most) * @retval None */ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength) @@ -105,8 +105,8 @@ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t Bl /** * @brief Update on the fly the receiver timeout value in RTOR register - * @param hsc: SMARTCARD handle - * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout + * @param hsc SMARTCARD handle + * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout * value must be less or equal to 0x0FFFFFFFF. * @retval None */ @@ -118,7 +118,7 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeO /** * @brief Enable the SMARTCARD receiver timeout feature - * @param hsc: SMARTCARD handle + * @param hsc SMARTCARD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc) @@ -141,7 +141,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef /** * @brief Disable the SMARTCARD receiver timeout feature - * @param hsc: SMARTCARD handle + * @param hsc SMARTCARD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smbus.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smbus.c index f6c56a4661..185b027125 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smbus.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smbus.c @@ -170,6 +170,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus); static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); + static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} @@ -213,6 +215,9 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration of the selected SMBUSx peripheral. + (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and + HAL_SMBUS_ConfigDigitalFilter(). + @endverbatim * @{ */ @@ -227,7 +232,7 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) { /* Check the SMBUS handle allocation */ - if(hsmbus == NULL) + if (hsmbus == NULL) { return HAL_ERROR; } @@ -245,7 +250,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode)); assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode)); - if(hsmbus->State == HAL_SMBUS_STATE_RESET) + if (hsmbus->State == HAL_SMBUS_STATE_RESET) { /* Allocate lock resource and initialize it */ hsmbus->Lock = HAL_UNLOCKED; @@ -273,9 +278,9 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /* Configure SMBUSx: Own Address1 and ack own address1 mode */ hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - if(hsmbus->Init.OwnAddress1 != 0U) + if (hsmbus->Init.OwnAddress1 != 0U) { - if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) + if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) { hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); } @@ -287,7 +292,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ /* Configure SMBUSx: Addressing Master mode */ - if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) + if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) { hsmbus->Instance->CR2 = (I2C_CR2_ADD10); } @@ -304,8 +309,8 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ - if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) - && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) ) + if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) + && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) { hsmbus->Instance->CR1 |= I2C_CR1_SBC; } @@ -329,7 +334,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) { /* Check the SMBUS handle allocation */ - if(hsmbus == NULL) + if (hsmbus == NULL) { return HAL_ERROR; } @@ -349,7 +354,7 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; hsmbus->State = HAL_SMBUS_STATE_RESET; - /* Release Lock */ + /* Release Lock */ __HAL_UNLOCK(hsmbus); return HAL_OK; @@ -387,6 +392,104 @@ __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) */ } +/** + * @brief Configure Analog noise filter. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref SMBUS_ANALOGFILTER_ENABLE + * @arg @ref SMBUS_ANALOGFILTER_DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Reset ANOFF bit */ + hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hsmbus->Instance->CR1 |= AnalogFilter; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure Digital noise filter. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter) +{ + uint32_t tmpreg = 0U; + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Get the old register value */ + tmpreg = hsmbus->Instance->CR1; + + /* Reset I2C DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos; + + /* Store the new register value */ + hsmbus->Instance->CR1 = tmpreg; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + /** * @} */ @@ -416,7 +519,7 @@ __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) (++) HAL_SMBUS_Master_Receive_IT() (++) HAL_SMBUS_Slave_Transmit_IT() (++) HAL_SMBUS_Slave_Receive_IT() - (++) HAL_SMBUS_EnableListen_IT() + (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT() (++) HAL_SMBUS_DisableListen_IT() (++) HAL_SMBUS_EnableAlert_IT() (++) HAL_SMBUS_DisableAlert_IT() @@ -438,8 +541,8 @@ __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition @@ -450,7 +553,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); @@ -464,12 +567,12 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* In case of Quick command, remove autoend mode */ /* Manage the stop generation by software */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; } - if(Size > MAX_NBYTE_SIZE) + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -480,17 +583,17 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -499,12 +602,12 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -531,8 +634,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition @@ -543,7 +646,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); @@ -558,12 +661,12 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* In case of Quick command, remove autoend mode */ /* Manage the stop generation by software */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; } - if(Size > MAX_NBYTE_SIZE) + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -574,17 +677,17 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); } else { /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0)) { - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -593,7 +696,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); } } @@ -618,24 +721,24 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 * @note This abort can be called only if state is ready * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @retval HAL status */ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) { - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsmbus); /* Keep the same state as previous */ /* to perform as well the call of the corresponding end of transfer callback */ - if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) { hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; } - else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) { hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; } @@ -657,11 +760,11 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ /* Note : The SMBUS interrupts must be enabled after unlocking current process to avoid the risk of SMBUS interrupt handle execution before current process unlock */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); } @@ -688,9 +791,9 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -718,7 +821,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Convert OTHER_xxx XferOptions if any */ SMBUS_ConvertOtherXferOptions(hsmbus); - if(Size > MAX_NBYTE_SIZE) + if (Size > MAX_NBYTE_SIZE) { hsmbus->XferSize = MAX_NBYTE_SIZE; } @@ -728,18 +831,18 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 } /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) + if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount)) { - SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -748,7 +851,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the HOST */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -781,9 +884,9 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -817,7 +920,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ - if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) + if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET))) { SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } @@ -828,7 +931,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the HOST */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -872,7 +975,7 @@ HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) { /* Disable Address listen mode only if a transfer is not ongoing */ - if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { hsmbus->State = HAL_SMBUS_STATE_READY; @@ -927,8 +1030,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @brief Check if target device is ready for communication. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface + * @param DevAddress Target device address which contain device 7 bits address value + * in datasheet must be shifted to the left before calling the interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status @@ -939,9 +1042,9 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t __IO uint32_t SMBUS_Trials = 0U; - if(hsmbus->State == HAL_SMBUS_STATE_READY) + if (hsmbus->State == HAL_SMBUS_STATE_READY) { - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) { return HAL_BUSY; } @@ -955,16 +1058,16 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t do { /* Generate Start */ - hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress); + hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); - while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) + while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Device is ready */ hsmbus->State = HAL_SMBUS_STATE_READY; @@ -980,7 +1083,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) { /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -999,7 +1102,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t else { /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -1018,7 +1121,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t hsmbus->Instance->CR2 |= I2C_CR2_STOP; /* Wait until STOPF flag is reset */ - if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -1026,7 +1129,8 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } - }while(SMBUS_Trials < Trials); + } + while (SMBUS_Trials < Trials); hsmbus->State = HAL_SMBUS_STATE_READY; @@ -1063,7 +1167,7 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus); /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) @@ -1071,14 +1175,14 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) SMBUS_Slave_ISR(hsmbus); } /* Master mode selected */ - else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) { SMBUS_Master_ISR(hsmbus); } } /* SMBUS in mode Receiver ----------------------------------------------------*/ - if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) + if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) @@ -1086,15 +1190,15 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) SMBUS_Slave_ISR(hsmbus); } /* Master mode selected */ - else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Master_ISR(hsmbus); } } - /* SMBUS in mode Listener Only --------------------------------------------------*/ + /* SMBUS in mode Listener Only --------------------------------------------------*/ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) - && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) + && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) { if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) { @@ -1111,79 +1215,7 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) */ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) { - /* SMBUS Bus error interrupt occurred ------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); - } - - /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); - } - - /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); - } - - /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; - - /* Clear TIMEOUT flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); - } - - /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; - - /* Clear ALERT flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); - } - - /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; - - /* Clear PEC error flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); - } - - /* Call the Error Callback in case of Error detected */ - if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) - { - /* Do not Reset the HAL state in case of ALERT error */ - if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) - { - if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) - || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) - { - /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ - /* keep HAL_SMBUS_STATE_LISTEN if set */ - hsmbus->PreviousState = HAL_SMBUS_STATE_READY; - hsmbus->State = HAL_SMBUS_STATE_LISTEN; - } - } - - /* Call the Error callback to prevent upper layer */ - HAL_SMBUS_ErrorCallback(hsmbus); - } + SMBUS_ITErrorHandler(hsmbus); } /** @@ -1253,8 +1285,8 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) * @brief Slave Address Match callback. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. - * @param TransferDirection: Master request Transfer Direction (Write/Read) - * @param AddrMatchCode: Address Match Code + * @param TransferDirection Master request Transfer Direction (Write/Read) + * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) @@ -1369,7 +1401,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Locked */ __HAL_LOCK(hsmbus); - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); @@ -1381,13 +1413,16 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* Call the Error callback to prevent upper layer */ + /* Call the Error callback to inform upper layer */ HAL_SMBUS_ErrorCallback(hsmbus); } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) { + /* Check and treat errors if errors occurs during STOP process */ + SMBUS_ITErrorHandler(hsmbus); + /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); @@ -1413,15 +1448,15 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { /* Store Last receive data if any */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; - if((hsmbus->XferSize > 0U)) + if ((hsmbus->XferSize > 0U)) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1446,27 +1481,27 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) HAL_SMBUS_MasterRxCpltCallback(hsmbus); } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; hsmbus->XferSize--; hsmbus->XferCount--; } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR */ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); hsmbus->XferSize--; hsmbus->XferCount--; } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) { - if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) + if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) { DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD); - if(hsmbus->XferCount > MAX_NBYTE_SIZE) + if (hsmbus->XferCount > MAX_NBYTE_SIZE) { SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; @@ -1474,23 +1509,23 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; } } } - else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U)) + else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U)) { /* Call TxCpltCallback() if no stop mode is set */ - if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); @@ -1502,7 +1537,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); hsmbus->PreviousState = hsmbus->State; @@ -1516,24 +1551,24 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) } } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) { - if(hsmbus->XferCount == 0U) + if (hsmbus->XferCount == 0U) { /* Specific use case for Quick command */ - if(hsmbus->pBuffPtr == NULL) + if (hsmbus->pBuffPtr == NULL) { /* Generate a Stop command */ hsmbus->Instance->CR2 |= I2C_CR2_STOP; } /* Call TxCpltCallback() if no stop mode is set */ - else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ /* Call the corresponding callback to inform upper layer of End of Transfer */ - if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) { /* Disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); @@ -1545,7 +1580,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) HAL_SMBUS_MasterTxCpltCallback(hsmbus); } - else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) { SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); hsmbus->PreviousState = hsmbus->State; @@ -1579,13 +1614,13 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Locked */ __HAL_LOCK(hsmbus); - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) { /* Check that SMBUS transfer finished */ /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ - if(hsmbus->XferCount == 0U) + if (hsmbus->XferCount == 0U) { /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); @@ -1614,11 +1649,11 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* Call the Error callback to prevent upper layer */ + /* Call the Error callback to inform upper layer */ HAL_SMBUS_ErrorCallback(hsmbus); } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) { TransferDirection = SMBUS_GET_DIR(hsmbus); SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus); @@ -1633,24 +1668,24 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Call Slave Addr callback */ HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); } - else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) + else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) { - if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; hsmbus->XferSize--; hsmbus->XferCount--; - if(hsmbus->XferCount == 1U) + if (hsmbus->XferCount == 1U) { /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ /* or only the last Byte of Transfer */ /* So reset the RELOAD bit mode */ hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; - SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } - else if(hsmbus->XferCount == 0U) + else if (hsmbus->XferCount == 0U) { /* Last Byte is received, disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); @@ -1674,11 +1709,11 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; } } - else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) { - if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U)) + if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U)) { - if(hsmbus->XferCount > MAX_NBYTE_SIZE) + if (hsmbus->XferCount > MAX_NBYTE_SIZE) { SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; @@ -1689,7 +1724,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if (SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1698,13 +1733,13 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } } } - else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if(hsmbus->XferCount > 0U) + if (hsmbus->XferCount > 0U) { /* Write data to TXDR */ hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); @@ -1712,7 +1747,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) hsmbus->XferSize--; } - if(hsmbus->XferCount == 0U) + if (hsmbus->XferCount == 0U) { /* Last Byte is Transmitted */ /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ @@ -1729,17 +1764,17 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } /* Check if STOPF is set */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) { - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { /* Store Last receive data if any */ - if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) { /* Read data from RXDR */ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; - if((hsmbus->XferSize > 0U)) + if ((hsmbus->XferSize > 0U)) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1761,8 +1796,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - /* Clear ADDR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); + /* Clear ADDR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); hsmbus->XferOptions = 0U; hsmbus->PreviousState = hsmbus->State; @@ -1771,7 +1806,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */ + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ HAL_SMBUS_ListenCpltCallback(hsmbus); } } @@ -1792,25 +1827,25 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t { uint32_t tmpisr = 0U; - if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) + if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) { /* Enable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) { /* Enable ADDR, STOP interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI; } - if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) { /* Enable ERR, TC, STOP, NACK, RXI interrupt */ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI; } - if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) { /* Enable ERR, TC, STOP, NACK, TXI interrupt */ tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI; @@ -1834,56 +1869,56 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t { uint32_t tmpisr = 0U; - if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) ) + if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) { /* Disable TC, STOP, NACK, TXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; - if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) { /* Disable STOPI, NACKI */ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; } } - if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) { /* Disable TC, STOP, NACK, RXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; - if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) - && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; } - if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) { /* Disable STOPI, NACKI */ tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; } } - if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) { /* Enable ADDR, STOP interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; - if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; @@ -1897,6 +1932,92 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t return HAL_OK; } + +/** + * @brief SMBUS interrupts error handler. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) +{ + uint32_t itflags = READ_REG(hsmbus->Instance->ISR); + uint32_t itsources = READ_REG(hsmbus->Instance->CR1); + + /* SMBUS Bus error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); + } + + /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); + } + + /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); + } + + /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ + if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; + + /* Clear TIMEOUT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); + } + + /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ + if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; + + /* Clear ALERT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); + } + + /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ + if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; + + /* Clear PEC error flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); + } + + /* Call the Error Callback in case of Error detected */ + if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) + { + /* Do not Reset the HAL state in case of ALERT error */ + if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) + { + if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) + { + /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ + /* keep HAL_SMBUS_STATE_LISTEN if set */ + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_LISTEN; + } + } + + /* Call the Error callback to inform upper layer */ + HAL_SMBUS_ErrorCallback(hsmbus); + } +} + /** * @brief Handle SMBUS Communication Timeout. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains @@ -1911,17 +2032,17 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu uint32_t tickstart = HAL_GetTick(); /* Wait until flag is set */ - if(Status == RESET) + if (Status == RESET) { - while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) + while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hsmbus->PreviousState = hsmbus->State; - hsmbus->State= HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -1933,15 +2054,15 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu } else { - while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) + while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hsmbus->PreviousState = hsmbus->State; - hsmbus->State= HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -1976,25 +2097,14 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu */ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { - uint32_t tmpreg = 0U; - /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); assert_param(IS_SMBUS_TRANSFER_MODE(Mode)); assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); - /* Get the CR2 register value */ - tmpreg = hsmbus->Instance->CR2; - - /* clear tmpreg specific bits */ - tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)); - - /* update tmpreg */ - tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request); - /* update CR2 register */ - hsmbus->Instance->CR2 = tmpreg; + MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** @@ -2007,14 +2117,14 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ /* it request implicitly to generate a restart condition */ /* set XferOptions to SMBUS_FIRST_FRAME */ - if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC) + if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC) { hsmbus->XferOptions = SMBUS_FIRST_FRAME; } /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */ /* it request implicitly to generate a restart condition */ /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */ - else if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC) + else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC) { hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE; } @@ -2022,7 +2132,7 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) /* it request implicitly to generate a restart condition */ /* then generate a stop condition at the end of transfer */ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */ - else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) { hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC; } @@ -2030,7 +2140,7 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) /* it request implicitly to generate a restart condition */ /* then generate a stop condition at the end of transfer */ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */ - else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) { hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC; } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spdifrx.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spdifrx.c index 9d89161988..27f165a45e 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spdifrx.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spdifrx.c @@ -192,7 +192,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef * /** * @brief Initializes the SPDIFRX according to the specified parameters * in the SPDIFRX_InitTypeDef and create the associated handle. - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) @@ -262,7 +262,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) /** * @brief DeInitializes the SPDIFRX peripheral - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) @@ -297,7 +297,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) /** * @brief SPDIFRX MSP Init - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif) @@ -312,7 +312,7 @@ __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif) /** * @brief SPDIFRX MSP DeInit - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) @@ -328,8 +328,8 @@ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Sets the SPDIFRX dtat format according to the specified parameters * in the SPDIFRX_InitTypeDef. - * @param hspdif: SPDIFRX handle - * @param sDataFormat: SPDIFRX data format + * @param hspdif SPDIFRX handle + * @param sDataFormat SPDIFRX data format * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat) @@ -425,11 +425,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF /** * @brief Receives an amount of data (Data Flow) in blocking mode. - * @param hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains + * @param hspdif pointer to SPDIFRX_HandleTypeDef structure that contains * the configuration information for SPDIFRX module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) @@ -495,11 +495,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin /** * @brief Receives an amount of data (Control Flow) in blocking mode. - * @param hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains + * @param hspdif pointer to a SPDIFRX_HandleTypeDef structure that contains * the configuration information for SPDIFRX module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) @@ -565,9 +565,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, /** * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be received . + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample to be received . * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -634,9 +634,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, /** * @brief Receive an amount of data (Control Flow) with Interrupt - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample (Control Flow) to be received : + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample (Control Flow) to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -703,9 +703,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi /** * @brief Receive an amount of data (Data Flow) mode with DMA - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be received : + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -775,9 +775,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, /** * @brief Receive an amount of data (Control Flow) with DMA - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data (Control Flow) sample to be received : + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data (Control Flow) sample to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -847,7 +847,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd /** * @brief stop the audio stream receive from the Media. - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif) @@ -876,7 +876,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif) /** * @brief This function handles SPDIFRX interrupt request. - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL status */ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) @@ -922,7 +922,7 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Rx Transfer (Data flow) half completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -937,7 +937,7 @@ __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Rx Transfer (Data flow) completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -952,7 +952,7 @@ __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Rx (Control flow) Transfer half completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -967,7 +967,7 @@ __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Rx Transfer (Control flow) completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -982,7 +982,7 @@ __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) /** * @brief SPDIFRX error callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -1016,7 +1016,7 @@ and the data flow. /** * @brief Return the SPDIFRX state - * @param hspdif : SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL state */ HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif) @@ -1026,7 +1026,7 @@ HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Return the SPDIFRX error code - * @param hspdif : SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval SPDIFRX Error Code */ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif) @@ -1040,7 +1040,7 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif) /** * @brief DMA SPDIFRX receive process (Data flow) complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -1059,7 +1059,7 @@ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPDIFRX receive process (Data flow) half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1072,7 +1072,7 @@ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPDIFRX receive process (Control flow) complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) @@ -1089,7 +1089,7 @@ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPDIFRX receive process (Control flow) half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1101,7 +1101,7 @@ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPDIFRX communication error callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) @@ -1121,7 +1121,7 @@ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) /** * @brief Receive an amount of data (Data Flow) with Interrupt - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) @@ -1146,7 +1146,7 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) /** * @brief Receive an amount of data (Control Flow) with Interrupt - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) @@ -1171,11 +1171,11 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) /** * @brief This function handles SPDIFRX Communication Timeout. - * @param hspdif: SPDIFRX handle - * @param Flag: Flag checked - * @param Status: Value of the flag expected - * @param Timeout: Duration of the timeout - * @param tickstart: Tick start value + * @param hspdif SPDIFRX handle + * @param Flag Flag checked + * @param Status Value of the flag expected + * @param Timeout Duration of the timeout + * @param tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c index e5e0b24dca..8792849d22 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c @@ -256,7 +256,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ /** * @brief Initialize the SPI according to the specified parameters * in the SPI_InitTypeDef and initialize the associated handle. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -381,7 +381,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI peripheral. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -415,7 +415,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /** * @brief Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -431,7 +431,7 @@ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -484,11 +484,11 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) /** * @brief Transmit an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -642,11 +642,11 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /** * @brief Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -872,12 +872,12 @@ error : /** * @brief Transmit and Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received - * @param Timeout: Timeout duration + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, @@ -1156,10 +1156,10 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -1239,10 +1239,10 @@ error : /** * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -1343,11 +1343,11 @@ error : /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) @@ -1451,10 +1451,10 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -1560,11 +1560,11 @@ error : /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer + * @param pData pointer to data buffer * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -1676,12 +1676,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, @@ -2161,7 +2161,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /** * @brief Pause the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2181,7 +2181,7 @@ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) /** * @brief Resume the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2201,7 +2201,7 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) /** * @brief Stop the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -2232,7 +2232,7 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) /** * @brief Handle SPI interrupt request. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval None */ @@ -2328,7 +2328,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /** * @brief Tx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2344,7 +2344,7 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2360,7 +2360,7 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx and Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2376,7 +2376,7 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2392,7 +2392,7 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Rx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2408,7 +2408,7 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx and Rx Half Transfer callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2424,7 +2424,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief SPI error callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2477,7 +2477,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI handle state. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI state */ @@ -2489,7 +2489,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI error code. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI error code in bitmap format */ @@ -2514,7 +2514,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) /** * @brief DMA SPI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2561,7 +2561,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2652,7 +2652,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2737,7 +2737,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2750,7 +2750,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2763,7 +2763,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2776,7 +2776,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2934,7 +2934,7 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2984,7 +2984,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3016,7 +3016,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3062,7 +3062,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3096,7 +3096,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3120,7 +3120,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3158,7 +3158,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 8-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3183,7 +3183,7 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the receive 8-bit in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3216,7 +3216,7 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3239,7 +3239,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3272,7 +3272,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 8-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3296,7 +3296,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 16-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3322,12 +3322,12 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle SPI Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Flag: SPI flag to check - * @param State: flag state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, @@ -3374,12 +3374,12 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, /** * @brief Handle SPI FIFO Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Fifo: Fifo to check - * @param State: Fifo state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Fifo Fifo to check + * @param State Fifo state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, @@ -3435,10 +3435,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, /** * @brief Handle the check of the RX transaction complete. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval None. */ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) @@ -3472,9 +3472,9 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t /** * @brief Handle the check of the RXTX or TX transaction complete. - * @param hspi: SPI handle - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param hspi SPI handle + * @param Timeout Timeout duration + * @param Tickstart tick start value */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { @@ -3501,7 +3501,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ /** * @brief Handle the end of the RXTX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3558,7 +3558,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the RX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3600,7 +3600,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the TX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3639,7 +3639,7 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Rx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3681,7 +3681,7 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Tx or Rx/Tx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sram.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sram.c index d89fc0b20c..83312827f1 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sram.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sram.c @@ -128,10 +128,10 @@ /** * @brief Performs the SRAM device initialization sequence - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param Timing: Pointer to SRAM control timing structure - * @param ExtTiming: Pointer to SRAM extended mode timing structure + * @param Timing Pointer to SRAM control timing structure + * @param ExtTiming Pointer to SRAM extended mode timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) @@ -167,7 +167,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp /** * @brief Performs the SRAM device De-initialization sequence. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ @@ -189,7 +189,7 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) /** * @brief SRAM MSP Init. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -205,7 +205,7 @@ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) /** * @brief SRAM MSP DeInit. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -221,7 +221,7 @@ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -237,7 +237,7 @@ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) /** * @brief DMA transfer complete error callback. - * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains + * @param hdma pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ @@ -271,11 +271,11 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) /** * @brief Reads 8-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) @@ -307,11 +307,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress /** * @brief Writes 8-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) @@ -349,11 +349,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Reads 16-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) @@ -385,11 +385,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Writes 16-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) @@ -427,11 +427,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Reads 32-bit buffer from SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) @@ -461,11 +461,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Writes 32-bit buffer to SRAM memory. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) @@ -501,11 +501,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Reads a Words data from the SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to read start address - * @param pDstBuffer: Pointer to destination buffer - * @param BufferSize: Size of the buffer to read from memory + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) @@ -534,11 +534,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /** * @brief Writes a Words data buffer to SRAM memory using DMA transfer. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param pAddress: Pointer to write start address - * @param pSrcBuffer: Pointer to source buffer to write - * @param BufferSize: Size of the buffer to write to memory + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) @@ -592,7 +592,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /** * @brief Enables dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ @@ -615,7 +615,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) /** * @brief Disables dynamically SRAM write operation. - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ @@ -660,7 +660,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) /** * @brief Returns the SRAM controller state - * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains + * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL state */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c index 9786ee257a..82ab6bb365 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c @@ -92,6 +92,63 @@ HAL_TIM_DMABurst_WriteStart() HAL_TIM_DMABurst_ReadStart() + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Function @ref HAL_TIM_RegisterCallback() to register a callback. + @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) BreakCallback : TIM Break Callback. + + By default, after the Init and when the state is HAL_TIM_STATE_RESET + all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init/DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim ****************************************************************************** * @attention @@ -159,6 +216,7 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); + /** * @} */ @@ -192,7 +250,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -203,21 +261,33 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - + if(htim->State == HAL_TIM_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if(htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } - /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; @@ -232,7 +302,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM Base peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -245,9 +315,18 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if(htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -260,7 +339,7 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Base MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -276,7 +355,7 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Base MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -292,7 +371,7 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -316,7 +395,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -340,7 +419,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -361,7 +440,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -381,10 +460,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to peripheral. + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -428,7 +507,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /** * @brief Stops the TIM Base generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -478,7 +557,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -497,13 +576,25 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if(htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspDeInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } - /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; @@ -518,7 +609,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) /** * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -531,10 +622,19 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if(htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspDeInit(htim); - +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -546,7 +646,7 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -562,7 +662,7 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Output Compare MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -578,9 +678,9 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -611,9 +711,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -644,9 +744,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -711,9 +811,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -778,16 +878,16 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -898,9 +998,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -994,7 +1094,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1015,11 +1115,23 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) if(htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if(htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } - /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; @@ -1034,7 +1146,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1047,10 +1159,19 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if(htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspDeInit(htim); - +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1062,7 +1183,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM PWM MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1078,7 +1199,7 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM PWM MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1094,9 +1215,9 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the PWM signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1127,9 +1248,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the PWM signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1163,9 +1284,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1230,9 +1351,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1297,16 +1418,16 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1417,9 +1538,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1513,7 +1634,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1532,13 +1653,26 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if(htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } - + /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; @@ -1553,7 +1687,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1566,10 +1700,19 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if(htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspDeInit(htim); - +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1581,7 +1724,7 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM INput Capture MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1597,7 +1740,7 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Input Capture MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1613,9 +1756,9 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Input Capture measurement. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1640,9 +1783,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Input Capture measurement. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1667,9 +1810,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1727,9 +1870,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1788,16 +1931,16 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement on in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1904,9 +2047,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement on in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1994,9 +2137,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OnePulseMode: Select the One pulse mode. + * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. @@ -2018,13 +2161,26 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if(htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspDeInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } - + /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; @@ -2045,7 +2201,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /** * @brief DeInitializes the TIM One Pulse - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -2058,10 +2214,19 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if(htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_OnePulse_MspDeInit(htim); - +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2073,7 +2238,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM One Pulse MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2089,7 +2254,7 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM One Pulse MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2105,9 +2270,9 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2115,6 +2280,9 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and @@ -2139,9 +2307,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be disable. + * @param OutputChannel TIM Channels to be disable. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2149,6 +2317,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and @@ -2173,9 +2344,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2191,7 +2362,10 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ - + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -2213,9 +2387,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2223,6 +2397,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); @@ -2277,9 +2454,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ /** * @brief Initializes the TIM Encoder Interface and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Encoder Interface configuration structure + * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) @@ -2310,13 +2487,26 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); if(htim->State == HAL_TIM_STATE_RESET) - { + { /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if(htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } - + /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; @@ -2370,7 +2560,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /** * @brief DeInitializes the TIM Encoder interface - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -2383,10 +2573,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if(htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Encoder_MspDeInit(htim); - +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2398,7 +2597,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Encoder Interface MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2414,7 +2613,7 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2430,9 +2629,9 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Encoder Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2473,9 +2672,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM Encoder Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2517,9 +2716,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2566,9 +2765,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2618,16 +2817,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1: The destination Buffer address for IC1. - * @param pData2: The destination Buffer address for IC2. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) @@ -2739,9 +2938,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /** * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2807,7 +3006,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ /** * @brief This function handles TIM interrupts requests. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2825,13 +3024,22 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* Input capture event */ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } @@ -2846,14 +3054,23 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) - { + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } @@ -2868,13 +3085,22 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* Input capture event */ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } @@ -2889,13 +3115,22 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /* Input capture event */ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } @@ -2906,7 +3141,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ @@ -2915,7 +3154,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } } @@ -2925,7 +3169,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } @@ -2935,7 +3183,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ @@ -2944,7 +3196,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else HAL_TIMEx_CommutationCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } @@ -2975,10 +3231,10 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Output Compare configuration structure - * @param Channel: TIM Channels to be enabled. + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3045,10 +3301,10 @@ __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Input Capture configuration structure - * @param Channel: TIM Channels to be enabled. + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3142,10 +3398,10 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM PWM configuration structure - * @param Channel: TIM Channels to be enabled. + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3241,14 +3497,14 @@ __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_ /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM One Pulse configuration structure - * @param OutputChannel: TIM Channels to be enabled. + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel: TIM Channels to be enabled. + * @param InputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3354,9 +3610,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write. + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write. * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3377,7 +3633,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources. + * @param BurstRequestSrc TIM DMA Request sources. * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3386,8 +3642,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ @@ -3518,9 +3774,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM DMA Burst mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstRequestSrc: TIM DMA Request sources to disable + * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3579,9 +3835,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read. + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read. * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3602,7 +3858,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources. + * @param BurstRequestSrc TIM DMA Request sources. * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3611,8 +3867,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ @@ -3744,9 +4000,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Stop the DMA burst reading - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstRequestSrc: TIM DMA Request sources to disable. + * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3805,9 +4061,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu /** * @brief Generate a software event - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param EventSource: specifies the event source. + * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source @@ -3849,11 +4105,11 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS /** * @brief Configures the OCRef clear feature - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel. + * @param Channel specifies the TIM Channel. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3959,9 +4215,9 @@ __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_C /** * @brief Configures the clock source to be used - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ @@ -4111,9 +4367,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param TI1_Selection: Indicate whether or not channel 1 is connected to the + * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input @@ -4146,9 +4402,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S /** * @brief Configures the TIM in Slave mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4294,8 +4550,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI /** * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4330,9 +4586,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, /** * @brief Read the captured value from Capture Compare unit - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -4417,6 +4673,8 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) (+) Timer Input capture callback (+) Timer Trigger callback (+) Timer Error callback + (+) Timer_RegisterCallback + (+) Timer_UnRegisterCallback @endverbatim * @{ @@ -4424,7 +4682,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Period elapsed callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4440,7 +4698,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Output Compare callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4455,7 +4713,7 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Input Capture callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4471,7 +4729,7 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) /** * @brief PWM Pulse finished callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4487,7 +4745,7 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Trigger detection callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4503,7 +4761,7 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) /** * @brief Timer error callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4517,6 +4775,438 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) */ } +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htim); + + if(htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htim); + + if(htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = HAL_TIMEx_CommutationCallback; /* Legacy weak Commutation Callback */ + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /** * @} */ @@ -4538,7 +5228,7 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Base state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4549,7 +5239,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM OC state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4560,7 +5250,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM PWM state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4571,7 +5261,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Input Capture state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4582,7 +5272,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM One Pulse Mode state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4593,7 +5283,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Encoder Mode state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4608,7 +5298,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4617,13 +5307,16 @@ void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma) TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; htim->State= HAL_TIM_STATE_READY; - +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Delay Pulse complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4650,13 +5343,16 @@ void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else HAL_TIM_PWM_PulseFinishedCallback(htim); - +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Capture complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4682,31 +5378,36 @@ void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } - - HAL_TIM_IC_CaptureCallback(htim); - +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Period Elapse complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + htim->State= HAL_TIM_STATE_READY; - +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Trigger callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4715,14 +5416,17 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; htim->State= HAL_TIM_STATE_READY; - +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else HAL_TIM_TriggerCallback(htim); + #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief Time Base configuration - * @param TIMx: TIM peripheral - * @param Structure: pointer on TIM Time Base required parameters + * @param TIMx TIM peripheral + * @param Structure pointer on TIM Time Base required parameters * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) @@ -4770,7 +5474,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Time Output Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4835,7 +5539,7 @@ void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Output Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4902,7 +5606,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Output Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4968,7 +5672,7 @@ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Output Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -5024,9 +5728,9 @@ void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Output Compare 4 configuration - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sSlaveConfig: The slave configuration structure + * @param sSlaveConfig The slave configuration structure * @retval None */ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, @@ -5157,17 +5861,17 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 @@ -5212,12 +5916,12 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5247,17 +5951,17 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 @@ -5295,12 +5999,12 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5330,17 +6034,17 @@ uint32_t tmpccmr1 = 0; /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 @@ -5378,17 +6082,17 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 @@ -5426,7 +6130,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral - * @param TIM_ITRx: The Input Trigger source. + * @param TIM_ITRx The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 @@ -5455,17 +6159,17 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx) /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF. * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. + * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ @@ -5489,13 +6193,13 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 * @arg TIM_Channel_4: TIM Channel 4 - * @param ChannelState: specifies the TIM Channel CCxE bit new state. + * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. * @retval None */ @@ -5516,7 +6220,26 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat TIMx->CCER |= (uint32_t)(ChannelState << Channel); } - +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy week callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ + htim->CommutationCallback = HAL_TIMEx_CommutationCallback; /* Legacy weak CommutationCallback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c index f58f6574ec..9cfbc68c77 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c @@ -156,9 +156,9 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); */ /** * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Hall Sensor configuration structure + * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) @@ -179,12 +179,30 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if(htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIMEx_HallSensor_MspInit(htim); - + /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); @@ -231,7 +249,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen /** * @brief DeInitializes the TIM Hall Sensor interface - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -244,10 +262,19 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if(htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIMEx_HallSensor_MspDeInit(htim); - +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -259,7 +286,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Hall Sensor MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -275,7 +302,7 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -291,7 +318,7 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -313,7 +340,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall sensor Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -335,7 +362,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -360,7 +387,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -385,10 +412,10 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -435,7 +462,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -486,14 +513,13 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -517,14 +543,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -548,14 +573,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -616,14 +640,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -690,16 +713,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -808,14 +830,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -909,14 +930,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Starts the PWM signal generation on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -939,14 +959,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -970,14 +989,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1038,14 +1056,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1112,16 +1129,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1230,14 +1246,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1320,9 +1335,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complemetary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be enabled. + * @param OutputChannel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1346,9 +1361,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be disabled. + * @param OutputChannel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1376,9 +1391,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be enabled. + * @param OutputChannel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1408,9 +1423,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be disabled. + * @param OutputChannel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1471,16 +1486,16 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. + * @param CommutationSource the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1521,16 +1536,16 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. + * @param CommutationSource the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1575,16 +1590,16 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. + * @param CommutationSource the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1628,9 +1643,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM in master mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status @@ -1690,9 +1705,9 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @retval HAL status */ @@ -1717,8 +1732,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, /* Check input state */ __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ @@ -1757,12 +1770,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, #if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) /** * @brief Configures the break input source. - * @param htim: TIM handle. - * @param BreakInput: Break input to configure + * @param htim TIM handle. + * @param BreakInput Break input to configure * This parameter can be one of the following values: * @arg TIM_BREAKINPUT_BRK: Timer break input * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input - * @param sBreakInputConfig: Break input source configuration + * @param sBreakInputConfig Break input source configuration * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, @@ -1862,9 +1875,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Remap: specifies the TIM input remapping source. + * @param Remap specifies the TIM input remapping source. * This parameter can be one of the following values: * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. @@ -1901,8 +1914,8 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) /** * @brief Group channel 5 and channel 1, 2 or 3 - * @param htim: TIM handle. - * @param OCRef: specifies the reference signal(s) the OC5REF is combined with. + * @param htim TIM handle. + * @param OCRef specifies the reference signal(s) the OC5REF is combined with. * This parameter can be any combination of the following values: * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF @@ -1955,7 +1968,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRe /** * @brief Hall commutation changed callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1971,7 +1984,7 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Break detection callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2006,7 +2019,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Hall Sensor interface state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -2021,7 +2034,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA Commutation callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2030,8 +2043,12 @@ void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; htim->State= HAL_TIM_STATE_READY; - + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else HAL_TIMEx_CommutationCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @} @@ -2039,10 +2056,10 @@ void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) /** * @brief Configures the OCRef clear feature - * @param htim: TIM handle - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 @@ -2195,9 +2212,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM Output Compare handle - * @param sConfig: TIM Output Compare configuration structure - * @param Channel : TIM Channels to configure + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2295,9 +2312,9 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: TIM PWM handle - * @param sConfig: TIM PWM configuration structure - * @param Channel : TIM Channels to be configured + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2440,12 +2457,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 - * @param ChannelNState: specifies the TIM Channel CCxNE bit new state. + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ @@ -2469,7 +2486,7 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha /** * @brief Timer Output Compare 5 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -2521,7 +2538,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 6 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_alarm_template.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_alarm_template.c index 0106ad3fdb..e8b49a0268 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_alarm_template.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_alarm_template.c @@ -105,7 +105,7 @@ void RTC_Alarm_IRQHandler(void); * Tick interrupt priority. * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) @@ -261,7 +261,7 @@ void HAL_ResumeTick(void) * @note This function is called when RTC_ALARM interrupt took place, inside * RTC_ALARM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment * a global variable "uwTick" used as application time base. - * @param hrtc : RTC handle + * @param hrtc RTC handle * @retval None */ void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_wakeup_template.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_wakeup_template.c index d203843398..21c242401d 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_wakeup_template.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_wakeup_template.c @@ -112,7 +112,7 @@ void RTC_WKUP_IRQHandler(void); = 1 ms * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) @@ -263,7 +263,7 @@ void HAL_ResumeTick(void) * @note This function is called when RTC_WKUP interrupt took place, inside * RTC_WKUP_IRQHandler(). It makes a direct call to HAL_IncTick() to increment * a global variable "uwTick" used as application time base. - * @param hrtc : RTC handle + * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_tim_template.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_tim_template.c index 82b1a4b74f..fe3d3efd0e 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_tim_template.c @@ -65,7 +65,7 @@ void TIM6_DAC_IRQHandler(void); * Tick interrupt priority. * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) @@ -154,7 +154,7 @@ void HAL_ResumeTick(void) * @note This function is called when TIM6 interrupt took place, inside * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment * a global variable "uwTick" used as application time base. - * @param htim : TIM handle + * @param htim TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c index 55c4638413..93e4008b24 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c @@ -235,7 +235,7 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); /** * @brief Initializes the UART mode according to the specified * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: uart handle + * @param huart uart handle * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) @@ -298,7 +298,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /** * @brief Initializes the half-duplex mode according to the specified * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: UART handle + * @param huart UART handle * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) @@ -354,8 +354,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /** * @brief Initialize the LIN mode according to the specified * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: UART handle. - * @param BreakDetectLength: specifies the LIN break detection length. + * @param huart UART handle. + * @param BreakDetectLength specifies the LIN break detection length. * This parameter can be one of the following values: * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection @@ -422,9 +422,9 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /** * @brief Initialize the multiprocessor mode according to the specified * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart: UART handle. - * @param Address: UART node address (4-, 6-, 7- or 8-bit long). - * @param WakeUpMethod: specifies the UART wakeup method. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod specifies the UART wakeup method. * This parameter can be one of the following values: * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark @@ -497,16 +497,16 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /** * @brief Initialize the RS485 Driver enable feature according to the specified * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle. - * @param Polarity: select the driver enable polarity. + * @param huart UART handle. + * @param Polarity select the driver enable polarity. * This parameter can be one of the following values: * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high * @arg @ref UART_DE_POLARITY_LOW DE signal is active low - * @param AssertionTime: Driver Enable assertion time: + * @param AssertionTime Driver Enable assertion time: * 5-bit value defining the time between the activation of the DE (Driver Enable) * signal and the beginning of the start bit. It is expressed in sample time * units (1/8 or 1/16 bit time, depending on the oversampling rate) - * @param DeassertionTime: Driver Enable deassertion time: + * @param DeassertionTime Driver Enable deassertion time: * 5-bit value defining the time between the end of the last stop bit, in a * transmitted message, and the de-activation of the DE (Driver Enable) signal. * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the @@ -579,7 +579,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, /** * @brief DeInitializes the UART peripheral - * @param huart: uart handle + * @param huart uart handle * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) @@ -617,7 +617,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /** * @brief UART MSP Init - * @param huart: uart handle + * @param huart uart handle * @retval None */ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) @@ -632,7 +632,7 @@ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) /** * @brief UART MSP DeInit - * @param huart: uart handle + * @param huart uart handle * @retval None */ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) @@ -707,10 +707,10 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) /** * @brief Send an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: Pointer to data buffer. - * @param Size: Amount of data to be sent. - * @param Timeout: Timeout duration. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -776,10 +776,10 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. - * @param Timeout: Timeout duration. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -848,9 +848,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -889,9 +889,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -936,9 +936,9 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -999,9 +999,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /** * @brief Receive an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. * @note When the UART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). * @retval HAL status @@ -1066,7 +1066,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Pause the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) @@ -1099,7 +1099,7 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /** * @brief Resume the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) @@ -1137,7 +1137,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) /** * @brief Stop the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) @@ -1184,7 +1184,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) /** * @brief This function handles UART interrupt request. - * @param huart: uart handle + * @param huart uart handle * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) @@ -1360,7 +1360,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /** * @brief DMA UART transmit process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -1388,7 +1388,7 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART transmit process half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1400,7 +1400,7 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART receive process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -1428,7 +1428,7 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART receive process half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1440,7 +1440,7 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART communication error callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) @@ -1468,7 +1468,7 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA UART communication abort callback, when call by HAL services on Error * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) @@ -1482,7 +1482,7 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) /** * @brief Tx Transfer completed callbacks - * @param huart: uart handle + * @param huart uart handle * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) @@ -1497,7 +1497,7 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) /** * @brief Tx Half Transfer completed callbacks. - * @param huart: UART handle + * @param huart UART handle * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) @@ -1512,7 +1512,7 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) /** * @brief Rx Transfer completed callbacks - * @param huart: uart handle + * @param huart uart handle * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) @@ -1527,7 +1527,7 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Half Transfer completed callbacks. - * @param huart: UART handle + * @param huart UART handle * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) @@ -1542,7 +1542,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief UART error callbacks - * @param huart: uart handle + * @param huart uart handle * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) @@ -1559,7 +1559,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) * @brief Send an amount of data in interrupt mode * Function called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT() - * @param huart: UART handle + * @param huart UART handle * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) @@ -1606,7 +1606,7 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) /** * @brief Wrap up transmission in non-blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1627,7 +1627,7 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) * @brief Receive an amount of data in interrupt mode * Function called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart: UART handle + * @param huart UART handle * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) @@ -1679,7 +1679,7 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) /** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) @@ -1694,7 +1694,7 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) @@ -1740,7 +1740,7 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) /** * @brief Enable UART in mute mode (doesn't mean UART enters mute mode; * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called) - * @param huart: UART handle + * @param huart UART handle * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) @@ -1761,7 +1761,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) /** * @brief Disable UART mute mode (doesn't mean it actually wakes up the software, * as it may not have been in mute mode at this very moment). - * @param huart: uart handle + * @param huart uart handle * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) @@ -1782,7 +1782,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) /** * @brief Enter UART mute mode (means UART actually enters mute mode). * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. - * @param huart: uart handle + * @param huart uart handle * @retval HAL status */ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) @@ -1794,7 +1794,7 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) /** * @brief return the UART state - * @param huart: uart handle + * @param huart uart handle * @retval HAL state */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) @@ -1808,7 +1808,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) /** * @brief Return the UART error code -* @param huart : pointer to a UART_HandleTypeDef structure that contains +* @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code */ @@ -1819,7 +1819,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) /** * @brief Configure the UART peripheral - * @param huart: uart handle + * @param huart uart handle * @retval None */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) @@ -1930,7 +1930,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) /** * @brief Configure the UART peripheral advanced features - * @param huart: uart handle + * @param huart uart handle * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) @@ -2005,7 +2005,7 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) /** * @brief Check the UART Idle State - * @param huart: uart handle + * @param huart uart handle * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) @@ -2041,7 +2041,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /** * @brief Enables the UART transmitter and disables the UART receiver. - * @param huart: UART handle + * @param huart UART handle * @retval HAL status * @retval None */ @@ -2065,7 +2065,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) /** * @brief Enables the UART receiver and disables the UART transmitter. - * @param huart: UART handle + * @param huart UART handle * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) @@ -2089,7 +2089,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) /** * @brief Transmits break characters. - * @param huart: UART handle + * @param huart UART handle * @retval HAL status */ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) @@ -2120,8 +2120,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) * long). * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. - * @param huart: UART handle. - * @param AddressLength: this parameter can be one of the following values: + * @param huart UART handle. + * @param AddressLength this parameter can be one of the following values: * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address * @retval HAL status diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c index b6b263ae2c..af6e932da1 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c @@ -183,7 +183,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); /** * @brief Initializes the USART mode according to the specified * parameters in the USART_InitTypeDef and create the associated handle. - * @param husart: USART handle + * @param husart USART handle * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) @@ -231,7 +231,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /** * @brief DeInitializes the USART peripheral - * @param husart: USART handle + * @param husart USART handle * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) @@ -265,7 +265,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief USART MSP Init - * @param husart: USART handle + * @param husart USART handle * @retval None */ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) @@ -280,7 +280,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief USART MSP DeInit - * @param husart: USART handle + * @param husart USART handle * @retval None */ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) @@ -356,10 +356,10 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief Simplex Send an amount of data in blocking mode - * @param husart: USART handle - * @param pTxData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout : Timeout duration + * @param husart USART handle + * @param pTxData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) @@ -427,10 +427,10 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Receive an amount of data in blocking mode * @note To receive synchronous data, dummy data are simultaneously transmitted - * @param husart: USART handle - * @param pRxData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout : Timeout duration + * @param husart USART handle + * @param pRxData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) @@ -509,11 +509,11 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /** * @brief Full-Duplex Send and Receive an amount of data in blocking mode - * @param husart: USART handle - * @param pTxData: pointer to TX data buffer - * @param pRxData: pointer to RX data buffer - * @param Size: amount of data to be sent (same amount to be received) - * @param Timeout : Timeout duration + * @param husart USART handle + * @param pTxData pointer to TX data buffer + * @param pRxData pointer to RX data buffer + * @param Size amount of data to be sent (same amount to be received) + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) @@ -601,9 +601,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t /** * @brief Send an amount of data in interrupt mode - * @param husart: USART handle - * @param pTxData: pointer to data buffer - * @param Size: amount of data to be sent + * @param husart USART handle + * @param pTxData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) @@ -635,7 +635,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT __HAL_UNLOCK(husart); /* Enable the USART Transmit Data Register Empty Interrupt */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); return HAL_OK; } @@ -648,9 +648,9 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /** * @brief Receive an amount of data in blocking mode * To receive synchronous data, dummy data are simultaneously transmitted - * @param husart: USART handle - * @param pRxData: pointer to data buffer - * @param Size: amount of data to be received + * @param husart USART handle + * @param pRxData pointer to data buffer + * @param Size amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) @@ -703,10 +703,10 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /** * @brief Full-Duplex Send and Receive an amount of data in interrupt mode - * @param husart: USART handle - * @param pTxData: pointer to TX data buffer - * @param pRxData: pointer to RX data buffer - * @param Size: amount of data to be sent (same amount to be received) + * @param husart USART handle + * @param pTxData pointer to TX data buffer + * @param pRxData pointer to RX data buffer + * @param Size amount of data to be sent (same amount to be received) * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) @@ -759,9 +759,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /** * @brief Send an amount of data in DMA mode - * @param husart: USART handle - * @param pTxData: pointer to data buffer - * @param Size: amount of data to be sent + * @param husart USART handle + * @param pTxData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) @@ -821,9 +821,9 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p /** * @brief Receive an amount of data in DMA mode - * @param husart: USART handle - * @param pRxData: pointer to data buffer - * @param Size: amount of data to be received + * @param husart USART handle + * @param pRxData pointer to data buffer + * @param Size amount of data to be received * @note When the USART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position) * @retval HAL status @@ -912,10 +912,10 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /** * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode - * @param husart: USART handle - * @param pTxData: pointer to TX data buffer - * @param pRxData: pointer to RX data buffer - * @param Size: amount of data to be received/sent + * @param husart USART handle + * @param pTxData pointer to TX data buffer + * @param pRxData pointer to RX data buffer + * @param Size amount of data to be received/sent * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status */ @@ -1000,7 +1000,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /** * @brief Pauses the DMA Transfer. - * @param husart: USART handle + * @param husart USART handle * @retval None */ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) @@ -1037,7 +1037,7 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) /** * @brief Resumes the DMA Transfer. - * @param husart: USART handle + * @param husart USART handle * @retval None */ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) @@ -1082,7 +1082,7 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) /** * @brief Stops the DMA Transfer. - * @param husart: USART handle + * @param husart USART handle * @retval None */ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) @@ -1131,7 +1131,7 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) /** * @brief This function handles USART interrupt request. - * @param husart: USART handle + * @param husart USART handle * @retval None */ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) @@ -1279,7 +1279,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /** * @brief Tx Transfer completed callbacks - * @param husart: USART handle + * @param husart USART handle * @retval None */ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) @@ -1294,7 +1294,7 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx Half Transfer completed callbacks. - * @param husart: USART handle + * @param husart USART handle * @retval None */ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) @@ -1309,7 +1309,7 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Rx Transfer completed callbacks. - * @param husart: USART handle + * @param husart USART handle * @retval None */ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) @@ -1324,7 +1324,7 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) /** * @brief Rx Half Transfer completed callbacks - * @param husart: usart handle + * @param husart usart handle * @retval None */ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) @@ -1339,7 +1339,7 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) /** * @brief Tx/Rx Transfers completed callback for the non-blocking process - * @param husart: USART handle + * @param husart USART handle * @retval None */ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) @@ -1354,7 +1354,7 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) /** * @brief USART error callbacks - * @param husart: USART handle + * @param husart USART handle * @retval None */ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) @@ -1392,7 +1392,7 @@ __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) /** * @brief return the USART state - * @param husart: USART handle + * @param husart USART handle * @retval HAL state */ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) @@ -1402,7 +1402,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) /** * @brief Return the USART error code - * @param husart : pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART. * @retval USART Error Code */ @@ -1420,7 +1420,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) * @brief Simplex Send an amount of data in non-blocking mode. * @note Function called under interruption only, once * interruptions have been enabled by HAL_USART_Transmit_IT(). - * @param husart: USART handle + * @param husart USART handle * @retval HAL status * @note The USART errors are not managed to avoid the overrun error. */ @@ -1467,7 +1467,7 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) /** * @brief Wraps up transmission in non-blocking mode. - * @param husart: pointer to a USART_HandleTypeDef structure that contains + * @param husart pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ @@ -1490,7 +1490,7 @@ static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) * @brief Simplex Receive an amount of data in non-blocking mode. * Function called under interruption only, once * interruptions have been enabled by HAL_USART_Receive_IT() - * @param husart: USART handle + * @param husart USART handle * @retval HAL status */ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) @@ -1543,7 +1543,7 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). * Function called under interruption only, once * interruptions have been enabled by HAL_USART_TransmitReceive_IT() - * @param husart: USART handle + * @param husart USART handle * @retval HAL status */ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) @@ -1667,7 +1667,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar /** * @brief DMA USART transmit process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -1702,7 +1702,7 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA USART transmit process half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1714,7 +1714,7 @@ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA USART receive process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -1765,7 +1765,7 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA USART receive process half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1777,7 +1777,7 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA USART communication error callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void USART_DMAError(DMA_HandleTypeDef *hdma) @@ -1810,7 +1810,7 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA USART communication abort callback * (To be called at end of DMA Abort procedure). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) @@ -1824,7 +1824,7 @@ static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) /** * @brief End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion). - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ static void USART_EndTxTransfer(USART_HandleTypeDef *husart) @@ -1838,7 +1838,7 @@ static void USART_EndTxTransfer(USART_HandleTypeDef *husart) /** * @brief End ongoing Rx transfer on USART peripheral (following error detection or Reception completion). - * @param husart: USART handle. + * @param husart USART handle. * @retval None */ static void USART_EndRxTransfer(USART_HandleTypeDef *husart) @@ -1853,7 +1853,7 @@ static void USART_EndRxTransfer(USART_HandleTypeDef *husart) /** * @brief Configure the USART peripheral - * @param husart: USART handle + * @param husart USART handle * @retval None */ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) @@ -1935,7 +1935,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /** * @brief Check the USART Idle State - * @param husart: USART handle + * @param husart USART handle * @retval HAL status */ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma2d.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma2d.c index 2a59462757..63099dbd39 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma2d.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma2d.c @@ -170,7 +170,7 @@ ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) * @note DMA2D transfers must be disabled to set initialization bits in configuration registers, * otherwise ERROR result is returned. * @param DMA2Dx DMA2D Instance - * @param DMA2D_InitStruct: pointer to a LL_DMA2D_InitTypeDef structure + * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure * that contains the configuration information for the specified DMA2D peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content @@ -241,7 +241,7 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini /** * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value. - * @param DMA2D_InitStruct: pointer to a @ref LL_DMA2D_InitTypeDef structure + * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -268,9 +268,9 @@ void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct) * @brief Configure the foreground or background according to the specified parameters * in the LL_DMA2D_LayerCfgTypeDef structure. * @param DMA2Dx DMA2D Instance - * @param DMA2D_LayerCfg: pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains + * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains * the configuration information for the specified layer. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval None @@ -362,7 +362,7 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D /** * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value. - * @param DMA2D_LayerCfg: pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure + * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -390,7 +390,7 @@ void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg) * @brief Initialize DMA2D output color register according to the specified parameters * in DMA2D_ColorStruct. * @param DMA2Dx DMA2D Instance - * @param DMA2D_ColorStruct: pointer to a LL_DMA2D_ColorTypeDef structure that contains + * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains * the color configuration information for the specified DMA2D peripheral. * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c index 9c03fa6977..695a76a5e4 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c @@ -141,8 +141,8 @@ /** * @brief Initialize the FMC_NORSRAM device according to the specified * control parameters in the FMC_NORSRAM_InitTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Init: Pointer to NORSRAM Initialization structure + * @param Device Pointer to NORSRAM device instance + * @param Init Pointer to NORSRAM Initialization structure * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) @@ -217,9 +217,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini /** * @brief DeInitialize the FMC_NORSRAM peripheral - * @param Device: Pointer to NORSRAM device instance - * @param ExDevice: Pointer to NORSRAM extended mode device instance - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param ExDevice Pointer to NORSRAM extended mode device instance + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) @@ -254,9 +254,9 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EX /** * @brief Initialize the FMC_NORSRAM Timing according to the specified * parameters in the FMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) @@ -308,9 +308,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR /** * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified * parameters in the FMC_NORSRAM_TimingTypeDef - * @param Device: Pointer to NORSRAM device instance - * @param Timing: Pointer to NORSRAM Timing structure - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) @@ -377,8 +377,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef /** * @brief Enables dynamically FMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) @@ -395,8 +395,8 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, /** * @brief Disables dynamically FMC_NORSRAM write operation. - * @param Device: Pointer to NORSRAM device instance - * @param Bank: NORSRAM bank number + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) @@ -464,8 +464,8 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device /** * @brief Initializes the FMC_NAND device according to the specified * control parameters in the FMC_NAND_HandleTypeDef - * @param Device: Pointer to NAND device instance - * @param Init: Pointer to NAND Initialization structure + * @param Device Pointer to NAND device instance + * @param Init Pointer to NAND Initialization structure * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) @@ -508,9 +508,9 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * /** * @brief Initializes the FMC_NAND Common space Timing according to the specified * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) @@ -547,9 +547,9 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC /** * @brief Initializes the FMC_NAND Attribute space Timing according to the specified * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device: Pointer to NAND device instance - * @param Timing: Pointer to NAND timing structure - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) @@ -584,8 +584,8 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, /** * @brief DeInitializes the FMC_NAND device - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) @@ -628,8 +628,8 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) /** * @brief Enables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) @@ -647,8 +647,8 @@ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) /** * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param Bank: NAND bank number + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) @@ -665,10 +665,10 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) /** * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device: Pointer to NAND device instance - * @param ECCval: Pointer to ECC value - * @param Bank: NAND bank number - * @param Timeout: Timeout wait value + * @param Device Pointer to NAND device instance + * @param ECCval Pointer to ECC value + * @param Bank NAND bank number + * @param Timeout Timeout wait value * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) @@ -751,8 +751,8 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui /** * @brief Initializes the FMC_SDRAM device according to the specified * control parameters in the FMC_SDRAM_InitTypeDef - * @param Device: Pointer to SDRAM device instance - * @param Init: Pointer to SDRAM Initialization structure + * @param Device Pointer to SDRAM device instance + * @param Init Pointer to SDRAM Initialization structure * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) @@ -831,9 +831,9 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe /** * @brief Initializes the FMC_SDRAM device timing according to the specified * parameters in the FMC_SDRAM_TimingTypeDef - * @param Device: Pointer to SDRAM device instance - * @param Timing: Pointer to SDRAM Timing structure - * @param Bank: SDRAM bank number + * @param Device Pointer to SDRAM device instance + * @param Timing Pointer to SDRAM Timing structure + * @param Bank SDRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) @@ -903,7 +903,7 @@ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Tim /** * @brief DeInitializes the FMC_SDRAM peripheral - * @param Device: Pointer to SDRAM device instance + * @param Device Pointer to SDRAM device instance * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) @@ -943,8 +943,8 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) /** * @brief Enables dynamically FMC_SDRAM write protection. - * @param Device: Pointer to SDRAM device instance - * @param Bank: SDRAM bank number + * @param Device Pointer to SDRAM device instance + * @param Bank SDRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) @@ -961,7 +961,7 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, ui /** * @brief Disables dynamically FMC_SDRAM write protection. - * @param hsdram: FMC_SDRAM handle + * @param hsdram FMC_SDRAM handle * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) @@ -978,16 +978,15 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, u /** * @brief Send Command to the FMC SDRAM bank - * @param Device: Pointer to SDRAM device instance - * @param Command: Pointer to SDRAM command structure - * @param Timing: Pointer to SDRAM Timing structure - * @param Timeout: Timeout wait value + * @param Device Pointer to SDRAM device instance + * @param Command Pointer to SDRAM command structure + * @param Timing Pointer to SDRAM Timing structure + * @param Timeout Timeout wait value * @retval HAL state */ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) { __IO uint32_t tmpr = 0; - uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -1004,30 +1003,14 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Com ); Device->SDCMR = tmpr; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* wait until command is send */ - while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } return HAL_OK; } /** * @brief Program the SDRAM Memory Refresh rate. - * @param Device: Pointer to SDRAM device instance - * @param RefreshRate: The SDRAM refresh rate value. + * @param Device Pointer to SDRAM device instance + * @param RefreshRate The SDRAM refresh rate value. * @retval HAL state */ HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) @@ -1044,8 +1027,8 @@ HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32 /** * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. - * @param Device: Pointer to SDRAM device instance - * @param AutoRefreshNumber: Specifies the auto Refresh number. + * @param Device Pointer to SDRAM device instance + * @param AutoRefreshNumber Specifies the auto Refresh number. * @retval None */ HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) @@ -1062,8 +1045,8 @@ HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint /** * @brief Returns the indicated FMC SDRAM bank mode status. - * @param Device: Pointer to SDRAM device instance - * @param Bank: Defines the FMC SDRAM bank. This parameter can be + * @param Device Pointer to SDRAM device instance + * @param Bank Defines the FMC SDRAM bank. This parameter can be * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. * @retval The FMC SDRAM bank mode status, could be on of the following values: * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c index 2941e15930..87f5beed00 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c @@ -207,7 +207,7 @@ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) /** * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. * @param GPIOx GPIO Port - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * that contains the configuration information for the specified GPIO peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content @@ -284,7 +284,7 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /** * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * whose fields will be set to default values. * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c index 06e64515f2..93bae62e20 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c @@ -166,7 +166,7 @@ uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void); * @brief Reset the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source - * - HSE and PLL OFF + * - HSE, PLL, PLLI2S, PLLSAI OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO OFF * - All interrupts disabled @@ -179,24 +179,20 @@ uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void); */ ErrorStatus LL_RCC_DeInit(void) { - uint32_t vl_mask = 0U; + uint32_t vl_mask = 0xFFFFFFFFU; /* Set HSION bit */ LL_RCC_HSI_Enable(); + /* Wait for HSI READY bit */ + while(LL_RCC_HSI_IsReady() != 1U) + {} + /* Reset CFGR register */ LL_RCC_WriteReg(CFGR, 0x00000000U); - vl_mask = 0xFFFFFFFFU; - - /* Reset HSEON, PLLSYSON bits */ - CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON)); - - /* Reset PLLSAION bit */ - CLEAR_BIT(vl_mask, RCC_CR_PLLSAION); - - /* Reset PLLI2SON bit */ - CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON); + /* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */ + CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION | RCC_CR_PLLI2SON)); /* Write new mask in CR register */ LL_RCC_WriteReg(CR, vl_mask); @@ -204,6 +200,18 @@ ErrorStatus LL_RCC_DeInit(void) /* Set HSITRIM bits to the reset value*/ LL_RCC_HSI_SetCalibTrimming(0x10U); + /* Wait for PLL READY bit to be reset */ + while(LL_RCC_PLL_IsReady() != 0U) + {} + + /* Wait for PLLI2S READY bit to be reset */ + while(LL_RCC_PLLI2S_IsReady() != 0U) + {} + + /* Wait for PLLSAI READY bit to be reset */ + while(LL_RCC_PLLSAI_IsReady() != 0U) + {} + /* Reset PLLCFGR register */ LL_RCC_WriteReg(PLLCFGR, 0x24003010U); @@ -213,11 +221,17 @@ ErrorStatus LL_RCC_DeInit(void) /* Reset PLLSAICFGR register */ LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U); - /* Reset HSEBYP bit */ - LL_RCC_HSE_DisableBypass(); - /* Disable all interrupts */ - LL_RCC_WriteReg(CIR, 0x00000000U); + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE); + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC); + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); return SUCCESS; } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rtc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rtc.c index 7ecabbd8d7..5029a83dcb 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rtc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rtc.c @@ -382,7 +382,7 @@ void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) * @param RTC_Format This parameter can be one of the following values: * @arg @ref LL_RTC_FORMAT_BIN * @arg @ref LL_RTC_FORMAT_BCD - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains * the date configuration information for the RTC. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Day register is configured diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c index ef1bdcf5e2..3ea5950735 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c @@ -220,8 +220,8 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ /** * @brief Initializes the SDMMC according to the specified * parameters in the SDMMC_InitTypeDef and create the associated handle. - * @param SDMMCx: Pointer to SDMMC register base - * @param Init: SDMMC initialization structure + * @param SDMMCx Pointer to SDMMC register base + * @param Init SDMMC initialization structure * @retval HAL status */ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) @@ -274,7 +274,7 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) /** * @brief Read data (word) from Rx FIFO in blocking mode (polling) - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) @@ -285,8 +285,8 @@ uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) /** * @brief Write data (word) to Tx FIFO in blocking mode (polling) - * @param SDMMCx: Pointer to SDMMC register base - * @param pWriteData: pointer to data to write + * @param SDMMCx Pointer to SDMMC register base + * @param pWriteData pointer to data to write * @retval HAL status */ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) @@ -318,7 +318,7 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) /** * @brief Set SDMMC Power state to ON. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) @@ -331,7 +331,7 @@ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) /** * @brief Set SDMMC Power state to OFF. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) @@ -344,7 +344,7 @@ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) /** * @brief Get SDMMC Power state. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval Power status of the controller. The returned value can be one of the * following values: * - 0x00: Power OFF @@ -359,8 +359,8 @@ uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) /** * @brief Configure the SDMMC command path according to the specified parameters in * SDMMC_CmdInitTypeDef structure and send the command - * @param SDMMCx: Pointer to SDMMC register base - * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains + * @param SDMMCx Pointer to SDMMC register base + * @param Command pointer to a SDMMC_CmdInitTypeDef structure that contains * the configuration information for the SDMMC command * @retval HAL status */ @@ -391,7 +391,7 @@ HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef /** * @brief Return the command index of last command for which response received - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval Command index of the last command response received */ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) @@ -402,8 +402,8 @@ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) /** * @brief Return the response received from the card for the last command - * @param SDMMCx: Pointer to SDMMC register base - * @param Response: Specifies the SDMMC response register. + * @param SDMMCx Pointer to SDMMC register base + * @param Response Specifies the SDMMC response register. * This parameter can be one of the following values: * @arg SDMMC_RESP1: Response Register 1 * @arg SDMMC_RESP2: Response Register 2 @@ -427,8 +427,8 @@ uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) /** * @brief Configure the SDMMC data path according to the specified * parameters in the SDMMC_DataInitTypeDef. - * @param SDMMCx: Pointer to SDMMC register base - * @param Data : pointer to a SDMMC_DataInitTypeDef structure + * @param SDMMCx Pointer to SDMMC register base + * @param Data pointer to a SDMMC_DataInitTypeDef structure * that contains the configuration information for the SDMMC data. * @retval HAL status */ @@ -464,7 +464,7 @@ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* /** * @brief Returns number of remaining data bytes to be transferred. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval Number of remaining data bytes to be transferred */ uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) @@ -474,7 +474,7 @@ uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) /** * @brief Get the FIFO data - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval Data received */ uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) @@ -484,8 +484,8 @@ uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) /** * @brief Sets one of the two options of inserting read wait interval. - * @param SDMMCx: Pointer to SDMMC register base - * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode. + * @param SDMMCx Pointer to SDMMC register base + * @param SDMMC_ReadWaitMode SDMMC Read Wait operation mode. * This parameter can be: * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2 @@ -523,7 +523,7 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM /** * @brief Send the Data Block Lenght command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) @@ -547,7 +547,7 @@ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) /** * @brief Send the Read Single Block command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) @@ -571,7 +571,7 @@ uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) /** * @brief Send the Read Multi Block command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) @@ -595,7 +595,7 @@ uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) /** * @brief Send the Write Single Block command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) @@ -619,7 +619,7 @@ uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) /** * @brief Send the Write Multi Block command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) @@ -643,7 +643,7 @@ uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) /** * @brief Send the Start Address Erase command for SD and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) @@ -667,7 +667,7 @@ uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) /** * @brief Send the End Address Erase command for SD and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) @@ -691,7 +691,7 @@ uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) /** * @brief Send the Start Address Erase command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) @@ -715,7 +715,7 @@ uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) /** * @brief Send the End Address Erase command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) @@ -739,7 +739,7 @@ uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) /** * @brief Send the Erase command and check the response - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) @@ -763,7 +763,7 @@ uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) /** * @brief Send the Stop Transfer command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) @@ -787,8 +787,8 @@ uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) /** * @brief Send the Select Deselect command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @param addr: Address of the card to be selected + * @param SDMMCx Pointer to SDMMC register base + * @param addr Address of the card to be selected * @retval HAL status */ uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) @@ -812,7 +812,7 @@ uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) /** * @brief Send the Go Idle State command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) @@ -835,7 +835,7 @@ uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) /** * @brief Send the Operating Condition command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) @@ -865,7 +865,7 @@ uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) * @brief Send the Application command to verify that that the next command * is an application specific com-mand rather than a standard command * and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) @@ -892,7 +892,7 @@ uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Send the command asking the accessed card to send its operating * condition register (OCR) - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType) @@ -915,7 +915,7 @@ uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType) /** * @brief Send the Bus Width command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) @@ -938,7 +938,7 @@ uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) /** * @brief Send the Send SCR command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) @@ -962,7 +962,7 @@ uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) /** * @brief Send the Send CID command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) @@ -986,7 +986,7 @@ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) /** * @brief Send the Send CSD command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) @@ -1010,7 +1010,7 @@ uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Send the Send CSD command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) @@ -1034,7 +1034,7 @@ uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) /** * @brief Send the Status command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) @@ -1057,7 +1057,7 @@ uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Send the Status register command and check the response. - * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMCx Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) @@ -1081,8 +1081,8 @@ uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) /** * @brief Sends host capacity support information and activates the card's * initialization process. Send SDMMC_CMD_SEND_OP_COND command - * @param SDIOx: Pointer to SDIO register base - * @parame Argument: Argument used for the command + * @param SDIOx Pointer to SDIO register base + * @parame Argument Argument used for the command * @retval HAL status */ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) @@ -1105,8 +1105,8 @@ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand - * @param SDIOx: Pointer to SDIO register base - * @parame Argument: Argument used for the command + * @param SDIOx Pointer to SDIO register base + * @parame Argument Argument used for the command * @retval HAL status */ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) @@ -1138,7 +1138,7 @@ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Checks for error conditions for CMD0. - * @param hsd: SD handle + * @param hsd SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) @@ -1164,8 +1164,8 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) /** * @brief Checks for error conditions for R1 response. - * @param hsd: SD handle - * @param SD_CMD: The sent command index + * @param hsd SD handle + * @param SD_CMD The sent command index * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout) @@ -1294,7 +1294,7 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ /** * @brief Checks for error conditions for R2 (CID or CSD) response. - * @param hsd: SD handle + * @param hsd SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) @@ -1336,7 +1336,7 @@ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) /** * @brief Checks for error conditions for R3 (OCR) response. - * @param hsd: SD handle + * @param hsd SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) @@ -1372,9 +1372,9 @@ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) /** * @brief Checks for error conditions for R6 (RCA) response. - * @param hsd: SD handle - * @param SD_CMD: The sent command index - * @param pRCA: Pointer to the variable that will contain the SD card relative + * @param hsd SD handle + * @param SD_CMD The sent command index + * @param pRCA Pointer to the variable that will contain the SD card relative * address RCA * @retval SD Card error state */ @@ -1442,7 +1442,7 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ /** * @brief Checks for error conditions for R7 response. - * @param hsd: SD handle + * @param hsd SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c index ac863dc3ca..d7b65c2356 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c @@ -547,7 +547,7 @@ void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). * @param SPIx SPI Instance - * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF. + * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. * @param PrescalerParity This parameter can be one of the following values: * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN * @arg @ref LL_I2S_PRESCALER_PARITY_ODD diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c index 77aead523e..7b5a3b876d 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c @@ -76,8 +76,10 @@ #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 27000000U) /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ -#define IS_LL_USART_BRR(__VALUE__) (((__VALUE__) >= 16U) \ - && ((__VALUE__) <= 0x0000FFFFU)) +#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) + +/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ +#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ || ((__VALUE__) == LL_USART_DIRECTION_RX) \ @@ -225,7 +227,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). * @param USARTx USART Instance - * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure + * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure * that contains the configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers are initialized according to USART_InitStruct content @@ -330,7 +332,10 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini USART_InitStruct->BaudRate); /* Check BRR is greater than or equal to 16d */ - assert_param(IS_LL_USART_BRR(USARTx->BRR)); + assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); + + /* Check BRR is greater than or equal to 16d */ + assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); } } /* Endif (=> USART not in Disabled state => return ERROR) */ @@ -340,7 +345,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /** * @brief Set each @ref LL_USART_InitTypeDef field to default value. - * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure + * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -363,7 +368,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @param USARTx USART Instance - * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * that contains the Clock configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content @@ -424,7 +429,7 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef /** * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. - * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * whose fields will be set to default values. * @retval None */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c index 330903d089..02af81a3fd 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c @@ -94,8 +94,8 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx); /** * @brief Initializes the USB Core - * @param USBx: USB Instance - * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -170,7 +170,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /** * @brief USB_EnableGlobalInt * Enables the controller's Global Int in the AHB Config reg - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) @@ -183,7 +183,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_DisableGlobalInt * Disable the controller's Global Int in the AHB Config reg - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) @@ -194,8 +194,8 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_SetCurrentMode : Set functional mode - * @param USBx : Selected device - * @param mode : current core mode + * @param USBx Selected device + * @param mode current core mode * This parameter can be one of these values: * @arg USB_OTG_DEVICE_MODE: Peripheral mode * @arg USB_OTG_HOST_MODE: Host mode @@ -222,8 +222,8 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeT /** * @brief USB_DevInit : Initializes the USB_OTG controller registers * for device mode - * @param USBx : Selected device - * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -369,8 +369,8 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /** * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO - * @param USBx : Selected device - * @param num : FIFO number + * @param USBx Selected device + * @param num FIFO number * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status @@ -396,7 +396,7 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) /** * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) @@ -420,8 +420,8 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register * depending the PHY type and the enumeration speed of the device. - * @param USBx : Selected device - * @param speed : device speed + * @param USBx Selected device + * @param speed device speed * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode @@ -437,7 +437,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) /** * @brief USB_GetDevSpeed :Return the Dev Speed - * @param USBx : Selected device + * @param USBx Selected device * @retval speed : device speed * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode @@ -467,8 +467,8 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) /** * @brief Activate and configure an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -498,8 +498,8 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy } /** * @brief Activate and configure a dedicated endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -541,8 +541,8 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB } /** * @brief De-activate and de-initialize an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -565,8 +565,8 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP /** * @brief De-activate and de-initialize a dedicated endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -587,9 +587,9 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U /** * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -709,9 +709,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe /** * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -796,11 +796,11 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD /** * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel - * @param USBx : Selected device - * @param src : pointer to source buffer - * @param ch_ep_num : endpoint or host channel number - * @param len : Number of bytes to write - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -824,11 +824,11 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin /** * @brief USB_ReadPacket : read a packet from the Tx FIFO associated * with the EP/channel - * @param USBx : Selected device - * @param src : source pointer - * @param ch_ep_num : endpoint or host channel number - * @param len : Number of bytes to read - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param src source pointer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to read + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -849,8 +849,8 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) /** * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) @@ -877,8 +877,8 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef /** * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -904,7 +904,7 @@ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe /** * @brief USB_StopDevice : Stop the usb device mode - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) @@ -933,8 +933,8 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_SetDevAddress : Stop the usb device mode - * @param USBx : Selected device - * @param address : new device address to be assigned + * @param USBx Selected device + * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ @@ -948,7 +948,7 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t addre /** * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) @@ -961,7 +961,7 @@ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) @@ -974,7 +974,7 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) @@ -988,7 +988,7 @@ uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) @@ -1001,7 +1001,7 @@ uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) @@ -1014,8 +1014,8 @@ uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) /** * @brief Returns Device OUT EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number + * @param USBx Selected device + * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ @@ -1029,8 +1029,8 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) /** * @brief Returns Device IN EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number + * @param USBx Selected device + * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ @@ -1047,8 +1047,8 @@ uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) /** * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx : Selected device - * @param interrupt : interrupt flag + * @param USBx Selected device + * @param interrupt interrupt flag * @retval None */ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) @@ -1058,7 +1058,7 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) /** * @brief Returns USB core mode - * @param USBx : Selected device + * @param USBx Selected device * @retval return core mode : Host or Device * This parameter can be one of these values: * 0 : Host @@ -1072,7 +1072,7 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) /** * @brief Activate EP0 for Setup transactions - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) @@ -1092,12 +1092,12 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) /** * @brief Prepare the EP0 to start the first control setup - * @param USBx : Selected device - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used - * @param psetup : pointer to setup packet + * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) @@ -1120,7 +1120,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin /** * @brief Reset the USB Core (needed after USB clock settings change) - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) @@ -1157,7 +1157,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) /** * @brief Enables control of a High Speed USB PHY’s * Init the low level hardware : GPIO, CLOCK, NVIC... - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx) @@ -1219,8 +1219,8 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_HostInit : Initializes the USB OTG controller registers * for Host mode - * @param USBx : Selected device - * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -1299,8 +1299,8 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef /** * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the * HCFG register on the PHY type and set the right frame interval - * @param USBx : Selected device - * @param freq : clock frequency + * @param USBx Selected device + * @param freq clock frequency * This parameter can be one of these values: * HCFG_48_MHZ : Full Speed 48 MHz Clock * HCFG_6_MHZ : Low Speed 6 MHz Clock @@ -1324,7 +1324,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq /** * @brief USB_OTG_ResetPort : Reset Host Port - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status * @note : (1)The application must wait at least 10 ms * before clearing the reset bit. @@ -1348,7 +1348,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_DriveVbus : activate or de-activate vbus - * @param state : VBUS state + * @param state VBUS state * This parameter can be one of these values: * 0 : VBUS Active * 1 : VBUS Inactive @@ -1376,7 +1376,7 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) /** * @brief Return Host Core speed - * @param USBx : Selected device + * @param USBx Selected device * @retval speed : Host speed * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode @@ -1393,7 +1393,7 @@ uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) /** * @brief Return Host Current Frame number - * @param USBx : Selected device + * @param USBx Selected device * @retval current frame number */ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) @@ -1403,25 +1403,25 @@ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) /** * @brief Initialize a host channel - * @param USBx : Selected device - * @param ch_num : Channel number + * @param USBx Selected device + * @param ch_num Channel number * This parameter can be a value from 1 to 15 - * @param epnum : Endpoint number + * @param epnum Endpoint number * This parameter can be a value from 1 to 15 - * @param dev_address : Current device address + * @param dev_address Current device address * This parameter can be a value from 0 to 255 - * @param speed : Current device speed + * @param speed Current device speed * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @arg USB_OTG_SPEED_LOW: Low speed mode - * @param ep_type : Endpoint Type + * @param ep_type Endpoint Type * This parameter can be one of these values: * @arg EP_TYPE_CTRL: Control type * @arg EP_TYPE_ISOC: Isochronous type * @arg EP_TYPE_BULK: Bulk type * @arg EP_TYPE_INTR: Interrupt type - * @param mps : Max Packet Size + * @param mps Max Packet Size * This parameter can be a value from 0 to32K * @retval HAL state */ @@ -1517,9 +1517,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, /** * @brief Start a transfer over a host channel - * @param USBx : Selected device - * @param hc : pointer to host channel structure - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param hc pointer to host channel structure + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -1585,6 +1585,16 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe /* Set host channel enable */ tmpreg = USBx_HC(hc->ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in) + { + tmpreg |= USB_OTG_HCCHAR_EPDIR; + } + else + { + tmpreg &= ~USB_OTG_HCCHAR_EPDIR; + } tmpreg |= USB_OTG_HCCHAR_CHENA; USBx_HC(hc->ch_num)->HCCHAR = tmpreg; @@ -1633,7 +1643,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe /** * @brief Read all host channel interrupts status - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL state */ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) @@ -1643,8 +1653,8 @@ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) /** * @brief Halt a host channel - * @param USBx : Selected device - * @param hc_num : Host Channel number + * @param USBx Selected device + * @param hc_num Host Channel number * This parameter can be a value from 1 to 15 * @retval HAL state */ @@ -1706,8 +1716,8 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) /** * @brief Initiate Do Ping protocol - * @param USBx : Selected device - * @param hc_num : Host Channel number + * @param USBx Selected device + * @param hc_num Host Channel number * This parameter can be a value from 1 to 15 * @retval HAL state */ @@ -1730,7 +1740,7 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) /** * @brief Stop Host Core - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL state */ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 379be2a3e9..610c4ab514 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -5,7 +5,7 @@ * STM32F2: 1.2.2 * STM32F3: 1.5.0 * STM32F4: 1.7.3 - * STM32F7: 1.2.3 + * STM32F7: 1.2.4 * STM32L0: 1.8.2 * STM32L1: 1.3.1 * STM32L4: 1.8.2 From 09211600486b2b06d6dc831c61e9f7a2eb92f3a8 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 24 Jan 2018 11:17:58 +0100 Subject: [PATCH 8/9] Updated STM32F7xx CMSIS to v1.2.2 Included in STM32CubeF7 FW V1.9.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32F7xx/Include/stm32f723xx.h | 47 ++++++++++++++----- .../Device/ST/STM32F7xx/Include/stm32f733xx.h | 47 ++++++++++++++----- .../Device/ST/STM32F7xx/Include/stm32f7xx.h | 4 +- .../Device/ST/STM32F7xx/Release_Notes.html | 7 ++- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 5 files changed, 76 insertions(+), 31 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h index 1a8a71282d..3c65ad03b7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h @@ -14634,16 +14634,22 @@ typedef struct #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!

            Update History

            -

            V1.2.1 +

            V1.2.2 +/ 26-December-2017

            Main +Changes

            +
            • Update bits definition for USBPHYC_PLL1 and USBPHYC_LDO registers to be inline with products documentation.

            V1.2.1 / 25-August-2017

            Main Changes

            -
            • Update FLASHSIZE_BASE and UID_BASE defined values for STM32F72x and STM32F73x devices.
            • Update stm32f7xx.h to include stm32f7xx_hal.h file instead of stm32f7xx_hal_conf.h file
            • Remove Date and Version from header files

            V1.2.0 +
            • Update FLASHSIZE_BASE and UID_BASE defined values for STM32F72x and STM32F73x devices.
            • Update stm32f7xx.h to include stm32f7xx_hal.h file instead of stm32f7xx_hal_conf.h file
            • Remove Date and Version from header files

            V1.2.0 / 30-December-2016

            Main Changes

            • Add the support of STM32F722xx, STM32F723xx, STM32F732xx and STM32F733xx devices
              • Add "stm32f722xx.h", "stm32f723xx.h", "stm32f732xx.h" and "stm32f733xx.h" header files
              • Add startup files "startup_stm32f722xx.s", "startup_stm32f723xx.s", "startup_stm32f732xx.s" and "startup_stm32f733xx.s" for EWARM, MDK-ARM and SW4STM32 toolchains
              • Add Linker files "stm32f722xx_flash.icf", "stm32f722xx_sram.icf" and "stm32f722xx_ITCM_flash.icf" used within EWARM Workspaces
              • Add Linker files "stm32f723xx_flash.icf", "stm32f723xx_sram.icf" and "stm32f723xx_ITCM_flash.icf" used within EWARM Workspaces
              • Add Linker files "stm32f732xx_flash.icf", "stm32f732xx_sram.icf" and "stm32f732xx_ITCM_flash.icf" used within EWARM Workspaces
              • Add Linker files "stm32f733xx_flash.icf", "stm32f733xx_sram.icf" and "stm32f733xx_ITCM_flash.icf" used within EWARM Workspaces
            • All devices header files
              • Use _Pos and _Mask macro for all Bit Definitions
              • Use DAC1 instance instead of DAC
              • Add IS_SMBUS_ALL_INSTANCE macro
              • Add ADC123_COMMON instance
              • Add DMA_SxPAR_PA, DMA_SxM0AR_M0A and DMA_SxM1AR_M1A registers Bits Definition
              • Add DBGMCU_APB1_FZ_DBG_LPTIM1_STOP and DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT Bits Definition
              • Add FLASH_OTP_BASE and FLASH_OTP_END defines
              • Add MACDBGR register Bits Definition
              • Add GPIO_AFRL and GPIO_AFRH registers Bits Definition 
              • Add TIM2_OR, TIM5_OR and TIM11_OR registers Bits Definition
              • Add TIM1_AF1_BKINP Bit Definition for TIM1_AF1 register
              • Add diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 1b81cc0269..96d6b9e57f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -5,7 +5,7 @@ * STM32F2: 2.2.1 * STM32F3: 2.3.2 * STM32F4: 2.6.2 - * STM32F7: 1.2.1 + * STM32F7: 1.2.2 * STM32L0: 1.7.2 * STM32L1: 2.2.3 * STM32L4: 1.4.2 From 8726db2067f9887008297514670bbab972654276 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 24 Jan 2018 11:26:45 +0100 Subject: [PATCH 9/9] Updated stm32f7xx_hal_conf.h in variant Signed-off-by: Frederic Pillon --- variants/DISCO_F746NG/stm32f7xx_hal_conf.h | 79 +++++++++++----------- 1 file changed, 41 insertions(+), 38 deletions(-) diff --git a/variants/DISCO_F746NG/stm32f7xx_hal_conf.h b/variants/DISCO_F746NG/stm32f7xx_hal_conf.h index edce6b06d8..8b6a92a455 100644 --- a/variants/DISCO_F746NG/stm32f7xx_hal_conf.h +++ b/variants/DISCO_F746NG/stm32f7xx_hal_conf.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_conf_template.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32f7xx_hal_conf.h. @@ -55,50 +53,51 @@ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED #define HAL_CAN_MODULE_ENABLED -// #define HAL_CEC_MODULE_ENABLED -// #define HAL_CRC_MODULE_ENABLED -// #define HAL_CRYP_MODULE_ENABLED +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ #define HAL_DAC_MODULE_ENABLED -// #define HAL_DCMI_MODULE_ENABLED +/* #define HAL_DCMI_MODULE_ENABLED */ #define HAL_DMA_MODULE_ENABLED -// #define HAL_DMA2D_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ #define HAL_ETH_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED -// #define HAL_NAND_MODULE_ENABLED -// #define HAL_NOR_MODULE_ENABLED -// #define HAL_SRAM_MODULE_ENABLED -// #define HAL_SDRAM_MODULE_ENABLED -// #define HAL_HASH_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED -// #define HAL_I2S_MODULE_ENABLED -// #define HAL_IWDG_MODULE_ENABLED -// #define HAL_LPTIM_MODULE_ENABLED -// #define HAL_LTDC_MODULE_ENABLED +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ #define HAL_PWR_MODULE_ENABLED -// #define HAL_QSPI_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ #define HAL_RCC_MODULE_ENABLED -// #define HAL_RNG_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ #define HAL_RTC_MODULE_ENABLED -// #define HAL_SAI_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ #define HAL_SD_MODULE_ENABLED -// #define HAL_SPDIFRX_MODULE_ENABLED +/* #define HAL_SPDIFRX_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED -// #define HAL_USART_MODULE_ENABLED -// #define HAL_IRDA_MODULE_ENABLED -// #define HAL_SMARTCARD_MODULE_ENABLED -// #define HAL_WWDG_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ #define HAL_CORTEX_MODULE_ENABLED #define HAL_PCD_MODULE_ENABLED #define HAL_HCD_MODULE_ENABLED -// #define HAL_DFSDM_MODULE_ENABLED -// #define HAL_DSI_MODULE_ENABLED -// #define HAL_JPEG_MODULE_ENABLED -// #define HAL_MDIOS_MODULE_ENABLED -// #define HAL_SMBUS_MODULE_ENABLED -// #define HAL_MMC_MODULE_ENABLED +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ /* ########################## HSE/HSI Values adaptation ##################### */ @@ -162,8 +161,8 @@ #define VDD_VALUE 3300U /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ #define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */ +#define PREFETCH_ENABLE 1U /* To enable prefetch */ +#define ART_ACCLERATOR_ENABLE 1U /* To enable ART Accelerator */ /* ########################## Assert Selection ############################## */ /** @@ -187,8 +186,8 @@ /* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB (4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB (4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ +#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ /* Section 2: PHY configuration section */ /* LAN8742A PHY Address*/ @@ -203,8 +202,8 @@ /* Section 3: Common PHY Registers */ -#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ +#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ #define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ @@ -271,6 +270,10 @@ #include "stm32f7xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f7xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CEC_MODULE_ENABLED #include "stm32f7xx_hal_cec.h" #endif /* HAL_CEC_MODULE_ENABLED */ @@ -435,7 +438,7 @@ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function + * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source * line number of the call that failed. * If expr is true, it returns no value. @@ -445,7 +448,7 @@ /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t* file, uint32_t line); #else - #define assert_param(expr) ((void)0) + #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */