From 6b81de1da9138e256bbc0057d924a011ea23e19d Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 11 Apr 2023 14:35:22 +0200 Subject: [PATCH 1/2] fix(GNSE): add missing LSE config prevents RTC to be properly initialized within STM32LoRaWAN. Signed-off-by: Frederic Pillon --- .../variant_GENERIC_NODE_SE_TTI.cpp | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_GENERIC_NODE_SE_TTI.cpp b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_GENERIC_NODE_SE_TTI.cpp index fec1879805..4b2a342057 100644 --- a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_GENERIC_NODE_SE_TTI.cpp +++ b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_GENERIC_NODE_SE_TTI.cpp @@ -70,15 +70,20 @@ WEAK void SystemClock_Config(void) RCC_OscInitTypeDef RCC_OscInitStruct = {}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); /** Configure the main internal regulator output voltage */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /** Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); @@ -94,7 +99,7 @@ WEAK void SystemClock_Config(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { Error_Handler(); } } @@ -102,4 +107,4 @@ WEAK void SystemClock_Config(void) #ifdef __cplusplus } #endif -#endif /* ARDUINO_GENERIC_* */ +#endif /* ARDUINO_GENERIC_NODE_SE_TTI */ From 97d0273ed3ae87643bc72024fd63634a4c680331 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 11 Apr 2023 14:42:16 +0200 Subject: [PATCH 2/2] chore(GNSE): moved to LoRa menu Signed-off-by: Frederic Pillon --- boards.txt | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/boards.txt b/boards.txt index 0f74df728b..8d6ccd1461 100644 --- a/boards.txt +++ b/boards.txt @@ -9772,15 +9772,6 @@ GenWL.build.flash_offset=0x0 GenWL.upload.maximum_size=0 GenWL.upload.maximum_data_size=0 -# Generic node SE by The Things Industries -GenWL.menu.pnum.GENERIC_NODE_SE_TTI=Generic Node SE (TTI) -GenWL.menu.pnum.GENERIC_NODE_SE_TTI.upload.maximum_size=262144 -GenWL.menu.pnum.GENERIC_NODE_SE_TTI.upload.maximum_data_size=65536 -GenWL.menu.pnum.GENERIC_NODE_SE_TTI.build.board=GENERIC_NODE_SE_TTI -GenWL.menu.pnum.GENERIC_NODE_SE_TTI.build.product_line=STM32WL55xx -GenWL.menu.pnum.GENERIC_NODE_SE_TTI.build.variant_h=variant_GENERIC_NODE_SE_TTI.h -GenWL.menu.pnum.GENERIC_NODE_SE_TTI.build.variant=STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U - # Generic WL54CCUx GenWL.menu.pnum.GENERIC_WL54CCUX=Generic WL54CCUx GenWL.menu.pnum.GENERIC_WL54CCUX.upload.maximum_size=262144 @@ -10465,6 +10456,19 @@ LoRa.menu.pnum.ACSIP_S76S.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS LoRa.menu.pnum.ACSIP_S76S.build.cmsis_lib_gcc=arm_cortexM0l_math LoRa.menu.pnum.ACSIP_S76S.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 +# Generic node SE by The Things Industries +LoRa.menu.pnum.GENERIC_NODE_SE_TTI=Generic Node SE (TTI) +LoRa.menu.pnum.GENERIC_NODE_SE_TTI.upload.maximum_size=262144 +LoRa.menu.pnum.GENERIC_NODE_SE_TTI.upload.maximum_data_size=65536 +LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.mcu=cortex-m4 +LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.board=GENERIC_NODE_SE_TTI +LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.series=STM32WLxx +LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.product_line=STM32WL55xx +LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.variant=STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U +LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.variant_h=variant_GENERIC_NODE_SE_TTI.h +LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.cmsis_lib_gcc=arm_cortexM4l_math +LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.st_extra_flags=-D{build.product_line} -DUSE_CM4_STARTUP_FILE {build.xSerial} + # LORA_E5_MINI board LoRa.menu.pnum.LORA_E5_MINI=LoRa-E5 mini LoRa.menu.pnum.LORA_E5_MINI.upload.maximum_size=262144 @@ -10478,7 +10482,6 @@ LoRa.menu.pnum.LORA_E5_MINI.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS LoRa.menu.pnum.LORA_E5_MINI.build.variant_h=variant_LORA_E5_MINI.h LoRa.menu.pnum.LORA_E5_MINI.build.cmsis_lib_gcc=arm_cortexM4l_math - # RAK811_TRACKER board LoRa.menu.pnum.RAK811_TRACKER=RAK811 LoRa Tracker (16kb RAM) LoRa.menu.pnum.RAK811_TRACKER.upload.maximum_size=131072