From 0f6d78aa3505300768f28d5a1cf8d9ad1148d691 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 5 Apr 2023 08:50:33 +0200 Subject: [PATCH] system(WB) update STM32WBxx HAL Drivers to v1.13.0 Included in STM32CubeWB FW v1.16.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 404 +++++++++++++-- .../STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h | 4 +- .../Inc/stm32wbxx_hal_cortex.h | 22 +- .../Inc/stm32wbxx_hal_dma.h | 166 +++--- .../Inc/stm32wbxx_hal_flash.h | 120 +++-- .../Inc/stm32wbxx_hal_flash_ex.h | 1 - .../Inc/stm32wbxx_hal_gpio.h | 2 +- .../Inc/stm32wbxx_hal_gpio_ex.h | 34 +- .../Inc/stm32wbxx_hal_i2c.h | 11 +- .../Inc/stm32wbxx_hal_ipcc.h | 32 +- .../Inc/stm32wbxx_hal_pwr.h | 86 ++-- .../Inc/stm32wbxx_hal_pwr_ex.h | 130 ++--- .../Inc/stm32wbxx_hal_rcc_ex.h | 86 ++-- .../Inc/stm32wbxx_hal_sai.h | 8 +- .../Inc/stm32wbxx_hal_smbus.h | 4 +- .../Inc/stm32wbxx_hal_tsc.h | 12 +- .../Inc/stm32wbxx_ll_bus.h | 60 +-- .../Inc/stm32wbxx_ll_cortex.h | 3 +- .../Inc/stm32wbxx_ll_dma.h | 168 +++--- .../Inc/stm32wbxx_ll_dmamux.h | 82 +-- .../Inc/stm32wbxx_ll_gpio.h | 2 +- .../Inc/stm32wbxx_ll_i2c.h | 120 ++--- .../Inc/stm32wbxx_ll_ipcc.h | 3 +- .../Inc/stm32wbxx_ll_pwr.h | 124 ++--- .../Inc/stm32wbxx_ll_rcc.h | 108 ++-- .../Inc/stm32wbxx_ll_utils.h | 12 +- .../STM32WBxx_HAL_Driver/Release_Notes.html | 116 +++-- .../STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c | 4 +- .../Src/stm32wbxx_hal_cortex.c | 8 +- .../Src/stm32wbxx_hal_dma.c | 34 +- .../Src/stm32wbxx_hal_dma_ex.c | 9 +- .../Src/stm32wbxx_hal_flash.c | 23 +- .../Src/stm32wbxx_hal_flash_ex.c | 45 +- .../Src/stm32wbxx_hal_i2c.c | 380 +++++++++----- .../Src/stm32wbxx_hal_ipcc.c | 64 ++- .../Src/stm32wbxx_hal_pwr.c | 184 +++---- .../Src/stm32wbxx_hal_pwr_ex.c | 477 +++++++++--------- .../Src/stm32wbxx_hal_rcc.c | 2 +- .../Src/stm32wbxx_hal_smbus.c | 29 +- ...tm32wbxx_hal_timebase_rtc_alarm_template.c | 333 +++++++----- ...m32wbxx_hal_timebase_rtc_wakeup_template.c | 245 +++++---- .../Src/stm32wbxx_hal_timebase_tim_template.c | 132 +++-- .../Src/stm32wbxx_hal_tsc.c | 6 +- .../Src/stm32wbxx_hal_uart.c | 75 ++- .../Src/stm32wbxx_ll_dma.c | 78 +-- .../Src/stm32wbxx_ll_gpio.c | 2 +- .../Src/stm32wbxx_ll_i2c.c | 4 +- .../Src/stm32wbxx_ll_pwr.c | 18 +- .../Src/stm32wbxx_ll_rcc.c | 2 +- .../Src/stm32wbxx_ll_utils.c | 109 ++-- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 51 files changed, 2445 insertions(+), 1740 deletions(-) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 73380827d7..8d702ae5f0 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -113,6 +113,9 @@ extern "C" { #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 #endif /* STM32U5 */ +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ /** * @} */ @@ -140,7 +143,8 @@ extern "C" { #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) @@ -239,10 +243,12 @@ extern "C" { /** @defgroup CRC_Aliases CRC API aliases * @{ */ -#if defined(STM32C0) +#if defined(STM32H5) || defined(STM32C0) #else -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ #endif /** * @} @@ -285,7 +291,13 @@ extern "C" { #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -350,7 +362,8 @@ extern "C" { #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING -#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI #endif @@ -582,6 +595,106 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + /** * @} */ @@ -649,14 +762,16 @@ extern "C" { #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS -#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ #endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH @@ -678,8 +793,10 @@ extern "C" { #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32H5) #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ @@ -694,7 +811,23 @@ extern "C" { #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI #define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB #endif /* STM32U5 */ - +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ /** * @} */ @@ -875,7 +1008,8 @@ extern "C" { #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX @@ -1109,6 +1243,26 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32H5) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA */ + #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK @@ -1119,12 +1273,12 @@ extern "C" { #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 */ +#endif /* STM32F7 || STM32H7 || STM32L0 */ /** * @} @@ -1291,7 +1445,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) || defined(STM32MP2) +#if defined(STM32U5) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -1404,30 +1558,40 @@ extern "C" { #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ #endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ @@ -1598,7 +1762,8 @@ extern "C" { #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ - )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1607,8 +1772,10 @@ extern "C" { #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode @@ -1642,16 +1809,21 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ - )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA @@ -1776,6 +1948,17 @@ extern "C" { #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP @@ -1784,6 +1967,8 @@ extern "C" { #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY @@ -1794,6 +1979,7 @@ extern "C" { #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK #endif @@ -1802,6 +1988,20 @@ extern "C" { * @} */ +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA */ + +/** + * @} + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ @@ -1827,7 +2027,8 @@ extern "C" { #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback @@ -2084,7 +2285,8 @@ extern "C" { #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) @@ -2256,8 +2458,10 @@ extern "C" { /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ /** * @} */ @@ -2416,7 +2620,9 @@ extern "C" { #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE @@ -2425,8 +2631,12 @@ extern "C" { #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 @@ -2462,8 +2672,8 @@ extern "C" { #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -3436,7 +3646,8 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3581,6 +3792,92 @@ extern "C" { #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE #endif /* STM32U5 */ +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + /** * @} */ @@ -3597,9 +3894,9 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ - defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32C0) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3652,6 +3949,11 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h index 2c2375ceed..7c39315860 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h @@ -534,13 +534,13 @@ typedef enum (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) -#if defined(STM32WB15xx) +#if defined(STM32WB15xx) || defined(STM32WB10xx) #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU)) #define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x0000000FU)) #else #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU)) #define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__) IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) -#endif /* STM32WB15xx */ +#endif /* STM32WB15xx || STM32WB10xx */ #if defined(VREFBUF) #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cortex.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cortex.h index 57c0ac9bc9..8664363cc9 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cortex.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cortex.h @@ -48,27 +48,27 @@ extern "C" { */ typedef struct { - uint8_t Enable; /*!< Specifies the status of the region. + uint8_t Enable; /*!< Specifies the status of the region. This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ - uint8_t Number; /*!< Specifies the number of the region to protect. + uint8_t Number; /*!< Specifies the number of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Number */ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint8_t Size; /*!< Specifies the size of the region to protect. + uint8_t Size; /*!< Specifies the size of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Size */ - uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint8_t TypeExtField; /*!< Specifies the TEX field level. This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ - uint8_t AccessPermission; /*!< Specifies the region access permission type. + uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ - uint8_t DisableExec; /*!< Specifies the instruction access status. + uint8_t DisableExec; /*!< Specifies the instruction access status. This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ - uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ - uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ - uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ } MPU_Region_InitTypeDef; /** @@ -213,8 +213,8 @@ typedef struct /** * @} */ - -/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_dma.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_dma.h index cb5716bd0f..d46cd6fbc4 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_dma.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_dma.h @@ -403,29 +403,29 @@ typedef struct __DMA_HandleTypeDef #if defined(DMA2) #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ DMA_FLAG_TC7) #else #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ DMA_FLAG_TC7) -#endif +#endif /* DMA2 */ /** * @brief Return the current DMA Channel half transfer complete flag. @@ -434,29 +434,29 @@ typedef struct __DMA_HandleTypeDef */ #if defined(DMA2) #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ DMA_FLAG_HT7) #else #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ DMA_FLAG_HT7) -#endif +#endif /* DMA2 */ /** * @brief Return the current DMA Channel transfer error flag. @@ -465,29 +465,29 @@ typedef struct __DMA_HandleTypeDef */ #if defined(DMA2) #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ DMA_FLAG_TE7) #else #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ DMA_FLAG_TE7) -#endif +#endif /* DMA2 */ /** * @brief Return the current DMA Channel Global interrupt flag. @@ -496,29 +496,29 @@ typedef struct __DMA_HandleTypeDef */ #if defined(DMA2) #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ DMA_ISR_GIF7) #else #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ + (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ DMA_ISR_GIF7) -#endif +#endif /* DMA2 */ /** * @brief Get the DMA Channel pending flags. @@ -534,10 +534,10 @@ typedef struct __DMA_HandleTypeDef */ #if defined(DMA2) #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ - (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) + (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) #else #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) -#endif +#endif /* DMA2 */ /** * @brief Clear the DMA Channel pending flags. @@ -553,10 +553,10 @@ typedef struct __DMA_HandleTypeDef */ #if defined(DMA2) #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ - (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) + (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) #else #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) -#endif +#endif /* DMA2 */ /** * @brief Enable the specified DMA Channel interrupts. @@ -629,10 +629,12 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h index 605e4f2dc4..012de7626c 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h @@ -112,8 +112,8 @@ typedef struct } FLASH_OBProgramInitTypeDef; /** -* @brief FLASH handle Structure definition -*/ + * @brief FLASH handle Structure definition + */ typedef struct { HAL_LockTypeDef Lock; /* FLASH locking object */ @@ -282,7 +282,7 @@ typedef struct #define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */ #if defined(FLASH_OPTR_IRHEN) #define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN /*!< Internal reset holder enable */ -#endif +#endif /* FLASH_OPTR_IRHEN */ #define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ #define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */ #define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */ @@ -294,7 +294,7 @@ typedef struct #define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */ #if defined(FLASH_OPTR_nRST_MODE) #define OB_USER_NRST_MODE FLASH_OPTR_nRST_MODE /*!< Reset pin configuration */ -#endif +#endif /* FLASH_OPTR_nRST_MODE */ #define OB_USER_AGC_TRIM FLASH_OPTR_AGC_TRIM /*!< Automatic Gain Control Trimming */ #if defined(FLASH_OPTR_IRHEN) && defined(FLASH_OPTR_nRST_MODE) #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ @@ -309,7 +309,7 @@ typedef struct OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \ OB_USER_SRAM2PE | OB_USER_SRAM2RST | OB_USER_nSWBOOT0 | \ OB_USER_nBOOT0 | OB_USER_AGC_TRIM) /*!< all option bits */ -#endif +#endif /* FLASH_OPTR_IRHEN */ /** * @} @@ -460,7 +460,7 @@ typedef struct /** * @} */ -#endif +#endif /* FLASH_OPTR_nRST_MODE */ #if defined(FLASH_OPTR_IRHEN) /** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit @@ -471,7 +471,7 @@ typedef struct /** * @} */ -#endif +#endif /* FLASH_OPTR_IRHEN */ /** @defgroup FLASH_OB_PCROP_ZONE FLASH PCROP ZONE * @{ @@ -564,7 +564,7 @@ typedef struct #define SRAM2B_START_SECURE_ADDR_1 (SRAM2B_BASE + 0x0400U) /* When in secure mode (SRAM2B_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_2 (SRAM2B_BASE + 0x0800U) /* When in secure mode (SRAM2B_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_3 (SRAM2B_BASE + 0x0C00U) /* When in secure mode (SRAM2B_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ -#if !defined(STM32WB15xx) && !defined(STM32WB1Mxx) +#if !defined(STM32WB10xx) && !defined(STM32WB15xx) && !defined(STM32WB1Mxx) #define SRAM2B_START_SECURE_ADDR_4 (SRAM2B_BASE + 0x1000U) /* When in secure mode (SRAM2B_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_5 (SRAM2B_BASE + 0x1400U) /* When in secure mode (SRAM2B_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_6 (SRAM2B_BASE + 0x1800U) /* When in secure mode (SRAM2B_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ @@ -595,8 +595,8 @@ typedef struct #define SRAM2B_START_SECURE_ADDR_31 (SRAM2B_BASE + 0x7C00U) /* When in secure mode (SRAM2B_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */ #define SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x8000U) /* The RAM2B is accessible to M0 Plus and M4 */ #else -#define SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x0C00U) /* The RAM2B is accessible to M0 Plus and M4 */ -#endif +#define SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x1000U) /* The RAM2B is accessible to M0 Plus and M4 */ +#endif /* !(STM32WB10xx) && !(STM32WB15xx) && !(STM32WB1Mxx) */ /** * @} @@ -694,9 +694,9 @@ typedef struct */ /** @defgroup FLASH_Interrupt FLASH Interrupts Macros - * @brief macros to handle FLASH interrupts - * @{ - */ + * @brief macros to handle FLASH interrupts + * @{ + */ /** * @brief Enable the specified FLASH interrupt. @@ -752,6 +752,7 @@ typedef struct #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \ (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) + /** * @brief Clear the FLASH's pending flags. * @param __FLAG__ specifies the FLASH flags to clear. @@ -777,6 +778,7 @@ typedef struct #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\ if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ } while(0) + /** * @} */ @@ -855,23 +857,23 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U) #define FLASH_BANK_SIZE FLASH_SIZE /*!< FLASH Bank Size */ -#if defined(STM32WB15xx) || defined(STM32WB1Mxx) +#if defined(STM32WB10xx) || defined(STM32WB15xx) || defined(STM32WB1Mxx) #define FLASH_PAGE_SIZE 0x00000800U /*!< FLASH Page Size, 2 KBytes */ #else #define FLASH_PAGE_SIZE 0x00001000U /*!< FLASH Page Size, 4 KBytes */ -#endif +#endif /* STM32WB10xx || STM32WB15xx || STM32WB1Mxx */ #define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE) #define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */ -#if defined(STM32WB15xx) || defined(STM32WB1Mxx) +#if defined(STM32WB10xx) || defined(STM32WB15xx) || defined(STM32WB1Mxx) #define FLASH_PCROP_GRANULARITY_OFFSET 10U /*!< FLASH Code Readout Protection granularity offset */ #define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 1 KBytes */ #else #define FLASH_PCROP_GRANULARITY_OFFSET 11U /*!< FLASH Code Readout Protection granularity offset */ #define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 2 KBytes */ -#endif +#endif /* STM32WB10xx || STM32WB15xx || STM32WB1Mxx */ -#define FLASH_TYPENONE 0x00000000U /*!< No Programmation Procedure On Going */ +#define FLASH_TYPENONE 0x00000000U /*!< No Programmation Procedure On Going */ /** * @} */ @@ -879,25 +881,30 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** @defgroup SRAM_MEMORY_SIZE SRAM memory size * @{ */ -#define SRAM_SECURE_PAGE_GRANULARITY_OFFSET 10U /*!< Secure SRAM2A and SRAM2B Protection granularity offset */ -#define SRAM_SECURE_PAGE_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< Secure SRAM2A and SRAM2B Protection granularity, 1KBytes */ +#define SRAM_SECURE_PAGE_GRANULARITY_OFFSET 10U /*!< Secure SRAM2A and SRAM2B Protection granularity offset */ +#define SRAM_SECURE_PAGE_GRANULARITY (1UL << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) /*!< Secure SRAM2A and SRAM2B Protection granularity, 1KBytes */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ -#define IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) + * @{ + */ +#define IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ + ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) -#define IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL)) +#define IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ + ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL)) -#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) +#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ + ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) -#define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) && ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) +#define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) &&\ + ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) -#define IS_FLASH_PROGRAM_ADDRESS(__VALUE__) (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) || IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__)) +#define IS_FLASH_PROGRAM_ADDRESS(__VALUE__) (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) ||\ + IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__)) #define IS_FLASH_PAGE(__VALUE__) ((__VALUE__) < FLASH_PAGE_NB) @@ -908,15 +915,20 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) -#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)(FLASH_PAGE_SIZE - 1U)) == (__VALUE__))) -#define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) -#define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) -#define IS_OB_SECURE_MODE(__VALUE__) (((__VALUE__) == SYSTEM_IN_SECURE_MODE) || ((__VALUE__) == SYSTEM_NOT_IN_SECURE_MODE)) +#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ + ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)(FLASH_PAGE_SIZE - 1U)) == (__VALUE__))) +#define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2A_BASE) &&\ + ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) +#define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2B_BASE) &&\ + ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) +#define IS_OB_SECURE_MODE(__VALUE__) (((__VALUE__) == SYSTEM_IN_SECURE_MODE) ||\ + ((__VALUE__) == SYSTEM_NOT_IN_SECURE_MODE)) #define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \ - OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_SECURE_MODE))) + OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_SECURE_MODE))) -#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) || ((__VALUE__) == OB_WRPAREA_BANK1_AREAB)) +#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) ||\ + ((__VALUE__) == OB_WRPAREA_BANK1_AREAB)) #define IS_OB_RDP_LEVEL(__VALUE__) (((__VALUE__) == OB_RDP_LEVEL_0) ||\ ((__VALUE__) == OB_RDP_LEVEL_1) ||\ @@ -926,21 +938,21 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); (((__VALUE__) & ~OB_USER_ALL) == 0U)) #define IS_OB_USER_CONFIG(__TYPE__, __VALUE__) ((((__TYPE__) & OB_USER_BOR_LEV) == OB_USER_BOR_LEV) \ - ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_0) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_1) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_2) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_3) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_4)) \ - : ((((__TYPE__) & OB_USER_AGC_TRIM) == OB_USER_AGC_TRIM) \ - ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_0) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_1) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_2) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_3) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_4) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_5) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_6) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_7)) \ - : ((~(__TYPE__) & (__VALUE__)) == 0U))) + ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_0) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_1) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_2) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_3) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_4)) \ + : ((((__TYPE__) & OB_USER_AGC_TRIM) == OB_USER_AGC_TRIM) \ + ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_0) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_1) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_2) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_3) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_4) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_5) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_6) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_7)) \ + : ((~(__TYPE__) & (__VALUE__)) == 0U))) #define IS_OB_USER_AGC_TRIMMING(__VALUE__) (((__VALUE__) == OB_AGC_TRIM_0) || ((__VALUE__) == OB_AGC_TRIM_1) || \ ((__VALUE__) == OB_AGC_TRIM_2) || ((__VALUE__) == OB_AGC_TRIM_3) || \ @@ -951,18 +963,22 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); ((__VALUE__) == OB_BOR_LEVEL_2) || ((__VALUE__) == OB_BOR_LEVEL_3) || \ ((__VALUE__) == OB_BOR_LEVEL_4)) -#define IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U) +#define IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) &\ + ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U) -#define IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__)) +#define IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) ||\ + IS_OB_SNBRSA_START_ADDR(__VALUE__)) #define IS_OB_BOOT_VECTOR_ADDR(__VALUE__) ((((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1U))) || \ (((__VALUE__) >= SRAM1_BASE) && ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE - 1U))) || \ (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U))) || \ (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)))) -#define IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) || ((__VALUE__) == OB_C2_BOOT_FROM_SRAM)) +#define IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) ||\ + ((__VALUE__) == OB_C2_BOOT_FROM_SRAM)) -#define IS_OB_SECURE_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_SECURE_CONFIG_MEMORY | OB_SECURE_CONFIG_BOOT_RESET)) == 0U) +#define IS_OB_SECURE_CONFIG(__VALUE__) (((__VALUE__) &\ + ~(OB_SECURE_CONFIG_MEMORY | OB_SECURE_CONFIG_BOOT_RESET)) == 0U) #define IS_FLASH_LATENCY(__VALUE__) (((__VALUE__) == FLASH_LATENCY_0) || \ ((__VALUE__) == FLASH_LATENCY_1) || \ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash_ex.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash_ex.h index 91b82cc346..90eb35c6ec 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash_ex.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash_ex.h @@ -49,7 +49,6 @@ extern "C" { * @} */ - /** @defgroup FLASHEx_ECC_CPUID FLASHEx ECC CPU Identification * @{ */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio.h index 2f884a4c5e..74f461f62a 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio.h @@ -242,7 +242,7 @@ typedef enum (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) #define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ -(((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) + (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h index dbf203408a..ff5bf63116 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h @@ -76,20 +76,20 @@ extern "C" { /** * @brief AF 1 selection */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */ /** * @brief AF 2 selection */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ /** * @brief AF 3 selection */ -#define GPIO_AF3_SAI1 ((uint8_t)0x03) /*!< SAI1_CK1 Alternate Function mapping */ +#define GPIO_AF3_SAI1 ((uint8_t)0x03) /*!< SAI1_CK1 Alternate Function mapping */ #define GPIO_AF3_SPI2 ((uint8_t)0x03) /*!< SPI2 Alternate Function mapping */ #define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */ @@ -97,7 +97,7 @@ extern "C" { * @brief AF 4 selection */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */ /** * @brief AF 5 selection @@ -135,13 +135,13 @@ extern "C" { /** * @brief AF 7 selection */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ /** * @brief AF 8 selection */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */ -#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */ /** * @brief AF 9 selection @@ -187,7 +187,7 @@ extern "C" { #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f) -#endif +#endif /* STM32WB55xx || STM32WB5Mxx */ #if defined (STM32WB50xx) @@ -285,12 +285,12 @@ extern "C" { /** * @brief AF 15 selection */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F)\ && ((AF) != (uint8_t)0x09) && ((AF) != (uint8_t)0x0A) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D)) -#endif +#endif /* STM32WB50xx */ #if defined (STM32WB35xx) @@ -413,7 +413,7 @@ extern "C" { #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D)) -#endif +#endif /* STM32WB35xx */ #if defined (STM32WB30xx) /** @@ -520,7 +520,7 @@ extern "C" { #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F)\ && ((AF) != (uint8_t)0x0A) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D)) -#endif +#endif /* STM32WB30xx */ #if defined (STM32WB15xx) || defined (STM32WB10xx) || defined (STM32WB1Mxx) /** @@ -625,7 +625,7 @@ extern "C" { #define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f) -#endif +#endif /* STM32WB15xx || STM32WB10xx || STM32WB1Mxx */ /** * @} @@ -654,7 +654,7 @@ extern "C" { ((__GPIOx__) == (GPIOB))? 1uL :\ ((__GPIOx__) == (GPIOC))? 2uL :\ ((__GPIOx__) == (GPIOE))? 4uL : 7uL) -#endif +#endif /* STM32WB55xx || STM32WB5Mxx */ /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c.h index c44a370229..3ebbcec654 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c.h @@ -203,10 +203,13 @@ typedef struct __I2C_HandleTypeDef HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ +#if defined(HAL_DMA_MODULE_ENABLED) DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ +#endif /*HAL_DMA_MODULE_ENABLED*/ + HAL_LockTypeDef Lock; /*!< I2C locking object */ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ @@ -661,6 +664,7 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); +#if defined(HAL_DMA_MODULE_ENABLED) /******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); @@ -681,6 +685,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +#endif /*HAL_DMA_MODULE_ENABLED*/ /** * @} */ @@ -709,9 +714,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); * @{ */ /* Peripheral State, Mode and Error functions *********************************/ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); /** * @} diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_ipcc.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_ipcc.h index 4761ae62fb..ea9606a9d3 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_ipcc.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_ipcc.h @@ -22,7 +22,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32wbxx_hal_def.h" @@ -199,8 +199,8 @@ typedef void ChannelCb(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CH /* Initialization and de-initialization functions *******************************/ /** @defgroup IPCC_Exported_Functions_Group1 Initialization and deinitialization functions - * @{ - */ + * @{ + */ HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc); HAL_StatusTypeDef HAL_IPCC_DeInit(IPCC_HandleTypeDef *hipcc); void HAL_IPCC_MspInit(IPCC_HandleTypeDef *hipcc); @@ -210,20 +210,24 @@ void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc); */ /** @defgroup IPCC_Exported_Functions_Group2 Communication functions - * @{ - */ + * @{ + */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb); -HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); -IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); -HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); +HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, + IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb); +HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, + IPCC_CHANNELDirTypeDef ChannelDir); +IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, + uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); +HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, + IPCC_CHANNELDirTypeDef ChannelDir); /** * @} */ /** @defgroup IPCC_Exported_Functions_Group3 Peripheral State and Error functions - * @{ - */ + * @{ + */ /* Peripheral State and Error functions ****************************************/ HAL_IPCC_StateTypeDef HAL_IPCC_GetState(IPCC_HandleTypeDef const *const hipcc); /** @@ -231,8 +235,8 @@ HAL_IPCC_StateTypeDef HAL_IPCC_GetState(IPCC_HandleTypeDef const *const hipcc); */ /** @defgroup IPCC_IRQ_Handler_and_Callbacks Peripheral IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /* IRQHandler and Callbacks used in non blocking modes ************************/ void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef *const hipcc); void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc); @@ -257,7 +261,7 @@ void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_ #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /* STM32WBxx_HAL_IPCC_H */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h index 497021871d..2c794e360b 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr.h @@ -21,7 +21,7 @@ #define STM32WBxx_HAL_PWR_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -55,7 +55,7 @@ typedef struct uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. This parameter can be a value of @ref PWR_PVD_Mode. */ -}PWR_PVDTypeDef; +} PWR_PVDTypeDef; /** * @} @@ -106,7 +106,7 @@ typedef struct #define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0) /*!< Stop 1: stop mode with low power regulator */ #if defined(PWR_SUPPORT_STOP2) #define PWR_LOWPOWERMODE_STOP2 (PWR_CR1_LPMS_1) /*!< Stop 2: stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/ -#endif +#endif /* PWR_SUPPORT_STOP2 */ #define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */ #define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2) /*!< Shutdown mode */ /** @@ -144,7 +144,7 @@ typedef struct * @} */ -/* Private define ------------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ /** @defgroup PWR_Private_Defines PWR Private Defines * @{ */ @@ -207,12 +207,12 @@ typedef struct * @arg @ref PWR_FLAG_SMPSBYPF SMPS Bypass Flag * * /--------------------------------SR2-------------------------------/ - * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the + * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the * low-power regulator is ready. - * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the - * regulator is ready in main mode or is in low-power mode. + * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the + * regulator is ready in main mode or is in low-power mode. * - * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready + * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready * in the selected voltage range or is still changing to the required voltage level. * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is * below or above the selected PVD threshold. @@ -220,37 +220,37 @@ typedef struct * @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is * is below or above PVM1 threshold (applicable when USB feature is supported). * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is - * is below or above PVM3 threshold. + * is below or above PVM3 threshold. * * /----------------------------EXTSCR--------------------------/ * @arg @ref PWR_FLAG_STOP System Stop Flag for CPU1. - * @arg @ref PWR_FLAG_SB System Standby Flag for CPU1. + * @arg @ref PWR_FLAG_SB System Standby Flag for CPU1. * * @arg @ref PWR_FLAG_C2STOP System Stop Flag for CPU2. - * @arg @ref PWR_FLAG_C2SB System Standby Flag for CPU2. + * @arg @ref PWR_FLAG_C2SB System Standby Flag for CPU2. * - * @arg @ref PWR_FLAG_CRITICAL_RF_PHASE Critical radio system phase flag. + * @arg @ref PWR_FLAG_CRITICAL_RF_PHASE Critical radio system phase flag. * * @arg @ref PWR_FLAG_C1DEEPSLEEP CPU1 DeepSleep Flag. - * @arg @ref PWR_FLAG_C2DEEPSLEEP CPU2 DeepSleep Flag. + * @arg @ref PWR_FLAG_C2DEEPSLEEP CPU2 DeepSleep Flag. * * @retval The new state of __FLAG__ (TRUE or FALSE). - */ + */ #define __HAL_PWR_GET_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR1) ? \ ( \ - PWR->SR1 & (1UL << ((__FLAG__) & 31UL)) \ + PWR->SR1 & (1UL << ((__FLAG__) & 31UL)) \ ) \ : \ ( \ - (((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR2) ? \ - ( \ - PWR->SR2 & (1UL << ((__FLAG__) & 31UL)) \ - ) \ - : \ - ( \ - PWR->EXTSCR & (1UL << ((__FLAG__) & 31UL)) \ - ) \ - ) \ + (((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR2) ? \ + ( \ + PWR->SR2 & (1UL << ((__FLAG__) & 31UL)) \ + ) \ + : \ + ( \ + PWR->EXTSCR & (1UL << ((__FLAG__) & 31UL)) \ + ) \ + ) \ ) /** @brief Clear a specific PWR flag. @@ -282,25 +282,25 @@ typedef struct * * /----------------------------EXTSCR--------------------------/ * @arg @ref PWR_FLAG_STOP System Stop Flag for CPU1. - * @arg @ref PWR_FLAG_SB System Standby Flag for CPU1. + * @arg @ref PWR_FLAG_SB System Standby Flag for CPU1. * * @arg @ref PWR_FLAG_C2STOP System Stop Flag for CPU2. - * @arg @ref PWR_FLAG_C2SB System Standby Flag for CPU2. + * @arg @ref PWR_FLAG_C2SB System Standby Flag for CPU2. * * @arg @ref PWR_FLAG_CRITICAL_RF_PHASE RF phase Flag. * - * @retval None - */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_EXTSCR) ? \ - ( \ - PWR->EXTSCR = (1UL << (((__FLAG__) & PWR_FLAG_EXTSCR_CLR_MASK) >> PWR_FLAG_EXTSCR_CLR_POS)) \ - ) \ - : \ - ( \ - (((__FLAG__)) == PWR_FLAG_WU) ? \ - (PWR->SCR = PWR_SCR_CWUF) : \ - (PWR->SCR = (1UL << ((__FLAG__) & 31UL))) \ - ) \ + * @retval None + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_EXTSCR) ? \ + ( \ + PWR->EXTSCR = (1UL << (((__FLAG__) & PWR_FLAG_EXTSCR_CLR_MASK) >> PWR_FLAG_EXTSCR_CLR_POS)) \ + ) \ + : \ + ( \ + (((__FLAG__)) == PWR_FLAG_WU) ? \ + (PWR->SCR = PWR_SCR_CWUF) : \ + (PWR->SCR = (1UL << ((__FLAG__) & 31UL))) \ + ) \ ) /** @@ -406,7 +406,7 @@ typedef struct /** * @} */ - + /* Private macros --------------------------------------------------------*/ /** @defgroup PWR_Private_Macros PWR Private Macros @@ -417,12 +417,12 @@ typedef struct ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) - + #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)) - + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)) + #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ @@ -446,7 +446,7 @@ typedef struct * @{ */ -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h index b5b6579970..413adc535e 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pwr_ex.h @@ -21,7 +21,7 @@ #define STM32WBxx_HAL_PWR_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -48,17 +48,17 @@ */ typedef struct { - uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. - This parameter can be a value of @ref PWREx_PVM_Type. - @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). - @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. + uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. + This parameter can be a value of @ref PWREx_PVM_Type. + @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). + @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. */ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. This parameter can be a value of @ref PWREx_PVM_Mode. */ - uint32_t WakeupTarget; /*!< Specifies the Wakeup Target + uint32_t WakeupTarget; /*!< Specifies the Wakeup Target This parameter can be a value of @ref PWREx_WakeUpTarget_Definition */ -}PWR_PVMTypeDef; +} PWR_PVMTypeDef; #if defined(PWR_CR5_SMPSEN) /** @@ -68,11 +68,11 @@ typedef struct { uint32_t StartupCurrent; /*!< SMPS step down converter supply startup current selection. This parameter can be a value of @ref PWREx_SMPS_STARTUP_CURRENT. */ - + uint32_t OutputVoltage; /*!< SMPS step down converter output voltage scaling voltage level. This parameter can be a value of @ref PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL */ -}PWR_SMPSTypeDef; -#endif +} PWR_SMPSTypeDef; +#endif /* PWR_CR5_SMPSEN */ /** * @} @@ -99,26 +99,26 @@ typedef struct #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ #if defined(PWR_CR3_EWUP2) #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ -#endif +#endif /* PWR_CR3_EWUP2 */ #if defined(PWR_CR3_EWUP3) #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ -#endif +#endif /* PWR_CR3_EWUP3 */ #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ #if defined(PWR_CR3_EWUP5) #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ -#endif +#endif /* PWR_CR3_EWUP5 */ #define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<CR1, PWR_CR1_VOS); \ UNUSED(tmpreg); \ } while(0) -#endif +#endif /* PWR_CR1_VOS */ /** * @brief Wakeup BLE controller from its sleep mode @@ -745,7 +745,7 @@ typedef struct /** * @} */ - + /* Private macros --------------------------------------------------------*/ /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros * @{ @@ -766,7 +766,7 @@ typedef struct ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ ((PIN) == PWR_WAKEUP_PIN4_LOW)) -#endif +#endif /* PWR_CR3_EWUP2 */ #define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \ ((POLARITY) == PWR_PIN_POLARITY_LOW)) @@ -776,7 +776,7 @@ typedef struct ((TYPE) == PWR_PVM_3)) #else #define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_3) -#endif +#endif /* PWR_CR2_PVME1 */ #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ @@ -784,21 +784,21 @@ typedef struct ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) - + ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) + #define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00u) && \ (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00u)) #if defined(PWR_CR1_VOS) #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) -#endif +#endif /* PWR_CR1_VOS */ #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ - ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) - + ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) + #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ - ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) + ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) @@ -816,7 +816,7 @@ typedef struct ((GPIO) == PWR_GPIO_C) ||\ ((GPIO) == PWR_GPIO_E) ||\ ((GPIO) == PWR_GPIO_H)) -#endif +#endif /* GPIOD */ #if defined(PWR_CR5_SMPSEN) #define IS_PWR_SMPS_MODE(SMPS_MODE) (((SMPS_MODE) == PWR_SMPS_BYPASS) ||\ @@ -846,7 +846,7 @@ typedef struct ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V80) ||\ ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V85) ||\ ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V90)) -#endif +#endif /* PWR_CR5_SMPSEN */ #define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2)) @@ -855,13 +855,13 @@ typedef struct /** * @} */ - + /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions * @{ */ - -/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + +/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions * @{ */ @@ -881,7 +881,7 @@ void HAL_PWREx_DisableInternalWakeUpLine(void); #if defined(PWR_CR5_SMPSEN) void HAL_PWREx_EnableBORH_SMPSBypassIT(void); void HAL_PWREx_DisableBORH_SMPSBypassIT(void); -#endif +#endif /* PWR_CR5_SMPSEN */ void HAL_PWREx_EnableRFPhaseIT(void); void HAL_PWREx_DisableRFPhaseIT(void); void HAL_PWREx_EnableBLEActivityIT(void); @@ -904,7 +904,7 @@ void HAL_PWREx_DisablePullUpPullDownConfig(void); #if defined(PWR_CR5_SMPSEN) void HAL_PWREx_SetBORConfig(uint32_t BORConfiguration); uint32_t HAL_PWREx_GetBORConfig(void); -#endif +#endif /* PWR_CR5_SMPSEN */ void HAL_PWREx_EnableSRAMRetention(void); void HAL_PWREx_DisableSRAMRetention(void); @@ -915,7 +915,7 @@ void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode); #if defined(PWR_CR2_PVME1) void HAL_PWREx_EnablePVM1(void); void HAL_PWREx_DisablePVM1(void); -#endif +#endif /* PWR_CR2_PVME1 */ void HAL_PWREx_EnablePVM3(void); void HAL_PWREx_DisablePVM3(void); @@ -926,7 +926,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS); void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode); uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void); -#endif +#endif /* PWR_CR5_SMPSEN */ /* WakeUp pins configuration functions ****************************************/ void HAL_PWREx_EnableWakeUpPin(uint32_t WakeUpPinPolarity, uint32_t wakeupTarget); @@ -941,14 +941,14 @@ void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); #if defined(PWR_SUPPORT_STOP2) void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); -#endif +#endif /* PWR_SUPPORT_STOP2 */ void HAL_PWREx_EnterSHUTDOWNMode(void); void HAL_PWREx_PVD_PVM_IRQHandler(void); #if defined(PWR_CR2_PVME1) void HAL_PWREx_PVM1Callback(void); -#endif +#endif /* PWR_CR2_PVME1 */ void HAL_PWREx_PVM3Callback(void); /** diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h index 64367fa0e2..dab095f84a 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rcc_ex.h @@ -67,7 +67,7 @@ extern "C" { #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_LPTIM1 | \ RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | \ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RFWAKEUP) -#endif +#endif /* LPUART1 */ /** * @} @@ -84,7 +84,7 @@ extern "C" { #else #define IS_RCC_LSCO(__LSCOX__) (((__LSCOX__) == RCC_LSCO1) || \ ((__LSCOX__) == RCC_LSCO2)) -#endif +#endif /* RCC_LSCO3_SUPPORT */ #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) @@ -104,7 +104,7 @@ extern "C" { ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) -#endif +#endif /* LPUART1 */ #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ @@ -116,7 +116,7 @@ extern "C" { (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) -#endif +#endif /* I2C3 */ #if defined(SAI1) #define IS_RCC_SAI1CLK(__SOURCE__) \ @@ -124,7 +124,7 @@ extern "C" { ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) -#endif +#endif /* SAI1 */ #define IS_RCC_LPTIM1CLK(__SOURCE__) \ (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ @@ -178,8 +178,8 @@ extern "C" { (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) -#endif -#endif +#endif /* SAI1 */ +#endif /* USB */ #if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined(STM32WB35xx) #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ @@ -198,7 +198,7 @@ extern "C" { (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) -#endif +#endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx */ #define IS_RCC_RFWKPCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_RFWKPCLKSOURCE_NONE) || \ @@ -216,7 +216,7 @@ extern "C" { (((__SOURCE__) == RCC_SMPSCLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_SMPSCLKSOURCE_MSI) || \ ((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE)) -#endif +#endif /* RCC_SMPS_SUPPORT */ #if defined(SAI1) @@ -227,7 +227,7 @@ extern "C" { #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) -#endif +#endif /* SAI1 */ #define IS_RCC_TRIMOSC(__VALUE__) ((__VALUE__) == RCC_OSCILLATORTYPE_LSI2) @@ -252,7 +252,7 @@ extern "C" { #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) -#endif +#endif /* CRS */ /** * @} */ @@ -285,7 +285,7 @@ typedef struct uint32_t PLLSAI1ClockOut; /*!< PLLSAI1ClockOut: specifies PLLSAI1 output clock to be enabled. This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ } RCC_PLLSAI1InitTypeDef; -#endif +#endif /* SAI1 */ /** * @brief RCC extended clocks structure definition @@ -299,7 +299,7 @@ typedef struct RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI, USB/RNG or ADC */ -#endif +#endif /* SAI1 */ uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ @@ -307,7 +307,7 @@ typedef struct #if defined(LPUART1) uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ -#endif +#endif /* LPUART1 */ uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ @@ -315,7 +315,7 @@ typedef struct #if defined(I2C3) uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ -#endif +#endif /* I2C3 */ uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ @@ -326,12 +326,12 @@ typedef struct #if defined(SAI1) uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ -#endif +#endif /* SAI1 */ #if defined(USB) uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG). This parameter can be a value of @ref RCCEx_USB_Clock_Source */ -#endif +#endif /* USB */ uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB). This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ @@ -352,7 +352,7 @@ typedef struct uint32_t SmpsDivSelection; /*!< Specifies SMPS clock division factor. This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */ -#endif +#endif /* RCC_SMPS_SUPPORT */ } RCC_PeriphCLKInitTypeDef; @@ -405,7 +405,7 @@ typedef struct This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ } RCC_CRSSynchroInfoTypeDef; -#endif +#endif /* CRS */ /** * @} @@ -423,7 +423,7 @@ typedef struct #define RCC_LSCO2 0x00000001U /*!< LSCO2 index */ #if defined(RCC_LSCO3_SUPPORT) #define RCC_LSCO3 0x00000002U /*!< LSCO3 index */ -#endif +#endif /* RCC_LSCO3_SUPPORT */ /** * @} */ @@ -444,27 +444,27 @@ typedef struct #define RCC_PERIPHCLK_USART1 0x00000001U /*!< USART1 Peripheral Clock Selection */ #if defined(LPUART1) #define RCC_PERIPHCLK_LPUART1 0x00000002U /*!< LPUART1 Peripheral Clock Selection */ -#endif +#endif /* LPUART1 */ #define RCC_PERIPHCLK_I2C1 0x00000004U /*!< I2C1 Peripheral Clock Selection */ #if defined(I2C3) #define RCC_PERIPHCLK_I2C3 0x00000008U /*!< I2C3 Peripheral Clock Selection */ -#endif +#endif /* I2C3 */ #define RCC_PERIPHCLK_LPTIM1 0x00000010U /*!< LPTIM1 Peripheral Clock Selection */ #define RCC_PERIPHCLK_LPTIM2 0x00000020U /*!< LPTIM2 Peripheral Clock Selection */ #if defined(SAI1) #define RCC_PERIPHCLK_SAI1 0x00000040U /*!< SAI1 Peripheral Clock Selection */ -#endif +#endif /* SAI1 */ #define RCC_PERIPHCLK_CLK48SEL 0x00000100U /*!< 48 MHz clock source selection */ #if defined(USB) #define RCC_PERIPHCLK_USB RCC_PERIPHCLK_CLK48SEL /*!< USB Peripheral Clock Selection */ -#endif +#endif /* USB */ #define RCC_PERIPHCLK_RNG 0x00000200U /*!< RNG Peripheral Clock Selection */ #define RCC_PERIPHCLK_ADC 0x00000400U /*!< ADC Peripheral Clock Selection */ #define RCC_PERIPHCLK_RTC 0x00000800U /*!< RTC Peripheral Clock Selection */ #define RCC_PERIPHCLK_RFWAKEUP 0x00001000U /*!< RF Wakeup Peripheral Clock Selection */ #if defined(RCC_SMPS_SUPPORT) #define RCC_PERIPHCLK_SMPS 0x00002000U /*!< SMPS Peripheral Clock Selection */ -#endif +#endif /* RCC_SMPS_SUPPORT */ /** * @} */ @@ -491,7 +491,7 @@ typedef struct /** * @} */ -#endif +#endif /* LPUART1 */ /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source * @{ @@ -513,7 +513,7 @@ typedef struct /** * @} */ -#endif +#endif /* I2C3 */ #if defined(SAI1) /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source @@ -526,7 +526,7 @@ typedef struct /** * @} */ -#endif +#endif /* SAI1 */ /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source * @{ @@ -573,13 +573,13 @@ typedef struct #define RCC_USBCLKSOURCE_HSI48 LL_RCC_USB_CLKSOURCE_HSI48 /*!< HSI48 clock selected as USB clock */ #if defined(SAI1) #define RCC_USBCLKSOURCE_PLLSAI1 LL_RCC_USB_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "Q" clock selected as USB clock */ -#endif +#endif /* SAI1 */ #define RCC_USBCLKSOURCE_PLL LL_RCC_USB_CLKSOURCE_PLL /*!< PLL "Q" clock selected as USB clock */ #define RCC_USBCLKSOURCE_MSI LL_RCC_USB_CLKSOURCE_MSI /*!< MSI clock selected as USB clock */ /** * @} */ -#endif +#endif /* USB */ /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source * @{ @@ -590,7 +590,7 @@ typedef struct #define RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "R" clock selected as ADC clock */ #elif defined (STM32WB15xx) || defined(STM32WB1Mxx) #define RCC_ADCCLKSOURCE_HSI LL_RCC_ADC_CLKSOURCE_HSI /*!< HSI clock selected as ADC clock */ -#endif +#endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx */ #define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL /*!< PLL "P" clock selected as ADC clock */ #define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as ADC clock */ @@ -656,7 +656,7 @@ typedef struct /** * @} */ -#endif +#endif /* RCC_SMPS_SUPPORT */ /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line @@ -783,7 +783,7 @@ typedef struct /** * @} */ -#endif +#endif /* CRS */ /** * @} @@ -973,7 +973,7 @@ typedef struct * @retval None */ #define __HAL_RCC_GET_SAI1_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE) -#endif +#endif /* SAI1 */ /** @brief Macro to configure the I2C1 clock (I2C1CLK). * @@ -1013,7 +1013,7 @@ typedef struct * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock */ #define __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE) -#endif +#endif /* I2C3 */ /** @brief Macro to configure the USART1 clock (USART1CLK). * @@ -1057,7 +1057,7 @@ typedef struct * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock */ #define __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE) -#endif +#endif /* LPUART1 */ /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). * @@ -1169,7 +1169,7 @@ typedef struct * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock */ #define __HAL_RCC_GET_USB_SOURCE() LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE) -#endif +#endif /* USB */ /** @brief Macro to configure the ADC interface clock. * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. @@ -1271,7 +1271,7 @@ typedef struct * @arg @ref RCC_SMPSCLKSOURCE_STATUS_HSE HSE Clock selected as SMPS clock */ #define __HAL_RCC_GET_SMPS_SOURCE_STATUS() LL_RCC_GetSMPSClockSource() -#endif +#endif /* RCC_SMPS_SUPPORT */ /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. @@ -1304,7 +1304,7 @@ typedef struct * @retval TRUE or FALSE. */ #define __HAL_RCC_PLLSAI1_GET_FLAG() LL_RCC_PLLSAI1_IsReady() -#endif +#endif /* SAI1 */ /** * @brief Enable the RCC LSE CSS Extended Interrupt C1 Line. @@ -1513,7 +1513,7 @@ typedef struct WRITE_REG(CRS->ICR, (__FLAG__)); \ } \ } while(0) -#endif +#endif /* CRS */ /** * @} */ @@ -1564,7 +1564,7 @@ typedef struct /** * @} */ -#endif +#endif /* CRS */ /** * @} @@ -1595,7 +1595,7 @@ uint32_t HAL_RCCEx_GetRngCLKSource(void); #if defined(SAI1) HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); -#endif +#endif /* SAI1 */ void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); @@ -1639,7 +1639,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); * @} */ -#endif +#endif /* CRS */ /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_sai.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_sai.h index ab00e495b2..c30d6b2c6c 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_sai.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_sai.h @@ -356,6 +356,7 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); #define SAI_AUDIO_FREQUENCY_48K 48000U #define SAI_AUDIO_FREQUENCY_44K 44100U #define SAI_AUDIO_FREQUENCY_32K 32000U +#define SAI_AUDIO_FREQUENCY_24K 24000U #define SAI_AUDIO_FREQUENCY_22K 22050U #define SAI_AUDIO_FREQUENCY_16K 16000U #define SAI_AUDIO_FREQUENCY_11K 11025U @@ -839,9 +840,10 @@ uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); #define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \ ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \ - ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \ - ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \ - ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV)) + ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_24K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV)) #define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \ ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE)) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smbus.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smbus.h index 27849a0c63..cdddf89b63 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smbus.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smbus.h @@ -751,8 +751,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); */ /* Peripheral State and Errors functions **************************************************/ -uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); -uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus); /** * @} diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tsc.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tsc.h index 63310dd274..8f8273d9e9 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tsc.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tsc.h @@ -684,7 +684,7 @@ when the selected signal is detected on the SYNC input pin) */ ((__VALUE__) == TSC_MCV_2047) || \ ((__VALUE__) == TSC_MCV_4095) || \ ((__VALUE__) == TSC_MCV_8191) || \ - ((__VALUE__) == TSC_MCV_16383)) + ((__VALUE__) == TSC_MCV_16383)) #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) @@ -765,8 +765,8 @@ HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); -TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index); -uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index); +TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index); +uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index); /** * @} */ @@ -775,7 +775,7 @@ uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config); +HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config); HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); /** * @} @@ -791,8 +791,8 @@ HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); */ /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /******* TSC IRQHandler and Callbacks used in Interrupt mode */ void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_bus.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_bus.h index c91a50569e..7bbb1348c6 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_bus.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_bus.h @@ -76,13 +76,13 @@ extern "C" { #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN #if defined(DMA2) #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN -#endif +#endif /* DMA2 */ #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN #if defined(TSC) #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN -#endif +#endif /* TSC */ /** * @} */ @@ -97,15 +97,15 @@ extern "C" { #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN #if defined(GPIOD) #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN -#endif +#endif /* GPIOD */ #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN #if defined(ADC_SUPPORT_5_MSPS) #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN -#endif +#endif /* ADC_SUPPORT_5_MSPS */ #if defined(AES1) #define LL_AHB2_GRP1_PERIPH_AES1 RCC_AHB2ENR_AES1EN -#endif +#endif /* AES1 */ /** * @} */ @@ -116,7 +116,7 @@ extern "C" { #define LL_AHB3_GRP1_PERIPH_ALL (0xFFFFFFFFU) #if defined(QUADSPI) #define LL_AHB3_GRP1_PERIPH_QUADSPI RCC_AHB3ENR_QUADSPIEN -#endif +#endif /* QUADSPI */ #define LL_AHB3_GRP1_PERIPH_PKA RCC_AHB3ENR_PKAEN #define LL_AHB3_GRP1_PERIPH_AES2 RCC_AHB3ENR_AES2EN #define LL_AHB3_GRP1_PERIPH_RNG RCC_AHB3ENR_RNGEN @@ -135,22 +135,22 @@ extern "C" { #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN #if defined(LCD) #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN -#endif +#endif /* LCD */ #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN #if defined(SPI2) #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN -#endif +#endif /* SPI2 */ #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN #if defined(I2C3) #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN -#endif +#endif /* I2C3 */ #if defined(CRS) #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN -#endif +#endif /* CRS */ #if defined(USB) #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN -#endif +#endif /* USB */ #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN /** * @} @@ -164,7 +164,7 @@ extern "C" { #if defined(LPUART1) #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN -#endif +#endif /* LPUART1 */ #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN /** * @} @@ -177,19 +177,19 @@ extern "C" { #if defined(ADC_SUPPORT_2_5_MSPS) #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2ENR_ADCEN -#endif +#endif /* ADC_SUPPORT_2_5_MSPS */ #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN #if defined(TIM16) #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN -#endif +#endif /* TIM16 */ #if defined(TIM17) #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN -#endif +#endif /* TIM17 */ #if defined(SAI1) #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN -#endif +#endif /* SAI1 */ /** * @} */ @@ -210,13 +210,13 @@ extern "C" { #define LL_C2_AHB1_GRP1_PERIPH_DMA1 RCC_C2AHB1ENR_DMA1EN #if defined(DMA2) #define LL_C2_AHB1_GRP1_PERIPH_DMA2 RCC_C2AHB1ENR_DMA2EN -#endif +#endif /* DMA2 */ #define LL_C2_AHB1_GRP1_PERIPH_DMAMUX1 RCC_C2AHB1ENR_DMAMUX1EN #define LL_C2_AHB1_GRP1_PERIPH_SRAM1 RCC_C2AHB1ENR_SRAM1EN #define LL_C2_AHB1_GRP1_PERIPH_CRC RCC_C2AHB1ENR_CRCEN #if defined(TSC) #define LL_C2_AHB1_GRP1_PERIPH_TSC RCC_C2AHB1ENR_TSCEN -#endif +#endif /* TSC */ /** * @} */ @@ -230,15 +230,15 @@ extern "C" { #define LL_C2_AHB2_GRP1_PERIPH_GPIOC RCC_C2AHB2ENR_GPIOCEN #if defined(GPIOD) #define LL_C2_AHB2_GRP1_PERIPH_GPIOD RCC_C2AHB2ENR_GPIODEN -#endif +#endif /* GPIOD */ #define LL_C2_AHB2_GRP1_PERIPH_GPIOE RCC_C2AHB2ENR_GPIOEEN #define LL_C2_AHB2_GRP1_PERIPH_GPIOH RCC_C2AHB2ENR_GPIOHEN #if defined(ADC_SUPPORT_5_MSPS) #define LL_C2_AHB2_GRP1_PERIPH_ADC RCC_C2AHB2ENR_ADCEN -#endif +#endif /* ADC_SUPPORT_5_MSPS */ #if defined(AES1) #define LL_C2_AHB2_GRP1_PERIPH_AES1 RCC_C2AHB2ENR_AES1EN -#endif +#endif /* AES1 */ /** * @} */ @@ -265,17 +265,17 @@ extern "C" { #define LL_C2_APB1_GRP1_PERIPH_TIM2 RCC_C2APB1ENR1_TIM2EN #if defined(LCD) #define LL_C2_APB1_GRP1_PERIPH_LCD RCC_C2APB1ENR1_LCDEN -#endif +#endif /* LCD */ #define LL_C2_APB1_GRP1_PERIPH_RTCAPB RCC_C2APB1ENR1_RTCAPBEN #if defined(SPI2) #define LL_C2_APB1_GRP1_PERIPH_SPI2 RCC_C2APB1ENR1_SPI2EN -#endif +#endif /* SPI2 */ #define LL_C2_APB1_GRP1_PERIPH_I2C1 RCC_C2APB1ENR1_I2C1EN #if defined(I2C3) #define LL_C2_APB1_GRP1_PERIPH_I2C3 RCC_C2APB1ENR1_I2C3EN #define LL_C2_APB1_GRP1_PERIPH_CRS RCC_C2APB1ENR1_CRSEN #define LL_C2_APB1_GRP1_PERIPH_USB RCC_C2APB1ENR1_USBEN -#endif +#endif /* I2C3 */ #define LL_C2_APB1_GRP1_PERIPH_LPTIM1 RCC_C2APB1ENR1_LPTIM1EN /** * @} @@ -287,7 +287,7 @@ extern "C" { */ #if defined(LPUART1) #define LL_C2_APB1_GRP2_PERIPH_LPUART1 RCC_C2APB1ENR2_LPUART1EN -#endif +#endif /* LPUART1 */ #define LL_C2_APB1_GRP2_PERIPH_LPTIM2 RCC_C2APB1ENR2_LPTIM2EN /** * @} @@ -299,19 +299,19 @@ extern "C" { */ #if defined(ADC_SUPPORT_2_5_MSPS) #define LL_C2_APB2_GRP1_PERIPH_ADC RCC_C2APB2ENR_ADCEN -#endif +#endif /* ADC_SUPPORT_5_MSPS */ #define LL_C2_APB2_GRP1_PERIPH_TIM1 RCC_C2APB2ENR_TIM1EN #define LL_C2_APB2_GRP1_PERIPH_SPI1 RCC_C2APB2ENR_SPI1EN #define LL_C2_APB2_GRP1_PERIPH_USART1 RCC_C2APB2ENR_USART1EN #if defined(TIM16) #define LL_C2_APB2_GRP1_PERIPH_TIM16 RCC_C2APB2ENR_TIM16EN -#endif +#endif /* TIM16 */ #if defined(TIM17) #define LL_C2_APB2_GRP1_PERIPH_TIM17 RCC_C2APB2ENR_TIM17EN -#endif +#endif /* TIM17 */ #if defined(SAI1) #define LL_C2_APB2_GRP1_PERIPH_SAI1 RCC_C2APB2ENR_SAI1EN -#endif +#endif /* SAI1 */ /** * @} */ @@ -323,7 +323,7 @@ extern "C" { #define LL_C2_APB3_GRP1_PERIPH_BLE RCC_C2APB3ENR_BLEEN #if defined(RCC_802_SUPPORT) #define LL_C2_APB3_GRP1_PERIPH_802 RCC_C2APB3ENR_802EN -#endif +#endif /* RCC_802_SUPPORT */ /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_cortex.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_cortex.h index 67ad56e1e9..4101f2f0e5 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_cortex.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_cortex.h @@ -586,7 +586,8 @@ __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) * (*) value not defined for CM0+ core. * @retval None */ -__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, + uint32_t Attributes) { /* Set Region number */ WRITE_REG(MPU->RNR, Region); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dma.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dma.h index b783cfb9f2..b764388427 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dma.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dma.h @@ -54,11 +54,11 @@ extern "C" { */ #if defined (DMA2) #define __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__) \ -(((__DMA_INSTANCE__) == DMA1) ? (DMA1_Channel1 + (__CHANNEL_INDEX__)) : (DMA2_Channel1 + (__CHANNEL_INDEX__))) + (((__DMA_INSTANCE__) == DMA1) ? (DMA1_Channel1 + (__CHANNEL_INDEX__)) : (DMA2_Channel1 + (__CHANNEL_INDEX__))) #else #define __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__) \ -(DMA1_Channel1 + (__CHANNEL_INDEX__)) -#endif + (DMA1_Channel1 + (__CHANNEL_INDEX__)) +#endif /* DMA2 */ /** * @brief Helper macro to convert DMA Instance and index into DMAMUX channel @@ -70,11 +70,11 @@ extern "C" { */ #if defined (DMA2) #define __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__)\ -(((__DMA_INSTANCE__) == DMA1) ? (DMAMUX1_Channel0 + (__CHANNEL_INDEX__)) : (DMAMUX1_Channel7 + (__CHANNEL_INDEX__))) + (((__DMA_INSTANCE__) == DMA1) ? (DMAMUX1_Channel0 + (__CHANNEL_INDEX__)) : (DMAMUX1_Channel7 + (__CHANNEL_INDEX__))) #else #define __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__)\ -(DMAMUX1_Channel0 + (__CHANNEL_INDEX__)) -#endif + (DMAMUX1_Channel0 + (__CHANNEL_INDEX__)) +#endif /* DMA2 */ /** * @} */ @@ -255,7 +255,7 @@ typedef struct #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ #if defined(USE_FULL_LL_DRIVER) #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ -#endif /*USE_FULL_LL_DRIVER*/ +#endif /* USE_FULL_LL_DRIVER */ /** * @} */ @@ -370,10 +370,10 @@ typedef struct */ #if defined(DMA2) #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) + (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) #else #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) -#endif +#endif /* DMA2 */ /** * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y @@ -383,44 +383,44 @@ typedef struct #if defined (DMA2) #if defined (DMA2_Channel6) && defined (DMA2_Channel7) #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ - LL_DMA_CHANNEL_7) + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) #else #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ - LL_DMA_CHANNEL_7) -#endif + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#endif /* DMA2_Channel6 && DMA2_Channel7 */ #else #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ - LL_DMA_CHANNEL_7) -#endif + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#endif /* DMA2 */ /** * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely @@ -431,45 +431,45 @@ typedef struct #if defined (DMA2) #if defined (DMA2_Channel6) && defined (DMA2_Channel7) #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ - DMA2_Channel7) + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ + DMA2_Channel7) #else #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ - DMA1_Channel7) -#endif + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#endif /* DMA2_Channel6 && DMA2_Channel7 */ #else #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ - DMA1_Channel7) -#endif + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#endif /* DMA2 */ /** * @} @@ -481,8 +481,8 @@ typedef struct /* Exported functions --------------------------------------------------------*/ /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions - * @{ - */ + * @{ + */ /** @defgroup DMA_LL_EF_Configuration Configuration * @{ @@ -542,7 +542,7 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) { return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, - DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); + DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); } /** @@ -2078,7 +2078,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, - DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); + DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); } /** @@ -2098,7 +2098,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, - DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); + DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); } /** @@ -2118,7 +2118,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, - DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); + DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); } /** diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dmamux.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dmamux.h index 710d729757..606b8f7c05 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dmamux.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_dmamux.h @@ -138,26 +138,26 @@ extern "C" { #if defined(SPI2) #define LL_DMAMUX_REQ_SPI2_RX 0x00000008U /*!< DMAMUX SPI2 RX request */ #define LL_DMAMUX_REQ_SPI2_TX 0x00000009U /*!< DMAMUX SPI2 TX request */ -#endif +#endif /* SPI2 */ #define LL_DMAMUX_REQ_I2C1_RX 0x0000000AU /*!< DMAMUX I2C1 RX request */ #define LL_DMAMUX_REQ_I2C1_TX 0x0000000BU /*!< DMAMUX I2C1 TX request */ #if defined(I2C3) #define LL_DMAMUX_REQ_I2C3_RX 0x0000000CU /*!< DMAMUX I2C3 RX request */ #define LL_DMAMUX_REQ_I2C3_TX 0x0000000DU /*!< DMAMUX I2C3 TX request */ -#endif +#endif /* I2C3 */ #define LL_DMAMUX_REQ_USART1_RX 0x0000000EU /*!< DMAMUX USART1 RX request */ #define LL_DMAMUX_REQ_USART1_TX 0x0000000FU /*!< DMAMUX USART1 TX request */ #if defined(LPUART1) #define LL_DMAMUX_REQ_LPUART1_RX 0x00000010U /*!< DMAMUX LPUART1 RX request */ #define LL_DMAMUX_REQ_LPUART1_TX 0x00000011U /*!< DMAMUX LPUART1 TX request */ -#endif +#endif /* LPUART1 */ #if defined(SAI1) #define LL_DMAMUX_REQ_SAI1_A 0x00000012U /*!< DMAMUX SAI1 A request */ #define LL_DMAMUX_REQ_SAI1_B 0x00000013U /*!< DMAMUX SAI1 B request */ -#endif +#endif /* SAI1 */ #if defined(QUADSPI) #define LL_DMAMUX_REQ_QUADSPI 0x00000014U /*!< DMAMUX QUADSPI request */ -#endif +#endif /* QUADSPI */ #define LL_DMAMUX_REQ_TIM1_CH1 0x00000015U /*!< DMAMUX TIM1 CH1 request */ #define LL_DMAMUX_REQ_TIM1_CH2 0x00000016U /*!< DMAMUX TIM1 CH2 request */ #define LL_DMAMUX_REQ_TIM1_CH3 0x00000017U /*!< DMAMUX TIM1 CH3 request */ @@ -177,7 +177,7 @@ extern "C" { #if defined(AES1) #define LL_DMAMUX_REQ_AES1_IN 0x00000025U /*!< DMAMUX AES1_IN request */ #define LL_DMAMUX_REQ_AES1_OUT 0x00000026U /*!< DMAMUX AES1_OUT request */ -#endif +#endif /* AES1 */ #define LL_DMAMUX_REQ_AES2_IN 0x00000027U /*!< DMAMUX AES2_IN request */ #define LL_DMAMUX_REQ_AES2_OUT 0x00000028U /*!< DMAMUX AES2_OUT request */ /** @@ -202,7 +202,7 @@ extern "C" { #define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */ #define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 6 */ #define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX Channel 13 connected to DMA2 Channel 7 */ -#endif +#endif /* DMA2 */ /** * @} */ @@ -332,8 +332,8 @@ extern "C" { /* Exported functions --------------------------------------------------------*/ /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions - * @{ - */ + * @{ + */ /** @defgroup DMAMUX_LL_EF_Configuration Configuration * @{ @@ -920,7 +920,8 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, ui __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); + SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); } /** @@ -937,7 +938,8 @@ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); } /** @@ -954,7 +956,8 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); } /** @@ -973,10 +976,12 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *D * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, + uint32_t Polarity) { (void)(DMAMUXx); - MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); } /** @@ -997,7 +1002,8 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMA __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); } /** @@ -1013,10 +1019,12 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, + uint32_t RequestNb) { (void)(DMAMUXx); - MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); } /** @@ -1033,7 +1041,8 @@ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); } /** @@ -1068,10 +1077,12 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMU * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, + uint32_t RequestSignalID) { (void)(DMAMUXx); - MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); } /** @@ -1108,7 +1119,8 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUX __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); } /** @@ -1216,7 +1228,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAM return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel7 */ #if defined(DMAMUX1_Channel8) /** * @brief Get Synchronization Event Overrun Flag Channel 8. @@ -1230,7 +1242,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAM return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel8 */ #if defined(DMAMUX1_Channel9) /** * @brief Get Synchronization Event Overrun Flag Channel 9. @@ -1244,7 +1256,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAM return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel9 */ #if defined(DMAMUX1_Channel10) /** * @brief Get Synchronization Event Overrun Flag Channel 10. @@ -1258,7 +1270,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMA return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel10 */ #if defined(DMAMUX1_Channel11) /** * @brief Get Synchronization Event Overrun Flag Channel 11. @@ -1272,7 +1284,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMA return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel11 */ #if defined(DMAMUX1_Channel12) /** * @brief Get Synchronization Event Overrun Flag Channel 12. @@ -1286,7 +1298,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMA return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel12 */ #if defined(DMAMUX1_Channel13) /** * @brief Get Synchronization Event Overrun Flag Channel 13. @@ -1300,7 +1312,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMA return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel13 */ /** * @brief Get Request Generator 0 Trigger Event Overrun Flag. * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 @@ -1446,7 +1458,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7); } -#endif +#endif /* DMAMUX1_Channel7 */ #if defined(DMAMUX1_Channel8) /** * @brief Clear Synchronization Event Overrun Flag Channel 8. @@ -1460,7 +1472,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8); } -#endif +#endif /* DMAMUX1_Channel8 */ #if defined(DMAMUX1_Channel9) /** * @brief Clear Synchronization Event Overrun Flag Channel 9. @@ -1474,7 +1486,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9); } -#endif +#endif /* DMAMUX1_Channel9 */ #if defined(DMAMUX1_Channel10) /** * @brief Clear Synchronization Event Overrun Flag Channel 10. @@ -1488,7 +1500,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10); } -#endif +#endif /* DMAMUX1_Channel10 */ #if defined(DMAMUX1_Channel11) /** * @brief Clear Synchronization Event Overrun Flag Channel 11. @@ -1502,7 +1514,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11); } -#endif +#endif /* DMAMUX1_Channel11 */ #if defined(DMAMUX1_Channel12) /** * @brief Clear Synchronization Event Overrun Flag Channel 12. @@ -1516,7 +1528,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12); } -#endif +#endif /* DMAMUX1_Channel12 */ #if defined(DMAMUX1_Channel13) /** * @brief Clear Synchronization Event Overrun Flag Channel 13. @@ -1530,7 +1542,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13); } -#endif +#endif /* DMAMUX1_Channel13 */ /** * @brief Clear Request Generator 0 Trigger Event Overrun Flag. * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_gpio.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_gpio.h index 16ea3856eb..2c3c205f4a 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_gpio.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_gpio.h @@ -57,7 +57,7 @@ extern "C" { /** * @} */ -#endif /*USE_FULL_LL_DRIVER*/ +#endif /* USE_FULL_LL_DRIVER */ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_i2c.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_i2c.h index c747ff3550..4d0c6f265c 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_i2c.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_i2c.h @@ -451,7 +451,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); } @@ -500,7 +500,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); } @@ -535,7 +535,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); } @@ -568,7 +568,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); } @@ -601,7 +601,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); } @@ -616,7 +616,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction) { uint32_t data_reg_addr; @@ -664,7 +664,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); } @@ -697,7 +697,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); } @@ -737,7 +737,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); } @@ -772,7 +772,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); } @@ -800,7 +800,7 @@ __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT */ -__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); } @@ -849,7 +849,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); } @@ -905,7 +905,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); } @@ -930,7 +930,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); } @@ -941,7 +941,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); } @@ -952,7 +952,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); } @@ -963,7 +963,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); } @@ -974,7 +974,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); } @@ -1011,7 +1011,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) * @arg @ref LL_I2C_MODE_SMBUS_DEVICE * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP */ -__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); } @@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); } @@ -1099,7 +1099,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); } @@ -1150,7 +1150,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout * @param I2Cx I2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); } @@ -1182,7 +1182,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); } @@ -1210,7 +1210,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout * @param I2Cx I2C Instance. * @retval Value between Min_Data=0 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); } @@ -1264,7 +1264,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout) { return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ (ClockTimeout)) ? 1UL : 0UL); @@ -1306,7 +1306,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); } @@ -1339,7 +1339,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); } @@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); } @@ -1405,7 +1405,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); } @@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); } @@ -1477,7 +1477,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); } @@ -1528,7 +1528,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); } @@ -1549,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); } @@ -1562,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); } @@ -1575,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); } @@ -1588,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); } @@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); } @@ -1614,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); } @@ -1627,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); } @@ -1640,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); } @@ -1653,7 +1653,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); } @@ -1666,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); } @@ -1679,7 +1679,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); } @@ -1694,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); } @@ -1709,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); } @@ -1725,7 +1725,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); } @@ -1738,7 +1738,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); } @@ -1899,7 +1899,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); } @@ -1934,7 +1934,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); } @@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); } @@ -2035,7 +2035,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); } @@ -2063,7 +2063,7 @@ __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t Trans * @arg @ref LL_I2C_REQUEST_WRITE * @arg @ref LL_I2C_REQUEST_READ */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); } @@ -2087,7 +2087,7 @@ __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x0 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); } @@ -2150,7 +2150,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr * @arg @ref LL_I2C_DIRECTION_WRITE * @arg @ref LL_I2C_DIRECTION_READ */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); } @@ -2161,7 +2161,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); } @@ -2191,7 +2191,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx) { return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); } @@ -2204,7 +2204,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); } @@ -2215,7 +2215,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx) { return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); } @@ -2241,8 +2241,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) * @{ */ -ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); -ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx); +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx); void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_ipcc.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_ipcc.h index 1d84c0fd74..474dd72640 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_ipcc.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_ipcc.h @@ -710,7 +710,6 @@ __STATIC_INLINE uint32_t LL_IPCC_GetChannelNumber(IPCC_TypeDef *IPCCx) * @} */ - /** * @} */ @@ -719,7 +718,7 @@ __STATIC_INLINE uint32_t LL_IPCC_GetChannelNumber(IPCC_TypeDef *IPCCx) * @} */ -#endif /* defined(IPCC) */ +#endif /* IPCC */ /** * @} diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h index c79a945083..eaecf9fef0 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_pwr.h @@ -48,7 +48,7 @@ extern "C" { #if defined(PWR_CR5_SMPSEN) /** @defgroup PWR_SMPS_Calibration PWR SMPS calibration * @{ - */ + */ #define SMPS_VOLTAGE_CAL_ADDR ((uint32_t*) (0x1FFF7558UL)) /* SMPS output voltage calibration level corresponding to voltage "SMPS_VOLTAGE_CAL_VOLTAGE_MV" */ #define SMPS_VOLTAGE_CAL_POS (8UL) /* SMPS output voltage calibration level bitfield position */ #define SMPS_VOLTAGE_CAL (0xFUL << SMPS_VOLTAGE_CAL_POS) /* SMPS output voltage calibration level bitfield mask */ @@ -58,7 +58,7 @@ extern "C" { /** * @} */ -#endif +#endif /* PWR_CR5_SMPSEN */ /** * @} @@ -79,14 +79,14 @@ extern "C" { #define LL_PWR_SCR_CWUF PWR_SCR_CWUF #if defined(PWR_CR3_EWUP2) #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5 -#endif +#endif /* PWR_CR3_EWUP2 */ #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4 #if defined(PWR_CR3_EWUP3) #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3 -#endif +#endif /* PWR_CR3_EWUP3 */ #if defined(PWR_CR3_EWUP2) #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2 -#endif +#endif /* PWR_CR3_EWUP2 */ #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 #define LL_PWR_SCR_CC2HF PWR_SCR_CC2HF #define LL_PWR_SCR_CBLEAF PWR_SCR_CBLEAF @@ -94,12 +94,12 @@ extern "C" { #if defined(PWR_CR3_E802A) #define LL_PWR_SCR_C802AF PWR_SCR_C802AF #define LL_PWR_SCR_C802WUF PWR_SCR_C802WUF -#endif +#endif /* PWR_CR3_E802A */ #define LL_PWR_SCR_CBLEWUF PWR_SCR_CBLEWUF #if defined(PWR_CR5_SMPSEN) #define LL_PWR_SCR_CBORHF PWR_SCR_CBORHF #define LL_PWR_SCR_CSMPSFBF PWR_SCR_CSMPSFBF -#endif +#endif /* PWR_CR5_SMPSEN */ #define LL_PWR_EXTSCR_CCRPF PWR_EXTSCR_CCRPF #define LL_PWR_EXTSCR_C2CSSF PWR_EXTSCR_C2CSSF #define LL_PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF @@ -114,23 +114,23 @@ extern "C" { #define LL_PWR_SR1_WUFI PWR_SR1_WUFI #if defined(PWR_CR3_EWUP5) #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5 -#endif +#endif /* PWR_CR3_EWUP5 */ #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 #if defined(PWR_CR3_EWUP3) #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3 -#endif +#endif /* PWR_CR3_EWUP3 */ #if defined(PWR_CR3_EWUP2) #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2 -#endif +#endif /* PWR_CR3_EWUP2 */ #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3 #if defined(PWR_CR2_PVME1) #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1 -#endif +#endif /* PWR_CR2_PVME1 */ #define LL_PWR_SR2_PVDO PWR_SR2_PVDO #if defined(PWR_CR1_VOS) #define LL_PWR_SR2_VOSF PWR_SR2_VOSF -#endif +#endif /* PWR_CR1_VOS */ #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS @@ -142,7 +142,7 @@ extern "C" { #define LL_PWR_FLAG_SMPS PWR_SR2_SMPSF /* SMPS step down converter ready flag */ #define LL_PWR_FLAG_SMPSB PWR_SR2_SMPSBF /* SMPS step down converter in bypass mode flag */ #define LL_PWR_FLAG_SMPSFB PWR_SR1_SMPSFB /* SMPS step down converter forced in bypass mode interrupt flag */ -#endif +#endif /* PWR_CR5_SMPSEN */ /* Radio (BLE or 802.15.4) flags */ #define LL_PWR_FLAG_BLEWU PWR_SR1_BLEWUF /* BLE wakeup interrupt flag */ @@ -151,7 +151,7 @@ extern "C" { #if defined(PWR_CR3_E802A) #define LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */ #define LL_PWR_FLAG_802A PWR_SR1_802AF /* 802.15.4 end of activity interrupt flag */ -#endif +#endif /* PWR_CR3_E802A */ #define LL_PWR_FLAG_CRPE PWR_SR1_CRPEF /* Critical radio phase end of activity interrupt flag */ #define LL_PWR_FLAG_CRP PWR_EXTSCR_CRPF /* Critical radio system phase */ @@ -176,7 +176,7 @@ extern "C" { /** * @} */ -#endif +#endif /* PWR_CR1_VOS */ /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR * @{ @@ -185,7 +185,7 @@ extern "C" { #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0) #if defined(PWR_SUPPORT_STOP2) #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_1) -#endif +#endif /* PWR_SUPPORT_STOP2 */ #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2) /** @@ -215,12 +215,12 @@ extern "C" { */ #if defined(PWR_CR2_PVME1) #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */ -#endif +#endif /* PWR_CR2_PVME1 */ #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */ /** * @} */ - + /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL * @{ */ @@ -242,14 +242,14 @@ extern "C" { #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1) #if defined(PWR_CR3_EWUP2) #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2) -#endif +#endif /* PWR_CR3_EWUP2 */ #if defined(PWR_CR3_EWUP3) #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3) -#endif +#endif /* PWR_CR3_EWUP3 */ #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4) #if defined(PWR_CR3_EWUP5) #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5) -#endif +#endif /* PWR_CR3_EWUP5 */ /** * @} */ @@ -315,7 +315,7 @@ extern "C" { #define LL_PWR_GPIO_BIT_13 (PWR_PUCRA_PA13) #define LL_PWR_GPIO_BIT_14 (PWR_PUCRC_PC14) #define LL_PWR_GPIO_BIT_15 (PWR_PUCRC_PC15) -#endif +#endif /* PWR_PUCRC_PC0 */ /** * @} */ @@ -383,7 +383,7 @@ extern "C" { /** * @} */ -#endif +#endif /* PWR_CR5_SMPSEN */ /** * @} @@ -463,7 +463,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) #if defined(PWR_CR1_VOS) /** * @brief Set the main internal regulator output voltage - * @note A delay is required for the internal regulator to be ready + * @note A delay is required for the internal regulator to be ready * after the voltage scaling has been changed. * Check whether regulator reached the selected voltage level * can be done using function @ref LL_PWR_IsActiveFlag_VOS(). @@ -489,7 +489,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) { return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); } -#endif +#endif /* PWR_CR1_VOS */ /** * @brief Enable access to the backup domain @@ -568,7 +568,7 @@ __STATIC_INLINE void LL_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode) { /* Unlock bit FPDR */ WRITE_REG(PWR->CR1, 0x0000C1B0UL); - + /* Update bit FPDR */ MODIFY_REG(PWR->CR1, PWR_CR1_FPDR, FlashLowPowerMode); } @@ -1306,7 +1306,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetBORConfig(void) { return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_BORHC)); } -#endif +#endif /* PWR_CR5_SMPSEN */ /** * @} @@ -1322,7 +1322,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetBORConfig(void) * @note When SMPS step down converter SMPS mode is enabled, * it is good practice to enable the BORH to monitor the supply: * in this case, when the supply drops below the SMPS step down - * converter SMPS mode operating supply level, + * converter SMPS mode operating supply level, * switching on the fly is performed automaticcaly * and interruption is generated. * Refer to function @ref LL_PWR_SetBORConfig(). @@ -1370,9 +1370,9 @@ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void) /* "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()" */ /* and "LL_PWR_SMPS_GetEffectiveMode()". */ uint32_t OperatingMode = (READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) >> (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSF_Pos)); - + OperatingMode = (OperatingMode | ((~OperatingMode >> 1U) & PWR_SR2_SMPSBF)); - + return OperatingMode; } @@ -1506,10 +1506,10 @@ __STATIC_INLINE void LL_PWR_SMPS_SetOutputVoltageLevel(uint32_t OutputVoltageLev int32_t TrimmingSteps; /* Trimming steps between theoretical output voltage and calibrated output voltage */ int32_t OutputVoltageLevelTrimmed; /* SMPS output voltage level after calibration: trimming value added to required level */ - if(OutputVoltageLevel_calibration == 0UL) + if (OutputVoltageLevel_calibration == 0UL) { /* Device with SMPS output voltage not calibrated in production: Apply output voltage value directly */ - + /* Update register */ MODIFY_REG(PWR->CR5, PWR_CR5_SMPSVOS, OutputVoltageLevel); } @@ -1521,13 +1521,13 @@ __STATIC_INLINE void LL_PWR_SMPS_SetOutputVoltageLevel(uint32_t OutputVoltageLev OutputVoltageLevelTrimmed = ((int32_t)((uint32_t)(OutputVoltageLevel >> PWR_CR5_SMPSVOS_Pos)) + (int32_t)TrimmingSteps); /* Clamp value to voltage trimming bitfield range */ - if(OutputVoltageLevelTrimmed < 0) + if (OutputVoltageLevelTrimmed < 0) { OutputVoltageLevelTrimmed = 0; } else { - if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS) + if (OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS) { OutputVoltageLevelTrimmed = (int32_t)PWR_CR5_SMPSVOS; } @@ -1567,10 +1567,10 @@ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetOutputVoltageLevel(void) int32_t TrimmingSteps; /* Trimming steps between theoretical output voltage and calibrated output voltage */ int32_t OutputVoltageLevelTrimmed; /* SMPS output voltage level after calibration: trimming value added to required level */ - if(OutputVoltageLevel_calibration == 0UL) + if (OutputVoltageLevel_calibration == 0UL) { /* Device with SMPS output voltage not calibrated in production: Return output voltage value directly */ - + return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSVOS)); } else @@ -1582,13 +1582,13 @@ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetOutputVoltageLevel(void) OutputVoltageLevelTrimmed = ((int32_t)((uint32_t)READ_BIT(PWR->CR5, PWR_CR5_SMPSVOS)) - TrimmingSteps); /* Clamp value to voltage range */ - if(OutputVoltageLevelTrimmed < 0) + if (OutputVoltageLevelTrimmed < 0) { OutputVoltageLevelTrimmed = (int32_t)LL_PWR_SMPS_OUTPUT_VOLTAGE_1V20; } else { - if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS) + if (OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS) { OutputVoltageLevelTrimmed = (int32_t)LL_PWR_SMPS_OUTPUT_VOLTAGE_1V90; } @@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetOutputVoltageLevel(void) /** * @} */ -#endif +#endif /* PWR_CR5_SMPSEN */ /** @defgroup PWR_LL_EF_Configuration_Multicore Configuration of multicore, intended to be executed by CPU1 * @{ @@ -1694,7 +1694,7 @@ __STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode { /* Unlock bit FPDR */ WRITE_REG(PWR->C2CR1, 0x0000C1B0UL); - + /* Update bit FPDR */ MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDR, FlashLowPowerMode); } @@ -1917,7 +1917,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_802_15_4(void) { return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_802EWKUP) == (PWR_C2CR1_802EWKUP)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR3_E802A */ /** * @} @@ -1947,7 +1947,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR3_EWUP5 */ /** * @brief Get Wake-up Flag 4 @@ -1969,7 +1969,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR3_EWUP3 */ #if defined(PWR_CR3_EWUP2) /** @@ -1981,7 +1981,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR3_EWUP2 */ /** * @brief Get Wake-up Flag 1 @@ -2013,7 +2013,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) { WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); } -#endif +#endif /* PWR_CR3_EWUP5 */ /** * @brief Clear Wake-up Flag 4 @@ -2035,7 +2035,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) { WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); } -#endif +#endif /* PWR_CR3_EWUP3 */ #if defined(PWR_CR3_EWUP2) /** @@ -2047,7 +2047,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) { WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); } -#endif +#endif /* PWR_CR3_EWUP2 */ /** * @brief Clear Wake-up Flag 1 @@ -2080,7 +2080,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void) { return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR2_PVME1 */ /** * @brief Indicate whether VDD voltage is below or above the selected PVD threshold @@ -2102,7 +2102,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) { return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR1_VOS */ /** * @brief Indicate whether the regulator is ready in main mode or is in low-power mode @@ -2185,7 +2185,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_SMPSFB(void) /** * @} */ -#endif +#endif /* PWR_CR5_SMPSEN */ /** @defgroup PWR_LL_EF_FLAG_Management_Radio FLAG management for radio (BLE or 802.15.4) * @{ @@ -2211,7 +2211,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802WU(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_802WUF) == (PWR_SR1_802WUF)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR3_E802A */ /** * @brief Get BLE end of activity interrupt flag @@ -2233,7 +2233,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802A(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_802AF) == (PWR_SR1_802AF)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR3_E802A */ /** * @brief Get critical radio phase end of activity interrupt flag @@ -2275,7 +2275,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_802WU(void) { WRITE_REG(PWR->SCR, PWR_SCR_C802WUF); } -#endif +#endif /* PWR_CR3_E802A */ /** * @brief Clear BLE end of activity interrupt flag @@ -2297,7 +2297,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_802A(void) { WRITE_REG(PWR->SCR, PWR_SCR_C802AF); } -#endif +#endif /* PWR_CR3_E802A */ /** * @brief Clear critical radio phase end of activity interrupt flag @@ -2475,7 +2475,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_BORH_SMPSFB(void) /** * @} */ -#endif +#endif /* PWR_CR5_SMPSEN */ /** @defgroup PWR_LL_EF_IT_Management_Radio PWR IT management for radio (BLE or 802.15.4) * @{ @@ -2501,7 +2501,7 @@ __STATIC_INLINE void LL_PWR_EnableIT_802A(void) { SET_BIT(PWR->CR3, PWR_CR3_E802A); } -#endif +#endif /* PWR_CR3_E802A */ /** * @brief Disable BLE end of activity interrupt for CPU1 @@ -2523,7 +2523,7 @@ __STATIC_INLINE void LL_PWR_DisableIT_802A(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_E802A); } -#endif +#endif /* PWR_CR3_E802A */ /** * @brief Check if BLE end of activity interrupt is enabled for CPU1 @@ -2545,7 +2545,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_802A(void) { return ((READ_BIT(PWR->CR3, PWR_CR3_E802A) == (PWR_CR3_E802A)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR3_E802A */ /** * @brief Enable critical radio phase end of activity interrupt for CPU1 @@ -2643,7 +2643,7 @@ __STATIC_INLINE void LL_C2_PWR_EnableIT_802WU(void) { SET_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP); } -#endif +#endif /* PWR_CR3_E802A */ /** * @brief Disable BLE host wakeup interrupt for CPU2 @@ -2665,7 +2665,7 @@ __STATIC_INLINE void LL_C2_PWR_DisableIT_802WU(void) { CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP); } -#endif +#endif /* PWR_CR3_E802A */ /** * @brief Check if BLE host wakeup interrupt is enabled for CPU2 @@ -2687,7 +2687,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_802WU(void) { return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP) == (PWR_C2CR3_E802WUP)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR3_E802A */ /** * @} @@ -2711,7 +2711,7 @@ ErrorStatus LL_PWR_DeInit(void); * @} */ -#endif /* defined(PWR) */ +#endif /* PWR */ /** * @} diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h index feb73d8395..c00c0d5082 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_rcc.h @@ -58,7 +58,7 @@ extern "C" { /** * @} */ -#endif /*USE_FULL_LL_DRIVER*/ +#endif /* USE_FULL_LL_DRIVER */ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) @@ -106,11 +106,11 @@ typedef struct */ #if !defined (HSE_VALUE) #define HSE_VALUE 32000000U /*!< Value of the HSE oscillator in Hz */ -#endif /* HSE_VALUE */ +#endif /* !HSE_VALUE */ #if !defined (HSI_VALUE) #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ -#endif /* HSI_VALUE */ +#endif /* !HSI_VALUE */ #if !defined (LSE_VALUE) #if defined(STM32WB5Mxx) @@ -118,17 +118,17 @@ typedef struct #else #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ #endif /* STM32WB5Mxx */ -#endif /* LSE_VALUE */ +#endif /* !LSE_VALUE */ #if !defined (LSI_VALUE) #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ -#endif /* LSI_VALUE */ +#endif /* !LSI_VALUE */ #if defined(RCC_HSI48_SUPPORT) #if !defined (HSI48_VALUE) #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ -#endif /* HSI48_VALUE */ -#endif +#endif /* !HSI48_VALUE */ +#endif /* RCC_HSI48_SUPPORT */ /** * @} @@ -147,10 +147,10 @@ typedef struct #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ #if defined(RCC_HSI48_SUPPORT) #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ -#endif +#endif /* RCC_HSI48_SUPPORT */ #if defined(SAI1) #define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */ -#endif +#endif /* SAI1 */ #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ /** @@ -170,10 +170,10 @@ typedef struct #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ #if defined(RCC_HSI48_SUPPORT) #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ -#endif +#endif /* RCC_HSI48_SUPPORT */ #if defined(SAI1) #define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ -#endif +#endif /* SAI1 */ #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ @@ -200,10 +200,10 @@ typedef struct #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ #if defined(RCC_HSI48_SUPPORT) #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ -#endif +#endif /* RCC_HSI48_SUPPORT */ #if defined(SAI1) #define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /*!< PLLSAI1 Ready Interrupt Enable */ -#endif +#endif /* SAI1 */ #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */ /** * @} @@ -372,7 +372,7 @@ typedef struct #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_3 /*!< LSE selection as MCO1 source */ #if defined(RCC_HSI48_SUPPORT) #define LL_RCC_MCO1SOURCE_HSI48 (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_3) /*!< HSI48 selection as MCO1 source */ -#endif +#endif /* RCC_HSI48_SUPPORT */ #define LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB (RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3) /*!< HSE before stabilization selection as MCO1 source */ /** * @} @@ -422,7 +422,7 @@ typedef struct /** * @} */ -#endif +#endif /* RCC_SMPS_SUPPORT */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency @@ -457,7 +457,7 @@ typedef struct /** * @} */ -#endif +#endif /* LPUART1 */ /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE I2Cx CLKSOURCE * @{ @@ -469,7 +469,7 @@ typedef struct #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C3 clock */ #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4)) /*!< SYSCLK selected as I2C3 clock */ #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI selected as I2C3 clock */ -#endif +#endif /* I2C3 */ /** * @} */ @@ -500,17 +500,17 @@ typedef struct /** * @} */ -#endif +#endif /* SAI1 */ /** @defgroup RCC_LL_EC_CLK48_CLKSOURCE CLK48 CLKSOURCE * @{ */ #if defined(RCC_HSI48_SUPPORT) #define LL_RCC_CLK48_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 selected as CLK48 clock */ -#endif +#endif /* RCC_HSI48_SUPPORT */ #if defined(SAI1) #define LL_RCC_CLK48_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 selected as CLK48 clock */ -#endif +#endif /* SAI1 */ #define LL_RCC_CLK48_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL selected as CLK48 clock */ #define LL_RCC_CLK48_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI selected as CLK48 clock */ /** @@ -522,10 +522,10 @@ typedef struct */ #if defined(RCC_HSI48_SUPPORT) #define LL_RCC_USB_CLKSOURCE_HSI48 LL_RCC_CLK48_CLKSOURCE_HSI48 /*!< HSI48 selected as USB clock */ -#endif +#endif /* RCC_HSI48_SUPPORT */ #if defined(SAI1) #define LL_RCC_USB_CLKSOURCE_PLLSAI1 LL_RCC_CLK48_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 selected as USB clock */ -#endif +#endif /* SAI1 */ #define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CLK48_CLKSOURCE_PLL /*!< PLL selected as USB clock */ #define LL_RCC_USB_CLKSOURCE_MSI LL_RCC_CLK48_CLKSOURCE_MSI /*!< MSI selected as USB clock */ /** @@ -540,7 +540,7 @@ typedef struct #define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /*!< PLLSAI1 selected as ADC clock*/ #elif defined (STM32WB15xx) || defined(STM32WB1Mxx) #define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_0 /*!< HSI selected as ADC clock */ -#endif +#endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx */ #define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock */ #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock */ /** @@ -574,7 +574,7 @@ typedef struct /** * @} */ -#endif +#endif /* LPUART1 */ /** @defgroup RCC_LL_EC_I2C1 I2C1 * @{ @@ -602,7 +602,7 @@ typedef struct /** * @} */ -#endif +#endif /* SAI1 */ /** @defgroup RCC_LL_EC_CLK48 CLK48 * @{ @@ -823,7 +823,7 @@ typedef struct /** * @} */ -#endif +#endif /* SAI1 */ /** * @} @@ -939,7 +939,7 @@ typedef struct */ #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U))/ \ (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) -#endif +#endif /* SAI1 */ /** * @brief Helper macro to calculate the PLLPCLK frequency used on ADC domain @@ -1133,7 +1133,7 @@ typedef struct #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \ ((__INPUTFREQ__) * (__PLLSAI1N__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ (((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLR_Pos) + 1U)) -#endif +#endif /* SAI1 */ /** * @brief Helper macro to calculate the HCLK1 frequency @@ -1609,7 +1609,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) /** * @} */ -#endif +#endif /* RCC_HSI48_SUPPORT */ /** @defgroup RCC_LL_EF_LSE LSE * @{ @@ -2450,7 +2450,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetSMPSPrescaler(void) /** * @} */ -#endif +#endif /* RCC_SMPS_SUPPORT */ /** @defgroup RCC_LL_EF_MCO MCO * @{ @@ -2524,7 +2524,7 @@ __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) { MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); } -#endif +#endif /* LPUART1 */ /** * @brief Configure I2Cx clock source @@ -2578,7 +2578,7 @@ __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) { MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource); } -#endif +#endif /* SAI1 */ /** * @brief Configure RNG clock source @@ -2626,7 +2626,7 @@ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) { LL_RCC_SetCLK48ClockSource(USBxSource); } -#endif +#endif /* USB */ /** * @brief Configure RNG clock source @@ -2706,7 +2706,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) { return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); } -#endif +#endif /* LPUART1 */ /** * @brief Get I2Cx clock source @@ -2765,7 +2765,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) { return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx)); } -#endif +#endif /* SAI1 */ /** * @brief Get RNGx clock source @@ -2815,7 +2815,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) { return LL_RCC_GetCLK48ClockSource(USBx); } -#endif +#endif /* USB */ /** * @brief Get ADCx clock source @@ -3066,7 +3066,7 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); } -#endif +#endif /* SAI1 */ /** * @brief Configure PLL used for ADC domain clock @@ -3301,7 +3301,7 @@ __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void) { CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); } -#endif +#endif /* SAI1 */ /** * @brief Check if PLL output mapped on SAI domain clock is enabled @@ -3781,7 +3781,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsEnabledDomain_ADC(void) { return ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLREN) == (RCC_PLLSAI1CFGR_PLLREN)) ? 1UL : 0UL); } -#endif +#endif /* SAI1 */ /** * @} @@ -3901,7 +3901,7 @@ __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) { SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); } -#endif +#endif /* RCC_HSI48_SUPPORT */ #if defined(SAI1) /** @@ -3913,7 +3913,7 @@ __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void) { SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC); } -#endif +#endif /* SAI1 */ /** * @brief Clear Clock security system interrupt flag @@ -4015,7 +4015,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) { return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL); } -#endif +#endif /* RCC_HSI48_SUPPORT */ #if defined(SAI1) /** @@ -4027,7 +4027,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void) { return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF)) ? 1UL : 0UL); } -#endif +#endif /* SAI1 */ /** * @brief Check if Clock security system interrupt occurred or not @@ -4267,7 +4267,7 @@ __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) { SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); } -#endif +#endif /* RCC_HSI48_SUPPORT */ #if defined(SAI1) /** @@ -4279,7 +4279,7 @@ __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void) { SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); } -#endif +#endif /* SAI1 */ /** * @brief Enable LSE clock security system interrupt @@ -4370,7 +4370,7 @@ __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) { CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); } -#endif +#endif /* RCC_HSI48_SUPPORT */ #if defined(SAI1) /** @@ -4382,7 +4382,7 @@ __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void) { CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE); } -#endif +#endif /* SAI1 */ /** * @brief Disable LSE clock security system interrupt @@ -4473,7 +4473,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) { return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL); } -#endif +#endif /* RCC_HSI48_SUPPORT */ #if defined(SAI1) /** @@ -4485,7 +4485,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void) { return ((READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE)) ? 1UL : 0UL); } -#endif +#endif /* SAI1 */ /** * @brief Checks if LSECSS interrupt source is enabled or disabled. @@ -4516,21 +4516,21 @@ ErrorStatus LL_RCC_DeInit(void); void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); #if defined(RCC_SMPS_SUPPORT) uint32_t LL_RCC_GetSMPSClockFreq(void); -#endif +#endif /* RCC_SMPS_SUPPORT */ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); #if defined(LPUART1) uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); -#endif +#endif /* LPUART1 */ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); #if defined(SAI1) uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); -#endif +#endif /* SAI1 */ uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource); uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); #if defined(USB) uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); -#endif +#endif /* USB */ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); uint32_t LL_RCC_GetRTCClockFreq(void); uint32_t LL_RCC_GetRFWKPClockFreq(void); @@ -4547,7 +4547,7 @@ uint32_t LL_RCC_GetRFWKPClockFreq(void); * @} */ -#endif /* defined(RCC) */ +#endif /* RCC */ /** * @} diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_utils.h b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_utils.h index 4fc5054a65..9742652309 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_utils.h +++ b/system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_utils.h @@ -60,18 +60,18 @@ extern "C" { #define LL_MAX_DELAY 0xFFFFFFFFU /** - * @brief Unique device ID register base address - */ + * @brief Unique device ID register base address + */ #define UID_BASE_ADDRESS UID_BASE /** - * @brief Flash size data register base address - */ + * @brief Flash size data register base address + */ #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE /** - * @brief Package data register base address - */ + * @brief Package data register base address + */ #define PACKAGE_BASE_ADDRESS PACKAGE_BASE /** diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html index 2680d838d1..c141efca5a 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32WBxx_HAL_Driver/Release_Notes.html @@ -40,16 +40,60 @@

Purpose

Update History

- +

Main Changes

  • Maintenance release of HAL and Low Layer drivers to include latest corrections
    • -
  • Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & HAL_xxxx_UnregisterCallback for IPs (IRDA, LPTIM, SMARTCARD, TIM, UART, USART)
    • +
  • HAL/LL code quality enhancement

Contents

HAL Drivers updates

    +
  • HAL FLASH driver +
      +
    • Fix missing STM32WB10xx preprocessor checks for several constants (FLASH_PCROP_GRANULARITY_OFFSET,SRAM2B_START_SECURE_ADDR_4,FLASH_PAGE_SIZE..)
      • +
    • Fix wrong value of constant SRAM_SECURE_PAGE_GRANULARITY for STM32WB5x & STM32WB3x devices
      • +
    • +
  • HAL Generic driver +
      +
    • Add missing preprocessor directive on macros IS_SYSCFG_SRAM2WRP_PAGE & IS_SYSCFG_SRAM2WRP2_PAGE for STM32WB10xx device
      • +
    • Fix Tick priority handling in HAL_Init_Tick()
      • +
    • +
  • HAL I2C driver +
      +
    • Enhance I2C HAL to be thread safe
      • +
    • Remove HAL DMA dependency thanks to the HAL_DMA_MODULE_ENABLED define
      • +
    • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers
      • +
    • +
  • HAL SAI driver +
      +
    • Add 24kHz audio frequency for SAI
      • +
    • +
  • HAL TSC driver
    • +

  • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers

    • +
  • HAL UART driver +
      +
    • Rework of UART_WaitOnFlagUntilTimeout() API to avoid being stuck forever when UART overrun error occurs and to enhance behavior.
      • +
    • +
+


+

+

Backward Compatibility

+

This release is compatible with the previous versions.

+
+
+
+ +
+

Main Changes

+
    +
  • Maintenance release of HAL and Low Layer drivers to include latest corrections
    • +
  • Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & HAL_xxxx_UnregisterCallback for IPs (IRDA, LPTIM, SMARTCARD, TIM, UART, USART)
    • +
+

Contents

+

HAL Drivers updates

+
  • HAL ADC driver
    • Disable AutoPowerOff when performing calibration
      • @@ -116,20 +160,20 @@

      LL Drivers updates


    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

  • Maintenance release of HAL and Low Layer drivers to include latest corrections
  • Correct English spelling errors and typos
-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL EXTI driver
      @@ -241,19 +285,19 @@

      LL Drivers updates


    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

  • Patch release of HAL and Low Layer drivers
-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL COMP driver
      @@ -271,21 +315,21 @@

      LL Drivers updates


    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

  • Maintenance release of HAL and Low Layer drivers to include latest corrections
  • All source files: update disclaimer to add reference to the new license agreement
  • Correct English spelling errors and typos
-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL ADC driver
      @@ -371,14 +415,14 @@

      LL Drivers updates


    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

  • Maintenance release of HAL and Low Layer drivers to include latest corrections
  • Update of HAL SMBUS driver to introduce fast mode and fast mode plus @@ -392,8 +436,8 @@

    Main Changes


-

Contents

-

HAL Drivers updates

+

Contents

+

HAL Drivers updates

  • HAL CORTEX driver
      @@ -496,14 +540,14 @@

      LL Drivers updates


    -

    Backward Compatibility

    +

    Backward Compatibility

    This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

Add support for STM32WB15xx and STM32WB10xx

@@ -639,14 +683,14 @@

Add support for STM32WB15xx

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

Maitenance release

All peripheral

@@ -719,14 +763,14 @@

Maitenance release

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

Maitenance release

All peripheral

@@ -831,14 +875,14 @@

Maitenance release

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

Introduction of STM32WB5M, STM32WB35xx and STM32WB30xx product

This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.

Added features:

@@ -883,14 +927,14 @@

Introduct -

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

-

Main Changes

+

Main Changes

Maitenance release

@@ -934,7 +978,7 @@

Maitenance release

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

Dependencies

This software release is compatible with:

@@ -944,7 +988,7 @@

Dependencies

-

Main Changes

+

Main Changes

Maitenance release

@@ -1016,7 +1060,7 @@

Maitenance release

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

Dependencies

This software release is compatible with:

@@ -1026,7 +1070,7 @@

Dependencies

-

Main Changes

+

Main Changes

STM32WB50xx introduction and maintenance release

First release for STM32WBxx HAL drivers introducing stm32wb50xx devices.

@@ -1095,7 +1139,7 @@

STM32WB50xx introducti

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

Dependencies

This software release is compatible with:

@@ -1105,7 +1149,7 @@

Dependencies

-

Main Changes

+

Main Changes

Maintenance release

Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.

@@ -1159,7 +1203,7 @@

Maintenance release

-

Backward Compatibility

+

Backward Compatibility

This release is compatible with the previous versions.

Dependencies

This software release is compatible with:

@@ -1169,7 +1213,7 @@

Dependencies

-

Main Changes

+

Main Changes

First release

First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.

diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c index c321a664fd..31abf2b62f 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c @@ -55,7 +55,7 @@ * @brief STM32WBxx HAL Driver version number */ #define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBxx_HAL_VERSION_SUB1 (0x0CU) /*!< [23:16] sub1 version */ +#define __STM32WBxx_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */ #define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\ @@ -360,7 +360,7 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) /* Update uwTickFreq global variable used by HAL_InitTick() */ uwTickFreq = Freq; - /* Apply the new tick Freq */ + /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); if (status != HAL_OK) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c index 3701c334ae..3e2384ed35 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cortex.c @@ -39,7 +39,7 @@ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() - + -@- Negative value of IRQn_Type are not allowed. *** How to configure Systick using CORTEX HAL driver *** @@ -386,7 +386,7 @@ void HAL_MPU_Disable(void) /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - + /* Disable the MPU and clear the control register*/ MPU->CTRL = 0U; } @@ -406,10 +406,10 @@ void HAL_MPU_Enable(uint32_t MPU_Control) { /* Enable the MPU */ MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); - + /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; - + /* Ensure MPU setting take effects */ __DSB(); __ISB(); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c index 37d0c3fbc8..316e71f64c 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma.c @@ -123,8 +123,8 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); */ /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * + * @brief Initialization and de-initialization functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -188,7 +188,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; hdma->DmaBaseAddress = DMA1; -#endif +#endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; @@ -298,7 +298,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; hdma->DmaBaseAddress = DMA1; -#endif +#endif /* DMA2 */ /* Reset DMA Channel control register */ hdma->Instance->CCR = 0U; @@ -359,8 +359,8 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) */ /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions - * @brief Input and Output operation functions - * + * @brief Input and Output operation functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -429,7 +429,8 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; @@ -508,7 +509,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) } /* Check the DMA peripheral state */ - if(hdma->State != HAL_DMA_STATE_BUSY) + if (hdma->State != HAL_DMA_STATE_BUSY) { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; @@ -621,7 +622,8 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout) { uint32_t temp; uint32_t tickstart; @@ -656,9 +658,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* Get tick */ tickstart = HAL_GetTick(); - while((hdma->DmaBaseAddress->ISR & temp) == 0U) + while ((hdma->DmaBaseAddress->ISR & temp) == 0U) { - if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U) + if ((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ @@ -679,7 +681,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; @@ -801,7 +803,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } /* Transfer Error Interrupt management **************************************/ - else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU)))!= 0U) && ((source_it & DMA_IT_TE) != 0U)) + else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ @@ -951,8 +953,8 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * + * @brief Peripheral State and Errors functions + * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### @@ -1072,7 +1074,7 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) #else /* DMA1 */ hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); -#endif +#endif /* DMA2 */ channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c index 87faff304d..239665cc64 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_dma_ex.c @@ -68,8 +68,8 @@ */ /** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions - * @brief Extended features functions - * + * @brief Extended features functions + * @verbatim =============================================================================== ##### Extended features functions ##### @@ -134,12 +134,13 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSy * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA channel. -* @param pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : + * @param pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : * contains the request generator parameters. * * @retval HAL status */ -HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, + HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) { /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c index 97d54a1334..4f2232aded 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash.c @@ -115,8 +115,8 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ + * @{ + */ /** * @brief Variable used for Program/Erase sectors under interruption */ @@ -133,8 +133,8 @@ FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ + * @{ + */ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); /** @@ -147,8 +147,8 @@ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); */ /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * + * @brief Programming operation functions + * @verbatim =============================================================================== ##### Programming operation functions ##### @@ -424,8 +424,8 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) */ /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief Management functions - * + * @brief Management functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -549,8 +549,8 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) */ /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral Errors functions - * + * @brief Peripheral Errors functions + * @verbatim =============================================================================== ##### Peripheral Errors functions ##### @@ -715,8 +715,7 @@ static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress dest_addr++; src_addr++; row_index--; - } - while (row_index != 0U); + } while (row_index != 0U); /* wait for BSY in order to be sure that flash operation is ended before allowing prefetch in flash. Timeout does not return status, as it will diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c index 401cc39c87..e54df6707a 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c @@ -95,22 +95,25 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions - * @{ - */ + * @{ + */ static void FLASH_AcknowledgePageErase(void); static void FLASH_FlushCaches(void); static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel); -static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr); +static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, + uint32_t PCROP1AEndAddr); static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr); static void FLASH_OB_IPCCBufferAddrConfig(uint32_t IPCCDataBufAddr); static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam); static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset); static uint32_t FLASH_OB_GetRDP(void); static uint32_t FLASH_OB_GetUser(void); -static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr, uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr); +static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr, + uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr); static uint32_t FLASH_OB_GetIPCCBufferAddr(void); -static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint32_t *SecureRAM2aStartAddr, uint32_t *SecureRAM2bStartAddr, uint32_t *SecureMode); +static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint32_t *SecureRAM2aStartAddr, + uint32_t *SecureRAM2bStartAddr, uint32_t *SecureMode); static void FLASH_OB_GetC2BootResetConfig(uint32_t *C2BootResetVectAddr, uint32_t *C2BootResetRegion); static HAL_StatusTypeDef FLASH_OB_ProceedWriteOperation(void); /** @@ -123,8 +126,8 @@ static HAL_StatusTypeDef FLASH_OB_ProceedWriteOperation(void); */ /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions - * @brief Extended IO operation functions - * + * @brief Extended IO operation functions + * @verbatim =============================================================================== ##### Extended programming operation functions ##### @@ -384,14 +387,16 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) pOBInit->UserType = OB_USER_ALL; /* Get the Zone 1A and 1B Proprietary code readout protection */ - FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROP1AStartAddr), &(pOBInit->PCROP1AEndAddr), &(pOBInit->PCROP1BStartAddr), &(pOBInit->PCROP1BEndAddr)); + FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROP1AStartAddr), &(pOBInit->PCROP1AEndAddr), + &(pOBInit->PCROP1BStartAddr), &(pOBInit->PCROP1BEndAddr)); pOBInit->PCROPConfig |= (OB_PCROP_ZONE_A | OB_PCROP_ZONE_B); /* Get the IPCC start Address */ pOBInit->IPCCdataBufAddr = FLASH_OB_GetIPCCBufferAddr(); /* Get the Secure Flash start address, Secure Backup RAM2a start address, Secure non-Backup RAM2b start address and the Security Mode, */ - FLASH_OB_GetSecureMemoryConfig(&(pOBInit->SecureFlashStartAddr), &(pOBInit->SecureRAM2aStartAddr), &(pOBInit->SecureRAM2bStartAddr), &(pOBInit->SecureMode)); + FLASH_OB_GetSecureMemoryConfig(&(pOBInit->SecureFlashStartAddr), &(pOBInit->SecureRAM2aStartAddr), + &(pOBInit->SecureRAM2bStartAddr), &(pOBInit->SecureMode)); /* Get the M0+ Secure Boot reset vector and Secure Boot memory selection */ FLASH_OB_GetC2BootResetConfig(&(pOBInit->C2SecureBootVectAddr), &(pOBInit->C2BootRegion)); @@ -777,7 +782,7 @@ static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam) MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA | FLASH_SRRVR_SNBRSA), \ (((((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_Pos)) | \ ((((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SNBRSA_Pos)))); -#endif +#endif /* FLASH_SRRVR_SBRSA_A */ /* If Full System Secure mode is requested, clear all the corresponding bit */ /* Else set the corresponding bit */ @@ -788,7 +793,7 @@ static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam) CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD_A | FLASH_SRRVR_BRSD_B)); #else CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD)); -#endif +#endif /* FLASH_SRRVR_BRSD_A */ } else { @@ -797,7 +802,7 @@ static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam) SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD_A | FLASH_SRRVR_BRSD_B)); #else SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD)); -#endif +#endif /* FLASH_SRRVR_BRSD_A */ } /* Update Flash registers */ @@ -814,11 +819,13 @@ static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam) /* Set the boot vector */ if (pOBParam->C2BootRegion == OB_C2_BOOT_FROM_FLASH) { - MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), (((pOBParam->C2SecureBootVectAddr - FLASH_BASE) >> 2) | pOBParam->C2BootRegion)); + MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), + (((pOBParam->C2SecureBootVectAddr - FLASH_BASE) >> 2) | pOBParam->C2BootRegion)); } else { - MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), (((pOBParam->C2SecureBootVectAddr - SRAM1_BASE) >> 2) | pOBParam->C2BootRegion)); + MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), + (((pOBParam->C2SecureBootVectAddr - SRAM1_BASE) >> 2) | pOBParam->C2BootRegion)); } } @@ -919,7 +926,8 @@ static uint32_t FLASH_OB_GetUser(void) * the Zone 1B Proprietary code readout protection * @retval None */ -static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr, uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr) +static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr, + uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr) { uint32_t pcrop; @@ -958,7 +966,8 @@ static uint32_t FLASH_OB_GetIPCCBufferAddr(void) * @arg @ref SYSTEM_NOT_IN_SECURE_MODE : Security disabled * @retval None */ -static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint32_t *SecureRAM2aStartAddr, uint32_t *SecureRAM2bStartAddr, uint32_t *SecureMode) +static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint32_t *SecureRAM2aStartAddr, + uint32_t *SecureRAM2bStartAddr, uint32_t *SecureMode) { uint32_t sfr_reg_val = READ_REG(FLASH->SFR); uint32_t srrvr_reg_val = READ_REG(FLASH->SRRVR); @@ -973,7 +982,7 @@ static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint3 user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA_A) >> FLASH_SRRVR_SBRSA_A_Pos); #else user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA) >> FLASH_SRRVR_SBRSA_Pos); -#endif +#endif /* FLASH_SRRVR_SBRSA_A */ *SecureRAM2aStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2A_BASE); @@ -982,7 +991,7 @@ static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint3 user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA_B) >> FLASH_SRRVR_SBRSA_B_Pos); #else user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SNBRSA) >> FLASH_SRRVR_SNBRSA_Pos); -#endif +#endif /* FLASH_SRRVR_SBRSA_B */ *SecureRAM2bStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2B_BASE); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c index 3250ae0582..d7acf1c2d8 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c @@ -400,9 +400,17 @@ * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macro + * @{ + */ +#if defined(HAL_DMA_MODULE_ENABLED) /* Macro to get remaining data to transfer on DMA side */ #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -410,6 +418,7 @@ /** @defgroup I2C_Private_Functions I2C Private Functions * @{ */ +#if defined(HAL_DMA_MODULE_ENABLED) /* Private functions to handle DMA transfer */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); @@ -418,6 +427,8 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAError(DMA_HandleTypeDef *hdma); static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ + /* Private functions to handle IT transfer */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); @@ -442,12 +453,14 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32 uint32_t ITSources); static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +#if defined(HAL_DMA_MODULE_ENABLED) static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +#endif /* HAL_DMA_MODULE_ENABLED */ /* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, @@ -711,6 +724,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) /** * @brief Register a User I2C Callback * To be used instead of the weak predefined callback + * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param CallbackID ID of the callback to be registered @@ -741,8 +756,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { @@ -831,14 +844,14 @@ HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } /** * @brief Unregister an I2C Callback * I2C callback is redirected to the weak predefined callback + * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param CallbackID ID of the callback to be unregistered @@ -861,9 +874,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hi2c); - if (HAL_I2C_STATE_READY == hi2c->State) { switch (CallbackID) @@ -951,8 +961,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -975,8 +983,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_Add return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { @@ -991,8 +997,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_Add status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -1007,9 +1011,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hi2c); - if (HAL_I2C_STATE_READY == hi2c->State) { hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ @@ -1023,8 +1024,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -1393,6 +1392,19 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData return HAL_ERROR; } + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1789,6 +1801,20 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_IT; + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1860,6 +1886,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Transmit in master mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -2187,67 +2214,99 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_DMA; - if (hi2c->hdmatx != NULL) + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; - /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); + hi2c->XferCount--; + hi2c->XferSize--; } - else + + if (hi2c->XferCount != 0U) { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; - return HAL_ERROR; - } + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; - if (dmaxferstatus == HAL_OK) - { - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + return HAL_ERROR; + } - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } } else { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); } return HAL_OK; @@ -2361,6 +2420,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD return HAL_BUSY; } } +#endif /* HAL_DMA_MODULE_ENABLED */ + /** * @brief Write an amount of data in blocking mode to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -2809,6 +2870,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre return HAL_BUSY; } } + +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -3100,6 +3163,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr return HAL_BUSY; } } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Checks if target device is ready for communication. @@ -3333,6 +3397,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. * @note This interface allow to manage repeated start condition when a direction change during transfer @@ -3500,6 +3565,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 return HAL_BUSY; } } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt @@ -3588,6 +3654,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA * @note This interface allow to manage repeated start condition when a direction change during transfer @@ -3755,6 +3822,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 return HAL_BUSY; } } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt @@ -3769,6 +3837,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3793,6 +3864,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +#if defined(HAL_DMA_MODULE_ENABLED) /* Abort DMA Xfer if any */ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { @@ -3812,6 +3884,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t } } } +#endif /* HAL_DMA_MODULE_ENABLED */ } hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; @@ -3828,7 +3901,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -3852,6 +3926,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA * @note This interface allow to manage repeated start condition when a direction change during transfer @@ -3865,6 +3940,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -3899,7 +3976,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA RX */ @@ -3921,7 +3998,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ if (hi2c->hdmatx != NULL) { /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA TX */ @@ -4006,7 +4083,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ return HAL_ERROR; } - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4032,6 +4110,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ return HAL_ERROR; } } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt @@ -4046,6 +4125,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -4070,6 +4152,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +#if defined(HAL_DMA_MODULE_ENABLED) if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -4089,6 +4172,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t } } } +#endif /* HAL_DMA_MODULE_ENABLED */ } hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; @@ -4105,7 +4189,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4129,6 +4214,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA * @note This interface allow to manage repeated start condition when a direction change during transfer @@ -4142,6 +4228,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -4283,7 +4371,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t return HAL_ERROR; } - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4309,6 +4398,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t return HAL_ERROR; } } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Enable the Address listen mode with Interrupt. @@ -4435,7 +4525,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA * the configuration information for the specified I2C. * @retval None */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ { /* Get current IT Flags and IT sources value */ uint32_t itflags = READ_REG(hi2c->Instance->ISR); @@ -4688,7 +4778,7 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval HAL state */ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) { /* Return I2C handle state */ return hi2c->State; @@ -4700,7 +4790,7 @@ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) * the configuration information for I2C module * @retval HAL mode */ -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) { return hi2c->Mode; } @@ -4711,7 +4801,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) * the configuration information for the specified I2C. * @retval I2C Error Code */ -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) { return hi2c->ErrorCode; } @@ -4883,7 +4973,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin * @retval HAL status */ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint32_t direction = I2C_GENERATE_START_WRITE; uint32_t tmpITFlags = ITFlags; @@ -5152,6 +5242,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint return HAL_OK; } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -5301,7 +5392,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui * @retval HAL status */ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint32_t direction = I2C_GENERATE_START_WRITE; @@ -5571,6 +5662,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin return HAL_OK; } +#endif /* HAL_DMA_MODULE_ENABLED */ /** * @brief Master sends target device address followed by internal memory address for write request. @@ -5843,6 +5935,7 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; +#if defined(HAL_DMA_MODULE_ENABLED) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { @@ -5858,6 +5951,7 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { /* Do nothing */ } +#endif /* HAL_DMA_MODULE_ENABLED */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { @@ -6087,6 +6181,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Flush TX register */ I2C_Flush_TXDR(hi2c); +#if defined(HAL_DMA_MODULE_ENABLED) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { @@ -6112,6 +6207,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { /* Do nothing */ } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Store Last receive data if any */ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) @@ -6266,7 +6362,10 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; + +#if defined(HAL_DMA_MODULE_ENABLED) uint32_t tmppreviousstate; +#endif /* HAL_DMA_MODULE_ENABLED */ /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; @@ -6293,18 +6392,37 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + } hi2c->XferISR = NULL; } +#if defined(HAL_DMA_MODULE_ENABLED) /* Abort DMA TX transfer if any */ tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { @@ -6365,6 +6483,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } } else +#endif /* HAL_DMA_MODULE_ENABLED */ { I2C_TreatErrorCallback(hi2c); } @@ -6429,6 +6548,7 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) } } +#if defined(HAL_DMA_MODULE_ENABLED) /** * @brief DMA I2C master transmit process complete callback. * @param hdma DMA handle @@ -6479,6 +6599,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C slave transmit process complete callback. * @param hdma DMA handle @@ -6507,6 +6628,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C master receive process complete callback. * @param hdma DMA handle @@ -6557,6 +6679,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C slave receive process complete callback. * @param hdma DMA handle @@ -6585,6 +6708,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) } } + /** * @brief DMA I2C communication error callback. * @param hdma DMA handle @@ -6602,6 +6726,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); } + /** * @brief DMA I2C communication abort callback * (To be called at end of DMA Abort procedure). @@ -6626,6 +6751,8 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) I2C_TreatErrorCallback(hi2c); } +#endif /* HAL_DMA_MODULE_ENABLED */ + /** * @brief This function handles I2C Communication Timeout. It waits * until a flag is no longer in the specified status. @@ -6647,13 +6774,16 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } } } } @@ -6684,14 +6814,17 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -6720,14 +6853,17 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -6794,13 +6930,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -6857,14 +6996,11 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + error_code |= HAL_I2C_ERROR_TIMEOUT; status = HAL_ERROR; + + break; } } } @@ -6989,8 +7125,11 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; - if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) +#if defined(HAL_DMA_MODULE_ENABLED) + if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + (hi2c->XferISR != I2C_Mem_ISR_DMA)) +#endif /* HAL_DMA_MODULE_ENABLED */ { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { @@ -6998,6 +7137,18 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ @@ -7007,20 +7158,16 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); - } - - if (InterruptRequest == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; + tmpisr |= I2C_IT_STOPI; } } + +#if defined(HAL_DMA_MODULE_ENABLED) else { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { - /* Enable ERR, STOP, NACK, and ADDR interrupts */ + /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } @@ -7045,9 +7192,16 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT)) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; } } +#endif /* HAL_DMA_MODULE_ENABLED */ /* Enable interrupts only at the end */ /* to avoid the risk of I2C interrupt handle execution before */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_ipcc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_ipcc.c index 9885924181..edaf870f6d 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_ipcc.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_ipcc.c @@ -48,7 +48,7 @@ or when a message has been retrieved from a chosen channel by calling the HAL_IPCC_NotifyCPU() API. - @endverbatim +@endverbatim ****************************************************************************** */ @@ -73,7 +73,7 @@ */ #define IPCC_ALL_RX_BUF 0x0000003FU /*!< Mask for all RX buffers. */ #define IPCC_ALL_TX_BUF 0x003F0000U /*!< Mask for all TX buffers. */ -#define CHANNEL_INDEX_Msk 0x0000000FU /*!< Mask the channel index to avoid overflow */ +#define CHANNEL_INDEX_MASK 0x0000000FU /*!< Mask the channel index to avoid overflow */ /** * @} */ @@ -97,8 +97,8 @@ void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance); */ /** @addtogroup IPCC_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions - * + * @brief Initialization and de-initialization functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -239,8 +239,8 @@ __weak void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc) /** @addtogroup IPCC_Exported_Functions_Group2 - * @brief Configuration, notification and Irq handling functions. - * + * @brief Configuration, notification and Irq handling functions. + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -301,7 +301,9 @@ __weak void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc) * @param cb Interrupt callback * @retval HAL status */ -HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb) +HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, + uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, + ChannelCb cb) { HAL_StatusTypeDef err = HAL_OK; @@ -318,12 +320,12 @@ HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint3 if (ChannelDir == IPCC_CHANNEL_DIR_TX) { hipcc->ChannelCallbackTx[ChannelIndex] = cb; - hipcc->callbackRequest |= (IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk)); + hipcc->callbackRequest |= (IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_MASK)); } else { hipcc->ChannelCallbackRx[ChannelIndex] = cb; - hipcc->callbackRequest |= (IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk)); + hipcc->callbackRequest |= (IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_MASK)); } /* Unmask only the channels in reception (Transmission channel mask/unmask is done in HAL_IPCC_NotifyCPU) */ @@ -358,7 +360,8 @@ HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint3 * @param ChannelDir Channel direction * @retval HAL status */ -HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) +HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, + uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) { HAL_StatusTypeDef err = HAL_OK; @@ -375,12 +378,12 @@ HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uin if (ChannelDir == IPCC_CHANNEL_DIR_TX) { hipcc->ChannelCallbackTx[ChannelIndex] = HAL_IPCC_TxCallback; - hipcc->callbackRequest &= ~(IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk)); + hipcc->callbackRequest &= ~(IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_MASK)); } else { hipcc->ChannelCallbackRx[ChannelIndex] = HAL_IPCC_RxCallback; - hipcc->callbackRequest &= ~(IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk)); + hipcc->callbackRequest &= ~(IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_MASK)); } /* Mask the interrupt */ @@ -412,7 +415,8 @@ HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uin * @param ChannelDir Channel direction * @retval Channel status */ -IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) +IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, + uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) { uint32_t channel_state; IPCC_CommonTypeDef *currentInstance = IPCC_C1; @@ -424,11 +428,11 @@ IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *co /* Read corresponding channel depending of the MCU and the direction */ if (ChannelDir == IPCC_CHANNEL_DIR_TX) { - channel_state = (currentInstance->SR) & (IPCC_SR_CH1F_Msk << (ChannelIndex & CHANNEL_INDEX_Msk)); + channel_state = (currentInstance->SR) & (IPCC_SR_CH1F_Msk << (ChannelIndex & CHANNEL_INDEX_MASK)); } else { - channel_state = (otherInstance->SR) & (IPCC_SR_CH1F_Msk << (ChannelIndex & CHANNEL_INDEX_Msk)); + channel_state = (otherInstance->SR) & (IPCC_SR_CH1F_Msk << (ChannelIndex & CHANNEL_INDEX_MASK)); } return (channel_state == 0UL) ? IPCC_CHANNEL_STATUS_FREE : IPCC_CHANNEL_STATUS_OCCUPIED ; @@ -448,7 +452,8 @@ IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *co * @param ChannelDir Channel direction * @retval HAL status */ -HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) +HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, + uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir) { HAL_StatusTypeDef err = HAL_OK; uint32_t mask; @@ -461,10 +466,13 @@ HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint if (hipcc->State == HAL_IPCC_STATE_READY) { /* For IPCC_CHANNEL_DIR_TX, set the status. For IPCC_CHANNEL_DIR_RX, clear the status */ - currentInstance->SCR |= ((ChannelDir == IPCC_CHANNEL_DIR_TX) ? IPCC_SCR_CH1S : IPCC_SCR_CH1C) << (ChannelIndex & CHANNEL_INDEX_Msk) ; + currentInstance->SCR |= ((ChannelDir == IPCC_CHANNEL_DIR_TX) ? IPCC_SCR_CH1S : + IPCC_SCR_CH1C) + << (ChannelIndex & CHANNEL_INDEX_MASK); /* Unmask interrupt if the callback is requested */ - mask = ((ChannelDir == IPCC_CHANNEL_DIR_TX) ? IPCC_MR_CH1FM_Msk : IPCC_MR_CH1OM_Msk) << (ChannelIndex & CHANNEL_INDEX_Msk) ; + mask = ((ChannelDir == IPCC_CHANNEL_DIR_TX) ? IPCC_MR_CH1FM_Msk : + IPCC_MR_CH1OM_Msk) << (ChannelIndex & CHANNEL_INDEX_MASK); if ((hipcc->callbackRequest & mask) == mask) { IPCC_UnmaskInterrupt(ChannelIndex, ChannelDir); @@ -483,8 +491,8 @@ HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint */ /** @addtogroup IPCC_IRQ_Handler_and_Callbacks - * @{ - */ + * @{ + */ /** * @brief This function handles IPCC Tx Free interrupt request. @@ -504,7 +512,7 @@ void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef *const hipcc) while (irqmask != 0UL) /* if several bits are set, it loops to serve all of them */ { - bit_pos = 1UL << (IPCC_MR_CH1FM_Pos + (ch_count & CHANNEL_INDEX_Msk)); + bit_pos = 1UL << (IPCC_MR_CH1FM_Pos + (ch_count & CHANNEL_INDEX_MASK)); if ((irqmask & bit_pos) != 0U) { @@ -539,7 +547,7 @@ void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc) while (irqmask != 0UL) /* if several bits are set, it loops to serve all of them */ { - bit_pos = 1UL << (ch_count & CHANNEL_INDEX_Msk); + bit_pos = 1UL << (ch_count & CHANNEL_INDEX_MASK); if ((irqmask & bit_pos) != 0U) { @@ -610,8 +618,8 @@ __weak void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex */ /** @addtogroup IPCC_Exported_Functions_Group3 - * @brief IPCC Peripheral State and Error functions - * + * @brief IPCC Peripheral State and Error functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -664,12 +672,12 @@ void IPCC_MaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir if (ChannelDir == IPCC_CHANNEL_DIR_TX) { /* Mask interrupt */ - currentInstance->MR |= (IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk)); + currentInstance->MR |= (IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_MASK)); } else { /* Mask interrupt */ - currentInstance->MR |= (IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk)); + currentInstance->MR |= (IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_MASK)); } } /** @@ -690,12 +698,12 @@ void IPCC_UnmaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelD if (ChannelDir == IPCC_CHANNEL_DIR_TX) { /* Unmask interrupt */ - currentInstance->MR &= ~(IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk)); + currentInstance->MR &= ~(IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_MASK)); } else { /* Unmask interrupt */ - currentInstance->MR &= ~(IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk)); + currentInstance->MR &= ~(IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_MASK)); } } diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c index 1019cba994..71d2bc49dc 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c @@ -35,7 +35,7 @@ #ifdef HAL_PWR_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -70,7 +70,7 @@ * @} */ - /** +/** * @} */ @@ -116,33 +116,33 @@ void HAL_PWR_DeInit(void) #if defined(GPIOD) LL_PWR_WriteReg(PUCRD, PWR_PUCRD_RESET_VALUE); LL_PWR_WriteReg(PDCRD, PWR_PDCRD_RESET_VALUE); -#endif +#endif /* GPIOD */ LL_PWR_WriteReg(PUCRE, PWR_PUCRE_RESET_VALUE); LL_PWR_WriteReg(PDCRE, PWR_PDCRE_RESET_VALUE); LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE); LL_PWR_WriteReg(PDCRH, PWR_PDCRH_RESET_VALUE); LL_PWR_WriteReg(C2CR1, PWR_C2CR1_RESET_VALUE); LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE); - + /* Clear all flags */ LL_PWR_WriteReg(SCR, - LL_PWR_SCR_CC2HF + LL_PWR_SCR_CC2HF | LL_PWR_SCR_CBLEAF | LL_PWR_SCR_CCRPEF #if defined(PWR_CR3_E802A) | LL_PWR_SCR_C802AF | LL_PWR_SCR_C802WUF -#endif +#endif /* PWR_CR3_E802A */ | LL_PWR_SCR_CBLEWUF #if defined(PWR_CR5_SMPSEN) | LL_PWR_SCR_CBORHF | LL_PWR_SCR_CSMPSFBF -#endif +#endif /* PWR_CR5_SMPSEN */ | LL_PWR_SCR_CWUF ); - + LL_PWR_WriteReg(EXTSCR, - LL_PWR_EXTSCR_CCRPF + LL_PWR_EXTSCR_CCRPF | LL_PWR_EXTSCR_C2CSSF | LL_PWR_EXTSCR_C1CSSF ); @@ -150,13 +150,13 @@ void HAL_PWR_DeInit(void) /** - * @brief Enable access to the backup domain + * @brief Enable access to the backup domain * (RTC registers, RTC backup data registers). - * @note After reset, the backup domain is protected against + * @note After reset, the backup domain is protected against * possible unwanted write accesses. * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain. * In order to set or modify the RTC clock, the backup domain access must be - * disabled. + * disabled. * @note LSEON bit that switches on and off the LSE crystal belongs as well to the * back-up domain. * @retval None @@ -205,8 +205,8 @@ void HAL_PWR_DisableBkUpAccess(void) *** WakeUp pin configuration *** ================================ [..] - (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. - The polarity of these pins can be set to configure event detection on high + (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. + The polarity of these pins can be set to configure event detection on high level (rising edge) or low level (falling edge). *** Low Power modes configuration *** @@ -234,7 +234,7 @@ void HAL_PWR_DisableBkUpAccess(void) ========================== [..] (+) Entry: (from main run mode) - (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. + (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. (+) Exit: (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only then can the system clock frequency be increased above 2 MHz. @@ -244,7 +244,7 @@ void HAL_PWR_DisableBkUpAccess(void) [..] (+) Entry: The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API - in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. + in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode). In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand. @@ -258,13 +258,13 @@ void HAL_PWR_DisableBkUpAccess(void) (+) WFE Exit: (++) Any wake-up event such as an EXTI line configured in event mode. - [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, - the MCU is in Low-power Run mode. + [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, + the MCU is in Low-power Run mode. *** Stop 0, Stop 1 and Stop 2 modes *** =============================== [..] - (+) Entry: + (+) Entry: The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's: (++) HAL_PWREx_EnterSTOP0Mode() for mode 0, HAL_PWREx_EnterSTOP1Mode() for mode 1, HAL_PWREx_EnterSTOP2Mode() for mode 2 or for porting reasons HAL_PWR_EnterSTOPMode(). @@ -278,48 +278,48 @@ void HAL_PWR_DisableBkUpAccess(void) (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction (+) WFI Exit: (++) Any EXTI Line (Internal or External) configured in Interrupt mode. - (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts - when programmed in wakeup mode. + (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts + when programmed in wakeup mode. (+) WFE Exit: (++) Any EXTI Line (Internal or External) configured in Event mode. - - [..] + + [..] When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode - depending on the LPR bit setting. - When exiting Stop 2 mode, the MCU is in Run mode. + depending on the LPR bit setting. + When exiting Stop 2 mode, the MCU is in Run mode. *** Standby mode *** ==================== - [..] The Standby mode offers two options: + [..] The Standby mode offers two options: (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode). - SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers - and Standby circuitry. + SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers + and Standby circuitry. (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled). - SRAM and register contents are lost except for the RTC registers, RTC backup registers + SRAM and register contents are lost except for the RTC registers, RTC backup registers and Standby circuitry. (++) Entry: - (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. - SRAM1 and register contents are lost except for registers in the Backup domain and - Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. + (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. + SRAM1 and register contents are lost except for registers in the Backup domain and + Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. To enable this feature, the user can resort to HAL_PWREx_EnableBKRAMContentRetention() API to set RRS bit. (++) Exit: - (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, + (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, external reset in NRST pin, IWDG reset. [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset. - + *** Shutdown mode *** ====================== [..] - In Shutdown mode, + In Shutdown mode, voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared. SRAM and registers contents are lost except for backup domain registers. (+) Entry: The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API. (+) Exit: - (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, + (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, external reset in NRST pin. [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset. @@ -332,7 +332,7 @@ void HAL_PWR_DisableBkUpAccess(void) an external interrupt (Auto-wakeup mode). (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes - + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. @@ -350,7 +350,7 @@ void HAL_PWR_DisableBkUpAccess(void) /** * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD). - * @param sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the PVD + * @param sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the PVD * configuration information. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage thresholds corresponding to each @@ -371,31 +371,31 @@ HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) /* Set PLS bits according to PVDLevel value */ MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel); - + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - + /* Note: On STM32WB series, power PVD event is not available on AIEC lines */ /* (only interruption is available through AIEC line 16). */ __HAL_PWR_PVD_EXTI_DISABLE_IT(); /*CPU1*/ __HAL_PWR_PVD_EXTIC2_DISABLE_IT(); /*CPU2*/ - + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); /* Configure interrupt mode */ - if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) { /* Set CPU1 as wakeup target */ __HAL_PWR_PVD_EXTI_ENABLE_IT(); } - + /* Configure the edge */ - if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } - - if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + + if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } @@ -427,28 +427,28 @@ void HAL_PWR_DisablePVD(void) /** * @brief Enable the WakeUp PINx functionality. * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. - * This parameter can be one of the following legacy values which set the default polarity + * This parameter can be one of the following legacy values which set the default polarity * i.e. detection on high level (rising edge): * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 - * + * * or one of the following value where the user can explicitly specify the enabled pin and - * the chosen polarity: + * the chosen polarity: * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW - * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) { - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); - - /* Specifies the Wake-Up pin polarity for the event detection + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* Specifies the Wake-Up pin polarity for the event detection (rising or falling edge) */ - MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); - + MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); + /* Enable wake-up pin */ SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); } @@ -477,21 +477,21 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) * @param Regulator Specifies the regulator state in Sleep/Low-power Sleep mode. * This parameter can be one of the following values: * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode) - * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) - * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet - * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set + * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) + * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet + * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the * Flash in power-down mode in setting the SLEEP_PD bit in FLASH_ACR register. * Additionally, the clock frequency must be reduced below 2 MHz. - * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must - * be done before calling HAL_PWR_EnterSLEEPMode() API. - * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in + * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must + * be done before calling HAL_PWR_EnterSLEEPMode() API. + * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API. * @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction - * @note When WFI entry is used, tick interrupt have to be disabled if not desired as + * @note When WFI entry is used, tick interrupt have to be disabled if not desired as * the interrupt wake up source. * @retval None */ @@ -511,7 +511,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { return ; } - } + } /* Regulator now in main mode. */ } else @@ -520,15 +520,15 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) The system clock frequency must be below 2 MHz at this point. */ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET) { - HAL_PWREx_EnableLowPowerRunMode(); - } - } - + HAL_PWREx_EnableLowPowerRunMode(); + } + } + /* Clear SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select SLEEP mode entry -------------------------------------------------*/ - if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); @@ -548,17 +548,17 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running * on devices where only "Stop mode" is mentioned with main or low power regulator ON. * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. - * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1). + * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1). * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * is set; the MSI oscillator is selected if STOPWUCK is cleared. * @note When the voltage regulator operates in low power mode (Stop 1), an additional * startup delay is incurred when waking up. * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption @@ -570,7 +570,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * @param Regulator Specifies the regulator state in Stop mode. * This parameter can be one of the following values: * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) - * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON) + * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON) * @param STOPEntry Specifies Stop 0, Stop 1 or Stop 2 mode is entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction. @@ -581,8 +581,8 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); - - if(Regulator == PWR_LOWPOWERREGULATOR_ON) + + if (Regulator == PWR_LOWPOWERREGULATOR_ON) { HAL_PWREx_EnterSTOP1Mode(STOPEntry); } @@ -595,7 +595,7 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) /** * @brief Enter Standby mode. - * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched + * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched * off. The voltage regulator is disabled, except when BKRAM content is preserved * in which case the regulator is in low-power mode. * SRAM and register contents are lost except for registers in the Backup domain and @@ -621,10 +621,10 @@ void HAL_PWR_EnterSTANDBYMode(void) /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) __force_stores(); -#endif +#endif /* __CC_ARM */ /* Request Wait For Interrupt */ __WFI(); @@ -637,11 +637,11 @@ void HAL_PWR_EnterSTANDBYMode(void) } /** - * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. + * interruptions handling. * @retval None */ void HAL_PWR_EnableSleepOnExit(void) @@ -651,8 +651,8 @@ void HAL_PWR_EnableSleepOnExit(void) } /** - * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * @retval None */ @@ -664,8 +664,8 @@ void HAL_PWR_DisableSleepOnExit(void) /** - * @brief Enable CORTEX M4 SEVONPEND bit. - * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes + * @brief Enable CORTEX M4 SEVONPEND bit. + * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ @@ -677,9 +677,9 @@ void HAL_PWR_EnableSEVOnPend(void) /** - * @brief Disable CORTEX M4 SEVONPEND bit. - * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. + * @brief Disable CORTEX M4 SEVONPEND bit. + * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_DisableSEVOnPend(void) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c index eed4a4ce6c..b39074dfba 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c @@ -7,7 +7,7 @@ * functionalities of the Power Controller (PWR) peripheral: * + Extended Initialization and de-initialization functions * + Extended Peripheral Control functions - * + * ****************************************************************************** * @attention * @@ -44,7 +44,7 @@ /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value * @{ - */ + */ #define PWR_FLAG_SETTING_DELAY_US 50U /*!< Time out value for REGLPF and VOSF flags setting */ /** * @} @@ -63,7 +63,7 @@ /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions * @{ */ - + /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions * @brief Extended Peripheral Control functions * @@ -76,16 +76,16 @@ @endverbatim * @{ */ - + #if defined(PWR_CR1_VOS) /** * @brief Return Voltage Scaling Range. * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2) - */ + */ uint32_t HAL_PWREx_GetVoltageRange(void) { - return (PWR->CR1 & PWR_CR1_VOS); + return (PWR->CR1 & PWR_CR1_VOS); } /** @@ -113,7 +113,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); - + /* If Set Range 1 */ if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) { @@ -121,7 +121,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - + /* Wait until VOSF is cleared */ wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U)); while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) @@ -143,10 +143,10 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) /* No need to wait for VOSF to be cleared for this transition */ } } - + return HAL_OK; } -#endif +#endif /* PWR_CR1_VOS */ /****************************************************************************/ @@ -162,22 +162,22 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) { assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); - + /* Specify resistor selection */ MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); - + /* Enable battery charging */ SET_BIT(PWR->CR4, PWR_CR4_VBE); } /** - * @brief Disable battery charging. + * @brief Disable battery charging. * @retval None */ void HAL_PWREx_DisableBatteryCharging(void) { - CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); -} + CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); +} /****************************************************************************/ #if defined(PWR_CR2_PVME1) @@ -192,14 +192,14 @@ void HAL_PWREx_EnableVddUSB(void) } /** - * @brief Disable VDDUSB supply. + * @brief Disable VDDUSB supply. * @retval None */ void HAL_PWREx_DisableVddUSB(void) { CLEAR_BIT(PWR->CR2, PWR_CR2_USV); } -#endif +#endif /* PWR_CR2_PVME1 */ /****************************************************************************/ @@ -241,7 +241,7 @@ void HAL_PWREx_DisableBORH_SMPSBypassIT(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB); } -#endif +#endif /* PWR_CR5_SMPSEN */ /** * @brief Enable RF Phase interrupt. @@ -298,7 +298,7 @@ void HAL_PWREx_Disable802ActivityIT(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_E802A); } -#endif +#endif /* PWR_CR3_E802A */ /** * @brief Enable CPU2 on-Hold interrupt. @@ -322,27 +322,27 @@ void HAL_PWREx_DisableHOLDC2IT(void) /** * @brief Enable GPIO pull-up state in Standby and Shutdown modes. - * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in - * pull-up state in Standby and Shutdown modes. - * @note This state is effective in Standby and Shutdown modes only if APC bit + * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in + * pull-up state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. - * @note The configuration is lost when exiting the Shutdown mode due to the - * power-on reset, maintained when exiting the Standby mode. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding - * PDy bit of PWR_PDCRx register is cleared unless it is reserved. - * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input - * parameter at the same time are set. - * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H + * PDy bit of PWR_PDCRx register is cleared unless it is reserved. + * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input + * parameter at the same time are set. + * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H * to select the GPIO peripheral. * @param GPIONumber Specify the I/O pins numbers. * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less - * I/O pins are available) or the logical OR of several of them to set + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less + * I/O pins are available) or the logical OR of several of them to set * several bits for a given port in a single API call. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) -{ +{ HAL_StatusTypeDef status = HAL_OK; assert_param(IS_PWR_GPIO(GPIO)); @@ -351,36 +351,36 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) switch (GPIO) { case PWR_GPIO_A: - SET_BIT(PWR->PUCRA, GPIONumber); - CLEAR_BIT(PWR->PDCRA, GPIONumber); - break; + SET_BIT(PWR->PUCRA, GPIONumber); + CLEAR_BIT(PWR->PDCRA, GPIONumber); + break; case PWR_GPIO_B: - SET_BIT(PWR->PUCRB, GPIONumber); - CLEAR_BIT(PWR->PDCRB, GPIONumber); - break; + SET_BIT(PWR->PUCRB, GPIONumber); + CLEAR_BIT(PWR->PDCRB, GPIONumber); + break; case PWR_GPIO_C: - SET_BIT(PWR->PUCRC, GPIONumber); - CLEAR_BIT(PWR->PDCRC, GPIONumber); - break; + SET_BIT(PWR->PUCRC, GPIONumber); + CLEAR_BIT(PWR->PDCRC, GPIONumber); + break; #if defined(GPIOD) case PWR_GPIO_D: - SET_BIT(PWR->PUCRD, GPIONumber); - CLEAR_BIT(PWR->PDCRD, GPIONumber); - break; -#endif + SET_BIT(PWR->PUCRD, GPIONumber); + CLEAR_BIT(PWR->PDCRD, GPIONumber); + break; +#endif /* GPIOD */ case PWR_GPIO_E: - SET_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); - CLEAR_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); - break; + SET_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); + break; case PWR_GPIO_H: - SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); - CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); - break; + SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); + break; default: status = HAL_ERROR; break; } - + return status; } @@ -388,51 +388,51 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O * in pull-up state in Standby and Shutdown modes. - * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input + * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input * parameter at the same time are reset. - * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H + * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H * to select the GPIO peripheral. * @param GPIONumber Specify the I/O pins numbers. * This parameter can be one of the following values: * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less - * I/O pins are available) or the logical OR of several of them to reset + * I/O pins are available) or the logical OR of several of them to reset * several bits for a given port in a single API call. * @retval HAL Status - */ + */ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) -{ +{ HAL_StatusTypeDef status = HAL_OK; - + assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - + switch (GPIO) { case PWR_GPIO_A: - CLEAR_BIT(PWR->PUCRA, GPIONumber); - break; + CLEAR_BIT(PWR->PUCRA, GPIONumber); + break; case PWR_GPIO_B: - CLEAR_BIT(PWR->PUCRB, GPIONumber); - break; + CLEAR_BIT(PWR->PUCRB, GPIONumber); + break; case PWR_GPIO_C: - CLEAR_BIT(PWR->PUCRC, GPIONumber); - break; + CLEAR_BIT(PWR->PUCRC, GPIONumber); + break; #if defined(GPIOD) case PWR_GPIO_D: - CLEAR_BIT(PWR->PUCRD, GPIONumber); - break; -#endif + CLEAR_BIT(PWR->PUCRD, GPIONumber); + break; +#endif /* GPIOD */ case PWR_GPIO_E: - CLEAR_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); - break; + CLEAR_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); + break; case PWR_GPIO_H: - CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); - break; + CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); + break; default: - status = HAL_ERROR; - break; + status = HAL_ERROR; + break; } - + return status; } @@ -440,75 +440,75 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber /** * @brief Enable GPIO pull-down state in Standby and Shutdown modes. - * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in - * pull-down state in Standby and Shutdown modes. + * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in + * pull-down state in Standby and Shutdown modes. * @note This state is effective in Standby and Shutdown modes only if APC bit - * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. - * @note The configuration is lost when exiting the Shutdown mode due to the - * power-on reset, maintained when exiting the Standby mode. + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding - * PUy bit of PWR_PUCRx register is cleared unless it is reserved. - * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input - * parameter at the same time are set. - * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H + * PUy bit of PWR_PUCRx register is cleared unless it is reserved. + * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input + * parameter at the same time are set. + * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H * to select the GPIO peripheral. * @param GPIONumber Specify the I/O pins numbers. * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less - * I/O pins are available) or the logical OR of several of them to set - * several bits for a given port in a single API call. + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. * @retval HAL Status - */ + */ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { HAL_StatusTypeDef status = HAL_OK; - + assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - + switch (GPIO) - { + { case PWR_GPIO_A: - SET_BIT(PWR->PDCRA, GPIONumber); - CLEAR_BIT(PWR->PUCRA, GPIONumber); - break; + SET_BIT(PWR->PDCRA, GPIONumber); + CLEAR_BIT(PWR->PUCRA, GPIONumber); + break; case PWR_GPIO_B: - SET_BIT(PWR->PDCRB, GPIONumber); - CLEAR_BIT(PWR->PUCRB, GPIONumber); - break; + SET_BIT(PWR->PDCRB, GPIONumber); + CLEAR_BIT(PWR->PUCRB, GPIONumber); + break; case PWR_GPIO_C: - SET_BIT(PWR->PDCRC, GPIONumber); - CLEAR_BIT(PWR->PUCRC, GPIONumber); - break; + SET_BIT(PWR->PDCRC, GPIONumber); + CLEAR_BIT(PWR->PUCRC, GPIONumber); + break; #if defined(GPIOD) - case PWR_GPIO_D: - SET_BIT(PWR->PDCRD, GPIONumber); - CLEAR_BIT(PWR->PUCRD, GPIONumber); - break; -#endif + case PWR_GPIO_D: + SET_BIT(PWR->PDCRD, GPIONumber); + CLEAR_BIT(PWR->PUCRD, GPIONumber); + break; +#endif /* GPIOD */ case PWR_GPIO_E: - SET_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); - CLEAR_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); - break; + SET_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); + break; case PWR_GPIO_H: - SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); - CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); - break; + SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); + CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); + break; default: status = HAL_ERROR; break; } - + return status; } /** * @brief Disable GPIO pull-down state in Standby and Shutdown modes. * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O - * in pull-down state in Standby and Shutdown modes. - * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input + * in pull-down state in Standby and Shutdown modes. + * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input * parameter at the same time are reset. - * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H + * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H * to select the GPIO peripheral. * @param GPIONumber Specify the I/O pins numbers. * This parameter can be one of the following values: @@ -516,51 +516,51 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe * I/O pins are available) or the logical OR of several of them to reset * several bits for a given port in a single API call. * @retval HAL Status - */ + */ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { HAL_StatusTypeDef status = HAL_OK; - + assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - + switch (GPIO) { case PWR_GPIO_A: - CLEAR_BIT(PWR->PDCRA, GPIONumber); - break; + CLEAR_BIT(PWR->PDCRA, GPIONumber); + break; case PWR_GPIO_B: - CLEAR_BIT(PWR->PDCRB, GPIONumber); - break; + CLEAR_BIT(PWR->PDCRB, GPIONumber); + break; case PWR_GPIO_C: - CLEAR_BIT(PWR->PDCRC, GPIONumber); - break; + CLEAR_BIT(PWR->PDCRC, GPIONumber); + break; #if defined(GPIOD) case PWR_GPIO_D: - CLEAR_BIT(PWR->PDCRD, GPIONumber); - break; -#endif + CLEAR_BIT(PWR->PDCRD, GPIONumber); + break; +#endif /* GPIOD */ case PWR_GPIO_E: - CLEAR_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); - break; + CLEAR_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); + break; case PWR_GPIO_H: CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); - break; + break; default: status = HAL_ERROR; break; } - + return status; } /** * @brief Enable pull-up and pull-down configuration. - * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in - * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. + * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding - * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). - * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there + * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there * is no conflict when setting PUy or PDy bit. * @retval None */ @@ -571,8 +571,8 @@ void HAL_PWREx_EnablePullUpPullDownConfig(void) /** * @brief Disable pull-up and pull-down configuration. - * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in - * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. + * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. * @retval None */ void HAL_PWREx_DisablePullUpPullDownConfig(void) @@ -604,7 +604,7 @@ uint32_t HAL_PWREx_GetBORConfig(void) { return LL_PWR_GetBORConfig(); } -#endif +#endif /* PWR_CR5_SMPSEN */ /****************************************************************************/ /** @@ -619,7 +619,7 @@ void HAL_PWREx_HoldCore(uint32_t CPU) { /* Check the parameters */ assert_param(IS_PWR_CORE_HOLD_RELEASE(CPU)); - + LL_PWR_DisableBootC2(); } @@ -634,7 +634,7 @@ void HAL_PWREx_ReleaseCore(uint32_t CPU) { /* Check the parameters */ assert_param(IS_PWR_CORE_HOLD_RELEASE(CPU)); - + LL_PWR_EnableBootC2(); } @@ -679,7 +679,7 @@ void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode) { assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode)); - if((PowerMode & PWR_FLASHPD_LPRUN) != 0U) + if ((PowerMode & PWR_FLASHPD_LPRUN) != 0U) { /* Unlock bit FPDR */ WRITE_REG(PWR->CR1, 0x0000C1B0UL); @@ -725,7 +725,7 @@ void HAL_PWREx_DisablePVM1(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_1); } -#endif +#endif /* PWR_CR2_PVME1 */ /** * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V. @@ -752,8 +752,8 @@ void HAL_PWREx_DisablePVM3(void) * @brief Configure the Peripheral Voltage Monitoring (PVM). * @param sConfigPVM pointer to a PWR_PVMTypeDef structure that contains the * PVM configuration information. - * @note The API configures a single PVM according to the information contained - * in the input structure. To configure several PVMs, the API must be singly + * @note The API configures a single PVM according to the information contained + * in the input structure. To configure several PVMs, the API must be singly * called for each PVM used. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage thresholds corresponding to each @@ -761,88 +761,88 @@ void HAL_PWREx_DisablePVM3(void) * @retval HAL status */ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) -{ +{ HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); - + /* Configure EXTI 31 and 33 interrupts if so required: scan thru PVMType to detect which PVMx is set and configure the corresponding EXTI line accordingly. */ switch (sConfigPVM->PVMType) { #if defined(PWR_CR2_PVME1) - case PWR_PVM_1: + case PWR_PVM_1: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM1_EXTI_DISABLE_IT(); - __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ - if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) { __HAL_PWR_PVM1_EXTI_ENABLE_IT(); } - + /* Configure event mode */ - if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM1_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ - if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); } - - if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + + if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); } break; -#endif - +#endif /* PWR_CR2_PVME1 */ + case PWR_PVM_3: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM3_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM3_EXTI_DISABLE_IT(); - __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ - if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) { __HAL_PWR_PVM3_EXTI_ENABLE_IT(); } - + /* Configure event mode */ - if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM3_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ - if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); } - - if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + + if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); } break; - + default: status = HAL_ERROR; break; - + } - + return status; } @@ -861,48 +861,49 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_PWR_SMPS_STARTUP_CURRENT(sConfigSMPS->StartupCurrent)); assert_param(IS_PWR_SMPS_OUTPUT_VOLTAGE(sConfigSMPS->OutputVoltage)); - + __IO const uint32_t OutputVoltageLevel_calibration = (((*SMPS_VOLTAGE_CAL_ADDR) & SMPS_VOLTAGE_CAL) >> SMPS_VOLTAGE_CAL_POS); /* SMPS output voltage level calibrated in production */ int32_t TrimmingSteps; /* Trimming steps between theoretical output voltage and calibrated output voltage */ int32_t OutputVoltageLevelTrimmed; /* SMPS output voltage level after calibration: trimming value added to required level */ - if(OutputVoltageLevel_calibration == 0UL) + if (OutputVoltageLevel_calibration == 0UL) { /* Device with SMPS output voltage not calibrated in production: Apply output voltage value directly */ - + /* Update register */ MODIFY_REG(PWR->CR5, PWR_CR5_SMPSVOS, (sConfigSMPS->StartupCurrent | sConfigSMPS->OutputVoltage)); } else { /* Device with SMPS output voltage calibrated in production: Apply output voltage value after correction by calibration value */ - + TrimmingSteps = ((int32_t)OutputVoltageLevel_calibration - (int32_t)(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V50 >> PWR_CR5_SMPSVOS_Pos)); OutputVoltageLevelTrimmed = ((int32_t)((uint32_t)(sConfigSMPS->OutputVoltage >> PWR_CR5_SMPSVOS_Pos)) + (int32_t)TrimmingSteps); - + /* Clamp value to voltage trimming bitfield range */ - if(OutputVoltageLevelTrimmed < 0) + if (OutputVoltageLevelTrimmed < 0) { OutputVoltageLevelTrimmed = 0; status = HAL_ERROR; } else { - if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS) + if (OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS) { OutputVoltageLevelTrimmed = (int32_t)PWR_CR5_SMPSVOS; status = HAL_ERROR; } } - + /* Update register */ - MODIFY_REG(PWR->CR5, (PWR_CR5_SMPSSC | PWR_CR5_SMPSVOS), (sConfigSMPS->StartupCurrent | ((uint32_t) OutputVoltageLevelTrimmed))); + MODIFY_REG(PWR->CR5, (PWR_CR5_SMPSSC | PWR_CR5_SMPSVOS), + (sConfigSMPS->StartupCurrent | ((uint32_t) OutputVoltageLevelTrimmed))); } - + return status; } @@ -946,19 +947,19 @@ uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void) { return (uint32_t)(READ_BIT(PWR->SR2, (PWR_SR2_SMPSF | PWR_SR2_SMPSBF))); } -#endif +#endif /* PWR_CR5_SMPSEN */ /****************************************************************************/ /** * @brief Enable the WakeUp PINx functionality. * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. - * This parameter can be one of the following legacy values which set the default polarity + * This parameter can be one of the following legacy values which set the default polarity * i.e. detection on high level (rising edge): * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 - * + * * or one of the following value where the user can explicitly specify the enabled pin and - * the chosen polarity: + * the chosen polarity: * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW @@ -967,19 +968,19 @@ uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void) * @param wakeupTarget Specifies the wake-up target * @arg @ref PWR_CORE_CPU1 * @arg @ref PWR_CORE_CPU2 - * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. * @retval None */ void HAL_PWREx_EnableWakeUpPin(uint32_t WakeUpPinPolarity, uint32_t wakeupTarget) { - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); - - /* Specifies the Wake-Up pin polarity for the event detection + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* Specifies the Wake-Up pin polarity for the event detection (rising or falling edge) */ - MODIFY_REG(PWR->CR4, (PWR_C2CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); - + MODIFY_REG(PWR->CR4, (PWR_C2CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); + /* Enable wake-up pin */ - if(PWR_CORE_CPU2 == wakeupTarget) + if (PWR_CORE_CPU2 == wakeupTarget) { SET_BIT(PWR->C2CR3, (PWR_C2CR3_EWUP & WakeUpPinPolarity)); } @@ -1020,7 +1021,7 @@ HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag) { PWR->SCR = (1UL << ((WakeUpFlag) & 31U)); - if((PWR->SR1 & (1UL << ((WakeUpFlag) & 31U))) != 0U) + if ((PWR->SR1 & (1UL << ((WakeUpFlag) & 31U))) != 0U) { return HAL_ERROR; } @@ -1031,35 +1032,35 @@ HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag) /** * @brief Enter Low-power Run mode - * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. + * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the * Flash in power-down mode in setting the RUN_PD bit in FLASH_ACR register. * Additionally, the clock frequency must be reduced below 2 MHz. - * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must - * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. + * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must + * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. * @retval None */ void HAL_PWREx_EnableLowPowerRunMode(void) { /* Set Regulator parameter */ - SET_BIT(PWR->CR1, PWR_CR1_LPR); + SET_BIT(PWR->CR1, PWR_CR1_LPR); } /** * @brief Exit Low-power Run mode. - * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that - * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode + * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that + * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode * returns HAL_TIMEOUT status). The system clock frequency can then be - * increased above 2 MHz. + * increased above 2 MHz. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) { uint32_t wait_loop_index; - + /* Clear LPR bit */ - CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); + CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); /* Wait until REGLPF is reset */ wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U)); @@ -1071,7 +1072,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) { return HAL_TIMEOUT; } - + return HAL_OK; } @@ -1081,16 +1082,16 @@ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) * @brief Enter Stop 0 mode. * @note In Stop 0 mode, main and low voltage regulators are ON. * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * is set; the MSI oscillator is selected if STOPWUCK is cleared. * @note By keeping the internal regulator ON during Stop 0 mode, the consumption * is higher although the startup time is reduced. * @note Case of Stop0 mode with SMPS: Before entering Stop 0 mode with SMPS Step Down converter enabled, @@ -1116,7 +1117,7 @@ void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) + if (STOPEntry == PWR_STOPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); @@ -1137,16 +1138,16 @@ void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) * @brief Enter Stop 1 mode. * @note In Stop 1 mode, only low power voltage regulator is ON. * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated + * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability + * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI + * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. + * is set; the MSI oscillator is selected if STOPWUCK is cleared. * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode. * @note According to system power policy, system entering in Stop mode * is depending on other CPU power mode. @@ -1160,7 +1161,7 @@ void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - + /* Stop 1 mode with Low-Power Regulator */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP1); @@ -1168,7 +1169,7 @@ void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) + if (STOPEntry == PWR_STOPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); @@ -1190,15 +1191,15 @@ void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) * @brief Enter Stop 2 mode. * @note In Stop 2 mode, only low power voltage regulator is ON. * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped, the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability - * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after - * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only + * @note All clocks in the VCORE domain are stopped, the PLL, the MSI, + * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability + * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after + * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only * to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. - * The BOR is available. + * The BOR is available. * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode. - * Otherwise, Stop 1 mode is entered. + * Otherwise, Stop 1 mode is entered. * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register * is set; the MSI oscillator is selected if STOPWUCK is cleared. @@ -1231,7 +1232,7 @@ void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) + if (STOPEntry == PWR_STOPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); @@ -1247,14 +1248,14 @@ void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) /* Reset SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); } -#endif +#endif /* PWR_SUPPORT_STOP2 */ /** - * @brief Enter Shutdown mode. - * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched - * off. The voltage regulator is disabled and Vcore domain is powered off. + * @brief Enter Shutdown mode. + * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched + * off. The voltage regulator is disabled and Vcore domain is powered off. * SRAM1, SRAM2, BKRAM and registers contents are lost except for registers in the Backup domain. - * The BOR is not available. + * The BOR is not available. * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. * @note According to system power policy, system entering in Shutdown mode * is depending on other CPU power mode. @@ -1264,14 +1265,14 @@ void HAL_PWREx_EnterSHUTDOWNMode(void) { /* Set Shutdown mode */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_SHUTDOWN); - + /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) __force_stores(); -#endif +#endif /* __CC_ARM */ /* Request Wait For Interrupt */ __WFI(); @@ -1286,13 +1287,13 @@ void HAL_PWREx_EnterSHUTDOWNMode(void) /** * @brief This function handles the PWR PVD/PVMx interrupt request. - * @note This API should be called under the PVD_PVM_IRQHandler(). + * @note This API should be called under the PVD_PVM_IRQHandler(). * @retval None */ void HAL_PWREx_PVD_PVM_IRQHandler(void) { /* Check PWR exti flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0U) + if (__HAL_PWR_PVD_EXTI_GET_FLAG() != 0U) { /* PWR PVD interrupt user callback */ HAL_PWR_PVDCallback(); @@ -1303,21 +1304,21 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void) #if defined(PWR_CR2_PVME1) /* Next, successively check PVMx exti flags */ - if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U) + if (__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U) { /* PWR PVM1 interrupt user callback */ HAL_PWREx_PVM1Callback(); - + /* Clear PVM1 exti pending bit */ __HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); } -#endif +#endif /* PWR_CR2_PVME1 */ - if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U) + if (__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U) { /* PWR PVM3 interrupt user callback */ HAL_PWREx_PVM3Callback(); - + /* Clear PVM3 exti pending bit */ __HAL_PWR_PVM3_EXTI_CLEAR_FLAG(); } @@ -1334,7 +1335,7 @@ __weak void HAL_PWREx_PVM1Callback(void) HAL_PWREx_PVM1Callback() API can be implemented in the user file */ } -#endif +#endif /* PWR_CR2_PVME1 */ /** * @brief PWR PVM3 interrupt callback diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c index 382baffda2..d2c2f5d815 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c @@ -1577,7 +1577,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) regvalue = RCC->CSR; /* Get the LSI configuration -----------------------------------------------*/ - RCC_OscInitStruct->LSIState = ((regvalue & RCC_LSI_ON) > 0U)?RCC_LSI_ON:0U; + RCC_OscInitStruct->LSIState = ((regvalue & RCC_LSI_ON) > 0U) ? RCC_LSI_ON : 0U; #if defined(RCC_HSI48_SUPPORT) /* Get Control/Status register */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c index 018a1f1dfd..2f4f9b7a52 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c @@ -584,6 +584,9 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /** * @brief Register a User SMBUS Callback * To be used instead of the weak predefined callback + * @note The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param CallbackID ID of the callback to be registered @@ -613,9 +616,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { switch (CallbackID) @@ -691,14 +691,15 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } /** * @brief Unregister an SMBUS Callback * SMBUS callback is redirected to the weak predefined callback + * @note The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param CallbackID ID of the callback to be unregistered @@ -719,9 +720,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { switch (CallbackID) @@ -797,8 +795,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -822,8 +818,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmbus); if (HAL_SMBUS_STATE_READY == hsmbus->State) { @@ -838,8 +832,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -854,9 +846,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ @@ -870,8 +859,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -1826,7 +1813,7 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval HAL state */ -uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) +uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus) { /* Return SMBUS handle state */ return hsmbus->State; @@ -1838,7 +1825,7 @@ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) * the configuration information for the specified SMBUS. * @retval SMBUS Error Code */ -uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) +uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus) { return hsmbus->ErrorCode; } diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_timebase_rtc_alarm_template.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_timebase_rtc_alarm_template.c index a7db6b36f6..0a2a323f2b 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_timebase_rtc_alarm_template.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_timebase_rtc_alarm_template.c @@ -6,9 +6,11 @@ * * This file override the native HAL time base functions (defined as weak) * to use the RTC ALARM for time base generation: - * + Initializes the RTC peripheral to increment the seconds registers each 1ms - * + The alarm is configured to assert an interrupt when the RTC reaches 1ms - * + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00 + * + Initializes the RTC peripheral to increment the seconds registers each 1s + * + The alarm is configured to assert an interrupt when the RTC + * subsecond register reaches 1ms when uwTickFreq is set to default + * value, else 10 ms or 100 ms, depending of above global variable value. + * + HAL_IncTick is called at each Alarm event * + HSE (default), LSE or LSI can be selected as RTC clock source ****************************************************************************** * @attention @@ -21,7 +23,7 @@ * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - @verbatim + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== @@ -45,6 +47,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wbxx_hal.h" + /** @addtogroup STM32WBxx_HAL_Driver * @{ */ @@ -63,86 +66,139 @@ + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing precision. */ -#define RTC_CLOCK_SOURCE_HSE +/* #define RTC_CLOCK_SOURCE_HSE */ /* #define RTC_CLOCK_SOURCE_LSE */ /* #define RTC_CLOCK_SOURCE_LSI */ -#ifdef RTC_CLOCK_SOURCE_HSE -#define RTC_ASYNCH_PREDIV 99U -#define RTC_SYNCH_PREDIV 9U -#define RCC_RTCCLKSOURCE_1MHZ ((uint32_t)((uint32_t)RCC_BDCR_RTCSEL | (uint32_t)((HSE_VALUE/1000000U) << 16U))) -#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */ -#define RTC_ASYNCH_PREDIV 0U -#define RTC_SYNCH_PREDIV 31U -#endif /* RTC_CLOCK_SOURCE_HSE */ +/* Minimize Asynchronous prescaler for power consumption : + ck_apre = RTCCLK / (ASYNC prediv + 1) + ck_spre = ck_apre /(SYNC prediv + 1) = 1 Hz */ +#if defined (RTC_CLOCK_SOURCE_LSE) +/* LSE Freq = 32.768 kHz RC */ +#define RTC_ASYNCH_PREDIV 1U +#define RTC_SYNCH_PREDIV 0x3FFFu /* (16384 - 1) */ +#elif defined (RTC_CLOCK_SOURCE_LSI) +/* LSI Freq = 32 kHz RC */ +#define RTC_ASYNCH_PREDIV 1U +#define RTC_SYNCH_PREDIV 0x3E7Fu /* (16000 - 1) */ +#elif defined (RTC_CLOCK_SOURCE_HSE) +/* HSE Freq as RTCCLK = 32 MHz / 32 = 1 MHz */ +#define RTC_ASYNCH_PREDIV 0x27u +#define RTC_SYNCH_PREDIV 0x5161 +#endif /* RTC_CLOCK_SOURCE_LSE */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ extern RTC_HandleTypeDef hRTC_Handle; -RTC_HandleTypeDef hRTC_Handle; +RTC_HandleTypeDef hRTC_Handle; /* Private function prototypes -----------------------------------------------*/ void RTC_Alarm_IRQHandler(void); + /* Private functions ---------------------------------------------------------*/ /** - * @brief This function configures the RTC_ALARMA as a time base source. - * The time source is configured to have 1ms time base with a dedicated + * @brief This function configures the RTC ALARM A as a time base source. + * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after + * Calendar time base is = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK + * = 1s + * Alarm interrupt timebase is = (RTC_SYNCH_PREDIV / (1000 / uwTickFreq)) + * = 1 ms when uwTickFreq is set to 1 kHz + * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - __IO uint32_t counter = 0U; + HAL_StatusTypeDef status = HAL_OK; RCC_OscInitTypeDef RCC_OscInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + RTC_TimeTypeDef time; + RTC_DateTypeDef date; + RTC_AlarmTypeDef alarm; -#ifdef RTC_CLOCK_SOURCE_LSE - /* Configure LSE as RTC clock source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero) */ + if ((uint32_t)uwTickFreq != 0U) + { + /* Disable backup domeain protection */ + HAL_PWR_EnableBkUpAccess(); + + /* Enable RTC APB clock gating */ + __HAL_RCC_RTCAPB_CLK_ENABLE(); + + /* Disable the Alarm A */ + __HAL_RTC_ALARMA_DISABLE(&hRTC_Handle); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA); + __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF); + + /* Get RTC clock configuration */ + HAL_RCCEx_GetPeriphCLKConfig(&PeriphClkInitStruct); + + /*In case of RTC clock already enable, make sure it's the good one */ +#if defined (RTC_CLOCK_SOURCE_LSE) + if ((PeriphClkInitStruct.RTCClockSelection == RCC_RTCCLKSOURCE_LSE) + && (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0x00u)) #elif defined (RTC_CLOCK_SOURCE_LSI) - /* Configure LSI as RTC clock source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + if ((PeriphClkInitStruct.RTCClockSelection == RCC_RTCCLKSOURCE_LSI) + && (__HAL_RCC_GET_FLAG(RCC_FLAG_LSI1RDY) != 0x00u)) #elif defined (RTC_CLOCK_SOURCE_HSE) - /* Configure HSE as RTC clock source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - /* Ensure that RTC is clocked by 1MHz */ - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_1MHZ; + if ((PeriphClkInitStruct.RTCClockSelection == RCC_RTCCLKSOURCE_HSE_DIV32) + && (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0x00u)) #else #error Please select the RTC Clock source +#endif /* RTC_CLOCK_SOURCE_LSE */ + { + /* Do nothing */ + } + else + { +#ifdef RTC_CLOCK_SOURCE_LSE + /* Configue LSE as RTC clock source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; +#elif defined (RTC_CLOCK_SOURCE_LSI) + /* Configue LSI as RTC clock source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; +#elif defined (RTC_CLOCK_SOURCE_HSE) + /* Configue HSE as RTC clock source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + /* Ensure that RTC is clocked by 1MHz */ + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32; #endif /* RTC_CLOCK_SOURCE_LSE */ - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) - { - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK) + /* Configure oscillator */ + status = HAL_RCC_OscConfig(&RCC_OscInitStruct); + if(status == HAL_OK) + { + /* Configure RTC clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Enable RTC Clock */ + if(status == HAL_OK) + { + __HAL_RCC_RTC_ENABLE(); + } + } + } + + /* If RTC Clock configuration is ok */ + if (status == HAL_OK) { - /* Enable RTC Clock */ - __HAL_RCC_RTC_ENABLE(); - /* The time base should be 1ms - Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK - HSE as RTC clock - Time base = ((99 + 1) * (9 + 1)) / 1MHz - = 1ms - LSE as RTC clock - Time base = ((31 + 1) * (0 + 1)) / 32.768KHz - = ~1ms - LSI as RTC clock - Time base = ((31 + 1) * (0 + 1)) / 32KHz - = 1ms - */ + /* The time base is defined to have highest synchronous prescaler but keeping + a 1Hz RTC frequency. */ hRTC_Handle.Instance = RTC; hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24; hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV; @@ -150,81 +206,105 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE; hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - if (HAL_RTC_Init(&hRTC_Handle) != HAL_OK) + status = HAL_RTC_Init(&hRTC_Handle); + } + + /* HAL RTC Init is ok & calendar has never been initialized */ + if (status == HAL_OK) + { + time.Hours = 0x00u; + time.Minutes = 0x00u; + time.Seconds = 0x00u; + time.TimeFormat = RTC_HOURFORMAT12_PM; + time.SubSeconds = 0x00u; + time.SecondFraction = 0x00u; + time.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + time.StoreOperation = RTC_STOREOPERATION_RESET; + status = HAL_RTC_SetTime(&hRTC_Handle, &time, RTC_FORMAT_BCD); + if ((status == HAL_OK)&& (__HAL_RTC_IS_CALENDAR_INITIALIZED(&hRTC_Handle) == 0u)) { - return HAL_ERROR; + date.WeekDay = RTC_WEEKDAY_MONDAY; + date.Date = 0x01u; + date.Month = RTC_MONTH_JANUARY; + date.Year = 0x01u; + status = HAL_RTC_SetDate(&hRTC_Handle, &date, RTC_FORMAT_BCD); } + } - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); - - /* Disable the Alarm A interrupt */ - __HAL_RTC_ALARMA_DISABLE(&hRTC_Handle); - - /* Clear flag alarm A */ - __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF); - - counter = 0U; - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == 0U) + /* If RTC calendar is initialized */ + if (status == HAL_OK) + { + alarm.AlarmTime.Hours = 0x00u; + alarm.AlarmTime.Minutes = 0x00u; + alarm.AlarmTime.Seconds = 0x00u; + alarm.AlarmTime.TimeFormat = RTC_HOURFORMAT12_PM; + alarm.AlarmTime.SubSeconds = ((RTC_SYNCH_PREDIV + 1) / (1000 / (uint32_t)uwTickFreq)); + alarm.AlarmTime.SecondFraction = 0x00u; + alarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + alarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_RESET; + alarm.AlarmMask = RTC_ALARMMASK_ALL; + + /* Depending on input frequency select Subsecond mask */ + if (uwTickFreq == HAL_TICK_FREQ_1KHZ) { - if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */ - { - return HAL_ERROR; - } +#if defined (RTC_CLOCK_SOURCE_HSE) + alarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_SS14_5; +#else + alarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_SS14_4; +#endif + } + else if (uwTickFreq == HAL_TICK_FREQ_100HZ) + { +#if defined (RTC_CLOCK_SOURCE_HSE) + alarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_SS14_8; +#else + alarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_SS14_7; +#endif + } + else + { + alarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_SS14_11; } - hRTC_Handle.Instance->ALRMAR = (uint32_t)0x01U; - - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(&hRTC_Handle); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA); - - /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); - - /* Check if the Initialization mode is set */ - if ((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + alarm.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_DATE; + alarm.AlarmDateWeekDay = RTC_WEEKDAY_MONDAY; + alarm.Alarm = RTC_ALARM_A; + status = HAL_RTC_SetAlarm_IT(&hRTC_Handle, &alarm, RTC_FORMAT_BCD); + if(status == HAL_OK) { - /* Set the Initialization mode */ - hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK; - counter = 0U; - while ((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + /* Enable the RTC global Interrupt */ + HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else { - if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */ - { - return HAL_ERROR; - } + status = HAL_ERROR; } } - hRTC_Handle.Instance->DR = 0U; - hRTC_Handle.Instance->TR = 0U; - - hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); - - HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U); - HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); - return HAL_OK; } } - return HAL_ERROR; + else + { + status = HAL_ERROR; + } + return status; } /** * @brief Suspend Tick increment. - * @note Disable the tick increment by disabling RTC ALARM interrupt. + * @note Disable the tick increment by disabling ALARM A interrupt. * @retval None */ void HAL_SuspendTick(void) { /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); - /* Disable RTC ALARM update Interrupt */ + /* Disable ALARM A Interrupt */ __HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); @@ -232,57 +312,34 @@ void HAL_SuspendTick(void) /** * @brief Resume Tick increment. - * @note Enable the tick increment by Enabling RTC ALARM interrupt. + * @note Enable the tick increment by Enabling ALARM A interrupt. * @retval None */ void HAL_ResumeTick(void) { /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); - /* Enable RTC ALARM Update interrupt */ + /* Enable ALARM A interrupt */ __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); } /** - * @brief ALARM A Event Callback in non blocking mode - * @note This function is called when RTC_ALARM interrupt took place, inside - * RTC_ALARM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment - * a global variable "uwTick" used as application time base. - * @param hrtc : RTC handle + * @brief Alarm Timer Event Callback in non blocking mode + * @note This function is called when RTC Alarm takes place, inside + * HAL_RTC_AlarmIRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param hrtc RTC handle * @retval None */ void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) { - __IO uint32_t counter = 0U; - HAL_IncTick(); - - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set the Initialization mode */ - hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; - - while ((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */ - { - break; - } - } - - hrtc->Instance->DR = 0U; - hrtc->Instance->TR = 0U; - - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /** - * @brief This function handles RTC ALARM interrupt request. + * @brief This function handles Alarm interrupt request. * @retval None */ void RTC_Alarm_IRQHandler(void) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_timebase_rtc_wakeup_template.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_timebase_rtc_wakeup_template.c index 60ac51db5e..d8fc341a76 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_timebase_rtc_wakeup_template.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_timebase_rtc_wakeup_template.c @@ -7,8 +7,8 @@ * This file overrides the native HAL time base functions (defined as weak) * to use the RTC WAKEUP for the time base generation: * + Initializes the RTC peripheral and configures the wakeup timer to be - * incremented each 1ms - * + The wakeup feature is configured to assert an interrupt each 1ms + * incremented each 1ms when uwTickFreq is set to default value, else + * 10 ms or 100 ms, depending of above global variable value. * + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback * + HSE (default), LSE or LSI can be selected as RTC clock source ****************************************************************************** @@ -22,7 +22,7 @@ * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - @verbatim + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== @@ -46,6 +46,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wbxx_hal.h" + /** @addtogroup STM32WBxx_HAL_Driver * @{ */ @@ -64,18 +65,26 @@ + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing precision. */ -#define RTC_CLOCK_SOURCE_HSE +/* #define RTC_CLOCK_SOURCE_HSE */ /* #define RTC_CLOCK_SOURCE_LSE */ /* #define RTC_CLOCK_SOURCE_LSI */ -#ifdef RTC_CLOCK_SOURCE_HSE -#define RTC_ASYNCH_PREDIV 99U -#define RTC_SYNCH_PREDIV 9U -#define RCC_RTCCLKSOURCE_1MHZ ((uint32_t)((uint32_t)RCC_BDCR_RTCSEL | (uint32_t)((HSE_VALUE/1000000U) << 16U))) -#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */ -#define RTC_ASYNCH_PREDIV 0U -#define RTC_SYNCH_PREDIV 31U -#endif /* RTC_CLOCK_SOURCE_HSE */ +/* Maximize Asynchronous prescaler for low power consumption : + ck_apre = RTCCLK / (ASYNC prediv + 1) + ck_spre = ck_apre /(SYNC prediv + 1) = 1 Hz */ +#if defined (RTC_CLOCK_SOURCE_LSE) +/* LSE Freq = 32.768 kHz RC */ +#define RTC_ASYNCH_PREDIV 0x7Fu +#define RTC_SYNCH_PREDIV 0x00FFu +#elif defined (RTC_CLOCK_SOURCE_LSI) +/* LSI Freq = 32 kHz RC */ +#define RTC_ASYNCH_PREDIV 0x7Fu +#define RTC_SYNCH_PREDIV 0x00FEu +#elif defined (RTC_CLOCK_SOURCE_HSE) +/* HSE Freq as RTCCLK = 32 MHz / 32 = 1 MHz */ +#define RTC_ASYNCH_PREDIV 0x7Fu +#define RTC_SYNCH_PREDIV 0x1E83u +#endif /* RTC_CLOCK_SOURCE_LSE */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -89,66 +98,102 @@ void RTC_WKUP_IRQHandler(void); /** * @brief This function configures the RTC_WKUP as a time base source. - * The time source is configured to have 1ms time base with a dedicated + * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * Wakeup Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK = 1ms * Wakeup Time = WakeupTimebase * WakeUpCounter (0 + 1) = 1 ms - * @note This function is called automatically at the beginning of program after + * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - __IO uint32_t counter = 0U; - + HAL_StatusTypeDef status = HAL_OK; + uint32_t wucounter; RCC_OscInitTypeDef RCC_OscInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; -#ifdef RTC_CLOCK_SOURCE_LSE - /* Configure LSE as RTC clock source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero) */ + if ((uint32_t)uwTickFreq != 0U) + { + /* Disable backup domeain protection */ + HAL_PWR_EnableBkUpAccess(); + + /* Enable RTC APB clock gating */ + __HAL_RCC_RTCAPB_CLK_ENABLE(); + + /* Disable the Wake-up Timer */ + __HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle); + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT); + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF); + + /* Get RTC clock configuration */ + HAL_RCCEx_GetPeriphCLKConfig(&PeriphClkInitStruct); + + /*In case of RTC clock already enable, make sure it's the good one */ +#if defined (RTC_CLOCK_SOURCE_LSE) + if ((PeriphClkInitStruct.RTCClockSelection == RCC_RTCCLKSOURCE_LSE) + && (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0x00u)) #elif defined (RTC_CLOCK_SOURCE_LSI) - /* Configure LSI as RTC clock source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + if ((PeriphClkInitStruct.RTCClockSelection == RCC_RTCCLKSOURCE_LSI) + && (__HAL_RCC_GET_FLAG(RCC_FLAG_LSI1RDY) != 0x00u)) #elif defined (RTC_CLOCK_SOURCE_HSE) - /* Configure HSE as RTC clock source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - /* Ensure that RTC is clocked by 1MHz */ - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_1MHZ; + if ((PeriphClkInitStruct.RTCClockSelection == RCC_RTCCLKSOURCE_HSE_DIV32) + && (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0x00u)) #else #error Please select the RTC Clock source +#endif /* RTC_CLOCK_SOURCE_LSE */ + { + /* Do nothing */ + } + else + { +#ifdef RTC_CLOCK_SOURCE_LSE + /* Configue LSE as RTC clock source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; +#elif defined (RTC_CLOCK_SOURCE_LSI) + /* Configue LSI as RTC clock source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; +#elif defined (RTC_CLOCK_SOURCE_HSE) + /* Configue HSE as RTC clock source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + /* Ensure that RTC is clocked by 1MHz */ + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32; #endif /* RTC_CLOCK_SOURCE_LSE */ - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) - { - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK) + /* Configure oscillator */ + status = HAL_RCC_OscConfig(&RCC_OscInitStruct); + if(status == HAL_OK) + { + /* Configure RTC clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + /* Enable RTC Clock */ + if(status == HAL_OK) + { + __HAL_RCC_RTC_ENABLE(); + } + } + } + + /* If RTC Clock configuration is ok */ + if (status == HAL_OK) { - /* Enable RTC Clock */ - __HAL_RCC_RTC_ENABLE(); - /* The time base should be 1ms - Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK - HSE as RTC clock - Time base = ((99 + 1) * (9 + 1)) / 1Mhz - = 1ms - LSE as RTC clock - Time base = ((31 + 1) * (0 + 1)) / 32.768Khz - = ~1ms - LSI as RTC clock - Time base = ((31 + 1) * (0 + 1)) / 32Khz - = 1ms - */ + /* No care of RTC init parameter here. Only needed if RTC is being used + for other features in same time: calendar, alarm, timestamp, etc... */ hRTC_Handle.Instance = RTC; hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24; hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV; @@ -156,64 +201,48 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE; hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - if (HAL_RTC_Init(&hRTC_Handle) != HAL_OK) - { - return HAL_ERROR; - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); - - /* Disable the Wake-up Timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle); + status = HAL_RTC_Init(&hRTC_Handle); - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT); - - /* Wait till RTC WUTWF flag is set */ - while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == 0U) + if(status == HAL_OK) { - if (counter++ == (SystemCoreClock / 48U)) + /* The time base should be of (uint32_t)uwTickFreq) ms. Tick counter + is incremented eachtime wakeup time reaches zero. Wakeup timer is + clocked on RTCCLK divided by 2. So downcounting counter has to be + set to (RTCCLK / 2) / (1000 / (uint32_t)uwTickFreq)) minus 1 */ +#ifdef RTC_CLOCK_SOURCE_LSE + wucounter = LSE_VALUE; +#elif defined (RTC_CLOCK_SOURCE_LSI) + wucounter = LSI_VALUE; +#elif defined (RTC_CLOCK_SOURCE_HSE) + /* HSE input clock to RTC is divided by 32 */ + wucounter = (HSE_VALUE >> 5); +#endif + wucounter = ((wucounter >> 1) / (1000U / (uint32_t)uwTickFreq)) -1u; + status = HAL_RTCEx_SetWakeUpTimer_IT(&hRTC_Handle, wucounter, RTC_WAKEUPCLOCK_RTCCLK_DIV2); + + if(status == HAL_OK) { - return HAL_ERROR; + /* Enable the RTC global Interrupt */ + HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } } } - - /* Clear PWR wake up Flag */ - __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU); - - /* Clear RTC Wake Up timer Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF); - - /* Configure the Wake-up Timer counter */ - hRTC_Handle.Instance->WUTR = 0U; - - /* Clear the Wake-up Timer clock source bits in CR register */ - hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS; - - /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - - /* Configure the Interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT); - - /* Enable the Wake-up Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); - - HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U); - HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); - return HAL_OK; } } - return HAL_ERROR; + else + { + status = HAL_ERROR; + } + return status; } /** @@ -248,10 +277,10 @@ void HAL_ResumeTick(void) /** * @brief Wake Up Timer Event Callback in non blocking mode - * @note This function is called when RTC_WKUP interrupt took place, inside - * RTC_WKUP_IRQHandler(). It makes a direct call to HAL_IncTick() to increment - * a global variable "uwTick" used as application time base. - * @param hrtc : RTC handle + * @note This function is called when RTC_WKUP interrupt takes place, inside + * RTC_WKUP_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param hrtc RTC handle * @retval None */ void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) @@ -260,7 +289,7 @@ void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) } /** - * @brief This function handles WAKE UP TIMER interrupt request. + * @brief This function handles WAKE UP TIMER interrupt request. * @retval None */ void RTC_WKUP_IRQHandler(void) diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_timebase_tim_template.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_timebase_tim_template.c index cb285fdd8e..dcf86f3ca5 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_timebase_tim_template.c @@ -7,7 +7,9 @@ * This file overrides the native HAL time base functions (defined as weak) * the TIM time base: * + Initializes the TIM peripheral generate a Period elapsed Event each 1ms - * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms + * when uwTickFreq is set to default value, else 10 ms or + * 100 ms, depending of above global variable value. + * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback * ****************************************************************************** * @attention @@ -20,6 +22,17 @@ * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This file must be copied to the application folder and modified as follows: + (#) Rename it to 'stm32wlxx_hal_timebase_tim.c' + (#) Add this file and the TIM HAL drivers to your project and uncomment + HAL_TIM_MODULE_ENABLED define in stm32wlxx_hal_conf.h + + @endverbatim */ /* Includes ------------------------------------------------------------------*/ @@ -39,6 +52,7 @@ /* Private variables ---------------------------------------------------------*/ extern TIM_HandleTypeDef TimHandle; TIM_HandleTypeDef TimHandle; + /* Private function prototypes -----------------------------------------------*/ void TIM2_IRQHandler(void); /* Private functions ---------------------------------------------------------*/ @@ -47,9 +61,9 @@ void TIM2_IRQHandler(void); * @brief This function configures the TIM2 as a time base source. * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after + * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) @@ -59,56 +73,84 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) uint32_t uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; +HAL_StatusTypeDef status = HAL_OK; - /* Configure the TIM2 IRQ priority */ - HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority, 0U); - - /* Enable the TIM2 global Interrupt */ - HAL_NVIC_EnableIRQ(TIM2_IRQn); - - /* Enable TIM2 clock */ - __HAL_RCC_TIM2_CLK_ENABLE(); - - /* Get clock configuration */ - HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); - - /* Get APB1 prescaler */ - uwAPB1Prescaler = clkconfig.APB1CLKDivider; - - /* Compute TIM2 clock */ - if (uwAPB1Prescaler == RCC_HCLK_DIV1) + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ + if ((uint32_t)uwTickFreq != 0U) { - uwTimclock = HAL_RCC_GetPCLK1Freq(); + /* Enable TIM2 clock */ + __HAL_RCC_TIM2_CLK_ENABLE(); + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + + /* Get APB1 prescaler */ + uwAPB1Prescaler = clkconfig.APB1CLKDivider; + + /* Compute TIM2 clock */ + if (uwAPB1Prescaler == RCC_HCLK_DIV1) + { + uwTimclock = HAL_RCC_GetPCLK1Freq(); + } + else + { + uwTimclock = 2*HAL_RCC_GetPCLK1Freq(); + } + + /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); + + /* Initialize TIM2 */ + TimHandle.Instance = TIM2; + + /* Initialize TIMx peripheral as follow: + + Period = [(TIM2CLK/uwTickFreq) - 1]. to have a (1/uwTickFreq) s time base. + + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + + ClockDivision = 0 + + Counter direction = Up + */ + TimHandle.Init.Period = (1000000U / (1000U / (uint32_t)uwTickFreq)) - 1U; + TimHandle.Init.Prescaler = uwPrescalerValue; + TimHandle.Init.ClockDivision = 0U; + TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + TimHandle.Init.RepetitionCounter = 0U; + if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK) + { + /* Start the TIM time Base generation in interrupt mode */ + if (HAL_TIM_Base_Start_IT(&TimHandle) == HAL_OK) + { + /* Enable the TIM2 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM2_IRQn); + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /*Configure the TIM2 IRQ priority */ + HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } } else { - uwTimclock = 2U * HAL_RCC_GetPCLK1Freq(); - } - - /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */ - uwPrescalerValue = (uint32_t)((uwTimclock / 1000000U) - 1U); - - /* Initialize TIM2 */ - TimHandle.Instance = TIM2; - - /* Initialize TIMx peripheral as follow: - + Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base. - + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. - + ClockDivision = 0 - + Counter direction = Up - */ - TimHandle.Init.Period = (1000000U / 1000U) - 1U; - TimHandle.Init.Prescaler = uwPrescalerValue; - TimHandle.Init.ClockDivision = 0U; - TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; - if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK) - { - /* Start the TIM time Base generation in interrupt mode */ - return HAL_TIM_Base_Start_IT(&TimHandle); + status = HAL_ERROR; } /* Return function status */ - return HAL_ERROR; + return status; } /** diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tsc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tsc.c index 4e010161b6..facaf4be79 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tsc.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tsc.c @@ -818,7 +818,7 @@ HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc) * @param gx_index Index of the group * @retval Group status */ -TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index) +TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); @@ -835,7 +835,7 @@ TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t * @param gx_index Index of the group * @retval Acquisition measure */ -uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index) +uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); @@ -870,7 +870,7 @@ uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index) * @param config Pointer to the configuration structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config) +HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config) { /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c index 4f71c04b9d..23c7ce0502 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_uart.c @@ -177,12 +177,11 @@ /** @defgroup UART_Private_Constants UART Private Constants * @{ */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ - USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ - USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ + USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ #if defined(LPUART1) #define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ @@ -191,7 +190,6 @@ #define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ #define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ - /** * @} */ @@ -1168,6 +1166,9 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { + + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1185,6 +1186,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } @@ -1260,6 +1263,8 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { + huart->RxState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1394,7 +1399,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } -#endif +#endif /* LPUART1 */ return (UART_Start_Receive_IT(huart, pData, Size)); } @@ -1514,7 +1519,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } -#endif +#endif /* LPUART1 */ return (UART_Start_Receive_DMA(huart, pData, Size)); } @@ -3396,6 +3401,13 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + /* Timeout occurred */ return HAL_TIMEOUT; } @@ -3407,6 +3419,15 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + /* Timeout occurred */ return HAL_TIMEOUT; } @@ -3444,35 +3465,39 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); return HAL_TIMEOUT; } if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; huart->ErrorCode = HAL_UART_ERROR_RTO; /* Process Unlocked */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c index 25c5823153..ed44c2afef 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_dma.c @@ -24,7 +24,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WBxx_LL_Driver * @{ @@ -76,47 +76,47 @@ #if defined (DMA2) #if defined (DMA2_Channel6) && defined (DMA2_Channel7) #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ - (((CHANNEL) == LL_DMA_CHANNEL_1) || \ - ((CHANNEL) == LL_DMA_CHANNEL_2) || \ - ((CHANNEL) == LL_DMA_CHANNEL_3) || \ - ((CHANNEL) == LL_DMA_CHANNEL_4) || \ - ((CHANNEL) == LL_DMA_CHANNEL_5) || \ - ((CHANNEL) == LL_DMA_CHANNEL_6) || \ - ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ - (((INSTANCE) == DMA2) && \ - (((CHANNEL) == LL_DMA_CHANNEL_1) || \ - ((CHANNEL) == LL_DMA_CHANNEL_2) || \ - ((CHANNEL) == LL_DMA_CHANNEL_3) || \ - ((CHANNEL) == LL_DMA_CHANNEL_4) || \ - ((CHANNEL) == LL_DMA_CHANNEL_5) || \ - ((CHANNEL) == LL_DMA_CHANNEL_6) || \ - ((CHANNEL) == LL_DMA_CHANNEL_7)))) + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ + (((INSTANCE) == DMA2) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7)))) #else #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ - (((CHANNEL) == LL_DMA_CHANNEL_1) || \ - ((CHANNEL) == LL_DMA_CHANNEL_2) || \ - ((CHANNEL) == LL_DMA_CHANNEL_3) || \ - ((CHANNEL) == LL_DMA_CHANNEL_4) || \ - ((CHANNEL) == LL_DMA_CHANNEL_5) || \ - ((CHANNEL) == LL_DMA_CHANNEL_6) || \ - ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ - (((INSTANCE) == DMA2) && \ - (((CHANNEL) == LL_DMA_CHANNEL_1) || \ - ((CHANNEL) == LL_DMA_CHANNEL_2) || \ - ((CHANNEL) == LL_DMA_CHANNEL_3) || \ - ((CHANNEL) == LL_DMA_CHANNEL_4) || \ - ((CHANNEL) == LL_DMA_CHANNEL_5)))) -#endif + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ + (((INSTANCE) == DMA2) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5)))) +#endif /* DMA2_Channel6 && DMA2_Channel7*/ #else #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ - (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ - ((CHANNEL) == LL_DMA_CHANNEL_2) || \ - ((CHANNEL) == LL_DMA_CHANNEL_3) || \ - ((CHANNEL) == LL_DMA_CHANNEL_4) || \ - ((CHANNEL) == LL_DMA_CHANNEL_5) || \ - ((CHANNEL) == LL_DMA_CHANNEL_6) || \ - ((CHANNEL) == LL_DMA_CHANNEL_7)))) -#endif + (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7)))) +#endif /* DMA2 */ /** * @} */ @@ -175,7 +175,7 @@ ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) /* Release reset of DMA clock */ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); } -#endif +#endif /* DMA2 */ else { status = ERROR; diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c index d750f5df75..fb672a54dd 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_gpio.c @@ -24,7 +24,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WBxx_LL_Driver * @{ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_i2c.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_i2c.c index 70fe40c86c..be313fb6f5 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_i2c.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_i2c.c @@ -83,7 +83,7 @@ * - SUCCESS: I2C registers are de-initialized * - ERROR: I2C registers are not de-initialized */ -ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx) { ErrorStatus status = SUCCESS; @@ -124,7 +124,7 @@ ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) * - SUCCESS: I2C registers are initialized * - ERROR: Not applicable */ -ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct) { /* Check the I2C Instance I2Cx */ assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c index 7eebe1b960..dbf02092dc 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c @@ -97,37 +97,37 @@ ErrorStatus LL_PWR_DeInit(void) #if defined(GPIOD) LL_PWR_WriteReg(PUCRD, PWR_PUCRD_RESET_VALUE); LL_PWR_WriteReg(PDCRD, PWR_PDCRD_RESET_VALUE); -#endif +#endif /* GPIOD */ LL_PWR_WriteReg(PUCRE, PWR_PUCRE_RESET_VALUE); LL_PWR_WriteReg(PDCRE, PWR_PDCRE_RESET_VALUE); LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE); LL_PWR_WriteReg(PDCRH, PWR_PDCRH_RESET_VALUE); LL_PWR_WriteReg(C2CR1, PWR_C2CR1_RESET_VALUE); LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE); - + /* Clear all flags */ LL_PWR_WriteReg(SCR, - LL_PWR_SCR_CC2HF + LL_PWR_SCR_CC2HF | LL_PWR_SCR_CBLEAF | LL_PWR_SCR_CCRPEF #if defined(PWR_CR3_E802A) | LL_PWR_SCR_C802AF | LL_PWR_SCR_C802WUF -#endif +#endif /* PWR_CR3_E802A */ | LL_PWR_SCR_CBLEWUF #if defined(PWR_CR5_SMPSEN) | LL_PWR_SCR_CBORHF | LL_PWR_SCR_CSMPSFBF -#endif +#endif /* PWR_CR5_SMPSEN */ | LL_PWR_SCR_CWUF ); - + LL_PWR_WriteReg(EXTSCR, - LL_PWR_EXTSCR_CCRPF + LL_PWR_EXTSCR_CCRPF | LL_PWR_EXTSCR_C2CSSF | LL_PWR_EXTSCR_C1CSSF ); - + return SUCCESS; } @@ -142,7 +142,7 @@ ErrorStatus LL_PWR_DeInit(void) /** * @} */ -#endif /* defined(PWR) */ +#endif /* PWR */ /** * @} */ diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c index 21ea455105..0219ee8f03 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c @@ -1352,7 +1352,7 @@ static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) * @} */ -#endif /* defined(RCC) */ +#endif /* RCC */ /** * @} diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c index d09b530f34..d7cd274d3d 100644 --- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c +++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c @@ -24,7 +24,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WBxx_LL_Driver * @{ @@ -43,7 +43,7 @@ #define UTILS_MAX_FREQUENCY_SCALE1 64000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ #if defined(PWR_CR1_VOS) #define UTILS_MAX_FREQUENCY_SCALE2 16000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ -#endif +#endif /* PWR_CR1_VOS */ /* Defines used for PLL range */ #define UTILS_PLLVCO_INPUT_MIN 2660000U /*!< Frequency min for PLLVCO input, in Hz */ @@ -63,64 +63,66 @@ * @{ */ #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_3) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_5) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_6) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_10) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_32) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_3) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_5) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_6) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_10) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_32) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_16)) #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ - || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ - || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ - || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ - || ((__VALUE__) == LL_RCC_APB2_DIV_16)) + || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_16)) #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_8)) + || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \ + || ((__VALUE__) == LL_RCC_PLLM_DIV_8)) #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U)) #define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \ - || ((__VALUE__) == LL_RCC_PLLR_DIV_3) \ - || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \ - || ((__VALUE__) == LL_RCC_PLLR_DIV_5) \ - || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \ - || ((__VALUE__) == LL_RCC_PLLR_DIV_7) \ - || ((__VALUE__) == LL_RCC_PLLR_DIV_8)) + || ((__VALUE__) == LL_RCC_PLLR_DIV_3) \ + || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \ + || ((__VALUE__) == LL_RCC_PLLR_DIV_5) \ + || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \ + || ((__VALUE__) == LL_RCC_PLLR_DIV_7) \ + || ((__VALUE__) == LL_RCC_PLLR_DIV_8)) -#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX)) +#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) &&\ + ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX)) -#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX)) +#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) &&\ + ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX)) #if defined(PWR_CR1_VOS) #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ - ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2)) + ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2)) #else #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) -#endif +#endif /* PWR_CR1_VOS */ #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ - || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) #define countof(a) (sizeof(a) / sizeof(*(a))) /** @@ -130,8 +132,10 @@ /** @defgroup UTILS_LL_Private_Functions UTILS Private functions * @{ */ -static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); -static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_PLL_IsBusy(void); /** @@ -267,7 +271,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency) uint32_t maxfreq = (voltagescaling == LL_PWR_REGU_VOLTAGE_SCALE1) ? UTILS_MAX_FREQUENCY_SCALE1 : UTILS_MAX_FREQUENCY_SCALE2; #else uint32_t maxfreq = UTILS_MAX_FREQUENCY_SCALE1; -#endif +#endif /* PWR_CR1_VOS */ /* Array used for FLASH latency according to HCLK4 Frequency */ /* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */ @@ -276,7 +280,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency) #if defined(PWR_CR1_VOS) /* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */ const uint32_t UTILS_CLK_SRC_RANGE_VOS2[] = {6000000U, 12000000U, UTILS_MAX_FREQUENCY_SCALE2}; -#endif +#endif /* PWR_CR1_VOS */ /* Flash Latency range */ const uint32_t UTILS_LATENCY_RANGE[] = {LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3}; @@ -319,7 +323,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency) break; } } -#endif +#endif /* PWR_CR1_VOS */ } if (status != ERROR) @@ -334,8 +338,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency) /* Wait for Flash latency to be updated */ getlatency = LL_FLASH_GetLatency(); timeout--; - } - while ((getlatency != latency) && (timeout > 0U)); + } while ((getlatency != latency) && (timeout > 0U)); if (getlatency != latency) { @@ -531,7 +534,8 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS * - SUCCESS: Max frequency configuration done * - ERROR: Max frequency configuration not done */ -ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { ErrorStatus status; uint32_t pllrfreq, hclk2freq; @@ -568,7 +572,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass, LL_UTILS_PLLInitTyp { LL_RCC_HSE_DisableBypass(); } -#endif +#endif /* RCC_CR_HSEBYP */ /* Enable HSE */ LL_RCC_HSE_Enable(); while (LL_RCC_HSE_IsReady() != 1U) @@ -662,7 +666,7 @@ static ErrorStatus UTILS_PLL_IsBusy(void) /* PLLSAI1 configuration cannot be modified */ status = ERROR; } -#endif +#endif /* SAI1 */ return status; } @@ -676,7 +680,8 @@ static ErrorStatus UTILS_PLL_IsBusy(void) * - SUCCESS: No problem to switch system to PLL * - ERROR: Problem to switch system to PLL */ -static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { ErrorStatus status = SUCCESS; uint32_t hclks_frequency_target, hclks_frequency_current, sysclk_current; diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index b4df0f7818..fab7cd6a2e 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -16,7 +16,7 @@ * STM32L5: 1.0.5 * STM32MP1: 1.6.0 * STM32U5: 1.2.0 - * STM32WB: 1.12.0 + * STM32WB: 1.13.0 * STM32WL: 1.3.0 Release notes of each STM32YYxx HAL Drivers available here: