diff --git a/boards.txt b/boards.txt index 14f58ef044..7aa1c9ff76 100644 --- a/boards.txt +++ b/boards.txt @@ -43,7 +43,7 @@ Nucleo_144.menu.pnum.NUCLEO_F429ZI.node=NODE_F429ZI Nucleo_144.menu.pnum.NUCLEO_F429ZI.upload.maximum_size=2097152 Nucleo_144.menu.pnum.NUCLEO_F429ZI.upload.maximum_data_size=262144 Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.mcu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.f_cpu=16000000L +Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.f_cpu=18000000L Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.board=NUCLEO_F429ZI Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.series=STM32F4xx Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.product_line=STM32F429xx diff --git a/platform.txt b/platform.txt index 94a3f44dc5..da1a7e05e4 100644 --- a/platform.txt +++ b/platform.txt @@ -126,10 +126,10 @@ recipe.size.regex.eeprom=^(?:\.eeprom)\s+([0-9]+).* tools.massStorageCopy.cmd=massStorageCopy tools.massStorageCopy.cmd.windows=massStorageCopy.bat tools.massStorageCopy.cmd.macosx=massStorageCopyMacOsX -tools.massStorageCopy.path={runtime.hardware.path}/tools/win -tools.massStorageCopy.path.macosx={runtime.hardware.path}/tools/macosx -tools.massStorageCopy.path.linux={runtime.hardware.path}/tools/linux -tools.massStorageCopy.path.linux64={runtime.hardware.path}/tools/linux +tools.massStorageCopy.path={runtime.tools.STM32Tools.path}/tools/win +tools.massStorageCopy.path.macosx={runtime.tools.STM32Tools.path}/tools/macosx +tools.massStorageCopy.path.linux={runtime.tools.STM32Tools.path}/tools/linux +tools.massStorageCopy.path.linux64={runtime.tools.STM32Tools.path}/tools/linux tools.massStorageCopy.upload.params.verbose= tools.massStorageCopy.upload.params.quiet= tools.massStorageCopy.upload.pattern="{path}/{cmd}" {upload.verbose} -I "{build.path}/{build.project_name}.bin" -O "{node}" @@ -137,10 +137,10 @@ tools.massStorageCopy.upload.pattern="{path}/{cmd}" {upload.verbose} -I "{build. # ST-Link upload tools.stlink_upload.cmd=stlink_upload tools.stlink_upload.cmd.windows=stlink_upload.bat -tools.stlink_upload.path.windows={runtime.hardware.path}/tools/win -tools.stlink_upload.path.macosx={runtime.hardware.path}/tools/macosx -tools.stlink_upload.path.linux={runtime.hardware.path}/tools/linux -tools.stlink_upload.path.linux64={runtime.hardware.path}/tools/linux64 +tools.stlink_upload.path.windows={runtime.tools.STM32Tools.path}/tools/win +tools.stlink_upload.path.macosx={runtime.tools.STM32Tools.path}/tools/macosx +tools.stlink_upload.path.linux={runtime.tools.STM32Tools.path}/tools/linux +tools.stlink_upload.path.linux64={runtime.tools.STM32Tools.path}/tools/linux64 tools.stlink_upload.upload.params.verbose=-d tools.stlink_upload.upload.params.quiet= tools.stlink_upload.upload.pattern="{path}/{cmd}" {serial.port.file} {upload.altID} {upload.usbID} "{build.path}/{build.project_name}.bin" diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c index 5f41a88e9c..40d44e1ee4 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c @@ -5,11 +5,11 @@ * @version V1.1.1 * @date 12-May-2017 * @brief ETH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State and Errors functions * @verbatim @@ -19,21 +19,21 @@ [..] (#)Declare a ETH_HandleTypeDef handle structure, for example: ETH_HandleTypeDef heth; - + (#)Fill parameters of Init structure in heth handle - - (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) + + (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: - (##) Enable the Ethernet interface clock using + (##) Enable the Ethernet interface clock using (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); - + (##) Initialize the related GPIO clocks (##) Configure Ethernet pin-out - (##) Configure Ethernet NVIC interrupt (IT mode) - + (##) Configure Ethernet NVIC interrupt (IT mode) + (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: (##) HAL_ETH_DMATxDescListInit(); for Transmission process (##) HAL_ETH_DMARxDescListInit(); for Reception process @@ -41,11 +41,11 @@ (#)Enable MAC and DMA transmission and reception: (##) HAL_ETH_Start(); - (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer + (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer the frame to MAC TX FIFO: (##) HAL_ETH_TransmitFrame(); - (#)Poll for a received frame in ETH RX DMA Descriptors and get received + (#)Poll for a received frame in ETH RX DMA Descriptors and get received frame parameters (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) @@ -53,18 +53,18 @@ (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) (#) Communicate with external PHY device: - (##) Read a specific register from the PHY + (##) Read a specific register from the PHY HAL_ETH_ReadPHYRegister(); (##) Write data to a specific RHY register: HAL_ETH_WritePHYRegister(); (#) Configure the Ethernet MAC after ETH peripheral initialization HAL_ETH_ConfigMAC(); all MAC parameters should be filled. - + (#) Configure the Ethernet DMA after ETH peripheral initialization HAL_ETH_ConfigDMA(); all DMA parameters should be filled. - - -@- The PTP protocol and the DMA descriptors ring mode are not supported + + -@- The PTP protocol and the DMA descriptors ring mode are not supported in this driver @endverbatim @@ -96,7 +96,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -153,10 +153,10 @@ static void ETH_Delay(uint32_t mdelay); * @{ */ -/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== @@ -181,19 +181,19 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) uint32_t hclk = 60000000U; uint32_t tickstart = 0U; uint32_t err = ETH_SUCCESS; - + /* Check the ETH peripheral state */ if(heth == NULL) { return HAL_ERROR; } - + /* Check parameters */ assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation)); assert_param(IS_ETH_RX_MODE(heth->Init.RxMode)); assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode)); - assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); - + assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); + if(heth->State == HAL_ETH_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -201,45 +201,45 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) /* Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspInit(heth); } - + /* Select MII or RMII Mode*/ AFIO->MAPR &= ~(AFIO_MAPR_MII_RMII_SEL); AFIO->MAPR |= (uint32_t)heth->Init.MediaInterface; - + /* Ethernet Software reset */ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ /* After reset all the registers holds their respective reset values */ (heth->Instance)->DMABMR |= ETH_DMABMR_SR; - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait for software reset */ while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET) - { + { heth->State= HAL_ETH_STATE_TIMEOUT; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - - /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are + + /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are not available, please check your external PHY or the IO configuration */ return HAL_TIMEOUT; } } - + /*-------------------------------- MAC Initialization ----------------------*/ /* Get the ETHERNET MACMIIAR value */ tmpreg1 = (heth->Instance)->MACMIIAR; /* Clear CSR Clock Range CR[2:0] bits */ tmpreg1 &= ETH_MACMIIAR_CR_MASK; - + /* Get hclk frequency value */ hclk = HAL_RCC_GetHCLKFreq(); - + /* Set CR bits depending on hclk value */ if((hclk >= 20000000U)&&(hclk < 35000000U)) { @@ -248,146 +248,146 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) } else if((hclk >= 35000000U)&&(hclk < 60000000U)) { - /* CSR Clock Range between 35-60 MHz */ + /* CSR Clock Range between 35-60 MHz */ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV26; - } + } else { - /* CSR Clock Range between 60-72 MHz */ + /* CSR Clock Range between 60-72 MHz */ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV42; - } - + } + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1; - + /*-------------------- PHY initialization and configuration ----------------*/ /* Put the PHY in reset mode */ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set the ETH peripheral state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return HAL_ERROR */ return HAL_ERROR; } - + /* Delay to assure PHY reset */ HAL_Delay(PHY_RESET_DELAY); - + if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE) { /* Get tick */ tickstart = HAL_GetTick(); - + /* We wait for linked status */ do { HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - + /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_TIMEOUT; } } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS)); - + /* Enable Auto-Negotiation */ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set the ETH peripheral state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return HAL_ERROR */ - return HAL_ERROR; + return HAL_ERROR; } - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait until the auto-negotiation will be completed */ do { HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - + /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_TIMEOUT; } - + } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE)); - + /* Read the result of the auto-negotiation */ if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set the ETH peripheral state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return HAL_ERROR */ - return HAL_ERROR; + return HAL_ERROR; } - + /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */ if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET) { /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; + (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; } else { /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; + (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; } /* Configure the MAC with the speed fixed by the auto-negotiation process */ if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS) - { + { /* Set Ethernet speed to 10M following the auto-negotiation */ - (heth->Init).Speed = ETH_SPEED_10M; + (heth->Init).Speed = ETH_SPEED_10M; } else - { - /* Set Ethernet speed to 100M following the auto-negotiation */ + { + /* Set Ethernet speed to 100M following the auto-negotiation */ (heth->Init).Speed = ETH_SPEED_100M; } } @@ -396,40 +396,40 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) /* Check parameters */ assert_param(IS_ETH_SPEED(heth->Init.Speed)); assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - + /* Set MAC Speed and Duplex Mode */ if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) | (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set the ETH peripheral state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return HAL_ERROR */ return HAL_ERROR; - } - + } + /* Delay to assure PHY configuration */ HAL_Delay(PHY_CONFIG_DELAY); } - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set ETH HAL State to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Return function status */ return HAL_OK; } /** - * @brief De-Initializes the ETH peripheral. + * @brief De-Initializes the ETH peripheral. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status @@ -438,10 +438,10 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) { /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspDeInit(heth); - + /* Set ETH HAL state to Disabled */ heth->State= HAL_ETH_STATE_RESET; @@ -455,8 +455,8 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) /** * @brief Initializes the DMA Tx descriptors in chain mode. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMATxDescTab: Pointer to the first Tx desc list + * the configuration information for ETHERNET module + * @param DMATxDescTab: Pointer to the first Tx desc list * @param TxBuff: Pointer to the first TxBuffer list * @param TxBuffCount: Number of the used Tx desc in the list * @retval HAL status @@ -465,34 +465,34 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc { uint32_t i = 0U; ETH_DMADescTypeDef *dmatxdesc; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ heth->TxDesc = DMATxDescTab; - - /* Fill each DMATxDesc descriptor with the right values */ + + /* Fill each DMATxDesc descriptor with the right values */ for(i=0U; i < TxBuffCount; i++) { /* Get the pointer on the ith member of the Tx Desc list */ dmatxdesc = DMATxDescTab + i; - + /* Set Second Address Chained bit */ - dmatxdesc->Status = ETH_DMATXDESC_TCH; - + dmatxdesc->Status = ETH_DMATXDESC_TCH; + /* Set Buffer1 address pointer */ dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]); - + if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { /* Set the DMA Tx descriptors checksum insertion */ dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; } - + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ if(i < (TxBuffCount-1U)) { @@ -501,20 +501,20 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc } else { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; } } - + /* Set Transmit Descriptor List Address Register */ (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab; - + /* Set ETH HAL State to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -522,8 +522,8 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc /** * @brief Initializes the DMA Rx descriptors in chain mode. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMARxDescTab: Pointer to the first Rx desc list + * the configuration information for ETHERNET module + * @param DMARxDescTab: Pointer to the first Rx desc list * @param RxBuff: Pointer to the first RxBuffer list * @param RxBuffCount: Number of the used Rx desc in the list * @retval HAL status @@ -532,59 +532,59 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc { uint32_t i = 0U; ETH_DMADescTypeDef *DMARxDesc; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */ - heth->RxDesc = DMARxDescTab; - + heth->RxDesc = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ for(i=0U; i < RxBuffCount; i++) { /* Get the pointer on the ith member of the Rx Desc list */ DMARxDesc = DMARxDescTab+i; - + /* Set Own bit of the Rx descriptor Status */ DMARxDesc->Status = ETH_DMARXDESC_OWN; - + /* Set Buffer1 size and Second Address Chained bit */ - DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; - + DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; + /* Set Buffer1 address pointer */ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]); - + if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) { /* Enable Ethernet DMA Rx Descriptor interrupt */ DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC; } - + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ if(i < (RxBuffCount-1U)) { /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U); + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U); } else { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); } } - + /* Set Receive Descriptor List Address Register */ (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab; - + /* Set ETH HAL State to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -623,13 +623,13 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) * @} */ -/** @defgroup ETH_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions +/** @defgroup ETH_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions * - @verbatim + @verbatim ============================================================================== ##### IO operation functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Transmit a frame HAL_ETH_TransmitFrame(); @@ -642,12 +642,12 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) HAL_ETH_WritePHYRegister(); @endverbatim - + * @{ */ /** - * @brief Sends an Ethernet frame. + * @brief Sends an Ethernet frame. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @param FrameLength: Amount of data to be sent @@ -656,47 +656,47 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) { uint32_t bufcount = 0U, size = 0U, i = 0U; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - - if (FrameLength == 0U) + + if (FrameLength == 0U) { /* Set ETH HAL state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - - return HAL_ERROR; - } - + + return HAL_ERROR; + } + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) - { + { /* OWN bit set */ heth->State = HAL_ETH_STATE_BUSY_TX; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_ERROR; } - + /* Get the number of needed Tx buffers for the current frame */ if (FrameLength > ETH_TX_BUF_SIZE) { bufcount = FrameLength/ETH_TX_BUF_SIZE; - if (FrameLength % ETH_TX_BUF_SIZE) + if (FrameLength % ETH_TX_BUF_SIZE) { bufcount++; } } - else - { + else + { bufcount = 1U; } if (bufcount == 1U) @@ -716,16 +716,16 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL { /* Clear FIRST and LAST segment bits */ heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); - - if (i == 0U) + + if (i == 0U) { /* Setting the first segment bit */ - heth->TxDesc->Status |= ETH_DMATXDESC_FS; + heth->TxDesc->Status |= ETH_DMATXDESC_FS; } - + /* Program size */ heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1); - + if (i == (bufcount-1U)) { /* Setting the last segment bit */ @@ -733,14 +733,14 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE; heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); } - + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ heth->TxDesc->Status |= ETH_DMATXDESC_OWN; /* point to next descriptor */ heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); } } - + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) { @@ -749,19 +749,19 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL /* Resume DMA transmission*/ (heth->Instance)->DMATPDR = 0U; } - + /* Set ETH HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } /** - * @brief Checks for received frames. + * @brief Checks for received frames. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status @@ -769,46 +769,46 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) { uint32_t framelength = 0U; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Check the ETH state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Check if segment is not owned by DMA */ /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */ if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET)) { /* Check if last segment */ - if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) + if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) { /* increment segment count */ (heth->RxFrameInfos).SegCount++; - + /* Check if last segment is first segment: one segment contains the frame */ if ((heth->RxFrameInfos).SegCount == 1U) { (heth->RxFrameInfos).FSRxDesc =heth->RxDesc; } - + heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; heth->RxFrameInfos.length = framelength; - + /* Get the address of the buffer start address */ heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; /* point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr); - + /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -821,27 +821,27 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); } - /* Check if intermediate segment */ + /* Check if intermediate segment */ else { (heth->RxFrameInfos).SegCount++; /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } + } } - + /* Set ETH HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_ERROR; } /** - * @brief Gets the Received frame in interrupt mode. + * @brief Gets the Received frame in interrupt mode. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status @@ -849,25 +849,25 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) { uint32_t descriptorscancounter = 0U; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set ETH HAL State to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Scan descriptors owned by CPU */ while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB)) { /* Just for security */ descriptorscancounter++; - + /* Check if first segment in frame */ - /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ + /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS) - { + { heth->RxFrameInfos.FSRxDesc = heth->RxDesc; - heth->RxFrameInfos.SegCount = 1U; + heth->RxFrameInfos.SegCount = 1U; /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); } @@ -882,34 +882,34 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) } /* Should be last segment */ else - { + { /* Last segment */ heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - + /* Increment segment count */ (heth->RxFrameInfos.SegCount)++; - + /* Check if last segment is first segment: one segment contains the frame */ if ((heth->RxFrameInfos.SegCount) == 1U) { heth->RxFrameInfos.FSRxDesc = heth->RxDesc; } - + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; - - /* Get the address of the buffer start address */ + + /* Get the address of the buffer start address */ heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; - - /* Point to next descriptor */ + + /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - + /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -917,10 +917,10 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_ERROR; } @@ -934,40 +934,40 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) { /* Frame received */ - if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) + if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) { /* Receive complete callback */ HAL_ETH_RxCpltCallback(heth); - + /* Clear the Eth DMA Rx IT pending bits */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R); /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); } /* Frame transmitted */ - else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) + else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) { /* Transfer complete callback */ HAL_ETH_TxCpltCallback(heth); - + /* Clear the Eth DMA Tx IT pending bits */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T); /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); } - + /* Clear the interrupt flags */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS); - + /* ETH DMA Error */ if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS)) { @@ -976,10 +976,10 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) /* Clear the interrupt flags */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS); - + /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); } @@ -997,7 +997,7 @@ __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) UNUSED(heth); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_TxCpltCallback could be implemented in the user file - */ + */ } /** @@ -1012,7 +1012,7 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) UNUSED(heth); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_TxCpltCallback could be implemented in the user file - */ + */ } /** @@ -1027,29 +1027,29 @@ __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) UNUSED(heth); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_TxCpltCallback could be implemented in the user file - */ + */ } /** * @brief Reads a PHY register * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Basic Control Register, - * PHY_BSR: Transceiver Basic Status Register. + * the configuration information for ETHERNET module + * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Basic Control Register, + * PHY_BSR: Transceiver Basic Status Register. * More PHY register could be read depending on the used PHY - * @param RegValue: PHY register value + * @param RegValue: PHY register value * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) { - uint32_t tmpreg1 = 0U; + uint32_t tmpreg1 = 0U; uint32_t tickstart = 0U; - + /* Check parameters */ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - + /* Check the ETH peripheral state */ if(heth->State == HAL_ETH_STATE_BUSY_RD) { @@ -1057,25 +1057,25 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR } /* Set ETH HAL State to BUSY_RD */ heth->State = HAL_ETH_STATE_BUSY_RD; - + /* Get the ETHERNET MACMIIAR value */ tmpreg1 = heth->Instance->MACMIIAR; - + /* Keep only the CSR Clock Range CR[2:0] bits value */ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; - + /* Prepare the MII address register value */ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - + /* Write the result value into the MII Address register */ heth->Instance->MACMIIAR = tmpreg1; - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Check for the Busy flag */ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) { @@ -1083,22 +1083,22 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR if((HAL_GetTick() - tickstart ) > PHY_READ_TO) { heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_TIMEOUT; } - + tmpreg1 = heth->Instance->MACMIIAR; } - + /* Get MACMIIDR value */ *RegValue = (uint16_t)(heth->Instance->MACMIIDR); - + /* Set ETH HAL State to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1106,10 +1106,10 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR /** * @brief Writes to a PHY register. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Control Register. + * the configuration information for ETHERNET module + * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Control Register. * More PHY register could be written depending on the used PHY * @param RegValue: the value to write * @retval HAL status @@ -1118,10 +1118,10 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY { uint32_t tmpreg1 = 0U; uint32_t tickstart = 0U; - + /* Check parameters */ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - + /* Check the ETH peripheral state */ if(heth->State == HAL_ETH_STATE_BUSY_WR) { @@ -1129,28 +1129,28 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY } /* Set ETH HAL State to BUSY_WR */ heth->State = HAL_ETH_STATE_BUSY_WR; - + /* Get the ETHERNET MACMIIAR value */ tmpreg1 = heth->Instance->MACMIIAR; - + /* Keep only the CSR Clock Range CR[2:0] bits value */ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; - + /* Prepare the MII register address value */ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - + /* Give the value to the MII data register */ heth->Instance->MACMIIDR = (uint16_t)RegValue; - + /* Write the result value into the MII Address register */ heth->Instance->MACMIIAR = tmpreg1; - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Check for the Busy flag */ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) { @@ -1158,21 +1158,21 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO) { heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_TIMEOUT; } - + tmpreg1 = heth->Instance->MACMIIAR; } - + /* Set ETH HAL State to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return function status */ - return HAL_OK; + return HAL_OK; } /** @@ -1180,16 +1180,16 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY */ /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Enable MAC and DMA transmission and reception. HAL_ETH_Start(); - (+) Disable MAC and DMA transmission and reception. + (+) Disable MAC and DMA transmission and reception. HAL_ETH_Stop(); (+) Set the MAC configuration in runtime mode HAL_ETH_ConfigMAC(); @@ -1198,82 +1198,82 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY @endverbatim * @{ - */ + */ /** - * @brief Enables Ethernet MAC and DMA reception/transmission + * @brief Enables Ethernet MAC and DMA reception/transmission * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) -{ +{ /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Enable transmit state machine of the MAC for transmission on the MII */ ETH_MACTransmissionEnable(heth); - + /* Enable receive state machine of the MAC for reception from the MII */ ETH_MACReceptionEnable(heth); - + /* Flush Transmit FIFO */ ETH_FlushTransmitFIFO(heth); - + /* Start DMA transmission */ ETH_DMATransmissionEnable(heth); - + /* Start DMA reception */ ETH_DMAReceptionEnable(heth); - + /* Set the ETH state to READY*/ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } /** - * @brief Stop Ethernet MAC and DMA reception/transmission + * @brief Stop Ethernet MAC and DMA reception/transmission * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) -{ +{ /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Stop DMA transmission */ ETH_DMATransmissionDisable(heth); - + /* Stop DMA reception */ ETH_DMAReceptionDisable(heth); - + /* Disable receive state machine of the MAC for reception from the MII */ ETH_MACReceptionDisable(heth); - + /* Flush Transmit FIFO */ ETH_FlushTransmitFIFO(heth); - + /* Disable transmit state machine of the MAC for transmission on the MII */ ETH_MACTransmissionDisable(heth); - + /* Set the ETH state*/ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -1282,22 +1282,22 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) * @brief Set ETH MAC Configuration. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param macconf: MAC Configuration structure + * @param macconf: MAC Configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) { uint32_t tmpreg1 = 0U; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State= HAL_ETH_STATE_BUSY; - + assert_param(IS_ETH_SPEED(heth->Init.Speed)); - assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - + assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); + if (macconf != NULL) { /* Check the parameters */ @@ -1328,86 +1328,86 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl)); assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison)); assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier)); - + /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ tmpreg1 = (heth->Instance)->MACCR; /* Clear WD, PCE, PS, TE and RE bits */ tmpreg1 &= ETH_MACCR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)(macconf->Watchdog | - macconf->Jabber | + + tmpreg1 |= (uint32_t)(macconf->Watchdog | + macconf->Jabber | macconf->InterFrameGap | macconf->CarrierSense | - (heth->Init).Speed | + (heth->Init).Speed | macconf->ReceiveOwn | macconf->LoopbackMode | - (heth->Init).DuplexMode | - macconf->ChecksumOffload | - macconf->RetryTransmission | - macconf->AutomaticPadCRCStrip | - macconf->BackOffLimit | + (heth->Init).DuplexMode | + macconf->ChecksumOffload | + macconf->RetryTransmission | + macconf->AutomaticPadCRCStrip | + macconf->BackOffLimit | macconf->DeferralCheck); - + /* Write to ETHERNET MACCR */ (heth->Instance)->MACCR = (uint32_t)tmpreg1; - + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | + (heth->Instance)->MACCR = tmpreg1; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Write to ETHERNET MACFFR */ + (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | macconf->SourceAddrFilter | macconf->PassControlFrames | - macconf->BroadcastFramesReception | + macconf->BroadcastFramesReception | macconf->DestinationAddrFilter | macconf->PromiscuousMode | macconf->MulticastFramesFilter | macconf->UnicastFramesFilter); - + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACFFR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACFFR = tmpreg1; - + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ /* Write to ETHERNET MACHTHR */ (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh; - + /* Write to ETHERNET MACHTLR */ (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow; /*----------------------- ETHERNET MACFCR Configuration --------------------*/ - - /* Get the ETHERNET MACFCR value */ + + /* Get the ETHERNET MACFCR value */ tmpreg1 = (heth->Instance)->MACFCR; /* Clear xx bits */ tmpreg1 &= ETH_MACFCR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | + + tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | macconf->ZeroQuantaPause | macconf->PauseLowThreshold | - macconf->UnicastPauseFrameDetect | + macconf->UnicastPauseFrameDetect | macconf->ReceiveFlowControl | - macconf->TransmitFlowControl); - + macconf->TransmitFlowControl); + /* Write to ETHERNET MACFCR */ (heth->Instance)->MACFCR = (uint32_t)tmpreg1; - + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACFCR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACFCR = tmpreg1; - + /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ - (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | + (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | macconf->VLANTagIdentifier); - + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACVLANTR; @@ -1419,37 +1419,37 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ tmpreg1 = (heth->Instance)->MACCR; - + /* Clear FES and DM bits */ tmpreg1 &= ~(0x00004800U); - + tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); - + /* Write to ETHERNET MACCR */ (heth->Instance)->MACCR = (uint32_t)tmpreg1; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACCR = tmpreg1; } - + /* Set the ETH state to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ - return HAL_OK; + return HAL_OK; } /** * @brief Sets ETH DMA Configuration. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param dmaconf: DMA Configuration structure + * @param dmaconf: DMA Configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) @@ -1458,7 +1458,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State= HAL_ETH_STATE_BUSY; @@ -1478,17 +1478,17 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength)); assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength)); assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration)); - + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ /* Get the ETHERNET DMAOMR value */ tmpreg1 = (heth->Instance)->DMAOMR; /* Clear xx bits */ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; - tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | + tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | dmaconf->ReceiveStoreForward | dmaconf->FlushReceivedFrame | - dmaconf->TransmitStoreForward | + dmaconf->TransmitStoreForward | dmaconf->TransmitThresholdControl | dmaconf->ForwardErrorFrames | dmaconf->ForwardUndersizedGoodFrames | @@ -1505,12 +1505,12 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef (heth->Instance)->DMAOMR = tmpreg1; /*----------------------- ETHERNET DMABMR Configuration --------------------*/ - (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | + (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | dmaconf->FixedBurst | dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ dmaconf->TxDMABurstLength | (dmaconf->DescriptorSkipLength << 2U) | - dmaconf->DMAArbitration | + dmaconf->DMAArbitration | ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ /* Wait until the write operation will be taken into account: @@ -1521,31 +1521,31 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef /* Set the ETH state to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ - return HAL_OK; + return HAL_OK; } /** * @} */ -/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions * - @verbatim + @verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. (+) Get the ETH handle state: HAL_ETH_GetState(); - + @endverbatim * @{ @@ -1558,7 +1558,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef * @retval HAL state */ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) -{ +{ /* Return ETH state */ return heth->State; } @@ -1566,11 +1566,11 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) /** * @} */ - + /** * @} */ - + /** @addtogroup ETH_Private_Functions * @{ */ @@ -1587,16 +1587,16 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) ETH_MACInitTypeDef macinit; ETH_DMAInitTypeDef dmainit; uint32_t tmpreg1 = 0U; - + if (err != ETH_SUCCESS) /* Auto-negotiation failed */ { /* Set Ethernet duplex mode to Full-duplex */ (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; - + /* Set Ethernet speed to 100M */ (heth->Init).Speed = ETH_SPEED_100M; } - + /* Ethernet MAC default initialization **************************************/ macinit.Watchdog = ETH_WATCHDOG_ENABLE; macinit.Jabber = ETH_JABBER_ENABLE; @@ -1622,7 +1622,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; - macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; + macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_HASHTABLE; macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; macinit.HashTableHigh = 0x0U; macinit.HashTableLow = 0x0U; @@ -1634,7 +1634,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; macinit.VLANTagIdentifier = 0x0U; - + /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ tmpreg1 = (heth->Instance)->MACCR; @@ -1644,39 +1644,39 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the JD: bit according to ETH Jabber value */ /* Set the IFG bit according to ETH InterFrameGap value */ /* Set the DCRS bit according to ETH CarrierSense value */ - /* Set the FES bit according to ETH Speed value */ - /* Set the DO bit according to ETH ReceiveOwn value */ + /* Set the FES bit according to ETH Speed value */ + /* Set the DO bit according to ETH ReceiveOwn value */ /* Set the LM bit according to ETH LoopbackMode value */ - /* Set the DM bit according to ETH Mode value */ + /* Set the DM bit according to ETH Mode value */ /* Set the IPCO bit according to ETH ChecksumOffload value */ /* Set the DR bit according to ETH RetryTransmission value */ /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ /* Set the BL bit according to ETH BackOffLimit value */ /* Set the DC bit according to ETH DeferralCheck value */ - tmpreg1 |= (uint32_t)(macinit.Watchdog | - macinit.Jabber | + tmpreg1 |= (uint32_t)(macinit.Watchdog | + macinit.Jabber | macinit.InterFrameGap | macinit.CarrierSense | - (heth->Init).Speed | + (heth->Init).Speed | macinit.ReceiveOwn | macinit.LoopbackMode | - (heth->Init).DuplexMode | - macinit.ChecksumOffload | - macinit.RetryTransmission | - macinit.AutomaticPadCRCStrip | - macinit.BackOffLimit | + (heth->Init).DuplexMode | + macinit.ChecksumOffload | + macinit.RetryTransmission | + macinit.AutomaticPadCRCStrip | + macinit.BackOffLimit | macinit.DeferralCheck); - + /* Write to ETHERNET MACCR */ (heth->Instance)->MACCR = (uint32_t)tmpreg1; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + (heth->Instance)->MACCR = tmpreg1; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ /* Set the RA bit according to ETH ReceiveAll value */ /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ /* Set the PCF bit according to ETH PassControlFrames value */ @@ -1685,74 +1685,74 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the PR bit according to ETH PromiscuousMode value */ /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | + /* Write to ETHERNET MACFFR */ + (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | macinit.SourceAddrFilter | macinit.PassControlFrames | - macinit.BroadcastFramesReception | + macinit.BroadcastFramesReception | macinit.DestinationAddrFilter | macinit.PromiscuousMode | macinit.MulticastFramesFilter | macinit.UnicastFramesFilter); - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACFFR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACFFR = tmpreg1; - + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ /* Write to ETHERNET MACHTHR */ (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh; - + /* Write to ETHERNET MACHTLR */ (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow; /*----------------------- ETHERNET MACFCR Configuration -------------------*/ - - /* Get the ETHERNET MACFCR value */ + + /* Get the ETHERNET MACFCR value */ tmpreg1 = (heth->Instance)->MACFCR; /* Clear xx bits */ tmpreg1 &= ETH_MACFCR_CLEAR_MASK; - + /* Set the PT bit according to ETH PauseTime value */ /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ /* Set the PLT bit according to ETH PauseLowThreshold value */ /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ /* Set the RFE bit according to ETH ReceiveFlowControl value */ - /* Set the TFE bit according to ETH TransmitFlowControl value */ - tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) | + /* Set the TFE bit according to ETH TransmitFlowControl value */ + tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) | macinit.ZeroQuantaPause | macinit.PauseLowThreshold | - macinit.UnicastPauseFrameDetect | + macinit.UnicastPauseFrameDetect | macinit.ReceiveFlowControl | - macinit.TransmitFlowControl); - + macinit.TransmitFlowControl); + /* Write to ETHERNET MACFCR */ (heth->Instance)->MACFCR = (uint32_t)tmpreg1; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACFCR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACFCR = tmpreg1; - + /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ /* Set the ETV bit according to ETH VLANTagComparison value */ - /* Set the VL bit according to ETH VLANTagIdentifier value */ - (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | + /* Set the VL bit according to ETH VLANTagIdentifier value */ + (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | macinit.VLANTagIdentifier); - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACVLANTR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACVLANTR = tmpreg1; - + /* Ethernet DMA default initialization ************************************/ dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; - dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; + dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; @@ -1764,12 +1764,12 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; dmainit.DescriptorSkipLength = 0x0U; dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; - + /* Get the ETHERNET DMAOMR value */ tmpreg1 = (heth->Instance)->DMAOMR; /* Clear xx bits */ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; - + /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ /* Set the RSF bit according to ETH ReceiveStoreForward value */ /* Set the DFF bit according to ETH FlushReceivedFrame value */ @@ -1779,25 +1779,25 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ /* Set the RTC bit according to ETH ReceiveThresholdControl value */ /* Set the OSF bit according to ETH SecondFrameOperate value */ - tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | + tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | dmainit.ReceiveStoreForward | dmainit.FlushReceivedFrame | - dmainit.TransmitStoreForward | + dmainit.TransmitStoreForward | dmainit.TransmitThresholdControl | dmainit.ForwardErrorFrames | dmainit.ForwardUndersizedGoodFrames | dmainit.ReceiveThresholdControl | dmainit.SecondFrameOperate); - + /* Write to ETHERNET DMAOMR */ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->DMAOMR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->DMAOMR = tmpreg1; - + /*----------------------- ETHERNET DMABMR Configuration ------------------*/ /* Set the AAL bit according to ETH AddressAlignedBeats value */ /* Set the FB bit according to ETH FixedBurst value */ @@ -1805,14 +1805,14 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */ /* Set the DSL bit according to ETH DesciptorSkipLength value */ /* Set the PR and DA bits according to ETH DMAArbitration value */ - (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | + (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | dmainit.FixedBurst | dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ dmainit.TxDMABurstLength | (dmainit.DescriptorSkipLength << 2U) | dmainit.DMAArbitration | ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->DMABMR; @@ -1825,7 +1825,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R); } - /* Initialize MAC address in ethernet MAC */ + /* Initialize MAC address in ethernet MAC */ ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); } @@ -1835,8 +1835,8 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) * the configuration information for ETHERNET module * @param MacAddr: The MAC address to configure * This parameter can be one of the following values: - * @arg ETH_MAC_Address0: MAC Address0 - * @arg ETH_MAC_Address1: MAC Address1 + * @arg ETH_MAC_Address0: MAC Address0 + * @arg ETH_MAC_Address1: MAC Address1 * @arg ETH_MAC_Address2: MAC Address2 * @arg ETH_MAC_Address3: MAC Address3 * @param Addr: Pointer to MAC address buffer data (6 bytes) @@ -1845,20 +1845,20 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) { uint32_t tmpreg1; - + /* Prevent unused argument(s) compilation warning */ UNUSED(heth); /* Check the parameters */ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - + /* Calculate the selected MAC address high register */ tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; /* Load the selected MAC address high register */ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; /* Calculate the selected MAC address low register */ tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U]; - + /* Load the selected MAC address low register */ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; } @@ -1866,16 +1866,16 @@ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint /** * @brief Enables the MAC transmission. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) -{ +{ __IO uint32_t tmpreg1 = 0U; - + /* Enable the MAC transmission */ (heth->Instance)->MACCR |= ETH_MACCR_TE; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; @@ -1886,16 +1886,16 @@ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the MAC transmission. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) -{ +{ __IO uint32_t tmpreg1 = 0U; - + /* Disable the MAC transmission */ (heth->Instance)->MACCR &= ~ETH_MACCR_TE; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; @@ -1906,16 +1906,16 @@ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the MAC reception. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) -{ +{ __IO uint32_t tmpreg1 = 0U; - + /* Enable the MAC reception */ (heth->Instance)->MACCR |= ETH_MACCR_RE; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; @@ -1926,16 +1926,16 @@ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the MAC reception. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) -{ +{ __IO uint32_t tmpreg1 = 0U; - + /* Disable the MAC reception */ - (heth->Instance)->MACCR &= ~ETH_MACCR_RE; - + (heth->Instance)->MACCR &= ~ETH_MACCR_RE; + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; @@ -1946,23 +1946,23 @@ static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the DMA transmission. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) { /* Enable the DMA transmission */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; + (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; } /** * @brief Disables the DMA transmission. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) -{ +{ /* Disable the DMA transmission */ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST; } @@ -1970,23 +1970,23 @@ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the DMA reception. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) -{ +{ /* Enable the DMA reception */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; + (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; } /** * @brief Disables the DMA reception. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) -{ +{ /* Disable the DMA reception */ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR; } @@ -2000,10 +2000,10 @@ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) { __IO uint32_t tmpreg1 = 0U; - + /* Set the Flush Transmit FIFO bit */ (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->DMAOMR; @@ -2019,10 +2019,10 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) static void ETH_Delay(uint32_t mdelay) { __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); - do + do { __NOP(); - } + } while (Delay --); } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c index 7bbe81dba4..9b36894c87 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c @@ -3,11 +3,11 @@ * @file stm32f4xx_hal_eth.c * @author MCD Application Team * @brief ETH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State and Errors functions * @verbatim @@ -17,21 +17,21 @@ [..] (#)Declare a ETH_HandleTypeDef handle structure, for example: ETH_HandleTypeDef heth; - + (#)Fill parameters of Init structure in heth handle - - (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) + + (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: - (##) Enable the Ethernet interface clock using + (##) Enable the Ethernet interface clock using (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); - + (##) Initialize the related GPIO clocks (##) Configure Ethernet pin-out - (##) Configure Ethernet NVIC interrupt (IT mode) - + (##) Configure Ethernet NVIC interrupt (IT mode) + (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: (##) HAL_ETH_DMATxDescListInit(); for Transmission process (##) HAL_ETH_DMARxDescListInit(); for Reception process @@ -39,11 +39,11 @@ (#)Enable MAC and DMA transmission and reception: (##) HAL_ETH_Start(); - (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer + (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer the frame to MAC TX FIFO: (##) HAL_ETH_TransmitFrame(); - (#)Poll for a received frame in ETH RX DMA Descriptors and get received + (#)Poll for a received frame in ETH RX DMA Descriptors and get received frame parameters (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) @@ -51,18 +51,18 @@ (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) (#) Communicate with external PHY device: - (##) Read a specific register from the PHY + (##) Read a specific register from the PHY HAL_ETH_ReadPHYRegister(); (##) Write data to a specific RHY register: HAL_ETH_WritePHYRegister(); (#) Configure the Ethernet MAC after ETH peripheral initialization HAL_ETH_ConfigMAC(); all MAC parameters should be filled. - + (#) Configure the Ethernet DMA after ETH peripheral initialization HAL_ETH_ConfigDMA(); all DMA parameters should be filled. - - -@- The PTP protocol and the DMA descriptors ring mode are not supported + + -@- The PTP protocol and the DMA descriptors ring mode are not supported in this driver @endverbatim @@ -94,7 +94,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -103,7 +103,7 @@ * @{ */ -/** @defgroup ETH ETH +/** @defgroup ETH ETH * @brief ETH HAL module driver * @{ */ @@ -118,7 +118,7 @@ /** @defgroup ETH_Private_Constants ETH Private Constants * @{ */ -#define ETH_TIMEOUT_SWRESET 500U +#define ETH_TIMEOUT_SWRESET 500U #define ETH_TIMEOUT_LINKED_STATE 5000U #define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U @@ -153,10 +153,10 @@ static void ETH_Delay(uint32_t mdelay); * @{ */ -/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== @@ -181,19 +181,19 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) uint32_t hclk = 60000000U; uint32_t tickstart = 0U; uint32_t err = ETH_SUCCESS; - + /* Check the ETH peripheral state */ if(heth == NULL) { return HAL_ERROR; } - + /* Check parameters */ assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation)); assert_param(IS_ETH_RX_MODE(heth->Init.RxMode)); assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode)); - assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); - + assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); + if(heth->State == HAL_ETH_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -201,48 +201,48 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) /* Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspInit(heth); } - + /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - + /* Select MII or RMII Mode*/ SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; - + /* Ethernet Software reset */ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ /* After reset all the registers holds their respective reset values */ (heth->Instance)->DMABMR |= ETH_DMABMR_SR; - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait for software reset */ while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET) - { + { heth->State= HAL_ETH_STATE_TIMEOUT; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - - /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are + + /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are not available, please check your external PHY or the IO configuration */ return HAL_TIMEOUT; } } - + /*-------------------------------- MAC Initialization ----------------------*/ /* Get the ETHERNET MACMIIAR value */ tmpreg1 = (heth->Instance)->MACMIIAR; /* Clear CSR Clock Range CR[2:0] bits */ tmpreg1 &= ETH_MACMIIAR_CR_MASK; - + /* Get hclk frequency value */ hclk = HAL_RCC_GetHCLKFreq(); - + /* Set CR bits depending on hclk value */ if((hclk >= 20000000U)&&(hclk < 35000000U)) { @@ -251,156 +251,156 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) } else if((hclk >= 35000000U)&&(hclk < 60000000U)) { - /* CSR Clock Range between 35-60 MHz */ + /* CSR Clock Range between 35-60 MHz */ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26; - } + } else if((hclk >= 60000000U)&&(hclk < 100000000U)) { - /* CSR Clock Range between 60-100 MHz */ + /* CSR Clock Range between 60-100 MHz */ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42; - } + } else if((hclk >= 100000000U)&&(hclk < 150000000U)) { - /* CSR Clock Range between 100-150 MHz */ + /* CSR Clock Range between 100-150 MHz */ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62; } else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */ { - /* CSR Clock Range between 150-183 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102; + /* CSR Clock Range between 150-183 MHz */ + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102; } - + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1; - + /*-------------------- PHY initialization and configuration ----------------*/ /* Put the PHY in reset mode */ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set the ETH peripheral state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return HAL_ERROR */ return HAL_ERROR; } - + /* Delay to assure PHY reset */ HAL_Delay(PHY_RESET_DELAY); - + if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE) { /* Get tick */ tickstart = HAL_GetTick(); - + /* We wait for linked status */ do { HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - + /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_TIMEOUT; } } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS)); - + /* Enable Auto-Negotiation */ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set the ETH peripheral state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return HAL_ERROR */ - return HAL_ERROR; + return HAL_ERROR; } - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait until the auto-negotiation will be completed */ do { HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - + /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_TIMEOUT; } - + } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE)); - + /* Read the result of the auto-negotiation */ if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set the ETH peripheral state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return HAL_ERROR */ - return HAL_ERROR; + return HAL_ERROR; } - + /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */ if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET) { /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; + (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; } else { /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; + (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; } /* Configure the MAC with the speed fixed by the auto-negotiation process */ if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS) - { + { /* Set Ethernet speed to 10M following the auto-negotiation */ - (heth->Init).Speed = ETH_SPEED_10M; + (heth->Init).Speed = ETH_SPEED_10M; } else - { - /* Set Ethernet speed to 100M following the auto-negotiation */ + { + /* Set Ethernet speed to 100M following the auto-negotiation */ (heth->Init).Speed = ETH_SPEED_100M; } } @@ -409,40 +409,40 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) /* Check parameters */ assert_param(IS_ETH_SPEED(heth->Init.Speed)); assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - + /* Set MAC Speed and Duplex Mode */ if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) | (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set the ETH peripheral state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return HAL_ERROR */ return HAL_ERROR; - } - + } + /* Delay to assure PHY configuration */ HAL_Delay(PHY_CONFIG_DELAY); } - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set ETH HAL State to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Return function status */ return HAL_OK; } /** - * @brief De-Initializes the ETH peripheral. + * @brief De-Initializes the ETH peripheral. * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status @@ -451,10 +451,10 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) { /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspDeInit(heth); - + /* Set ETH HAL state to Disabled */ heth->State= HAL_ETH_STATE_RESET; @@ -468,8 +468,8 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) /** * @brief Initializes the DMA Tx descriptors in chain mode. * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMATxDescTab Pointer to the first Tx desc list + * the configuration information for ETHERNET module + * @param DMATxDescTab Pointer to the first Tx desc list * @param TxBuff Pointer to the first TxBuffer list * @param TxBuffCount Number of the used Tx desc in the list * @retval HAL status @@ -478,34 +478,34 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc { uint32_t i = 0U; ETH_DMADescTypeDef *dmatxdesc; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ heth->TxDesc = DMATxDescTab; - - /* Fill each DMATxDesc descriptor with the right values */ + + /* Fill each DMATxDesc descriptor with the right values */ for(i=0U; i < TxBuffCount; i++) { /* Get the pointer on the ith member of the Tx Desc list */ dmatxdesc = DMATxDescTab + i; - + /* Set Second Address Chained bit */ - dmatxdesc->Status = ETH_DMATXDESC_TCH; - + dmatxdesc->Status = ETH_DMATXDESC_TCH; + /* Set Buffer1 address pointer */ dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]); - + if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { /* Set the DMA Tx descriptors checksum insertion */ dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; } - + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ if(i < (TxBuffCount-1U)) { @@ -514,20 +514,20 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc } else { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; } } - + /* Set Transmit Descriptor List Address Register */ (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab; - + /* Set ETH HAL State to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -535,8 +535,8 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc /** * @brief Initializes the DMA Rx descriptors in chain mode. * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMARxDescTab Pointer to the first Rx desc list + * the configuration information for ETHERNET module + * @param DMARxDescTab Pointer to the first Rx desc list * @param RxBuff Pointer to the first RxBuffer list * @param RxBuffCount Number of the used Rx desc in the list * @retval HAL status @@ -545,59 +545,59 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc { uint32_t i = 0U; ETH_DMADescTypeDef *DMARxDesc; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */ - heth->RxDesc = DMARxDescTab; - + heth->RxDesc = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ for(i=0U; i < RxBuffCount; i++) { /* Get the pointer on the ith member of the Rx Desc list */ DMARxDesc = DMARxDescTab+i; - + /* Set Own bit of the Rx descriptor Status */ DMARxDesc->Status = ETH_DMARXDESC_OWN; - + /* Set Buffer1 size and Second Address Chained bit */ - DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; - + DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; + /* Set Buffer1 address pointer */ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]); - + if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) { /* Enable Ethernet DMA Rx Descriptor interrupt */ DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC; } - + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ if(i < (RxBuffCount-1U)) { /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U); + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U); } else { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); } } - + /* Set Receive Descriptor List Address Register */ (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab; - + /* Set ETH HAL State to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -636,13 +636,13 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) * @} */ -/** @defgroup ETH_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions +/** @defgroup ETH_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions * - @verbatim + @verbatim ============================================================================== ##### IO operation functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Transmit a frame HAL_ETH_TransmitFrame(); @@ -655,12 +655,12 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) HAL_ETH_WritePHYRegister(); @endverbatim - + * @{ */ /** - * @brief Sends an Ethernet frame. + * @brief Sends an Ethernet frame. * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @param FrameLength Amount of data to be sent @@ -669,47 +669,47 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) { uint32_t bufcount = 0U, size = 0U, i = 0U; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - - if (FrameLength == 0U) + + if (FrameLength == 0U) { /* Set ETH HAL state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - - return HAL_ERROR; - } - + + return HAL_ERROR; + } + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) - { + { /* OWN bit set */ heth->State = HAL_ETH_STATE_BUSY_TX; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_ERROR; } - + /* Get the number of needed Tx buffers for the current frame */ if (FrameLength > ETH_TX_BUF_SIZE) { bufcount = FrameLength/ETH_TX_BUF_SIZE; - if (FrameLength % ETH_TX_BUF_SIZE) + if (FrameLength % ETH_TX_BUF_SIZE) { bufcount++; } } - else - { + else + { bufcount = 1U; } if (bufcount == 1U) @@ -729,16 +729,16 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL { /* Clear FIRST and LAST segment bits */ heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); - - if (i == 0U) + + if (i == 0U) { /* Setting the first segment bit */ - heth->TxDesc->Status |= ETH_DMATXDESC_FS; + heth->TxDesc->Status |= ETH_DMATXDESC_FS; } - + /* Program size */ heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1); - + if (i == (bufcount-1U)) { /* Setting the last segment bit */ @@ -746,14 +746,14 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE; heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); } - + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ heth->TxDesc->Status |= ETH_DMATXDESC_OWN; /* point to next descriptor */ heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); } } - + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) { @@ -762,19 +762,19 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL /* Resume DMA transmission*/ (heth->Instance)->DMATPDR = 0U; } - + /* Set ETH HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } /** - * @brief Checks for received frames. + * @brief Checks for received frames. * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status @@ -782,46 +782,46 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) { uint32_t framelength = 0U; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Check the ETH state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Check if segment is not owned by DMA */ /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */ if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET)) { /* Check if last segment */ - if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) + if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) { /* increment segment count */ (heth->RxFrameInfos).SegCount++; - + /* Check if last segment is first segment: one segment contains the frame */ if ((heth->RxFrameInfos).SegCount == 1U) { (heth->RxFrameInfos).FSRxDesc =heth->RxDesc; } - + heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; heth->RxFrameInfos.length = framelength; - + /* Get the address of the buffer start address */ heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; /* point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr); - + /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -834,27 +834,27 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); } - /* Check if intermediate segment */ + /* Check if intermediate segment */ else { (heth->RxFrameInfos).SegCount++; /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } + } } - + /* Set ETH HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_ERROR; } /** - * @brief Gets the Received frame in interrupt mode. + * @brief Gets the Received frame in interrupt mode. * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status @@ -862,25 +862,25 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) { uint32_t descriptorscancounter = 0U; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set ETH HAL State to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Scan descriptors owned by CPU */ while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB)) { /* Just for security */ descriptorscancounter++; - + /* Check if first segment in frame */ - /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ + /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS) - { + { heth->RxFrameInfos.FSRxDesc = heth->RxDesc; - heth->RxFrameInfos.SegCount = 1U; + heth->RxFrameInfos.SegCount = 1U; /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); } @@ -895,34 +895,34 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) } /* Should be last segment */ else - { + { /* Last segment */ heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - + /* Increment segment count */ (heth->RxFrameInfos.SegCount)++; - + /* Check if last segment is first segment: one segment contains the frame */ if ((heth->RxFrameInfos.SegCount) == 1U) { heth->RxFrameInfos.FSRxDesc = heth->RxDesc; } - + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; - - /* Get the address of the buffer start address */ + + /* Get the address of the buffer start address */ heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; - - /* Point to next descriptor */ + + /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - + /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -930,10 +930,10 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_ERROR; } @@ -947,40 +947,40 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) { /* Frame received */ - if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) + if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) { /* Receive complete callback */ HAL_ETH_RxCpltCallback(heth); - + /* Clear the Eth DMA Rx IT pending bits */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R); /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); } /* Frame transmitted */ - else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) + else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) { /* Transfer complete callback */ HAL_ETH_TxCpltCallback(heth); - + /* Clear the Eth DMA Tx IT pending bits */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T); /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); } - + /* Clear the interrupt flags */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS); - + /* ETH DMA Error */ if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS)) { @@ -989,10 +989,10 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) /* Clear the interrupt flags */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS); - + /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); } @@ -1010,7 +1010,7 @@ __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) UNUSED(heth); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_TxCpltCallback could be implemented in the user file - */ + */ } /** @@ -1025,7 +1025,7 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) UNUSED(heth); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_TxCpltCallback could be implemented in the user file - */ + */ } /** @@ -1040,29 +1040,29 @@ __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) UNUSED(heth); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_TxCpltCallback could be implemented in the user file - */ + */ } /** * @brief Reads a PHY register * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Basic Control Register, - * PHY_BSR: Transceiver Basic Status Register. + * the configuration information for ETHERNET module + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Basic Control Register, + * PHY_BSR: Transceiver Basic Status Register. * More PHY register could be read depending on the used PHY - * @param RegValue PHY register value + * @param RegValue PHY register value * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) { - uint32_t tmpreg1 = 0U; + uint32_t tmpreg1 = 0U; uint32_t tickstart = 0U; - + /* Check parameters */ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - + /* Check the ETH peripheral state */ if(heth->State == HAL_ETH_STATE_BUSY_RD) { @@ -1070,25 +1070,25 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR } /* Set ETH HAL State to BUSY_RD */ heth->State = HAL_ETH_STATE_BUSY_RD; - + /* Get the ETHERNET MACMIIAR value */ tmpreg1 = heth->Instance->MACMIIAR; - + /* Keep only the CSR Clock Range CR[2:0] bits value */ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; - + /* Prepare the MII address register value */ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - + /* Write the result value into the MII Address register */ heth->Instance->MACMIIAR = tmpreg1; - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Check for the Busy flag */ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) { @@ -1096,22 +1096,22 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR if((HAL_GetTick() - tickstart ) > PHY_READ_TO) { heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_TIMEOUT; } - + tmpreg1 = heth->Instance->MACMIIAR; } - + /* Get MACMIIDR value */ *RegValue = (uint16_t)(heth->Instance->MACMIIDR); - + /* Set ETH HAL State to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1119,10 +1119,10 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR /** * @brief Writes to a PHY register. * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Control Register. + * the configuration information for ETHERNET module + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Control Register. * More PHY register could be written depending on the used PHY * @param RegValue the value to write * @retval HAL status @@ -1131,10 +1131,10 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY { uint32_t tmpreg1 = 0U; uint32_t tickstart = 0U; - + /* Check parameters */ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - + /* Check the ETH peripheral state */ if(heth->State == HAL_ETH_STATE_BUSY_WR) { @@ -1142,28 +1142,28 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY } /* Set ETH HAL State to BUSY_WR */ heth->State = HAL_ETH_STATE_BUSY_WR; - + /* Get the ETHERNET MACMIIAR value */ tmpreg1 = heth->Instance->MACMIIAR; - + /* Keep only the CSR Clock Range CR[2:0] bits value */ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; - + /* Prepare the MII register address value */ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - + /* Give the value to the MII data register */ heth->Instance->MACMIIDR = (uint16_t)RegValue; - + /* Write the result value into the MII Address register */ heth->Instance->MACMIIAR = tmpreg1; - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Check for the Busy flag */ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) { @@ -1171,21 +1171,21 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO) { heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_TIMEOUT; } - + tmpreg1 = heth->Instance->MACMIIAR; } - + /* Set ETH HAL State to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return function status */ - return HAL_OK; + return HAL_OK; } /** @@ -1193,16 +1193,16 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY */ /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Enable MAC and DMA transmission and reception. HAL_ETH_Start(); - (+) Disable MAC and DMA transmission and reception. + (+) Disable MAC and DMA transmission and reception. HAL_ETH_Stop(); (+) Set the MAC configuration in runtime mode HAL_ETH_ConfigMAC(); @@ -1211,82 +1211,82 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY @endverbatim * @{ - */ + */ /** - * @brief Enables Ethernet MAC and DMA reception/transmission + * @brief Enables Ethernet MAC and DMA reception/transmission * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) -{ +{ /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Enable transmit state machine of the MAC for transmission on the MII */ ETH_MACTransmissionEnable(heth); - + /* Enable receive state machine of the MAC for reception from the MII */ ETH_MACReceptionEnable(heth); - + /* Flush Transmit FIFO */ ETH_FlushTransmitFIFO(heth); - + /* Start DMA transmission */ ETH_DMATransmissionEnable(heth); - + /* Start DMA reception */ ETH_DMAReceptionEnable(heth); - + /* Set the ETH state to READY*/ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } /** - * @brief Stop Ethernet MAC and DMA reception/transmission + * @brief Stop Ethernet MAC and DMA reception/transmission * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) -{ +{ /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Stop DMA transmission */ ETH_DMATransmissionDisable(heth); - + /* Stop DMA reception */ ETH_DMAReceptionDisable(heth); - + /* Disable receive state machine of the MAC for reception from the MII */ ETH_MACReceptionDisable(heth); - + /* Flush Transmit FIFO */ ETH_FlushTransmitFIFO(heth); - + /* Disable transmit state machine of the MAC for transmission on the MII */ ETH_MACTransmissionDisable(heth); - + /* Set the ETH state*/ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -1295,22 +1295,22 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) * @brief Set ETH MAC Configuration. * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param macconf MAC Configuration structure + * @param macconf MAC Configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) { uint32_t tmpreg1 = 0U; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State= HAL_ETH_STATE_BUSY; - + assert_param(IS_ETH_SPEED(heth->Init.Speed)); - assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - + assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); + if (macconf != NULL) { /* Check the parameters */ @@ -1341,86 +1341,86 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl)); assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison)); assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier)); - + /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ tmpreg1 = (heth->Instance)->MACCR; /* Clear WD, PCE, PS, TE and RE bits */ tmpreg1 &= ETH_MACCR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)(macconf->Watchdog | - macconf->Jabber | + + tmpreg1 |= (uint32_t)(macconf->Watchdog | + macconf->Jabber | macconf->InterFrameGap | macconf->CarrierSense | - (heth->Init).Speed | + (heth->Init).Speed | macconf->ReceiveOwn | macconf->LoopbackMode | - (heth->Init).DuplexMode | - macconf->ChecksumOffload | - macconf->RetryTransmission | - macconf->AutomaticPadCRCStrip | - macconf->BackOffLimit | + (heth->Init).DuplexMode | + macconf->ChecksumOffload | + macconf->RetryTransmission | + macconf->AutomaticPadCRCStrip | + macconf->BackOffLimit | macconf->DeferralCheck); - + /* Write to ETHERNET MACCR */ (heth->Instance)->MACCR = (uint32_t)tmpreg1; - + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | + (heth->Instance)->MACCR = tmpreg1; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Write to ETHERNET MACFFR */ + (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | macconf->SourceAddrFilter | macconf->PassControlFrames | - macconf->BroadcastFramesReception | + macconf->BroadcastFramesReception | macconf->DestinationAddrFilter | macconf->PromiscuousMode | macconf->MulticastFramesFilter | macconf->UnicastFramesFilter); - + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACFFR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACFFR = tmpreg1; - + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ /* Write to ETHERNET MACHTHR */ (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh; - + /* Write to ETHERNET MACHTLR */ (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow; /*----------------------- ETHERNET MACFCR Configuration --------------------*/ - - /* Get the ETHERNET MACFCR value */ + + /* Get the ETHERNET MACFCR value */ tmpreg1 = (heth->Instance)->MACFCR; /* Clear xx bits */ tmpreg1 &= ETH_MACFCR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | + + tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | macconf->ZeroQuantaPause | macconf->PauseLowThreshold | - macconf->UnicastPauseFrameDetect | + macconf->UnicastPauseFrameDetect | macconf->ReceiveFlowControl | - macconf->TransmitFlowControl); - + macconf->TransmitFlowControl); + /* Write to ETHERNET MACFCR */ (heth->Instance)->MACFCR = (uint32_t)tmpreg1; - + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACFCR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACFCR = tmpreg1; - + /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ - (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | + (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | macconf->VLANTagIdentifier); - + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACVLANTR; @@ -1432,37 +1432,37 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ tmpreg1 = (heth->Instance)->MACCR; - + /* Clear FES and DM bits */ tmpreg1 &= ~(0x00004800U); - - tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); - + + tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode ); + /* Write to ETHERNET MACCR */ (heth->Instance)->MACCR = (uint32_t)tmpreg1; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACCR = tmpreg1; } - + /* Set the ETH state to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ - return HAL_OK; + return HAL_OK; } /** * @brief Sets ETH DMA Configuration. * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param dmaconf DMA Configuration structure + * @param dmaconf DMA Configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) @@ -1471,7 +1471,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State= HAL_ETH_STATE_BUSY; @@ -1492,17 +1492,17 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat)); assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength)); assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration)); - + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ /* Get the ETHERNET DMAOMR value */ tmpreg1 = (heth->Instance)->DMAOMR; /* Clear xx bits */ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; - tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | + tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | dmaconf->ReceiveStoreForward | dmaconf->FlushReceivedFrame | - dmaconf->TransmitStoreForward | + dmaconf->TransmitStoreForward | dmaconf->TransmitThresholdControl | dmaconf->ForwardErrorFrames | dmaconf->ForwardUndersizedGoodFrames | @@ -1519,13 +1519,13 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef (heth->Instance)->DMAOMR = tmpreg1; /*----------------------- ETHERNET DMABMR Configuration --------------------*/ - (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | + (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | dmaconf->FixedBurst | dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ dmaconf->TxDMABurstLength | dmaconf->EnhancedDescriptorFormat | (dmaconf->DescriptorSkipLength << 2U) | - dmaconf->DMAArbitration | + dmaconf->DMAArbitration | ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ /* Wait until the write operation will be taken into account: @@ -1536,31 +1536,31 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef /* Set the ETH state to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ - return HAL_OK; + return HAL_OK; } /** * @} */ -/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions * - @verbatim + @verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. (+) Get the ETH handle state: HAL_ETH_GetState(); - + @endverbatim * @{ @@ -1573,7 +1573,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef * @retval HAL state */ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) -{ +{ /* Return ETH state */ return heth->State; } @@ -1581,11 +1581,11 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) /** * @} */ - + /** * @} */ - + /** @addtogroup ETH_Private_Functions * @{ */ @@ -1602,16 +1602,16 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) ETH_MACInitTypeDef macinit; ETH_DMAInitTypeDef dmainit; uint32_t tmpreg1 = 0U; - + if (err != ETH_SUCCESS) /* Auto-negotiation failed */ { /* Set Ethernet duplex mode to Full-duplex */ (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; - + /* Set Ethernet speed to 100M */ (heth->Init).Speed = ETH_SPEED_100M; } - + /* Ethernet MAC default initialization **************************************/ macinit.Watchdog = ETH_WATCHDOG_ENABLE; macinit.Jabber = ETH_JABBER_ENABLE; @@ -1632,12 +1632,13 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) macinit.BackOffLimit = ETH_BACKOFFLIMIT_10; macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE; macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE; + // macinit.ReceiveAll = ETH_RECEIVEALL_ENABLE; macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; - macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; + macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_HASHTABLE; macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; macinit.HashTableHigh = 0x0U; macinit.HashTableLow = 0x0U; @@ -1649,7 +1650,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; macinit.VLANTagIdentifier = 0x0U; - + /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ tmpreg1 = (heth->Instance)->MACCR; @@ -1659,39 +1660,39 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the JD: bit according to ETH Jabber value */ /* Set the IFG bit according to ETH InterFrameGap value */ /* Set the DCRS bit according to ETH CarrierSense value */ - /* Set the FES bit according to ETH Speed value */ - /* Set the DO bit according to ETH ReceiveOwn value */ + /* Set the FES bit according to ETH Speed value */ + /* Set the DO bit according to ETH ReceiveOwn value */ /* Set the LM bit according to ETH LoopbackMode value */ - /* Set the DM bit according to ETH Mode value */ + /* Set the DM bit according to ETH Mode value */ /* Set the IPCO bit according to ETH ChecksumOffload value */ /* Set the DR bit according to ETH RetryTransmission value */ /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ /* Set the BL bit according to ETH BackOffLimit value */ /* Set the DC bit according to ETH DeferralCheck value */ - tmpreg1 |= (uint32_t)(macinit.Watchdog | - macinit.Jabber | + tmpreg1 |= (uint32_t)(macinit.Watchdog | + macinit.Jabber | macinit.InterFrameGap | macinit.CarrierSense | - (heth->Init).Speed | + (heth->Init).Speed | macinit.ReceiveOwn | macinit.LoopbackMode | - (heth->Init).DuplexMode | - macinit.ChecksumOffload | - macinit.RetryTransmission | - macinit.AutomaticPadCRCStrip | - macinit.BackOffLimit | + (heth->Init).DuplexMode | + macinit.ChecksumOffload | + macinit.RetryTransmission | + macinit.AutomaticPadCRCStrip | + macinit.BackOffLimit | macinit.DeferralCheck); - + /* Write to ETHERNET MACCR */ (heth->Instance)->MACCR = (uint32_t)tmpreg1; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + (heth->Instance)->MACCR = tmpreg1; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ /* Set the RA bit according to ETH ReceiveAll value */ /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ /* Set the PCF bit according to ETH PassControlFrames value */ @@ -1700,74 +1701,74 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the PR bit according to ETH PromiscuousMode value */ /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | + /* Write to ETHERNET MACFFR */ + (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | macinit.SourceAddrFilter | macinit.PassControlFrames | - macinit.BroadcastFramesReception | + macinit.BroadcastFramesReception | macinit.DestinationAddrFilter | macinit.PromiscuousMode | macinit.MulticastFramesFilter | macinit.UnicastFramesFilter); - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACFFR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACFFR = tmpreg1; - + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ /* Write to ETHERNET MACHTHR */ (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh; - + /* Write to ETHERNET MACHTLR */ (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow; /*----------------------- ETHERNET MACFCR Configuration -------------------*/ - - /* Get the ETHERNET MACFCR value */ + + /* Get the ETHERNET MACFCR value */ tmpreg1 = (heth->Instance)->MACFCR; /* Clear xx bits */ tmpreg1 &= ETH_MACFCR_CLEAR_MASK; - + /* Set the PT bit according to ETH PauseTime value */ /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ /* Set the PLT bit according to ETH PauseLowThreshold value */ /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ /* Set the RFE bit according to ETH ReceiveFlowControl value */ - /* Set the TFE bit according to ETH TransmitFlowControl value */ - tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) | + /* Set the TFE bit according to ETH TransmitFlowControl value */ + tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) | macinit.ZeroQuantaPause | macinit.PauseLowThreshold | - macinit.UnicastPauseFrameDetect | + macinit.UnicastPauseFrameDetect | macinit.ReceiveFlowControl | - macinit.TransmitFlowControl); - + macinit.TransmitFlowControl); + /* Write to ETHERNET MACFCR */ (heth->Instance)->MACFCR = (uint32_t)tmpreg1; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACFCR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACFCR = tmpreg1; - + /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ /* Set the ETV bit according to ETH VLANTagComparison value */ - /* Set the VL bit according to ETH VLANTagIdentifier value */ - (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | + /* Set the VL bit according to ETH VLANTagIdentifier value */ + (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | macinit.VLANTagIdentifier); - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACVLANTR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACVLANTR = tmpreg1; - + /* Ethernet DMA default initialization ************************************/ dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; - dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; + dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; @@ -1780,12 +1781,12 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE; dmainit.DescriptorSkipLength = 0x0U; dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; - + /* Get the ETHERNET DMAOMR value */ tmpreg1 = (heth->Instance)->DMAOMR; /* Clear xx bits */ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; - + /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ /* Set the RSF bit according to ETH ReceiveStoreForward value */ /* Set the DFF bit according to ETH FlushReceivedFrame value */ @@ -1795,25 +1796,25 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ /* Set the RTC bit according to ETH ReceiveThresholdControl value */ /* Set the OSF bit according to ETH SecondFrameOperate value */ - tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | + tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | dmainit.ReceiveStoreForward | dmainit.FlushReceivedFrame | - dmainit.TransmitStoreForward | + dmainit.TransmitStoreForward | dmainit.TransmitThresholdControl | dmainit.ForwardErrorFrames | dmainit.ForwardUndersizedGoodFrames | dmainit.ReceiveThresholdControl | dmainit.SecondFrameOperate); - + /* Write to ETHERNET DMAOMR */ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->DMAOMR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->DMAOMR = tmpreg1; - + /*----------------------- ETHERNET DMABMR Configuration ------------------*/ /* Set the AAL bit according to ETH AddressAlignedBeats value */ /* Set the FB bit according to ETH FixedBurst value */ @@ -1822,7 +1823,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/ /* Set the DSL bit according to ETH DesciptorSkipLength value */ /* Set the PR and DA bits according to ETH DMAArbitration value */ - (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | + (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | dmainit.FixedBurst | dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ dmainit.TxDMABurstLength | @@ -1830,7 +1831,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) (dmainit.DescriptorSkipLength << 2U) | dmainit.DMAArbitration | ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->DMABMR; @@ -1843,7 +1844,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R); } - /* Initialize MAC address in ethernet MAC */ + /* Initialize MAC address in ethernet MAC */ ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); } @@ -1853,8 +1854,8 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) * the configuration information for ETHERNET module * @param MacAddr The MAC address to configure * This parameter can be one of the following values: - * @arg ETH_MAC_Address0: MAC Address0 - * @arg ETH_MAC_Address1: MAC Address1 + * @arg ETH_MAC_Address0: MAC Address0 + * @arg ETH_MAC_Address1: MAC Address1 * @arg ETH_MAC_Address2: MAC Address2 * @arg ETH_MAC_Address3: MAC Address3 * @param Addr Pointer to MAC address buffer data (6 bytes) @@ -1863,20 +1864,20 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) { uint32_t tmpreg1; - + /* Prevent unused argument(s) compilation warning */ UNUSED(heth); /* Check the parameters */ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - + /* Calculate the selected MAC address high register */ tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; /* Load the selected MAC address high register */ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; /* Calculate the selected MAC address low register */ tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U]; - + /* Load the selected MAC address low register */ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; } @@ -1884,16 +1885,16 @@ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint /** * @brief Enables the MAC transmission. * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) -{ +{ __IO uint32_t tmpreg1 = 0U; - + /* Enable the MAC transmission */ (heth->Instance)->MACCR |= ETH_MACCR_TE; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; @@ -1904,16 +1905,16 @@ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the MAC transmission. * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) -{ +{ __IO uint32_t tmpreg1 = 0U; - + /* Disable the MAC transmission */ (heth->Instance)->MACCR &= ~ETH_MACCR_TE; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; @@ -1924,16 +1925,16 @@ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the MAC reception. * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) -{ +{ __IO uint32_t tmpreg1 = 0U; - + /* Enable the MAC reception */ (heth->Instance)->MACCR |= ETH_MACCR_RE; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; @@ -1944,16 +1945,16 @@ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the MAC reception. * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) -{ +{ __IO uint32_t tmpreg1 = 0U; - + /* Disable the MAC reception */ - (heth->Instance)->MACCR &= ~ETH_MACCR_RE; - + (heth->Instance)->MACCR &= ~ETH_MACCR_RE; + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; @@ -1964,23 +1965,23 @@ static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the DMA transmission. * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) { /* Enable the DMA transmission */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; + (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; } /** * @brief Disables the DMA transmission. * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) -{ +{ /* Disable the DMA transmission */ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST; } @@ -1988,23 +1989,23 @@ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the DMA reception. * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) -{ +{ /* Enable the DMA reception */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; + (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; } /** * @brief Disables the DMA reception. * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) -{ +{ /* Disable the DMA reception */ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR; } @@ -2018,10 +2019,10 @@ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) { __IO uint32_t tmpreg1 = 0U; - + /* Set the Flush Transmit FIFO bit */ (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->DMAOMR; @@ -2037,10 +2038,10 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) static void ETH_Delay(uint32_t mdelay) { __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); - do + do { __NOP(); - } + } while (Delay --); } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c index fb8ffba829..ba7cfe1889 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c @@ -3,11 +3,11 @@ * @file stm32f7xx_hal_eth.c * @author MCD Application Team * @brief ETH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State and Errors functions * @verbatim @@ -17,21 +17,21 @@ [..] (#)Declare a ETH_HandleTypeDef handle structure, for example: ETH_HandleTypeDef heth; - + (#)Fill parameters of Init structure in heth handle - - (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) + + (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: - (##) Enable the Ethernet interface clock using + (##) Enable the Ethernet interface clock using (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); - + (##) Initialize the related GPIO clocks (##) Configure Ethernet pin-out - (##) Configure Ethernet NVIC interrupt (IT mode) - + (##) Configure Ethernet NVIC interrupt (IT mode) + (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: (##) HAL_ETH_DMATxDescListInit(); for Transmission process (##) HAL_ETH_DMARxDescListInit(); for Reception process @@ -39,11 +39,11 @@ (#)Enable MAC and DMA transmission and reception: (##) HAL_ETH_Start(); - (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer + (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer the frame to MAC TX FIFO: (##) HAL_ETH_TransmitFrame(); - (#)Poll for a received frame in ETH RX DMA Descriptors and get received + (#)Poll for a received frame in ETH RX DMA Descriptors and get received frame parameters (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) @@ -51,14 +51,14 @@ (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) (#) Communicate with external PHY device: - (##) Read a specific register from the PHY + (##) Read a specific register from the PHY HAL_ETH_ReadPHYRegister(); (##) Write data to a specific RHY register: HAL_ETH_WritePHYRegister(); (#) Configure the Ethernet MAC after ETH peripheral initialization HAL_ETH_ConfigMAC(); all MAC parameters should be filled. - + (#) Configure the Ethernet DMA after ETH peripheral initialization HAL_ETH_ConfigDMA(); all DMA parameters should be filled. @@ -91,7 +91,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -100,7 +100,7 @@ * @{ */ -/** @defgroup ETH ETH +/** @defgroup ETH ETH * @brief ETH HAL module driver * @{ */ @@ -113,9 +113,9 @@ /** @defgroup ETH_Private_Constants ETH Private Constants * @{ */ -#define ETH_TIMEOUT_SWRESET ((uint32_t)500) -#define ETH_TIMEOUT_LINKED_STATE ((uint32_t)5000) -#define ETH_TIMEOUT_AUTONEGO_COMPLETED ((uint32_t)5000) +#define ETH_TIMEOUT_SWRESET ((uint32_t)500) +#define ETH_TIMEOUT_LINKED_STATE ((uint32_t)5000) +#define ETH_TIMEOUT_AUTONEGO_COMPLETED ((uint32_t)5000) /** * @} @@ -147,10 +147,10 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); * @{ */ -/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== @@ -175,19 +175,19 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) uint32_t hclk = 60000000; uint32_t tickstart = 0; uint32_t err = ETH_SUCCESS; - + /* Check the ETH peripheral state */ if(heth == NULL) { return HAL_ERROR; } - + /* Check parameters */ assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation)); assert_param(IS_ETH_RX_MODE(heth->Init.RxMode)); assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode)); - assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); - + assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); + if(heth->State == HAL_ETH_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -195,49 +195,49 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) /* Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspInit(heth); } - + /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - + /* Select MII or RMII Mode*/ SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; - + /* Ethernet Software reset */ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ /* After reset all the registers holds their respective reset values */ (heth->Instance)->DMABMR |= ETH_DMABMR_SR; - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait for software reset */ while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET) - { + { heth->State= HAL_ETH_STATE_TIMEOUT; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - - /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are + + /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are not available, please check your external PHY or the IO configuration */ - + return HAL_TIMEOUT; } } - + /*-------------------------------- MAC Initialization ----------------------*/ /* Get the ETHERNET MACMIIAR value */ tempreg = (heth->Instance)->MACMIIAR; /* Clear CSR Clock Range CR[2:0] bits */ tempreg &= ETH_MACMIIAR_CR_MASK; - + /* Get hclk frequency value */ hclk = HAL_RCC_GetHCLKFreq(); - + /* Set CR bits depending on hclk value */ if((hclk >= 20000000)&&(hclk < 35000000)) { @@ -246,156 +246,156 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) } else if((hclk >= 35000000)&&(hclk < 60000000)) { - /* CSR Clock Range between 35-60 MHz */ + /* CSR Clock Range between 35-60 MHz */ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; - } + } else if((hclk >= 60000000)&&(hclk < 100000000)) { - /* CSR Clock Range between 60-100 MHz */ + /* CSR Clock Range between 60-100 MHz */ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; - } + } else if((hclk >= 100000000)&&(hclk < 150000000)) { - /* CSR Clock Range between 100-150 MHz */ + /* CSR Clock Range between 100-150 MHz */ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; } else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */ { - /* CSR Clock Range between 150-216 MHz */ - tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; + /* CSR Clock Range between 150-216 MHz */ + tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; } - + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ (heth->Instance)->MACMIIAR = (uint32_t)tempreg; - + /*-------------------- PHY initialization and configuration ----------------*/ /* Put the PHY in reset mode */ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set the ETH peripheral state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return HAL_ERROR */ return HAL_ERROR; } - + /* Delay to assure PHY reset */ HAL_Delay(PHY_RESET_DELAY); - + if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE) { /* Get tick */ tickstart = HAL_GetTick(); - + /* We wait for linked status */ do { HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - + /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_TIMEOUT; } } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS)); - + /* Enable Auto-Negotiation */ if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set the ETH peripheral state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return HAL_ERROR */ - return HAL_ERROR; + return HAL_ERROR; } - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait until the auto-negotiation will be completed */ do { HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - + /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_TIMEOUT; } - + } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE)); - + /* Read the result of the auto-negotiation */ if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set the ETH peripheral state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return HAL_ERROR */ - return HAL_ERROR; + return HAL_ERROR; } - + /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */ if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET) { /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; + (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; } else { /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; + (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; } /* Configure the MAC with the speed fixed by the auto-negotiation process */ if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS) - { + { /* Set Ethernet speed to 10M following the auto-negotiation */ - (heth->Init).Speed = ETH_SPEED_10M; + (heth->Init).Speed = ETH_SPEED_10M; } else - { - /* Set Ethernet speed to 100M following the auto-negotiation */ + { + /* Set Ethernet speed to 100M following the auto-negotiation */ (heth->Init).Speed = ETH_SPEED_100M; } } @@ -404,40 +404,40 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) /* Check parameters */ assert_param(IS_ETH_SPEED(heth->Init.Speed)); assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - + /* Set MAC Speed and Duplex Mode */ if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) | (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK) { /* In case of write timeout */ err = ETH_ERROR; - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set the ETH peripheral state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return HAL_ERROR */ return HAL_ERROR; - } - + } + /* Delay to assure PHY configuration */ HAL_Delay(PHY_CONFIG_DELAY); } - + /* Config MAC and DMA */ ETH_MACDMAConfig(heth, err); - + /* Set ETH HAL State to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Return function status */ return HAL_OK; } /** - * @brief De-Initializes the ETH peripheral. + * @brief De-Initializes the ETH peripheral. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status @@ -446,10 +446,10 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) { /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspDeInit(heth); - + /* Set ETH HAL state to Disabled */ heth->State= HAL_ETH_STATE_RESET; @@ -463,8 +463,8 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) /** * @brief Initializes the DMA Tx descriptors in chain mode. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMATxDescTab: Pointer to the first Tx desc list + * the configuration information for ETHERNET module + * @param DMATxDescTab: Pointer to the first Tx desc list * @param TxBuff: Pointer to the first TxBuffer list * @param TxBuffCount: Number of the used Tx desc in the list * @retval HAL status @@ -473,34 +473,34 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc { uint32_t i = 0; ETH_DMADescTypeDef *dmatxdesc; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ heth->TxDesc = DMATxDescTab; - - /* Fill each DMATxDesc descriptor with the right values */ + + /* Fill each DMATxDesc descriptor with the right values */ for(i=0; i < TxBuffCount; i++) { /* Get the pointer on the ith member of the Tx Desc list */ dmatxdesc = DMATxDescTab + i; - + /* Set Second Address Chained bit */ - dmatxdesc->Status = ETH_DMATXDESC_TCH; - + dmatxdesc->Status = ETH_DMATXDESC_TCH; + /* Set Buffer1 address pointer */ dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]); - + if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { /* Set the DMA Tx descriptors checksum insertion */ dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; } - + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ if(i < (TxBuffCount-1)) { @@ -509,20 +509,20 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc } else { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; } } - + /* Set Transmit Descriptor List Address Register */ (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab; - + /* Set ETH HAL State to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -530,8 +530,8 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc /** * @brief Initializes the DMA Rx descriptors in chain mode. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMARxDescTab: Pointer to the first Rx desc list + * the configuration information for ETHERNET module + * @param DMARxDescTab: Pointer to the first Rx desc list * @param RxBuff: Pointer to the first RxBuffer list * @param RxBuffCount: Number of the used Rx desc in the list * @retval HAL status @@ -540,59 +540,59 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc { uint32_t i = 0; ETH_DMADescTypeDef *DMARxDesc; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */ - heth->RxDesc = DMARxDescTab; - + heth->RxDesc = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ for(i=0; i < RxBuffCount; i++) { /* Get the pointer on the ith member of the Rx Desc list */ DMARxDesc = DMARxDescTab+i; - + /* Set Own bit of the Rx descriptor Status */ DMARxDesc->Status = ETH_DMARXDESC_OWN; - + /* Set Buffer1 size and Second Address Chained bit */ - DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; - + DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; + /* Set Buffer1 address pointer */ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]); - + if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) { /* Enable Ethernet DMA Rx Descriptor interrupt */ DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC; } - + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ if(i < (RxBuffCount-1)) { /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); } else { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); } } - + /* Set Receive Descriptor List Address Register */ (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab; - + /* Set ETH HAL State to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -607,7 +607,7 @@ __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) { /* Prevent unused argument(s) compilation warning */ UNUSED(heth); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_MspInit could be implemented in the user file */ @@ -623,7 +623,7 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) { /* Prevent unused argument(s) compilation warning */ UNUSED(heth); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_MspDeInit could be implemented in the user file */ @@ -633,13 +633,13 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) * @} */ -/** @defgroup ETH_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions +/** @defgroup ETH_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions * - @verbatim + @verbatim ============================================================================== ##### IO operation functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Transmit a frame HAL_ETH_TransmitFrame(); @@ -652,12 +652,12 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) HAL_ETH_WritePHYRegister(); @endverbatim - + * @{ */ /** - * @brief Sends an Ethernet frame. + * @brief Sends an Ethernet frame. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @param FrameLength: Amount of data to be sent @@ -666,47 +666,47 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) { uint32_t bufcount = 0, size = 0, i = 0; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - - if (FrameLength == 0) + + if (FrameLength == 0) { /* Set ETH HAL state to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - - return HAL_ERROR; - } - + + return HAL_ERROR; + } + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) - { + { /* OWN bit set */ heth->State = HAL_ETH_STATE_BUSY_TX; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_ERROR; } - + /* Get the number of needed Tx buffers for the current frame */ if (FrameLength > ETH_TX_BUF_SIZE) { bufcount = FrameLength/ETH_TX_BUF_SIZE; - if (FrameLength % ETH_TX_BUF_SIZE) + if (FrameLength % ETH_TX_BUF_SIZE) { bufcount++; } } - else - { + else + { bufcount = 1; } if (bufcount == 1) @@ -726,16 +726,16 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL { /* Clear FIRST and LAST segment bits */ heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); - - if (i == 0) + + if (i == 0) { /* Setting the first segment bit */ - heth->TxDesc->Status |= ETH_DMATXDESC_FS; + heth->TxDesc->Status |= ETH_DMATXDESC_FS; } - + /* Program size */ heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1); - + if (i == (bufcount-1)) { /* Setting the last segment bit */ @@ -743,14 +743,14 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE; heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); } - + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ heth->TxDesc->Status |= ETH_DMATXDESC_OWN; /* point to next descriptor */ heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); } } - + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) { @@ -759,19 +759,19 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL /* Resume DMA transmission*/ (heth->Instance)->DMATPDR = 0; } - + /* Set ETH HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } /** - * @brief Checks for received frames. + * @brief Checks for received frames. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status @@ -779,46 +779,46 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) { uint32_t framelength = 0; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Check the ETH state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Check if segment is not owned by DMA */ /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */ if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET)) { /* Check if last segment */ - if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) + if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) { /* increment segment count */ (heth->RxFrameInfos).SegCount++; - + /* Check if last segment is first segment: one segment contains the frame */ if ((heth->RxFrameInfos).SegCount == 1) { (heth->RxFrameInfos).FSRxDesc =heth->RxDesc; } - + heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4; heth->RxFrameInfos.length = framelength; - + /* Get the address of the buffer start address */ heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; /* point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr); - + /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -831,27 +831,27 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); } - /* Check if intermediate segment */ + /* Check if intermediate segment */ else { (heth->RxFrameInfos).SegCount++; /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } + } } - + /* Set ETH HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_ERROR; } /** - * @brief Gets the Received frame in interrupt mode. + * @brief Gets the Received frame in interrupt mode. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status @@ -859,25 +859,25 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) { uint32_t descriptorscancounter = 0; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set ETH HAL State to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Scan descriptors owned by CPU */ while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB)) { /* Just for security */ descriptorscancounter++; - + /* Check if first segment in frame */ - /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ + /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS) - { + { heth->RxFrameInfos.FSRxDesc = heth->RxDesc; - heth->RxFrameInfos.SegCount = 1; + heth->RxFrameInfos.SegCount = 1; /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); } @@ -892,34 +892,34 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) } /* Should be last segment */ else - { + { /* Last segment */ heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - + /* Increment segment count */ (heth->RxFrameInfos.SegCount)++; - + /* Check if last segment is first segment: one segment contains the frame */ if ((heth->RxFrameInfos.SegCount) == 1) { heth->RxFrameInfos.FSRxDesc = heth->RxDesc; } - + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4; - - /* Get the address of the buffer start address */ + + /* Get the address of the buffer start address */ heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; - - /* Point to next descriptor */ + + /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - + /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -927,10 +927,10 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_ERROR; } @@ -944,40 +944,40 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) { /* Frame received */ - if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) + if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) { /* Receive complete callback */ HAL_ETH_RxCpltCallback(heth); - + /* Clear the Eth DMA Rx IT pending bits */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R); /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); } /* Frame transmitted */ - else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) + else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) { /* Transfer complete callback */ HAL_ETH_TxCpltCallback(heth); - + /* Clear the Eth DMA Tx IT pending bits */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T); /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); } - + /* Clear the interrupt flags */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS); - + /* ETH DMA Error */ if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS)) { @@ -986,10 +986,10 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) /* Clear the interrupt flags */ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS); - + /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); } @@ -1005,10 +1005,10 @@ __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) { /* Prevent unused argument(s) compilation warning */ UNUSED(heth); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_TxCpltCallback could be implemented in the user file - */ + */ } /** @@ -1021,10 +1021,10 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) { /* Prevent unused argument(s) compilation warning */ UNUSED(heth); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_TxCpltCallback could be implemented in the user file - */ + */ } /** @@ -1037,32 +1037,32 @@ __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) { /* Prevent unused argument(s) compilation warning */ UNUSED(heth); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ETH_TxCpltCallback could be implemented in the user file - */ + */ } /** * @brief Reads a PHY register * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Basic Control Register, - * PHY_BSR: Transceiver Basic Status Register. + * the configuration information for ETHERNET module + * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Basic Control Register, + * PHY_BSR: Transceiver Basic Status Register. * More PHY register could be read depending on the used PHY - * @param RegValue: PHY register value + * @param RegValue: PHY register value * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0; uint32_t tickstart = 0; - + /* Check parameters */ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - + /* Check the ETH peripheral state */ if(heth->State == HAL_ETH_STATE_BUSY_RD) { @@ -1070,25 +1070,25 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR } /* Set ETH HAL State to BUSY_RD */ heth->State = HAL_ETH_STATE_BUSY_RD; - + /* Get the ETHERNET MACMIIAR value */ tmpreg = heth->Instance->MACMIIAR; - + /* Keep only the CSR Clock Range CR[2:0] bits value */ tmpreg &= ~ETH_MACMIIAR_CR_MASK; - + /* Prepare the MII address register value */ tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - + /* Write the result value into the MII Address register */ heth->Instance->MACMIIAR = tmpreg; - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Check for the Busy flag */ while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) { @@ -1096,22 +1096,22 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR if((HAL_GetTick() - tickstart ) > PHY_READ_TO) { heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_TIMEOUT; } - + tmpreg = heth->Instance->MACMIIAR; } - + /* Get MACMIIDR value */ *RegValue = (uint16_t)(heth->Instance->MACMIIDR); - + /* Set ETH HAL State to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return function status */ return HAL_OK; } @@ -1119,10 +1119,10 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR /** * @brief Writes to a PHY register. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Control Register. + * the configuration information for ETHERNET module + * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Control Register. * More PHY register could be written depending on the used PHY * @param RegValue: the value to write * @retval HAL status @@ -1131,10 +1131,10 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY { uint32_t tmpreg = 0; uint32_t tickstart = 0; - + /* Check parameters */ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - + /* Check the ETH peripheral state */ if(heth->State == HAL_ETH_STATE_BUSY_WR) { @@ -1142,28 +1142,28 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY } /* Set ETH HAL State to BUSY_WR */ heth->State = HAL_ETH_STATE_BUSY_WR; - + /* Get the ETHERNET MACMIIAR value */ tmpreg = heth->Instance->MACMIIAR; - + /* Keep only the CSR Clock Range CR[2:0] bits value */ tmpreg &= ~ETH_MACMIIAR_CR_MASK; - + /* Prepare the MII register address value */ tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - + /* Give the value to the MII data register */ heth->Instance->MACMIIDR = (uint16_t)RegValue; - + /* Write the result value into the MII Address register */ heth->Instance->MACMIIAR = tmpreg; - + /* Get tick */ tickstart = HAL_GetTick(); - + /* Check for the Busy flag */ while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) { @@ -1171,21 +1171,21 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO) { heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + return HAL_TIMEOUT; } - + tmpreg = heth->Instance->MACMIIAR; } - + /* Set ETH HAL State to READY */ heth->State = HAL_ETH_STATE_READY; - + /* Return function status */ - return HAL_OK; + return HAL_OK; } /** @@ -1193,16 +1193,16 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY */ /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Enable MAC and DMA transmission and reception. HAL_ETH_Start(); - (+) Disable MAC and DMA transmission and reception. + (+) Disable MAC and DMA transmission and reception. HAL_ETH_Stop(); (+) Set the MAC configuration in runtime mode HAL_ETH_ConfigMAC(); @@ -1211,82 +1211,82 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY @endverbatim * @{ - */ + */ /** - * @brief Enables Ethernet MAC and DMA reception/transmission + * @brief Enables Ethernet MAC and DMA reception/transmission * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) -{ +{ /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Enable transmit state machine of the MAC for transmission on the MII */ ETH_MACTransmissionEnable(heth); - + /* Enable receive state machine of the MAC for reception from the MII */ ETH_MACReceptionEnable(heth); - + /* Flush Transmit FIFO */ ETH_FlushTransmitFIFO(heth); - + /* Start DMA transmission */ ETH_DMATransmissionEnable(heth); - + /* Start DMA reception */ ETH_DMAReceptionEnable(heth); - + /* Set the ETH state to READY*/ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } /** - * @brief Stop Ethernet MAC and DMA reception/transmission + * @brief Stop Ethernet MAC and DMA reception/transmission * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) -{ +{ /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - + /* Stop DMA transmission */ ETH_DMATransmissionDisable(heth); - + /* Stop DMA reception */ ETH_DMAReceptionDisable(heth); - + /* Disable receive state machine of the MAC for reception from the MII */ ETH_MACReceptionDisable(heth); - + /* Flush Transmit FIFO */ ETH_FlushTransmitFIFO(heth); - + /* Disable transmit state machine of the MAC for transmission on the MII */ ETH_MACTransmissionDisable(heth); - + /* Set the ETH state*/ heth->State = HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ return HAL_OK; } @@ -1295,22 +1295,22 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) * @brief Set ETH MAC Configuration. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param macconf: MAC Configuration structure + * @param macconf: MAC Configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) { uint32_t tmpreg = 0; - + /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State= HAL_ETH_STATE_BUSY; - + assert_param(IS_ETH_SPEED(heth->Init.Speed)); - assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - + assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); + if (macconf != NULL) { /* Check the parameters */ @@ -1341,86 +1341,86 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl)); assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison)); assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier)); - + /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ tmpreg = (heth->Instance)->MACCR; /* Clear WD, PCE, PS, TE and RE bits */ tmpreg &= ETH_MACCR_CLEAR_MASK; - - tmpreg |= (uint32_t)(macconf->Watchdog | - macconf->Jabber | + + tmpreg |= (uint32_t)(macconf->Watchdog | + macconf->Jabber | macconf->InterFrameGap | macconf->CarrierSense | - (heth->Init).Speed | + (heth->Init).Speed | macconf->ReceiveOwn | macconf->LoopbackMode | - (heth->Init).DuplexMode | - macconf->ChecksumOffload | - macconf->RetryTransmission | - macconf->AutomaticPadCRCStrip | - macconf->BackOffLimit | + (heth->Init).DuplexMode | + macconf->ChecksumOffload | + macconf->RetryTransmission | + macconf->AutomaticPadCRCStrip | + macconf->BackOffLimit | macconf->DeferralCheck); - + /* Write to ETHERNET MACCR */ (heth->Instance)->MACCR = (uint32_t)tmpreg; - + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->MACCR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | + (heth->Instance)->MACCR = tmpreg; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Write to ETHERNET MACFFR */ + (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | macconf->SourceAddrFilter | macconf->PassControlFrames | - macconf->BroadcastFramesReception | + macconf->BroadcastFramesReception | macconf->DestinationAddrFilter | macconf->PromiscuousMode | macconf->MulticastFramesFilter | macconf->UnicastFramesFilter); - + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->MACFFR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACFFR = tmpreg; - + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ /* Write to ETHERNET MACHTHR */ (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh; - + /* Write to ETHERNET MACHTLR */ (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow; /*----------------------- ETHERNET MACFCR Configuration --------------------*/ - - /* Get the ETHERNET MACFCR value */ + + /* Get the ETHERNET MACFCR value */ tmpreg = (heth->Instance)->MACFCR; /* Clear xx bits */ tmpreg &= ETH_MACFCR_CLEAR_MASK; - - tmpreg |= (uint32_t)((macconf->PauseTime << 16) | + + tmpreg |= (uint32_t)((macconf->PauseTime << 16) | macconf->ZeroQuantaPause | macconf->PauseLowThreshold | - macconf->UnicastPauseFrameDetect | + macconf->UnicastPauseFrameDetect | macconf->ReceiveFlowControl | - macconf->TransmitFlowControl); - + macconf->TransmitFlowControl); + /* Write to ETHERNET MACFCR */ (heth->Instance)->MACFCR = (uint32_t)tmpreg; - + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->MACFCR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACFCR = tmpreg; - + /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ - (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | + (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | macconf->VLANTagIdentifier); - + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->MACVLANTR; @@ -1432,37 +1432,37 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ tmpreg = (heth->Instance)->MACCR; - + /* Clear FES and DM bits */ tmpreg &= ~((uint32_t)0x00004800); - + tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); - + /* Write to ETHERNET MACCR */ (heth->Instance)->MACCR = (uint32_t)tmpreg; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->MACCR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACCR = tmpreg; } - + /* Set the ETH state to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ - return HAL_OK; + return HAL_OK; } /** * @brief Sets ETH DMA Configuration. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param dmaconf: DMA Configuration structure + * @param dmaconf: DMA Configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) @@ -1471,7 +1471,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef /* Process Locked */ __HAL_LOCK(heth); - + /* Set the ETH peripheral state to BUSY */ heth->State= HAL_ETH_STATE_BUSY; @@ -1492,17 +1492,17 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat)); assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength)); assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration)); - + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ /* Get the ETHERNET DMAOMR value */ tmpreg = (heth->Instance)->DMAOMR; /* Clear xx bits */ tmpreg &= ETH_DMAOMR_CLEAR_MASK; - tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | + tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | dmaconf->ReceiveStoreForward | dmaconf->FlushReceivedFrame | - dmaconf->TransmitStoreForward | + dmaconf->TransmitStoreForward | dmaconf->TransmitThresholdControl | dmaconf->ForwardErrorFrames | dmaconf->ForwardUndersizedGoodFrames | @@ -1519,13 +1519,13 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef (heth->Instance)->DMAOMR = tmpreg; /*----------------------- ETHERNET DMABMR Configuration --------------------*/ - (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | + (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | dmaconf->FixedBurst | dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ dmaconf->TxDMABurstLength | dmaconf->EnhancedDescriptorFormat | (dmaconf->DescriptorSkipLength << 2) | - dmaconf->DMAArbitration | + dmaconf->DMAArbitration | ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ /* Wait until the write operation will be taken into account: @@ -1536,31 +1536,31 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef /* Set the ETH state to Ready */ heth->State= HAL_ETH_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(heth); - + /* Return function status */ - return HAL_OK; + return HAL_OK; } /** * @} */ -/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions * - @verbatim + @verbatim =============================================================================== ##### Peripheral State functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. (+) Get the ETH handle state: HAL_ETH_GetState(); - + @endverbatim * @{ @@ -1573,7 +1573,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef * @retval HAL state */ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) -{ +{ /* Return ETH state */ return heth->State; } @@ -1581,11 +1581,11 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) /** * @} */ - + /** * @} */ - + /** @addtogroup ETH_Private_Functions * @{ */ @@ -1602,16 +1602,16 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) ETH_MACInitTypeDef macinit; ETH_DMAInitTypeDef dmainit; uint32_t tmpreg = 0; - + if (err != ETH_SUCCESS) /* Auto-negotiation failed */ { /* Set Ethernet duplex mode to Full-duplex */ (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; - + /* Set Ethernet speed to 100M */ (heth->Init).Speed = ETH_SPEED_100M; } - + /* Ethernet MAC default initialization **************************************/ macinit.Watchdog = ETH_WATCHDOG_ENABLE; macinit.Jabber = ETH_JABBER_ENABLE; @@ -1637,7 +1637,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; - macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; + macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_HASHTABLE;; macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; macinit.HashTableHigh = 0x0; macinit.HashTableLow = 0x0; @@ -1649,7 +1649,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; macinit.VLANTagIdentifier = 0x0; - + /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ tmpreg = (heth->Instance)->MACCR; @@ -1659,39 +1659,39 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the JD: bit according to ETH Jabber value */ /* Set the IFG bit according to ETH InterFrameGap value */ /* Set the DCRS bit according to ETH CarrierSense value */ - /* Set the FES bit according to ETH Speed value */ - /* Set the DO bit according to ETH ReceiveOwn value */ + /* Set the FES bit according to ETH Speed value */ + /* Set the DO bit according to ETH ReceiveOwn value */ /* Set the LM bit according to ETH LoopbackMode value */ - /* Set the DM bit according to ETH Mode value */ + /* Set the DM bit according to ETH Mode value */ /* Set the IPCO bit according to ETH ChecksumOffload value */ /* Set the DR bit according to ETH RetryTransmission value */ /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ /* Set the BL bit according to ETH BackOffLimit value */ /* Set the DC bit according to ETH DeferralCheck value */ - tmpreg |= (uint32_t)(macinit.Watchdog | - macinit.Jabber | + tmpreg |= (uint32_t)(macinit.Watchdog | + macinit.Jabber | macinit.InterFrameGap | macinit.CarrierSense | - (heth->Init).Speed | + (heth->Init).Speed | macinit.ReceiveOwn | macinit.LoopbackMode | - (heth->Init).DuplexMode | - macinit.ChecksumOffload | - macinit.RetryTransmission | - macinit.AutomaticPadCRCStrip | - macinit.BackOffLimit | + (heth->Init).DuplexMode | + macinit.ChecksumOffload | + macinit.RetryTransmission | + macinit.AutomaticPadCRCStrip | + macinit.BackOffLimit | macinit.DeferralCheck); - + /* Write to ETHERNET MACCR */ (heth->Instance)->MACCR = (uint32_t)tmpreg; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->MACCR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + (heth->Instance)->MACCR = tmpreg; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ /* Set the RA bit according to ETH ReceiveAll value */ /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ /* Set the PCF bit according to ETH PassControlFrames value */ @@ -1700,74 +1700,74 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the PR bit according to ETH PromiscuousMode value */ /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | + /* Write to ETHERNET MACFFR */ + (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | macinit.SourceAddrFilter | macinit.PassControlFrames | - macinit.BroadcastFramesReception | + macinit.BroadcastFramesReception | macinit.DestinationAddrFilter | macinit.PromiscuousMode | macinit.MulticastFramesFilter | macinit.UnicastFramesFilter); - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->MACFFR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACFFR = tmpreg; - + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ /* Write to ETHERNET MACHTHR */ (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh; - + /* Write to ETHERNET MACHTLR */ (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow; /*----------------------- ETHERNET MACFCR Configuration -------------------*/ - - /* Get the ETHERNET MACFCR value */ + + /* Get the ETHERNET MACFCR value */ tmpreg = (heth->Instance)->MACFCR; /* Clear xx bits */ tmpreg &= ETH_MACFCR_CLEAR_MASK; - + /* Set the PT bit according to ETH PauseTime value */ /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ /* Set the PLT bit according to ETH PauseLowThreshold value */ /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ /* Set the RFE bit according to ETH ReceiveFlowControl value */ - /* Set the TFE bit according to ETH TransmitFlowControl value */ - tmpreg |= (uint32_t)((macinit.PauseTime << 16) | + /* Set the TFE bit according to ETH TransmitFlowControl value */ + tmpreg |= (uint32_t)((macinit.PauseTime << 16) | macinit.ZeroQuantaPause | macinit.PauseLowThreshold | - macinit.UnicastPauseFrameDetect | + macinit.UnicastPauseFrameDetect | macinit.ReceiveFlowControl | - macinit.TransmitFlowControl); - + macinit.TransmitFlowControl); + /* Write to ETHERNET MACFCR */ (heth->Instance)->MACFCR = (uint32_t)tmpreg; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->MACFCR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACFCR = tmpreg; - + /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ /* Set the ETV bit according to ETH VLANTagComparison value */ - /* Set the VL bit according to ETH VLANTagIdentifier value */ - (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | + /* Set the VL bit according to ETH VLANTagIdentifier value */ + (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | macinit.VLANTagIdentifier); - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->MACVLANTR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACVLANTR = tmpreg; - + /* Ethernet DMA default initialization ************************************/ dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; - dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; + dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; @@ -1780,12 +1780,12 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE; dmainit.DescriptorSkipLength = 0x0; dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; - + /* Get the ETHERNET DMAOMR value */ tmpreg = (heth->Instance)->DMAOMR; /* Clear xx bits */ tmpreg &= ETH_DMAOMR_CLEAR_MASK; - + /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ /* Set the RSF bit according to ETH ReceiveStoreForward value */ /* Set the DFF bit according to ETH FlushReceivedFrame value */ @@ -1795,25 +1795,25 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ /* Set the RTC bit according to ETH ReceiveThresholdControl value */ /* Set the OSF bit according to ETH SecondFrameOperate value */ - tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | + tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | dmainit.ReceiveStoreForward | dmainit.FlushReceivedFrame | - dmainit.TransmitStoreForward | + dmainit.TransmitStoreForward | dmainit.TransmitThresholdControl | dmainit.ForwardErrorFrames | dmainit.ForwardUndersizedGoodFrames | dmainit.ReceiveThresholdControl | dmainit.SecondFrameOperate); - + /* Write to ETHERNET DMAOMR */ (heth->Instance)->DMAOMR = (uint32_t)tmpreg; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->DMAOMR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->DMAOMR = tmpreg; - + /*----------------------- ETHERNET DMABMR Configuration ------------------*/ /* Set the AAL bit according to ETH AddressAlignedBeats value */ /* Set the FB bit according to ETH FixedBurst value */ @@ -1822,7 +1822,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/ /* Set the DSL bit according to ETH DesciptorSkipLength value */ /* Set the PR and DA bits according to ETH DMAArbitration value */ - (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | + (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | dmainit.FixedBurst | dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ dmainit.TxDMABurstLength | @@ -1830,7 +1830,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) (dmainit.DescriptorSkipLength << 2) | dmainit.DMAArbitration | ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->DMABMR; @@ -1843,7 +1843,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R); } - /* Initialize MAC address in ethernet MAC */ + /* Initialize MAC address in ethernet MAC */ ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); } @@ -1853,8 +1853,8 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) * the configuration information for ETHERNET module * @param MacAddr: The MAC address to configure * This parameter can be one of the following values: - * @arg ETH_MAC_Address0: MAC Address0 - * @arg ETH_MAC_Address1: MAC Address1 + * @arg ETH_MAC_Address0: MAC Address0 + * @arg ETH_MAC_Address1: MAC Address1 * @arg ETH_MAC_Address2: MAC Address2 * @arg ETH_MAC_Address3: MAC Address3 * @param Addr: Pointer to MAC address buffer data (6 bytes) @@ -1863,17 +1863,17 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) { uint32_t tmpreg; - + /* Check the parameters */ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - + /* Calculate the selected MAC address high register */ tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; /* Load the selected MAC address high register */ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg; /* Calculate the selected MAC address low register */ tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; - + /* Load the selected MAC address low register */ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg; } @@ -1881,16 +1881,16 @@ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint /** * @brief Enables the MAC transmission. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) -{ +{ __IO uint32_t tmpreg = 0; - + /* Enable the MAC transmission */ (heth->Instance)->MACCR |= ETH_MACCR_TE; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->MACCR; @@ -1901,16 +1901,16 @@ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the MAC transmission. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) -{ +{ __IO uint32_t tmpreg = 0; - + /* Disable the MAC transmission */ (heth->Instance)->MACCR &= ~ETH_MACCR_TE; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->MACCR; @@ -1921,16 +1921,16 @@ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the MAC reception. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) -{ +{ __IO uint32_t tmpreg = 0; - + /* Enable the MAC reception */ (heth->Instance)->MACCR |= ETH_MACCR_RE; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->MACCR; @@ -1941,16 +1941,16 @@ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) /** * @brief Disables the MAC reception. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) -{ +{ __IO uint32_t tmpreg = 0; - + /* Disable the MAC reception */ - (heth->Instance)->MACCR &= ~ETH_MACCR_RE; - + (heth->Instance)->MACCR &= ~ETH_MACCR_RE; + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->MACCR; @@ -1961,23 +1961,23 @@ static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the DMA transmission. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) { /* Enable the DMA transmission */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; + (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; } /** * @brief Disables the DMA transmission. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) -{ +{ /* Disable the DMA transmission */ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST; } @@ -1985,23 +1985,23 @@ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) /** * @brief Enables the DMA reception. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) -{ +{ /* Enable the DMA reception */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; + (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; } /** * @brief Disables the DMA reception. * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * the configuration information for ETHERNET module * @retval None */ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) -{ +{ /* Disable the DMA reception */ (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR; } @@ -2015,10 +2015,10 @@ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) { __IO uint32_t tmpreg = 0; - + /* Set the Flush Transmit FIFO bit */ (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; - + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ tmpreg = (heth->Instance)->DMAOMR; diff --git a/variants/DISCO_F746NG/Ethernet/lwipopts.h b/variants/DISCO_F746NG/Ethernet/lwipopts.h index ae718cba6a..a704a424e7 100644 --- a/variants/DISCO_F746NG/Ethernet/lwipopts.h +++ b/variants/DISCO_F746NG/Ethernet/lwipopts.h @@ -246,6 +246,8 @@ The STM32F4x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums * an operating system. */ //#define ETH_INPUT_USE_IT 1 +#define LWIP_IGMP 1 + #endif /* __LWIPOPTS_H__ */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/variants/NUCLEO_F429ZI/Ethernet/lwipopts.h b/variants/NUCLEO_F429ZI/Ethernet/lwipopts.h index ae718cba6a..a704a424e7 100644 --- a/variants/NUCLEO_F429ZI/Ethernet/lwipopts.h +++ b/variants/NUCLEO_F429ZI/Ethernet/lwipopts.h @@ -246,6 +246,8 @@ The STM32F4x7 allows computing and verifying the IP, UDP, TCP and ICMP checksums * an operating system. */ //#define ETH_INPUT_USE_IT 1 +#define LWIP_IGMP 1 + #endif /* __LWIPOPTS_H__ */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/