diff --git a/README.md b/README.md
index 447f1dd4e3..01b890763f 100644
--- a/README.md
+++ b/README.md
@@ -128,6 +128,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32L452RE | [Nucleo L452RE](http://www.st.com/en/evaluation-tools/nucleo-l452re.html) | *1.5.0* | |
| :green_heart: | STM32L452RE-P | [Nucleo L452RE-P](http://www.st.com/en/evaluation-tools/nucleo-l452re-p.html) | *1.8.0* | |
| :green_heart: | STM32L476RG | [Nucleo L476RG](http://www.st.com/en/evaluation-tools/nucleo-l476rg.html) | *0.1.0* | |
+| :yellow_heart: | STM32WB15CCU | [Nucleo-WB15CC](https://www.st.com/en/evaluation-tools/nucleo-wb15cc.html) | **2.5.0** | |
| :green_heart: | STM32WB55RG
STM32WB55CG | [P-Nucleo-WB55RG](https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html) | *1.6.0* | BLE support with [STM32duinoBLE](https://github.com/stm32duino/STM32duinoBLE) |
| :green_heart: | STM32WL55JC | [Nucleo WL55JC1](https://www.st.com/en/evaluation-tools/nucleo-wl55jc.html) | *2.1.0* | LoRa support not available |
@@ -661,6 +662,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| Status | Device(s) | Name | Release | Notes |
| :----: | :-------: | ---- | :-----: | :---- |
+| :yellow_heart: | STM32WB15CCU | Generic Board | **2.5.0** | |
| :green_heart: | STM32WB55CC
STM32WB55CE
STM32WB55CG | Generic Board | *2.0.0* | |
| :green_heart: | STM32WB5MMG | Generic Board | *2.1.0* | |
| :green_heart: | STM32WB55RC
STM32WB55RE
STM32WB55RG | Generic Board | *2.0.0* | |
diff --git a/boards.txt b/boards.txt
index 346c37b3d2..97d7a725b9 100644
--- a/boards.txt
+++ b/boards.txt
@@ -586,6 +586,20 @@ Nucleo_64.menu.pnum.NUCLEO_L476RG.build.product_line=STM32L476xx
Nucleo_64.menu.pnum.NUCLEO_L476RG.build.variant=STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT
Nucleo_64.menu.pnum.NUCLEO_L476RG.build.cmsis_lib_gcc=arm_cortexM4lf_math
+# NUCLEO_WB15CC
+Nucleo_64.menu.pnum.NUCLEO_WB15CC=Nucleo WB15CC
+Nucleo_64.menu.pnum.NUCLEO_WB15CC.node="NOD_WB15CC"
+Nucleo_64.menu.pnum.NUCLEO_WB15CC.upload.maximum_size=131072
+Nucleo_64.menu.pnum.NUCLEO_WB15CC.upload.maximum_data_size=12288
+Nucleo_64.menu.pnum.NUCLEO_WB15CC.build.mcu=cortex-m4
+Nucleo_64.menu.pnum.NUCLEO_WB15CC.build.fpu=-mfpu=fpv4-sp-d16
+Nucleo_64.menu.pnum.NUCLEO_WB15CC.build.float-abi=-mfloat-abi=hard
+Nucleo_64.menu.pnum.NUCLEO_WB15CC.build.board=NUCLEO_WB15CC
+Nucleo_64.menu.pnum.NUCLEO_WB15CC.build.series=STM32WBxx
+Nucleo_64.menu.pnum.NUCLEO_WB15CC.build.product_line=STM32WB15xx
+Nucleo_64.menu.pnum.NUCLEO_WB15CC.build.variant=STM32WBxx/WB15CCU
+Nucleo_64.menu.pnum.NUCLEO_WB15CC.build.cmsis_lib_gcc=arm_cortexM4lf_math
+
# P_NUCLEO_WB55RG board
Nucleo_64.menu.pnum.P_NUCLEO_WB55RG=P-Nucleo WB55RG
Nucleo_64.menu.pnum.P_NUCLEO_WB55RG.node="NODE_WB55RG,NOD_WB55RG"
@@ -9532,6 +9546,14 @@ GenWB.build.cmsis_lib_gcc=arm_cortexM4lf_math
GenWB.upload.maximum_size=0
GenWB.upload.maximum_data_size=0
+# Generic WB15CCUx
+GenWB.menu.pnum.GENERIC_WB15CCUX=Generic WB15CCUx
+GenWB.menu.pnum.GENERIC_WB15CCUX.upload.maximum_size=131072
+GenWB.menu.pnum.GENERIC_WB15CCUX.upload.maximum_data_size=12288
+GenWB.menu.pnum.GENERIC_WB15CCUX.build.board=GENERIC_WB15CCUX
+GenWB.menu.pnum.GENERIC_WB15CCUX.build.product_line=STM32WB15xx
+GenWB.menu.pnum.GENERIC_WB15CCUX.build.variant=STM32WBxx/WB15CCU
+
# Generic WB55CCUx
GenWB.menu.pnum.GENERIC_WB55CCUX=Generic WB55CCUx
GenWB.menu.pnum.GENERIC_WB55CCUX.upload.maximum_size=131072
diff --git a/cores/arduino/stm32/timer.h b/cores/arduino/stm32/timer.h
index 7b71dc6b0e..4cdb0575aa 100644
--- a/cores/arduino/stm32/timer.h
+++ b/cores/arduino/stm32/timer.h
@@ -47,7 +47,8 @@ extern "C" {
#elif defined (TIM10_BASE)
#define TIM1_IRQHandler TIM1_UP_TIM10_IRQHandler
#endif
-#elif defined(STM32F3xx) || defined(STM32L4xx) || defined(STM32WBxx)
+#elif (defined(STM32F3xx) || defined(STM32L4xx) || defined(STM32WBxx)) &&\
+ defined(TIM16_BASE)
#define TIM1_IRQn TIM1_UP_TIM16_IRQn
#define TIM1_IRQHandler TIM1_UP_TIM16_IRQHandler
#elif defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx)
@@ -59,7 +60,7 @@ extern "C" {
#define TIM1_IRQHandler TIM1_UP_TIM10_IRQHandler
#endif
#elif defined(STM32H7xx) || defined(STM32L5xx) || defined(STM32MP1xx) ||\
- defined(STM32U5xx) || defined(STM32WLxx)
+ defined(STM32U5xx) || defined(STM32WBxx) || defined(STM32WLxx)
#define TIM1_IRQn TIM1_UP_IRQn
#define TIM1_IRQHandler TIM1_UP_IRQHandler
#endif
diff --git a/libraries/SrcWrapper/src/stm32/analog.cpp b/libraries/SrcWrapper/src/stm32/analog.cpp
index 0df0aa1542..47062ac334 100644
--- a/libraries/SrcWrapper/src/stm32/analog.cpp
+++ b/libraries/SrcWrapper/src/stm32/analog.cpp
@@ -860,7 +860,7 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution)
#if !defined(STM32F1xx) && !defined(STM32F2xx) && !defined(STM32F3xx) && \
!defined(STM32F4xx) && !defined(STM32F7xx) && !defined(STM32G4xx) && \
!defined(STM32H7xx) && !defined(STM32L4xx) && !defined(STM32L5xx) && \
- !defined(STM32MP1xx) && !defined(STM32WBxx)
+ !defined(STM32MP1xx) && !defined(STM32WBxx) || defined(ADC_SUPPORT_2_5_MSPS)
AdcHandle.Init.LowPowerAutoPowerOff = DISABLE; /* ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered */
#endif
#ifdef ADC_CHANNELS_BANK_B
@@ -874,7 +874,7 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution)
#endif
AdcHandle.Init.DiscontinuousConvMode = DISABLE; /* Parameter discarded because sequencer is disabled */
#if !defined(STM32F0xx) && !defined(STM32G0xx) && !defined(STM32L0xx) && \
- !defined(STM32WLxx)
+ !defined(STM32WLxx) && !defined(ADC_SUPPORT_2_5_MSPS)
AdcHandle.Init.NbrOfDiscConversion = 0; /* Parameter discarded because sequencer is disabled */
#endif
AdcHandle.Init.ExternalTrigConv = ADC_SOFTWARE_START; /* Software start to trig the 1st conversion manually, without external event */
@@ -898,7 +898,8 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution)
#if defined(STM32F0xx)
AdcHandle.Init.SamplingTimeCommon = samplingTime;
#endif
-#if defined(STM32G0xx) || defined(STM32U5xx) || defined(STM32WLxx)
+#if defined(STM32G0xx) || defined(STM32U5xx) || defined(STM32WLxx) || \
+ defined(ADC_SUPPORT_2_5_MSPS)
AdcHandle.Init.SamplingTimeCommon1 = samplingTime; /* Set sampling time common to a group of channels. */
AdcHandle.Init.SamplingTimeCommon2 = samplingTime; /* Set sampling time common to a group of channels, second common setting possible.*/
#endif
@@ -908,7 +909,7 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution)
#endif
#if !defined(STM32F0xx) && !defined(STM32F1xx) && !defined(STM32F2xx) && \
!defined(STM32F3xx) && !defined(STM32F4xx) && !defined(STM32F7xx) && \
- !defined(STM32L1xx)
+ !defined(STM32L1xx) && !defined(ADC_SUPPORT_2_5_MSPS)
AdcHandle.Init.OversamplingMode = DISABLE;
/* AdcHandle.Init.Oversample ignore for STM32L0xx as oversampling disabled */
/* AdcHandle.Init.Oversampling ignored for other as oversampling disabled */
diff --git a/variants/STM32WBxx/WB15CCU/generic_clock.c b/variants/STM32WBxx/WB15CCU/generic_clock.c
index 07684ca047..213d6b63bd 100644
--- a/variants/STM32WBxx/WB15CCU/generic_clock.c
+++ b/variants/STM32WBxx/WB15CCU/generic_clock.c
@@ -12,6 +12,7 @@
*/
#if defined(ARDUINO_GENERIC_WB15CCUX)
#include "pins_arduino.h"
+#include "lock_resource.h"
/**
* @brief System Clock Configuration
@@ -20,8 +21,60 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
+
+ /* This prevents concurrent access to RCC registers by CPU2 (M0+) */
+ hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
+
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI1
+ | RCC_OSCILLATORTYPE_MSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_10;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
+ | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
+ PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
+ PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
+
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+ LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+ LL_PWR_SMPS_Enable();
+
+ /* Select HSI as system clock source after Wake Up from Stop mode */
+ LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
+
+ hsem_unlock(CFG_HW_RCC_SEMID);
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32WBxx/WB15CCU/ldscript.ld b/variants/STM32WBxx/WB15CCU/ldscript.ld
new file mode 100644
index 0000000000..b769e7e651
--- /dev/null
+++ b/variants/STM32WBxx/WB15CCU/ldscript.ld
@@ -0,0 +1,183 @@
+/*
+******************************************************************************
+**
+** File : LinkerScript.ld
+**
+** Author : STM32CubeIDE
+**
+** Abstract : Linker script for STM32WB15xC Device
+** 320Kbytes FLASH
+** 48Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of RAM1 */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+RAM1 (xrw) : ORIGIN = 0x20000004, LENGTH = LD_MAX_DATA_SIZE - 4
+RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM1 AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM1
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM1
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+ MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+ MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED
+
+ /* used by the startup to initialize .MB_MEM2 data */
+ _siMB_MEM2 = LOADADDR(.MB_MEM2);
+ .MB_MEM2 :
+ {
+ _sMB_MEM2 = . ;
+ *(.MB_MEM2) ;
+ _eMB_MEM2 = . ;
+ } >RAM_SHARED AT> FLASH
+}
+
+
diff --git a/variants/STM32WBxx/WB15CCU/variant_NUCLEO_WB15CC.cpp b/variants/STM32WBxx/WB15CCU/variant_NUCLEO_WB15CC.cpp
new file mode 100644
index 0000000000..0bc9891554
--- /dev/null
+++ b/variants/STM32WBxx/WB15CCU/variant_NUCLEO_WB15CC.cpp
@@ -0,0 +1,153 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2022, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_NUCLEO_WB15CC)
+#include "pins_arduino.h"
+#include "lock_resource.h"
+
+// Pin number
+const PinName digitalPin[] = {
+ PB_7,
+ PB_6,
+ PB_0,
+ PA_12,
+ PB_1,
+ PA_11,
+ PA_8,
+ PE_4,
+ PB_5,
+ PA_15,
+ PB_2,
+ PA_7,
+ PB_4,
+ PA_5,
+ PB_9,
+ PB_8,
+ PA_4,
+ PA_6,
+ PA_1,
+ PA_0,
+ PA_2,
+ PA_3,
+ // ST Morpho
+ // CN7 Left Side
+ PH_3,
+ PA_13,
+ PA_14,
+ PC_14,
+ PC_15,
+ // CN10 Right side
+ PA_9,
+ PA_10,
+ PB_3,
+};
+
+// Analog (Ax) pin number array
+const uint32_t analogInputPin[] = {
+ 16, // A0
+ 17, // A1
+ 18, // A2
+ 19, // A3
+ 20, // A4
+ 21, // A5
+ 6, // A6
+ 11, // A7
+ 13, // A8
+ 27 // A9
+};
+
+// ----------------------------------------------------------------------------
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief System Clock Configuration
+ * @param None
+ * @retval None
+ */
+WEAK void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
+
+ /* This prevents concurrent access to RCC registers by CPU2 (M0+) */
+ hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
+
+ /** Configure LSE Drive Capability
+ */
+ HAL_PWR_EnableBkUpAccess();
+ __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI1
+ | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
+ RCC_OscInitStruct.PLL.PLLN = 6;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV3;
+ RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
+ | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP;
+ PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
+ PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
+ PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
+
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
+ LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
+ LL_PWR_SMPS_Enable();
+
+ /* Select HSI as system clock source after Wake Up from Stop mode */
+ LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
+
+ hsem_unlock(CFG_HW_RCC_SEMID);
+}
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ARDUINO_NUCLEO_WB15CC */
diff --git a/variants/STM32WBxx/WB15CCU/variant_NUCLEO_WB15CC.h b/variants/STM32WBxx/WB15CCU/variant_NUCLEO_WB15CC.h
new file mode 100644
index 0000000000..e5a0e9b51a
--- /dev/null
+++ b/variants/STM32WBxx/WB15CCU/variant_NUCLEO_WB15CC.h
@@ -0,0 +1,122 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2022, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ * STM32 pins number
+ *----------------------------------------------------------------------------*/
+#define PB7 0
+#define PB6 1
+#define PB0 2
+#define PA12 3
+#define PB1 4
+#define PA11 5
+#define PA8 PIN_A6
+#define PE4 7
+#define PB5 8
+#define PA15 9
+#define PB2 10
+#define PA7 PIN_A7
+#define PB4 12
+#define PA5 PIN_A8
+#define PB9 14
+#define PB8 15
+#define PA4 PIN_A0
+#define PA6 PIN_A1
+#define PA1 PIN_A2
+#define PA0 PIN_A3
+#define PA2 PIN_A4
+#define PA3 PIN_A5
+// ST Morpho
+// CN7 Left Side
+#define PH3 22 // BOOT0
+#define PA13 23 // SWDIO
+#define PA14 24 // SWDCLK
+#define PC14 25 // OSC32_IN
+#define PC15 26 // OSC32_OUT
+// CN10 Right side
+#define PA9 PIN_A9
+#define PA10 28
+#define PB3 29
+
+#define NUM_DIGITAL_PINS 30
+#define NUM_ANALOG_INPUTS 10
+
+// On-board LED pin number
+#define LED1 PB5
+#define LED2 PB0
+#define LED3 PB1
+#ifndef LED_BUILTIN
+ #define LED_BUILTIN LED1
+#endif
+#define LED_BLUE LED1
+#define LED_GREEN LED2
+#define LED_RED LED3
+
+// On-board user button
+#define B1_BTN PA0
+#define B2_BTN PE4
+#define B3_BTN PA6
+#ifndef USER_BTN
+ #define USER_BTN B1_BTN
+#endif
+
+// Timer Definitions
+#ifndef TIMER_TONE
+ #define TIMER_TONE TIM2
+#endif
+#ifndef TIMER_SERVO
+ #define TIMER_SERVO TIM1
+#endif
+
+// UART Definitions
+#ifndef SERIAL_UART_INSTANCE
+ #define SERIAL_UART_INSTANCE 1 //Connected to ST-Link
+#endif
+
+// Default pin used for 'Serial' instance (ex: ST-Link)
+// Mandatory for Firmata
+#ifndef PIN_SERIAL_RX
+ #define PIN_SERIAL_RX PA10
+#endif
+#ifndef PIN_SERIAL_TX
+ #define PIN_SERIAL_TX PA9
+#endif
+
+// Only 128k provided for cpu1, so defined the FLASH_PAGE_NUMBER
+// for EEPROM emulation to the last 128k pages.
+#define FLASH_PAGE_NUMBER 63
+
+/*----------------------------------------------------------------------------
+ * Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ // These serial port names are intended to allow libraries and architecture-neutral
+ // sketches to automatically default to the correct port name for a particular type
+ // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+ // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+ //
+ // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
+ //
+ // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
+ //
+ // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
+ //
+ // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
+ //
+ // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
+ // pins are NOT connected to anything by default.
+ #define SERIAL_PORT_MONITOR Serial
+ #define SERIAL_PORT_HARDWARE Serial1
+#endif