diff --git a/README.md b/README.md
index 26a04d6ba8..43afda96ed 100644
--- a/README.md
+++ b/README.md
@@ -340,45 +340,118 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
 | :green_heart: | STM32G030F6<br>STM32G030F6 | Generic Board | *2.2.0* |
 | :green_heart: | STM32G030K8 | [Aurora One](https://www.bfy.kr/aurora-one/) | *2.0.0* |
 | :green_heart: | STM32G071CB | [AGAFIA SG0](https://www.sigmaic.com/store/p7/agafia-sgo.html) | *2.3.0* |
+| :yellow_heart: | STM32G030J6 | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G030K6<br>STM32G030K8 | Generic Board | *2.0.0* |  |
-| :green_heart: | STM32G031J4<br>STM32G031J6 | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32G031C4<br>STM32G031C6<br>STM32G031C8 | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G031F4<br>STM32G031F6<br>STM32G031F8 | Generic Board | *2.3.0* |  |
+| :yellow_heart: | STM32G031G4<br>STM32G031G6<br>STM32G031G8 | Generic Board | **2.4.0** |  |
+| :green_heart: | STM32G031J4<br>STM32G031J6 | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32G031K4<br>STM32G031K6<br>STM32G031K8 | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32G031Y8 | Generic Board | *2.3.0* |  |
-| :green_heart: | STM32G041J6 | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32G041C6<br>STM32G041C8 | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G041F6<br>STM32G041F8 | Generic Board | *2.3.0* |  |
+| :yellow_heart: | STM32G041G6<br>STM32G041G8 | Generic Board | **2.4.0** |  |
+| :green_heart: | STM32G041J6 | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32G041K6<br>STM32G041K8 | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32G041Y8 | Generic Board | *2.3.0* |  |
+| :yellow_heart: | STM32G050C6<br>STM32G050C8 | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G050F6 | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G050K6<br>STM32G050K8 | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G051C6<br>STM32G051C8 | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G051F6<br>STM32G051F8 | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G051G6<br>STM32G051G8 | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G051K6<br>STM32G051K8 | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G061C6<br>STM32G061C8 | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G061F6<br>STM32G061F8 | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G061G6<br>STM32G061G8 | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G061K6<br>STM32G061K8 | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G070CB | Generic Board | *2.3.0* |  |
 | :green_heart: | STM32G070KB | Generic Board | *2.3.0* |  |
 | :green_heart: | STM32G070RB | Generic Board | *2.3.0* |  |
-| :green_heart: | STM32G071C6T<br>STM32G071C8T<br>STM32G071CBT | Generic Board | *2.3.0* |  |
-| :green_heart: | STM32G071C6U<br>STM32G071C8U<br>STM32G071CBU | Generic Board | *2.3.0* |  |
+| :green_heart: | STM32G071C6<br>STM32G071C8<br>STM32G071CB | Generic Board | *2.3.0* |  |
+| :yellow_heart: | STM32G071EB | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G071G6<br>STM32G071G8<br>STM32G071GB | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G071G8UxN | Generic Board | *2.3.0* |  |
 | :green_heart: | STM32G071GBUxN | Generic Board | *2.3.0* |  |
+| :yellow_heart: | STM32G071K6<br>STM32G071K8<br>STM32G071KB | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G071R6<br>STM32G071R8<br>STM32G071RB | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32G081CBT<br>STM32G081CBU | Generic Board | *2.3.0* |  |
+| :yellow_heart: | STM32G081EB | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G081GB | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G081GBUxN | Generic Board | *2.3.0* |  |
+| :yellow_heart: | STM32G081KB | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G081RB | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32G0B0CE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G0B0RE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G0B0VE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G0B1CB<br>STM32G0B1CC<br>STM32G0B1CE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G0B1KB<br>STM32G0B1KC<br>STM32G0B1KE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G0B1MB<br>STM32G0B1MC<br>STM32G0B1ME | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G0B1NE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G0B1VB<br>STM32G0B1VC<br>STM32G0B1VE | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G0B1RB<br>STM32G0B1RC<br>STM32G0B1RE | Generic Board | *2.1.0* |  |
+| :yellow_heart: | STM32G0C1CC<br>STM32G0C1CE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G0C1KB<br>STM32G0C1KC<br>STM32G0C1KE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G0C1MC<br>STM32G0C1ME | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G0C1NE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G0C1VC<br>STM32G0C1VE | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G0C1RB<br>STM32G0C1RE | Generic Board | *2.1.0* |  |
 
 ### Generic STM32G4 boards
 
 | Status | Device(s) | Name | Release | Notes |
 | :----: | :-------: | ---- | :-----: | :---- |
+| :yellow_heart: | STM32G431C6<br>STM32G431C8<br>STM32G431CB | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G431C6U<br>STM32G431C8U<br>STM32G431CBU | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32G431M6<br>STM32G431M8<br>STM32G431MB | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G431V6<br>STM32G431V8<br>STM32G431VB | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G441CB | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G441CBU | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32G441MB | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G441VB | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G431K6<br>STM32G431K8<br>STM32G431KB | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32G441KB | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32G431R6<br>STM32G431R8<br>STM32G431RB | Generic Board | *2.0.0* |  |
 | :green_heart: | STM32G441RB  | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32G471CC<br>STM32G471CE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G471MC<br>STM32G471ME | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G471QC<br>STM32G471QE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G471RC<br>STM32G471RE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G471VC<br>STM32G471VE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G473CB<br>STM32G473CC<br>STM32G473CE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G473MB<br>STM32G473MC<br>STM32G473ME | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G473PB<br>STM32G473PC<br>STM32G473PE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G473QB<br>STM32G473QC<br>STM32G473QE | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G473RB<br>STM32G473RC<br>STM32G473RE | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32G473VB<br>STM32G473VC<br>STM32G473VE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G474CB<br>STM32G474CC<br>STM32G474CE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G474MB<br>STM32G474MC<br>STM32G474ME | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G474PB<br>STM32G474PC<br>STM32G474PE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G474QB<br>STM32G474QC<br>STM32G474QE | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G474RB<br>STM32G474RC<br>STM32G474RE | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32G474VB<br>STM32G474VC<br>STM32G474VE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G483CE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G483ME | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G483PE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G483QE | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G483RE | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32G483VE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G484CE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G484ME | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G484PE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G484QE | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G484RE | Generic Board | *2.0.0* |  |
+| :yellow_heart: | STM32G484VE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G491CC<br>STM32G491CE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G491KC<br>STM32G491KE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G491MC<br>STM32G491ME | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G491RC<br>STM32G491RE | Generic Board | *2.3.0* |  |
+| :yellow_heart: | STM32G491VC<br>STM32G491VE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G4A1CE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G4A1KE | Generic Board | **2.4.0** |  |
+| :yellow_heart: | STM32G4A1ME | Generic Board | **2.4.0** |  |
 | :green_heart: | STM32G4A1RE | Generic Board | *2.3.0* |  |
+| :yellow_heart: | STM32G4A1VE | Generic Board | **2.4.0** |  |
 
 ### Generic STM32H7 boards
 
@@ -529,6 +602,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
 | :green_heart:  | STM32F401VE | [STEVAL-3DP001V1](https://www.st.com/en/evaluation-tools/steval-3dp001v1.html) | *1.6.0* |  |
 | :green_heart:  | STM32F446RE | [VAkE v1.0](https://www.facebook.com/pages/category/Product-Service/VAkE-Board-2290066274575218/) | *1.6.0* |  |
 | :green_heart:  | STM32F446VE | [FYSETC_S6](https://wiki.fysetc.com/FYSETC_S6/) | *1.9.0* | |
+| :yellow_heart: | STM32G0B1CB | [BTT EBB42 CAN V1.1](https://github.com/bigtreetech/EBB/tree/master/EBB%20CAN%20V1.1%20(STM32G0B1)/EBB42%20CAN%20V1.1) | **2.4.0** |  |
 
 ### [Blues Wireless](https://blues.io/) boards
 
diff --git a/boards.txt b/boards.txt
index 48a050d075..9d11a4dec1 100644
--- a/boards.txt
+++ b/boards.txt
@@ -4136,6 +4136,14 @@ GenG0.menu.pnum.GENERIC_G030F6PX.build.board=GENERIC_G030F6PX
 GenG0.menu.pnum.GENERIC_G030F6PX.build.product_line=STM32G030xx
 GenG0.menu.pnum.GENERIC_G030F6PX.build.variant=STM32G0xx/G030F6P
 
+# Generic G030J6Mx
+GenG0.menu.pnum.GENERIC_G030J6MX=Generic G030J6Mx
+GenG0.menu.pnum.GENERIC_G030J6MX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G030J6MX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G030J6MX.build.board=GENERIC_G030J6MX
+GenG0.menu.pnum.GENERIC_G030J6MX.build.product_line=STM32G030xx
+GenG0.menu.pnum.GENERIC_G030J6MX.build.variant=STM32G0xx/G030J6M
+
 # Generic G030K6Tx
 GenG0.menu.pnum.GENERIC_G030K6TX=Generic G030K6Tx
 GenG0.menu.pnum.GENERIC_G030K6TX.upload.maximum_size=32768
@@ -4152,6 +4160,126 @@ GenG0.menu.pnum.GENERIC_G030K8TX.build.board=GENERIC_G030K8TX
 GenG0.menu.pnum.GENERIC_G030K8TX.build.product_line=STM32G030xx
 GenG0.menu.pnum.GENERIC_G030K8TX.build.variant=STM32G0xx/G030K(6-8)T
 
+# Generic G031C4Tx
+GenG0.menu.pnum.GENERIC_G031C4TX=Generic G031C4Tx
+GenG0.menu.pnum.GENERIC_G031C4TX.upload.maximum_size=16384
+GenG0.menu.pnum.GENERIC_G031C4TX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G031C4TX.build.board=GENERIC_G031C4TX
+GenG0.menu.pnum.GENERIC_G031C4TX.build.product_line=STM32G031xx
+GenG0.menu.pnum.GENERIC_G031C4TX.build.variant=STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)
+
+# Generic G031C6Tx
+GenG0.menu.pnum.GENERIC_G031C6TX=Generic G031C6Tx
+GenG0.menu.pnum.GENERIC_G031C6TX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G031C6TX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G031C6TX.build.board=GENERIC_G031C6TX
+GenG0.menu.pnum.GENERIC_G031C6TX.build.product_line=STM32G031xx
+GenG0.menu.pnum.GENERIC_G031C6TX.build.variant=STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)
+
+# Generic G031C8Tx
+GenG0.menu.pnum.GENERIC_G031C8TX=Generic G031C8Tx
+GenG0.menu.pnum.GENERIC_G031C8TX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G031C8TX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G031C8TX.build.board=GENERIC_G031C8TX
+GenG0.menu.pnum.GENERIC_G031C8TX.build.product_line=STM32G031xx
+GenG0.menu.pnum.GENERIC_G031C8TX.build.variant=STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)
+
+# Generic G031C4Ux
+GenG0.menu.pnum.GENERIC_G031C4UX=Generic G031C4Ux
+GenG0.menu.pnum.GENERIC_G031C4UX.upload.maximum_size=16384
+GenG0.menu.pnum.GENERIC_G031C4UX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G031C4UX.build.board=GENERIC_G031C4UX
+GenG0.menu.pnum.GENERIC_G031C4UX.build.product_line=STM32G031xx
+GenG0.menu.pnum.GENERIC_G031C4UX.build.variant=STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)
+
+# Generic G031C6Ux
+GenG0.menu.pnum.GENERIC_G031C6UX=Generic G031C6Ux
+GenG0.menu.pnum.GENERIC_G031C6UX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G031C6UX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G031C6UX.build.board=GENERIC_G031C6UX
+GenG0.menu.pnum.GENERIC_G031C6UX.build.product_line=STM32G031xx
+GenG0.menu.pnum.GENERIC_G031C6UX.build.variant=STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)
+
+# Generic G031C8Ux
+GenG0.menu.pnum.GENERIC_G031C8UX=Generic G031C8Ux
+GenG0.menu.pnum.GENERIC_G031C8UX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G031C8UX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G031C8UX.build.board=GENERIC_G031C8UX
+GenG0.menu.pnum.GENERIC_G031C8UX.build.product_line=STM32G031xx
+GenG0.menu.pnum.GENERIC_G031C8UX.build.variant=STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)
+
+# Generic G031G4Ux
+GenG0.menu.pnum.GENERIC_G031G4UX=Generic G031G4Ux
+GenG0.menu.pnum.GENERIC_G031G4UX.upload.maximum_size=16384
+GenG0.menu.pnum.GENERIC_G031G4UX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G031G4UX.build.board=GENERIC_G031G4UX
+GenG0.menu.pnum.GENERIC_G031G4UX.build.product_line=STM32G031xx
+GenG0.menu.pnum.GENERIC_G031G4UX.build.variant=STM32G0xx/G031G(4-6-8)U_G041G(6-8)U
+
+# Generic G031G6Ux
+GenG0.menu.pnum.GENERIC_G031G6UX=Generic G031G6Ux
+GenG0.menu.pnum.GENERIC_G031G6UX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G031G6UX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G031G6UX.build.board=GENERIC_G031G6UX
+GenG0.menu.pnum.GENERIC_G031G6UX.build.product_line=STM32G031xx
+GenG0.menu.pnum.GENERIC_G031G6UX.build.variant=STM32G0xx/G031G(4-6-8)U_G041G(6-8)U
+
+# Generic G031G8Ux
+GenG0.menu.pnum.GENERIC_G031G8UX=Generic G031G8Ux
+GenG0.menu.pnum.GENERIC_G031G8UX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G031G8UX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G031G8UX.build.board=GENERIC_G031G8UX
+GenG0.menu.pnum.GENERIC_G031G8UX.build.product_line=STM32G031xx
+GenG0.menu.pnum.GENERIC_G031G8UX.build.variant=STM32G0xx/G031G(4-6-8)U_G041G(6-8)U
+
+# Generic G041G6Ux
+GenG0.menu.pnum.GENERIC_G041G6UX=Generic G041G6Ux
+GenG0.menu.pnum.GENERIC_G041G6UX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G041G6UX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G041G6UX.build.board=GENERIC_G041G6UX
+GenG0.menu.pnum.GENERIC_G041G6UX.build.product_line=STM32G041xx
+GenG0.menu.pnum.GENERIC_G041G6UX.build.variant=STM32G0xx/G031G(4-6-8)U_G041G(6-8)U
+
+# Generic G041G8Ux
+GenG0.menu.pnum.GENERIC_G041G8UX=Generic G041G8Ux
+GenG0.menu.pnum.GENERIC_G041G8UX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G041G8UX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G041G8UX.build.board=GENERIC_G041G8UX
+GenG0.menu.pnum.GENERIC_G041G8UX.build.product_line=STM32G041xx
+GenG0.menu.pnum.GENERIC_G041G8UX.build.variant=STM32G0xx/G031G(4-6-8)U_G041G(6-8)U
+
+# Generic G041C6Tx
+GenG0.menu.pnum.GENERIC_G041C6TX=Generic G041C6Tx
+GenG0.menu.pnum.GENERIC_G041C6TX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G041C6TX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G041C6TX.build.board=GENERIC_G041C6TX
+GenG0.menu.pnum.GENERIC_G041C6TX.build.product_line=STM32G041xx
+GenG0.menu.pnum.GENERIC_G041C6TX.build.variant=STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)
+
+# Generic G041C8Tx
+GenG0.menu.pnum.GENERIC_G041C8TX=Generic G041C8Tx
+GenG0.menu.pnum.GENERIC_G041C8TX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G041C8TX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G041C8TX.build.board=GENERIC_G041C8TX
+GenG0.menu.pnum.GENERIC_G041C8TX.build.product_line=STM32G041xx
+GenG0.menu.pnum.GENERIC_G041C8TX.build.variant=STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)
+
+# Generic G041C6Ux
+GenG0.menu.pnum.GENERIC_G041C6UX=Generic G041C6Ux
+GenG0.menu.pnum.GENERIC_G041C6UX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G041C6UX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G041C6UX.build.board=GENERIC_G041C6UX
+GenG0.menu.pnum.GENERIC_G041C6UX.build.product_line=STM32G041xx
+GenG0.menu.pnum.GENERIC_G041C6UX.build.variant=STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)
+
+# Generic G041C8Ux
+GenG0.menu.pnum.GENERIC_G041C8UX=Generic G041C8Ux
+GenG0.menu.pnum.GENERIC_G041C8UX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G041C8UX.upload.maximum_data_size=8192
+GenG0.menu.pnum.GENERIC_G041C8UX.build.board=GENERIC_G041C8UX
+GenG0.menu.pnum.GENERIC_G041C8UX.build.product_line=STM32G041xx
+GenG0.menu.pnum.GENERIC_G041C8UX.build.variant=STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)
+
 # Generic G031J4Mx
 GenG0.menu.pnum.GENERIC_G031J4MX=Generic G031J4Mx
 GenG0.menu.pnum.GENERIC_G031J4MX.upload.maximum_size=16384
@@ -4312,6 +4440,254 @@ GenG0.menu.pnum.GENERIC_G041Y8YX.build.board=GENERIC_G041Y8YX
 GenG0.menu.pnum.GENERIC_G041Y8YX.build.product_line=STM32G041xx
 GenG0.menu.pnum.GENERIC_G041Y8YX.build.variant=STM32G0xx/G031F(4-6-8)P_G031Y8Y_G041F(6-8)P_G041Y8Y
 
+# Generic G050C6Tx
+GenG0.menu.pnum.GENERIC_G050C6TX=Generic G050C6Tx
+GenG0.menu.pnum.GENERIC_G050C6TX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G050C6TX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G050C6TX.build.board=GENERIC_G050C6TX
+GenG0.menu.pnum.GENERIC_G050C6TX.build.product_line=STM32G050xx
+GenG0.menu.pnum.GENERIC_G050C6TX.build.variant=STM32G0xx/G050C(6-8)T
+
+# Generic G050C8Tx
+GenG0.menu.pnum.GENERIC_G050C8TX=Generic G050C8Tx
+GenG0.menu.pnum.GENERIC_G050C8TX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G050C8TX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G050C8TX.build.board=GENERIC_G050C8TX
+GenG0.menu.pnum.GENERIC_G050C8TX.build.product_line=STM32G050xx
+GenG0.menu.pnum.GENERIC_G050C8TX.build.variant=STM32G0xx/G050C(6-8)T
+
+# Generic G050F6Px
+GenG0.menu.pnum.GENERIC_G050F6PX=Generic G050F6Px
+GenG0.menu.pnum.GENERIC_G050F6PX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G050F6PX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G050F6PX.build.board=GENERIC_G050F6PX
+GenG0.menu.pnum.GENERIC_G050F6PX.build.product_line=STM32G050xx
+GenG0.menu.pnum.GENERIC_G050F6PX.build.variant=STM32G0xx/G050F6P
+
+# Generic G050K6Tx
+GenG0.menu.pnum.GENERIC_G050K6TX=Generic G050K6Tx
+GenG0.menu.pnum.GENERIC_G050K6TX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G050K6TX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G050K6TX.build.board=GENERIC_G050K6TX
+GenG0.menu.pnum.GENERIC_G050K6TX.build.product_line=STM32G050xx
+GenG0.menu.pnum.GENERIC_G050K6TX.build.variant=STM32G0xx/G050K(6-8)T
+
+# Generic G050K8Tx
+GenG0.menu.pnum.GENERIC_G050K8TX=Generic G050K8Tx
+GenG0.menu.pnum.GENERIC_G050K8TX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G050K8TX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G050K8TX.build.board=GENERIC_G050K8TX
+GenG0.menu.pnum.GENERIC_G050K8TX.build.product_line=STM32G050xx
+GenG0.menu.pnum.GENERIC_G050K8TX.build.variant=STM32G0xx/G050K(6-8)T
+
+# Generic G051C6Tx
+GenG0.menu.pnum.GENERIC_G051C6TX=Generic G051C6Tx
+GenG0.menu.pnum.GENERIC_G051C6TX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G051C6TX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G051C6TX.build.board=GENERIC_G051C6TX
+GenG0.menu.pnum.GENERIC_G051C6TX.build.product_line=STM32G051xx
+GenG0.menu.pnum.GENERIC_G051C6TX.build.variant=STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)
+
+# Generic G051C8Tx
+GenG0.menu.pnum.GENERIC_G051C8TX=Generic G051C8Tx
+GenG0.menu.pnum.GENERIC_G051C8TX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G051C8TX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G051C8TX.build.board=GENERIC_G051C8TX
+GenG0.menu.pnum.GENERIC_G051C8TX.build.product_line=STM32G051xx
+GenG0.menu.pnum.GENERIC_G051C8TX.build.variant=STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)
+
+# Generic G051C6Ux
+GenG0.menu.pnum.GENERIC_G051C6UX=Generic G051C6Ux
+GenG0.menu.pnum.GENERIC_G051C6UX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G051C6UX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G051C6UX.build.board=GENERIC_G051C6UX
+GenG0.menu.pnum.GENERIC_G051C6UX.build.product_line=STM32G051xx
+GenG0.menu.pnum.GENERIC_G051C6UX.build.variant=STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)
+
+# Generic G051C8Ux
+GenG0.menu.pnum.GENERIC_G051C8UX=Generic G051C8Ux
+GenG0.menu.pnum.GENERIC_G051C8UX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G051C8UX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G051C8UX.build.board=GENERIC_G051C8UX
+GenG0.menu.pnum.GENERIC_G051C8UX.build.product_line=STM32G051xx
+GenG0.menu.pnum.GENERIC_G051C8UX.build.variant=STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)
+
+# Generic G061C6Tx
+GenG0.menu.pnum.GENERIC_G061C6TX=Generic G061C6Tx
+GenG0.menu.pnum.GENERIC_G061C6TX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G061C6TX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G061C6TX.build.board=GENERIC_G061C6TX
+GenG0.menu.pnum.GENERIC_G061C6TX.build.product_line=STM32G061xx
+GenG0.menu.pnum.GENERIC_G061C6TX.build.variant=STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)
+
+# Generic G061C8Tx
+GenG0.menu.pnum.GENERIC_G061C8TX=Generic G061C8Tx
+GenG0.menu.pnum.GENERIC_G061C8TX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G061C8TX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G061C8TX.build.board=GENERIC_G061C8TX
+GenG0.menu.pnum.GENERIC_G061C8TX.build.product_line=STM32G061xx
+GenG0.menu.pnum.GENERIC_G061C8TX.build.variant=STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)
+
+# Generic G061C6Ux
+GenG0.menu.pnum.GENERIC_G061C6UX=Generic G061C6Ux
+GenG0.menu.pnum.GENERIC_G061C6UX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G061C6UX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G061C6UX.build.board=GENERIC_G061C6UX
+GenG0.menu.pnum.GENERIC_G061C6UX.build.product_line=STM32G061xx
+GenG0.menu.pnum.GENERIC_G061C6UX.build.variant=STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)
+
+# Generic G061C8Ux
+GenG0.menu.pnum.GENERIC_G061C8UX=Generic G061C8Ux
+GenG0.menu.pnum.GENERIC_G061C8UX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G061C8UX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G061C8UX.build.board=GENERIC_G061C8UX
+GenG0.menu.pnum.GENERIC_G061C8UX.build.product_line=STM32G061xx
+GenG0.menu.pnum.GENERIC_G061C8UX.build.variant=STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)
+
+# Generic G051F6Px
+GenG0.menu.pnum.GENERIC_G051F6PX=Generic G051F6Px
+GenG0.menu.pnum.GENERIC_G051F6PX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G051F6PX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G051F6PX.build.board=GENERIC_G051F6PX
+GenG0.menu.pnum.GENERIC_G051F6PX.build.product_line=STM32G051xx
+GenG0.menu.pnum.GENERIC_G051F6PX.build.variant=STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)
+
+# Generic G051F8Px
+GenG0.menu.pnum.GENERIC_G051F8PX=Generic G051F8Px
+GenG0.menu.pnum.GENERIC_G051F8PX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G051F8PX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G051F8PX.build.board=GENERIC_G051F8PX
+GenG0.menu.pnum.GENERIC_G051F8PX.build.product_line=STM32G051xx
+GenG0.menu.pnum.GENERIC_G051F8PX.build.variant=STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)
+
+# Generic G051F8Yx
+GenG0.menu.pnum.GENERIC_G051F8YX=Generic G051F8Yx
+GenG0.menu.pnum.GENERIC_G051F8YX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G051F8YX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G051F8YX.build.board=GENERIC_G051F8YX
+GenG0.menu.pnum.GENERIC_G051F8YX.build.product_line=STM32G051xx
+GenG0.menu.pnum.GENERIC_G051F8YX.build.variant=STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)
+
+# Generic G061F6Px
+GenG0.menu.pnum.GENERIC_G061F6PX=Generic G061F6Px
+GenG0.menu.pnum.GENERIC_G061F6PX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G061F6PX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G061F6PX.build.board=GENERIC_G061F6PX
+GenG0.menu.pnum.GENERIC_G061F6PX.build.product_line=STM32G061xx
+GenG0.menu.pnum.GENERIC_G061F6PX.build.variant=STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)
+
+# Generic G061F8Px
+GenG0.menu.pnum.GENERIC_G061F8PX=Generic G061F8Px
+GenG0.menu.pnum.GENERIC_G061F8PX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G061F8PX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G061F8PX.build.board=GENERIC_G061F8PX
+GenG0.menu.pnum.GENERIC_G061F8PX.build.product_line=STM32G061xx
+GenG0.menu.pnum.GENERIC_G061F8PX.build.variant=STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)
+
+# Generic G061F8Yx
+GenG0.menu.pnum.GENERIC_G061F8YX=Generic G061F8Yx
+GenG0.menu.pnum.GENERIC_G061F8YX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G061F8YX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G061F8YX.build.board=GENERIC_G061F8YX
+GenG0.menu.pnum.GENERIC_G061F8YX.build.product_line=STM32G061xx
+GenG0.menu.pnum.GENERIC_G061F8YX.build.variant=STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)
+
+# Generic G051G6Ux
+GenG0.menu.pnum.GENERIC_G051G6UX=Generic G051G6Ux
+GenG0.menu.pnum.GENERIC_G051G6UX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G051G6UX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G051G6UX.build.board=GENERIC_G051G6UX
+GenG0.menu.pnum.GENERIC_G051G6UX.build.product_line=STM32G051xx
+GenG0.menu.pnum.GENERIC_G051G6UX.build.variant=STM32G0xx/G051G(6-8)U_G061G(6-8)U
+
+# Generic G051G8Ux
+GenG0.menu.pnum.GENERIC_G051G8UX=Generic G051G8Ux
+GenG0.menu.pnum.GENERIC_G051G8UX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G051G8UX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G051G8UX.build.board=GENERIC_G051G8UX
+GenG0.menu.pnum.GENERIC_G051G8UX.build.product_line=STM32G051xx
+GenG0.menu.pnum.GENERIC_G051G8UX.build.variant=STM32G0xx/G051G(6-8)U_G061G(6-8)U
+
+# Generic G061G6Ux
+GenG0.menu.pnum.GENERIC_G061G6UX=Generic G061G6Ux
+GenG0.menu.pnum.GENERIC_G061G6UX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G061G6UX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G061G6UX.build.board=GENERIC_G061G6UX
+GenG0.menu.pnum.GENERIC_G061G6UX.build.product_line=STM32G061xx
+GenG0.menu.pnum.GENERIC_G061G6UX.build.variant=STM32G0xx/G051G(6-8)U_G061G(6-8)U
+
+# Generic G061G8Ux
+GenG0.menu.pnum.GENERIC_G061G8UX=Generic G061G8Ux
+GenG0.menu.pnum.GENERIC_G061G8UX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G061G8UX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G061G8UX.build.board=GENERIC_G061G8UX
+GenG0.menu.pnum.GENERIC_G061G8UX.build.product_line=STM32G061xx
+GenG0.menu.pnum.GENERIC_G061G8UX.build.variant=STM32G0xx/G051G(6-8)U_G061G(6-8)U
+
+# Generic G051K6Tx
+GenG0.menu.pnum.GENERIC_G051K6TX=Generic G051K6Tx
+GenG0.menu.pnum.GENERIC_G051K6TX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G051K6TX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G051K6TX.build.board=GENERIC_G051K6TX
+GenG0.menu.pnum.GENERIC_G051K6TX.build.product_line=STM32G051xx
+GenG0.menu.pnum.GENERIC_G051K6TX.build.variant=STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)
+
+# Generic G051K8Tx
+GenG0.menu.pnum.GENERIC_G051K8TX=Generic G051K8Tx
+GenG0.menu.pnum.GENERIC_G051K8TX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G051K8TX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G051K8TX.build.board=GENERIC_G051K8TX
+GenG0.menu.pnum.GENERIC_G051K8TX.build.product_line=STM32G051xx
+GenG0.menu.pnum.GENERIC_G051K8TX.build.variant=STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)
+
+# Generic G051K6Ux
+GenG0.menu.pnum.GENERIC_G051K6UX=Generic G051K6Ux
+GenG0.menu.pnum.GENERIC_G051K6UX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G051K6UX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G051K6UX.build.board=GENERIC_G051K6UX
+GenG0.menu.pnum.GENERIC_G051K6UX.build.product_line=STM32G051xx
+GenG0.menu.pnum.GENERIC_G051K6UX.build.variant=STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)
+
+# Generic G051K8Ux
+GenG0.menu.pnum.GENERIC_G051K8UX=Generic G051K8Ux
+GenG0.menu.pnum.GENERIC_G051K8UX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G051K8UX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G051K8UX.build.board=GENERIC_G051K8UX
+GenG0.menu.pnum.GENERIC_G051K8UX.build.product_line=STM32G051xx
+GenG0.menu.pnum.GENERIC_G051K8UX.build.variant=STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)
+
+# Generic G061K6Tx
+GenG0.menu.pnum.GENERIC_G061K6TX=Generic G061K6Tx
+GenG0.menu.pnum.GENERIC_G061K6TX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G061K6TX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G061K6TX.build.board=GENERIC_G061K6TX
+GenG0.menu.pnum.GENERIC_G061K6TX.build.product_line=STM32G061xx
+GenG0.menu.pnum.GENERIC_G061K6TX.build.variant=STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)
+
+# Generic G061K8Tx
+GenG0.menu.pnum.GENERIC_G061K8TX=Generic G061K8Tx
+GenG0.menu.pnum.GENERIC_G061K8TX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G061K8TX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G061K8TX.build.board=GENERIC_G061K8TX
+GenG0.menu.pnum.GENERIC_G061K8TX.build.product_line=STM32G061xx
+GenG0.menu.pnum.GENERIC_G061K8TX.build.variant=STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)
+
+# Generic G061K6Ux
+GenG0.menu.pnum.GENERIC_G061K6UX=Generic G061K6Ux
+GenG0.menu.pnum.GENERIC_G061K6UX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G061K6UX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G061K6UX.build.board=GENERIC_G061K6UX
+GenG0.menu.pnum.GENERIC_G061K6UX.build.product_line=STM32G061xx
+GenG0.menu.pnum.GENERIC_G061K6UX.build.variant=STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)
+
+# Generic G061K8Ux
+GenG0.menu.pnum.GENERIC_G061K8UX=Generic G061K8Ux
+GenG0.menu.pnum.GENERIC_G061K8UX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G061K8UX.upload.maximum_data_size=18432
+GenG0.menu.pnum.GENERIC_G061K8UX.build.board=GENERIC_G061K8UX
+GenG0.menu.pnum.GENERIC_G061K8UX.build.product_line=STM32G061xx
+GenG0.menu.pnum.GENERIC_G061K8UX.build.variant=STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)
+
 # Generic G070CBTx
 GenG0.menu.pnum.GENERIC_G070CBTX=Generic G070CBTx
 GenG0.menu.pnum.GENERIC_G070CBTX.upload.maximum_size=131072
@@ -4320,6 +4696,54 @@ GenG0.menu.pnum.GENERIC_G070CBTX.build.board=GENERIC_G070CBTX
 GenG0.menu.pnum.GENERIC_G070CBTX.build.product_line=STM32G070xx
 GenG0.menu.pnum.GENERIC_G070CBTX.build.variant=STM32G0xx/G070CBT
 
+# Generic G071EBYx
+GenG0.menu.pnum.GENERIC_G071EBYX=Generic G071EBYx
+GenG0.menu.pnum.GENERIC_G071EBYX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G071EBYX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G071EBYX.build.board=GENERIC_G071EBYX
+GenG0.menu.pnum.GENERIC_G071EBYX.build.product_line=STM32G071xx
+GenG0.menu.pnum.GENERIC_G071EBYX.build.variant=STM32G0xx/G071EBY_G081EBY
+
+# Generic G081EBYx
+GenG0.menu.pnum.GENERIC_G081EBYX=Generic G081EBYx
+GenG0.menu.pnum.GENERIC_G081EBYX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G081EBYX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G081EBYX.build.board=GENERIC_G081EBYX
+GenG0.menu.pnum.GENERIC_G081EBYX.build.product_line=STM32G081xx
+GenG0.menu.pnum.GENERIC_G081EBYX.build.variant=STM32G0xx/G071EBY_G081EBY
+
+# Generic G071G6Ux
+GenG0.menu.pnum.GENERIC_G071G6UX=Generic G071G6Ux
+GenG0.menu.pnum.GENERIC_G071G6UX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G071G6UX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G071G6UX.build.board=GENERIC_G071G6UX
+GenG0.menu.pnum.GENERIC_G071G6UX.build.product_line=STM32G071xx
+GenG0.menu.pnum.GENERIC_G071G6UX.build.variant=STM32G0xx/G071G(6-8-B)U_G081GBU
+
+# Generic G071G8Ux
+GenG0.menu.pnum.GENERIC_G071G8UX=Generic G071G8Ux
+GenG0.menu.pnum.GENERIC_G071G8UX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G071G8UX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G071G8UX.build.board=GENERIC_G071G8UX
+GenG0.menu.pnum.GENERIC_G071G8UX.build.product_line=STM32G071xx
+GenG0.menu.pnum.GENERIC_G071G8UX.build.variant=STM32G0xx/G071G(6-8-B)U_G081GBU
+
+# Generic G071GBUx
+GenG0.menu.pnum.GENERIC_G071GBUX=Generic G071GBUx
+GenG0.menu.pnum.GENERIC_G071GBUX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G071GBUX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G071GBUX.build.board=GENERIC_G071GBUX
+GenG0.menu.pnum.GENERIC_G071GBUX.build.product_line=STM32G071xx
+GenG0.menu.pnum.GENERIC_G071GBUX.build.variant=STM32G0xx/G071G(6-8-B)U_G081GBU
+
+# Generic G081GBUx
+GenG0.menu.pnum.GENERIC_G081GBUX=Generic G081GBUx
+GenG0.menu.pnum.GENERIC_G081GBUX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G081GBUX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G081GBUX.build.board=GENERIC_G081GBUX
+GenG0.menu.pnum.GENERIC_G081GBUX.build.product_line=STM32G081xx
+GenG0.menu.pnum.GENERIC_G081GBUX.build.variant=STM32G0xx/G071G(6-8-B)U_G081GBU
+
 # Generic G070KBTx
 GenG0.menu.pnum.GENERIC_G070KBTX=Generic G070KBTx
 GenG0.menu.pnum.GENERIC_G070KBTX.upload.maximum_size=131072
@@ -4400,6 +4824,70 @@ GenG0.menu.pnum.GENERIC_G071GBUXN.build.board=GENERIC_G071GBUXN
 GenG0.menu.pnum.GENERIC_G071GBUXN.build.product_line=STM32G071xx
 GenG0.menu.pnum.GENERIC_G071GBUXN.build.variant=STM32G0xx/G071G(8-B)UxN_G081GBUxN
 
+# Generic G071K6Tx
+GenG0.menu.pnum.GENERIC_G071K6TX=Generic G071K6Tx
+GenG0.menu.pnum.GENERIC_G071K6TX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G071K6TX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G071K6TX.build.board=GENERIC_G071K6TX
+GenG0.menu.pnum.GENERIC_G071K6TX.build.product_line=STM32G071xx
+GenG0.menu.pnum.GENERIC_G071K6TX.build.variant=STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)
+
+# Generic G071K8Tx
+GenG0.menu.pnum.GENERIC_G071K8TX=Generic G071K8Tx
+GenG0.menu.pnum.GENERIC_G071K8TX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G071K8TX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G071K8TX.build.board=GENERIC_G071K8TX
+GenG0.menu.pnum.GENERIC_G071K8TX.build.product_line=STM32G071xx
+GenG0.menu.pnum.GENERIC_G071K8TX.build.variant=STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)
+
+# Generic G071KBTx
+GenG0.menu.pnum.GENERIC_G071KBTX=Generic G071KBTx
+GenG0.menu.pnum.GENERIC_G071KBTX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G071KBTX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G071KBTX.build.board=GENERIC_G071KBTX
+GenG0.menu.pnum.GENERIC_G071KBTX.build.product_line=STM32G071xx
+GenG0.menu.pnum.GENERIC_G071KBTX.build.variant=STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)
+
+# Generic G071K6Ux
+GenG0.menu.pnum.GENERIC_G071K6UX=Generic G071K6Ux
+GenG0.menu.pnum.GENERIC_G071K6UX.upload.maximum_size=32768
+GenG0.menu.pnum.GENERIC_G071K6UX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G071K6UX.build.board=GENERIC_G071K6UX
+GenG0.menu.pnum.GENERIC_G071K6UX.build.product_line=STM32G071xx
+GenG0.menu.pnum.GENERIC_G071K6UX.build.variant=STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)
+
+# Generic G071K8Ux
+GenG0.menu.pnum.GENERIC_G071K8UX=Generic G071K8Ux
+GenG0.menu.pnum.GENERIC_G071K8UX.upload.maximum_size=65536
+GenG0.menu.pnum.GENERIC_G071K8UX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G071K8UX.build.board=GENERIC_G071K8UX
+GenG0.menu.pnum.GENERIC_G071K8UX.build.product_line=STM32G071xx
+GenG0.menu.pnum.GENERIC_G071K8UX.build.variant=STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)
+
+# Generic G071KBUx
+GenG0.menu.pnum.GENERIC_G071KBUX=Generic G071KBUx
+GenG0.menu.pnum.GENERIC_G071KBUX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G071KBUX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G071KBUX.build.board=GENERIC_G071KBUX
+GenG0.menu.pnum.GENERIC_G071KBUX.build.product_line=STM32G071xx
+GenG0.menu.pnum.GENERIC_G071KBUX.build.variant=STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)
+
+# Generic G081KBTx
+GenG0.menu.pnum.GENERIC_G081KBTX=Generic G081KBTx
+GenG0.menu.pnum.GENERIC_G081KBTX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G081KBTX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G081KBTX.build.board=GENERIC_G081KBTX
+GenG0.menu.pnum.GENERIC_G081KBTX.build.product_line=STM32G081xx
+GenG0.menu.pnum.GENERIC_G081KBTX.build.variant=STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)
+
+# Generic G081KBUx
+GenG0.menu.pnum.GENERIC_G081KBUX=Generic G081KBUx
+GenG0.menu.pnum.GENERIC_G081KBUX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G081KBUX.upload.maximum_data_size=36864
+GenG0.menu.pnum.GENERIC_G081KBUX.build.board=GENERIC_G081KBUX
+GenG0.menu.pnum.GENERIC_G081KBUX.build.product_line=STM32G081xx
+GenG0.menu.pnum.GENERIC_G081KBUX.build.variant=STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)
+
 # Generic G071R6Tx
 GenG0.menu.pnum.GENERIC_G071R6TX=Generic G071R6Tx
 GenG0.menu.pnum.GENERIC_G071R6TX.upload.maximum_size=32768
@@ -4472,6 +4960,214 @@ GenG0.menu.pnum.GENERIC_G081RBTX.build.board=GENERIC_G081RBTX
 GenG0.menu.pnum.GENERIC_G081RBTX.build.product_line=STM32G081xx
 GenG0.menu.pnum.GENERIC_G081RBTX.build.variant=STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)
 
+# Generic G0B0CETx
+GenG0.menu.pnum.GENERIC_G0B0CETX=Generic G0B0CETx
+GenG0.menu.pnum.GENERIC_G0B0CETX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0B0CETX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B0CETX.build.board=GENERIC_G0B0CETX
+GenG0.menu.pnum.GENERIC_G0B0CETX.build.product_line=STM32G0B0xx
+GenG0.menu.pnum.GENERIC_G0B0CETX.build.variant=STM32G0xx/G0B0CET
+
+# Generic G0B0RETx
+GenG0.menu.pnum.GENERIC_G0B0RETX=Generic G0B0RETx
+GenG0.menu.pnum.GENERIC_G0B0RETX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0B0RETX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B0RETX.build.board=GENERIC_G0B0RETX
+GenG0.menu.pnum.GENERIC_G0B0RETX.build.product_line=STM32G0B0xx
+GenG0.menu.pnum.GENERIC_G0B0RETX.build.variant=STM32G0xx/G0B0RET
+
+# Generic G0B0VETx
+GenG0.menu.pnum.GENERIC_G0B0VETX=Generic G0B0VETx
+GenG0.menu.pnum.GENERIC_G0B0VETX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0B0VETX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B0VETX.build.board=GENERIC_G0B0VETX
+GenG0.menu.pnum.GENERIC_G0B0VETX.build.product_line=STM32G0B0xx
+GenG0.menu.pnum.GENERIC_G0B0VETX.build.variant=STM32G0xx/G0B0VET
+
+# Generic G0B1CBTx
+GenG0.menu.pnum.GENERIC_G0B1CBTX=Generic G0B1CBTx
+GenG0.menu.pnum.GENERIC_G0B1CBTX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G0B1CBTX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1CBTX.build.board=GENERIC_G0B1CBTX
+GenG0.menu.pnum.GENERIC_G0B1CBTX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1CBTX.build.variant=STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)
+
+# Generic G0B1CCTx
+GenG0.menu.pnum.GENERIC_G0B1CCTX=Generic G0B1CCTx
+GenG0.menu.pnum.GENERIC_G0B1CCTX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0B1CCTX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1CCTX.build.board=GENERIC_G0B1CCTX
+GenG0.menu.pnum.GENERIC_G0B1CCTX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1CCTX.build.variant=STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)
+
+# Generic G0B1CETx
+GenG0.menu.pnum.GENERIC_G0B1CETX=Generic G0B1CETx
+GenG0.menu.pnum.GENERIC_G0B1CETX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0B1CETX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1CETX.build.board=GENERIC_G0B1CETX
+GenG0.menu.pnum.GENERIC_G0B1CETX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1CETX.build.variant=STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)
+
+# Generic G0B1CBUx
+GenG0.menu.pnum.GENERIC_G0B1CBUX=Generic G0B1CBUx
+GenG0.menu.pnum.GENERIC_G0B1CBUX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G0B1CBUX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1CBUX.build.board=GENERIC_G0B1CBUX
+GenG0.menu.pnum.GENERIC_G0B1CBUX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1CBUX.build.variant=STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)
+
+# Generic G0B1CCUx
+GenG0.menu.pnum.GENERIC_G0B1CCUX=Generic G0B1CCUx
+GenG0.menu.pnum.GENERIC_G0B1CCUX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0B1CCUX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1CCUX.build.board=GENERIC_G0B1CCUX
+GenG0.menu.pnum.GENERIC_G0B1CCUX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1CCUX.build.variant=STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)
+
+# Generic G0B1CEUx
+GenG0.menu.pnum.GENERIC_G0B1CEUX=Generic G0B1CEUx
+GenG0.menu.pnum.GENERIC_G0B1CEUX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0B1CEUX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1CEUX.build.board=GENERIC_G0B1CEUX
+GenG0.menu.pnum.GENERIC_G0B1CEUX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1CEUX.build.variant=STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)
+
+# Generic G0B1KBTx
+GenG0.menu.pnum.GENERIC_G0B1KBTX=Generic G0B1KBTx
+GenG0.menu.pnum.GENERIC_G0B1KBTX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G0B1KBTX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1KBTX.build.board=GENERIC_G0B1KBTX
+GenG0.menu.pnum.GENERIC_G0B1KBTX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1KBTX.build.variant=STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)
+
+# Generic G0B1KCTx
+GenG0.menu.pnum.GENERIC_G0B1KCTX=Generic G0B1KCTx
+GenG0.menu.pnum.GENERIC_G0B1KCTX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0B1KCTX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1KCTX.build.board=GENERIC_G0B1KCTX
+GenG0.menu.pnum.GENERIC_G0B1KCTX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1KCTX.build.variant=STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)
+
+# Generic G0B1KETx
+GenG0.menu.pnum.GENERIC_G0B1KETX=Generic G0B1KETx
+GenG0.menu.pnum.GENERIC_G0B1KETX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0B1KETX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1KETX.build.board=GENERIC_G0B1KETX
+GenG0.menu.pnum.GENERIC_G0B1KETX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1KETX.build.variant=STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)
+
+# Generic G0B1KBUx
+GenG0.menu.pnum.GENERIC_G0B1KBUX=Generic G0B1KBUx
+GenG0.menu.pnum.GENERIC_G0B1KBUX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G0B1KBUX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1KBUX.build.board=GENERIC_G0B1KBUX
+GenG0.menu.pnum.GENERIC_G0B1KBUX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1KBUX.build.variant=STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)
+
+# Generic G0B1KCUx
+GenG0.menu.pnum.GENERIC_G0B1KCUX=Generic G0B1KCUx
+GenG0.menu.pnum.GENERIC_G0B1KCUX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0B1KCUX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1KCUX.build.board=GENERIC_G0B1KCUX
+GenG0.menu.pnum.GENERIC_G0B1KCUX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1KCUX.build.variant=STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)
+
+# Generic G0B1KEUx
+GenG0.menu.pnum.GENERIC_G0B1KEUX=Generic G0B1KEUx
+GenG0.menu.pnum.GENERIC_G0B1KEUX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0B1KEUX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1KEUX.build.board=GENERIC_G0B1KEUX
+GenG0.menu.pnum.GENERIC_G0B1KEUX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1KEUX.build.variant=STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)
+
+# Generic G0C1KCTx
+GenG0.menu.pnum.GENERIC_G0C1KCTX=Generic G0C1KCTx
+GenG0.menu.pnum.GENERIC_G0C1KCTX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0C1KCTX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1KCTX.build.board=GENERIC_G0C1KCTX
+GenG0.menu.pnum.GENERIC_G0C1KCTX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1KCTX.build.variant=STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)
+
+# Generic G0C1KETx
+GenG0.menu.pnum.GENERIC_G0C1KETX=Generic G0C1KETx
+GenG0.menu.pnum.GENERIC_G0C1KETX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0C1KETX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1KETX.build.board=GENERIC_G0C1KETX
+GenG0.menu.pnum.GENERIC_G0C1KETX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1KETX.build.variant=STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)
+
+# Generic G0C1KCUx
+GenG0.menu.pnum.GENERIC_G0C1KCUX=Generic G0C1KCUx
+GenG0.menu.pnum.GENERIC_G0C1KCUX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0C1KCUX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1KCUX.build.board=GENERIC_G0C1KCUX
+GenG0.menu.pnum.GENERIC_G0C1KCUX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1KCUX.build.variant=STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)
+
+# Generic G0C1KEUx
+GenG0.menu.pnum.GENERIC_G0C1KEUX=Generic G0C1KEUx
+GenG0.menu.pnum.GENERIC_G0C1KEUX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0C1KEUX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1KEUX.build.board=GENERIC_G0C1KEUX
+GenG0.menu.pnum.GENERIC_G0C1KEUX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1KEUX.build.variant=STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)
+
+# Generic G0B1MBTx
+GenG0.menu.pnum.GENERIC_G0B1MBTX=Generic G0B1MBTx
+GenG0.menu.pnum.GENERIC_G0B1MBTX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G0B1MBTX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1MBTX.build.board=GENERIC_G0B1MBTX
+GenG0.menu.pnum.GENERIC_G0B1MBTX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1MBTX.build.variant=STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T
+
+# Generic G0B1MCTx
+GenG0.menu.pnum.GENERIC_G0B1MCTX=Generic G0B1MCTx
+GenG0.menu.pnum.GENERIC_G0B1MCTX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0B1MCTX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1MCTX.build.board=GENERIC_G0B1MCTX
+GenG0.menu.pnum.GENERIC_G0B1MCTX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1MCTX.build.variant=STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T
+
+# Generic G0B1METx
+GenG0.menu.pnum.GENERIC_G0B1METX=Generic G0B1METx
+GenG0.menu.pnum.GENERIC_G0B1METX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0B1METX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1METX.build.board=GENERIC_G0B1METX
+GenG0.menu.pnum.GENERIC_G0B1METX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1METX.build.variant=STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T
+
+# Generic G0C1MCTx
+GenG0.menu.pnum.GENERIC_G0C1MCTX=Generic G0C1MCTx
+GenG0.menu.pnum.GENERIC_G0C1MCTX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0C1MCTX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1MCTX.build.board=GENERIC_G0C1MCTX
+GenG0.menu.pnum.GENERIC_G0C1MCTX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1MCTX.build.variant=STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T
+
+# Generic G0C1METx
+GenG0.menu.pnum.GENERIC_G0C1METX=Generic G0C1METx
+GenG0.menu.pnum.GENERIC_G0C1METX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0C1METX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1METX.build.board=GENERIC_G0C1METX
+GenG0.menu.pnum.GENERIC_G0C1METX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1METX.build.variant=STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T
+
+# Generic G0B1NEYx
+GenG0.menu.pnum.GENERIC_G0B1NEYX=Generic G0B1NEYx
+GenG0.menu.pnum.GENERIC_G0B1NEYX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0B1NEYX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1NEYX.build.board=GENERIC_G0B1NEYX
+GenG0.menu.pnum.GENERIC_G0B1NEYX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1NEYX.build.variant=STM32G0xx/G0B1NEY_G0C1NEY
+
+# Generic G0C1NEYx
+GenG0.menu.pnum.GENERIC_G0C1NEYX=Generic G0C1NEYx
+GenG0.menu.pnum.GENERIC_G0C1NEYX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0C1NEYX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1NEYX.build.board=GENERIC_G0C1NEYX
+GenG0.menu.pnum.GENERIC_G0C1NEYX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1NEYX.build.variant=STM32G0xx/G0B1NEY_G0C1NEY
+
 # Generic G0B1RBTx
 GenG0.menu.pnum.GENERIC_G0B1RBTX=Generic G0B1RBTx
 GenG0.menu.pnum.GENERIC_G0B1RBTX.upload.maximum_size=131072
@@ -4496,6 +5192,118 @@ GenG0.menu.pnum.GENERIC_G0B1RETX.build.board=GENERIC_G0B1RETX
 GenG0.menu.pnum.GENERIC_G0B1RETX.build.product_line=STM32G0B1xx
 GenG0.menu.pnum.GENERIC_G0B1RETX.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T
 
+# Generic G0B1VBIx
+GenG0.menu.pnum.GENERIC_G0B1VBIX=Generic G0B1VBIx
+GenG0.menu.pnum.GENERIC_G0B1VBIX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G0B1VBIX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1VBIX.build.board=GENERIC_G0B1VBIX
+GenG0.menu.pnum.GENERIC_G0B1VBIX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1VBIX.build.variant=STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)
+
+# Generic G0B1VCIx
+GenG0.menu.pnum.GENERIC_G0B1VCIX=Generic G0B1VCIx
+GenG0.menu.pnum.GENERIC_G0B1VCIX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0B1VCIX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1VCIX.build.board=GENERIC_G0B1VCIX
+GenG0.menu.pnum.GENERIC_G0B1VCIX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1VCIX.build.variant=STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)
+
+# Generic G0B1VEIx
+GenG0.menu.pnum.GENERIC_G0B1VEIX=Generic G0B1VEIx
+GenG0.menu.pnum.GENERIC_G0B1VEIX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0B1VEIX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1VEIX.build.board=GENERIC_G0B1VEIX
+GenG0.menu.pnum.GENERIC_G0B1VEIX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1VEIX.build.variant=STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)
+
+# Generic G0B1VBTx
+GenG0.menu.pnum.GENERIC_G0B1VBTX=Generic G0B1VBTx
+GenG0.menu.pnum.GENERIC_G0B1VBTX.upload.maximum_size=131072
+GenG0.menu.pnum.GENERIC_G0B1VBTX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1VBTX.build.board=GENERIC_G0B1VBTX
+GenG0.menu.pnum.GENERIC_G0B1VBTX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1VBTX.build.variant=STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)
+
+# Generic G0B1VCTx
+GenG0.menu.pnum.GENERIC_G0B1VCTX=Generic G0B1VCTx
+GenG0.menu.pnum.GENERIC_G0B1VCTX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0B1VCTX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1VCTX.build.board=GENERIC_G0B1VCTX
+GenG0.menu.pnum.GENERIC_G0B1VCTX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1VCTX.build.variant=STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)
+
+# Generic G0B1VETx
+GenG0.menu.pnum.GENERIC_G0B1VETX=Generic G0B1VETx
+GenG0.menu.pnum.GENERIC_G0B1VETX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0B1VETX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0B1VETX.build.board=GENERIC_G0B1VETX
+GenG0.menu.pnum.GENERIC_G0B1VETX.build.product_line=STM32G0B1xx
+GenG0.menu.pnum.GENERIC_G0B1VETX.build.variant=STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)
+
+# Generic G0C1VCIx
+GenG0.menu.pnum.GENERIC_G0C1VCIX=Generic G0C1VCIx
+GenG0.menu.pnum.GENERIC_G0C1VCIX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0C1VCIX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1VCIX.build.board=GENERIC_G0C1VCIX
+GenG0.menu.pnum.GENERIC_G0C1VCIX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1VCIX.build.variant=STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)
+
+# Generic G0C1VEIx
+GenG0.menu.pnum.GENERIC_G0C1VEIX=Generic G0C1VEIx
+GenG0.menu.pnum.GENERIC_G0C1VEIX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0C1VEIX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1VEIX.build.board=GENERIC_G0C1VEIX
+GenG0.menu.pnum.GENERIC_G0C1VEIX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1VEIX.build.variant=STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)
+
+# Generic G0C1VCTx
+GenG0.menu.pnum.GENERIC_G0C1VCTX=Generic G0C1VCTx
+GenG0.menu.pnum.GENERIC_G0C1VCTX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0C1VCTX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1VCTX.build.board=GENERIC_G0C1VCTX
+GenG0.menu.pnum.GENERIC_G0C1VCTX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1VCTX.build.variant=STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)
+
+# Generic G0C1VETx
+GenG0.menu.pnum.GENERIC_G0C1VETX=Generic G0C1VETx
+GenG0.menu.pnum.GENERIC_G0C1VETX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0C1VETX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1VETX.build.board=GENERIC_G0C1VETX
+GenG0.menu.pnum.GENERIC_G0C1VETX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1VETX.build.variant=STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)
+
+# Generic G0C1CCTx
+GenG0.menu.pnum.GENERIC_G0C1CCTX=Generic G0C1CCTx
+GenG0.menu.pnum.GENERIC_G0C1CCTX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0C1CCTX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1CCTX.build.board=GENERIC_G0C1CCTX
+GenG0.menu.pnum.GENERIC_G0C1CCTX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1CCTX.build.variant=STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)
+
+# Generic G0C1CETx
+GenG0.menu.pnum.GENERIC_G0C1CETX=Generic G0C1CETx
+GenG0.menu.pnum.GENERIC_G0C1CETX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0C1CETX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1CETX.build.board=GENERIC_G0C1CETX
+GenG0.menu.pnum.GENERIC_G0C1CETX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1CETX.build.variant=STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)
+
+# Generic G0C1CCUx
+GenG0.menu.pnum.GENERIC_G0C1CCUX=Generic G0C1CCUx
+GenG0.menu.pnum.GENERIC_G0C1CCUX.upload.maximum_size=262144
+GenG0.menu.pnum.GENERIC_G0C1CCUX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1CCUX.build.board=GENERIC_G0C1CCUX
+GenG0.menu.pnum.GENERIC_G0C1CCUX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1CCUX.build.variant=STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)
+
+# Generic G0C1CEUx
+GenG0.menu.pnum.GENERIC_G0C1CEUX=Generic G0C1CEUx
+GenG0.menu.pnum.GENERIC_G0C1CEUX.upload.maximum_size=524288
+GenG0.menu.pnum.GENERIC_G0C1CEUX.upload.maximum_data_size=147456
+GenG0.menu.pnum.GENERIC_G0C1CEUX.build.board=GENERIC_G0C1CEUX
+GenG0.menu.pnum.GENERIC_G0C1CEUX.build.product_line=STM32G0C1xx
+GenG0.menu.pnum.GENERIC_G0C1CEUX.build.variant=STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)
+
 # Generic G0C1RCTx
 GenG0.menu.pnum.GENERIC_G0C1RCTX=Generic G0C1RCTx
 GenG0.menu.pnum.GENERIC_G0C1RCTX.upload.maximum_size=262144
@@ -4543,6 +5351,30 @@ GenG4.build.cmsis_lib_gcc=arm_cortexM4lf_math
 GenG4.upload.maximum_size=0
 GenG4.upload.maximum_data_size=0
 
+# Generic G431C6Tx
+GenG4.menu.pnum.GENERIC_G431C6TX=Generic G431C6Tx
+GenG4.menu.pnum.GENERIC_G431C6TX.upload.maximum_size=32768
+GenG4.menu.pnum.GENERIC_G431C6TX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G431C6TX.build.board=GENERIC_G431C6TX
+GenG4.menu.pnum.GENERIC_G431C6TX.build.product_line=STM32G431xx
+GenG4.menu.pnum.GENERIC_G431C6TX.build.variant=STM32G4xx/G431C(6-8-B)T_G441CBT
+
+# Generic G431C8Tx
+GenG4.menu.pnum.GENERIC_G431C8TX=Generic G431C8Tx
+GenG4.menu.pnum.GENERIC_G431C8TX.upload.maximum_size=65536
+GenG4.menu.pnum.GENERIC_G431C8TX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G431C8TX.build.board=GENERIC_G431C8TX
+GenG4.menu.pnum.GENERIC_G431C8TX.build.product_line=STM32G431xx
+GenG4.menu.pnum.GENERIC_G431C8TX.build.variant=STM32G4xx/G431C(6-8-B)T_G441CBT
+
+# Generic G431CBTx
+GenG4.menu.pnum.GENERIC_G431CBTX=Generic G431CBTx
+GenG4.menu.pnum.GENERIC_G431CBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G431CBTX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G431CBTX.build.board=GENERIC_G431CBTX
+GenG4.menu.pnum.GENERIC_G431CBTX.build.product_line=STM32G431xx
+GenG4.menu.pnum.GENERIC_G431CBTX.build.variant=STM32G4xx/G431C(6-8-B)T_G441CBT
+
 # Generic G431C6Ux
 GenG4.menu.pnum.GENERIC_G431C6UX=Generic G431C6Ux
 GenG4.menu.pnum.GENERIC_G431C6UX.upload.maximum_size=32768
@@ -4615,29 +5447,29 @@ GenG4.menu.pnum.GENERIC_G431KBUX.build.board=GENERIC_G431KBUX
 GenG4.menu.pnum.GENERIC_G431KBUX.build.product_line=STM32G431xx
 GenG4.menu.pnum.GENERIC_G431KBUX.build.variant=STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)
 
-# Generic G441CBUx
-GenG4.menu.pnum.GENERIC_G441CBUX=Generic G441CBUx
-GenG4.menu.pnum.GENERIC_G441CBUX.upload.maximum_size=131072
-GenG4.menu.pnum.GENERIC_G441CBUX.upload.maximum_data_size=32768
-GenG4.menu.pnum.GENERIC_G441CBUX.build.board=GENERIC_G441CBUX
-GenG4.menu.pnum.GENERIC_G441CBUX.build.product_line=STM32G441xx
-GenG4.menu.pnum.GENERIC_G441CBUX.build.variant=STM32G4xx/G431C(6-8-B)U_G441CBU
-
-# Generic G441KBTx
-GenG4.menu.pnum.GENERIC_G441KBTX=Generic G441KBTx
-GenG4.menu.pnum.GENERIC_G441KBTX.upload.maximum_size=131072
-GenG4.menu.pnum.GENERIC_G441KBTX.upload.maximum_data_size=32768
-GenG4.menu.pnum.GENERIC_G441KBTX.build.board=GENERIC_G441KBTX
-GenG4.menu.pnum.GENERIC_G441KBTX.build.product_line=STM32G441xx
-GenG4.menu.pnum.GENERIC_G441KBTX.build.variant=STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)
-
-# Generic G441KBUx
-GenG4.menu.pnum.GENERIC_G441KBUX=Generic G441KBUx
-GenG4.menu.pnum.GENERIC_G441KBUX.upload.maximum_size=131072
-GenG4.menu.pnum.GENERIC_G441KBUX.upload.maximum_data_size=32768
-GenG4.menu.pnum.GENERIC_G441KBUX.build.board=GENERIC_G441KBUX
-GenG4.menu.pnum.GENERIC_G441KBUX.build.product_line=STM32G441xx
-GenG4.menu.pnum.GENERIC_G441KBUX.build.variant=STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)
+# Generic G431M6Tx
+GenG4.menu.pnum.GENERIC_G431M6TX=Generic G431M6Tx
+GenG4.menu.pnum.GENERIC_G431M6TX.upload.maximum_size=32768
+GenG4.menu.pnum.GENERIC_G431M6TX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G431M6TX.build.board=GENERIC_G431M6TX
+GenG4.menu.pnum.GENERIC_G431M6TX.build.product_line=STM32G431xx
+GenG4.menu.pnum.GENERIC_G431M6TX.build.variant=STM32G4xx/G431M(6-8-B)T_G441MBT
+
+# Generic G431M8Tx
+GenG4.menu.pnum.GENERIC_G431M8TX=Generic G431M8Tx
+GenG4.menu.pnum.GENERIC_G431M8TX.upload.maximum_size=65536
+GenG4.menu.pnum.GENERIC_G431M8TX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G431M8TX.build.board=GENERIC_G431M8TX
+GenG4.menu.pnum.GENERIC_G431M8TX.build.product_line=STM32G431xx
+GenG4.menu.pnum.GENERIC_G431M8TX.build.variant=STM32G4xx/G431M(6-8-B)T_G441MBT
+
+# Generic G431MBTx
+GenG4.menu.pnum.GENERIC_G431MBTX=Generic G431MBTx
+GenG4.menu.pnum.GENERIC_G431MBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G431MBTX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G431MBTX.build.board=GENERIC_G431MBTX
+GenG4.menu.pnum.GENERIC_G431MBTX.build.product_line=STM32G431xx
+GenG4.menu.pnum.GENERIC_G431MBTX.build.variant=STM32G4xx/G431M(6-8-B)T_G441MBT
 
 # Generic G431R6Ix
 GenG4.menu.pnum.GENERIC_G431R6IX=Generic G431R6Ix
@@ -4687,6 +5519,70 @@ GenG4.menu.pnum.GENERIC_G431RBTX.build.board=GENERIC_G431RBTX
 GenG4.menu.pnum.GENERIC_G431RBTX.build.product_line=STM32G431xx
 GenG4.menu.pnum.GENERIC_G431RBTX.build.variant=STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)
 
+# Generic G431V6Tx
+GenG4.menu.pnum.GENERIC_G431V6TX=Generic G431V6Tx
+GenG4.menu.pnum.GENERIC_G431V6TX.upload.maximum_size=32768
+GenG4.menu.pnum.GENERIC_G431V6TX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G431V6TX.build.board=GENERIC_G431V6TX
+GenG4.menu.pnum.GENERIC_G431V6TX.build.product_line=STM32G431xx
+GenG4.menu.pnum.GENERIC_G431V6TX.build.variant=STM32G4xx/G431V(6-8-B)T_G441VBT
+
+# Generic G431V8Tx
+GenG4.menu.pnum.GENERIC_G431V8TX=Generic G431V8Tx
+GenG4.menu.pnum.GENERIC_G431V8TX.upload.maximum_size=65536
+GenG4.menu.pnum.GENERIC_G431V8TX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G431V8TX.build.board=GENERIC_G431V8TX
+GenG4.menu.pnum.GENERIC_G431V8TX.build.product_line=STM32G431xx
+GenG4.menu.pnum.GENERIC_G431V8TX.build.variant=STM32G4xx/G431V(6-8-B)T_G441VBT
+
+# Generic G431VBTx
+GenG4.menu.pnum.GENERIC_G431VBTX=Generic G431VBTx
+GenG4.menu.pnum.GENERIC_G431VBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G431VBTX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G431VBTX.build.board=GENERIC_G431VBTX
+GenG4.menu.pnum.GENERIC_G431VBTX.build.product_line=STM32G431xx
+GenG4.menu.pnum.GENERIC_G431VBTX.build.variant=STM32G4xx/G431V(6-8-B)T_G441VBT
+
+# Generic G441CBTx
+GenG4.menu.pnum.GENERIC_G441CBTX=Generic G441CBTx
+GenG4.menu.pnum.GENERIC_G441CBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G441CBTX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G441CBTX.build.board=GENERIC_G441CBTX
+GenG4.menu.pnum.GENERIC_G441CBTX.build.product_line=STM32G441xx
+GenG4.menu.pnum.GENERIC_G441CBTX.build.variant=STM32G4xx/G431C(6-8-B)T_G441CBT
+
+# Generic G441CBUx
+GenG4.menu.pnum.GENERIC_G441CBUX=Generic G441CBUx
+GenG4.menu.pnum.GENERIC_G441CBUX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G441CBUX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G441CBUX.build.board=GENERIC_G441CBUX
+GenG4.menu.pnum.GENERIC_G441CBUX.build.product_line=STM32G441xx
+GenG4.menu.pnum.GENERIC_G441CBUX.build.variant=STM32G4xx/G431C(6-8-B)U_G441CBU
+
+# Generic G441MBTx
+GenG4.menu.pnum.GENERIC_G441MBTX=Generic G441MBTx
+GenG4.menu.pnum.GENERIC_G441MBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G441MBTX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G441MBTX.build.board=GENERIC_G441MBTX
+GenG4.menu.pnum.GENERIC_G441MBTX.build.product_line=STM32G441xx
+GenG4.menu.pnum.GENERIC_G441MBTX.build.variant=STM32G4xx/G431M(6-8-B)T_G441MBT
+
+# Generic G441KBTx
+GenG4.menu.pnum.GENERIC_G441KBTX=Generic G441KBTx
+GenG4.menu.pnum.GENERIC_G441KBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G441KBTX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G441KBTX.build.board=GENERIC_G441KBTX
+GenG4.menu.pnum.GENERIC_G441KBTX.build.product_line=STM32G441xx
+GenG4.menu.pnum.GENERIC_G441KBTX.build.variant=STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)
+
+# Generic G441KBUx
+GenG4.menu.pnum.GENERIC_G441KBUX=Generic G441KBUx
+GenG4.menu.pnum.GENERIC_G441KBUX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G441KBUX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G441KBUX.build.board=GENERIC_G441KBUX
+GenG4.menu.pnum.GENERIC_G441KBUX.build.product_line=STM32G441xx
+GenG4.menu.pnum.GENERIC_G441KBUX.build.variant=STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U)
+
 # Generic G441RBIx
 GenG4.menu.pnum.GENERIC_G441RBIX=Generic G441RBIx
 GenG4.menu.pnum.GENERIC_G441RBIX.upload.maximum_size=131072
@@ -4703,6 +5599,198 @@ GenG4.menu.pnum.GENERIC_G441RBTX.build.board=GENERIC_G441RBTX
 GenG4.menu.pnum.GENERIC_G441RBTX.build.product_line=STM32G441xx
 GenG4.menu.pnum.GENERIC_G441RBTX.build.variant=STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)
 
+# Generic G441VBTx
+GenG4.menu.pnum.GENERIC_G441VBTX=Generic G441VBTx
+GenG4.menu.pnum.GENERIC_G441VBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G441VBTX.upload.maximum_data_size=32768
+GenG4.menu.pnum.GENERIC_G441VBTX.build.board=GENERIC_G441VBTX
+GenG4.menu.pnum.GENERIC_G441VBTX.build.product_line=STM32G441xx
+GenG4.menu.pnum.GENERIC_G441VBTX.build.variant=STM32G4xx/G431V(6-8-B)T_G441VBT
+
+# Generic G471CCTx
+GenG4.menu.pnum.GENERIC_G471CCTX=Generic G471CCTx
+GenG4.menu.pnum.GENERIC_G471CCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G471CCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471CCTX.build.board=GENERIC_G471CCTX
+GenG4.menu.pnum.GENERIC_G471CCTX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471CCTX.build.variant=STM32G4xx/G471C(C-E)T
+
+# Generic G471CETx
+GenG4.menu.pnum.GENERIC_G471CETX=Generic G471CETx
+GenG4.menu.pnum.GENERIC_G471CETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G471CETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471CETX.build.board=GENERIC_G471CETX
+GenG4.menu.pnum.GENERIC_G471CETX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471CETX.build.variant=STM32G4xx/G471C(C-E)T
+
+# Generic G471MCTx
+GenG4.menu.pnum.GENERIC_G471MCTX=Generic G471MCTx
+GenG4.menu.pnum.GENERIC_G471MCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G471MCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471MCTX.build.board=GENERIC_G471MCTX
+GenG4.menu.pnum.GENERIC_G471MCTX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471MCTX.build.variant=STM32G4xx/G471M(C-E)T
+
+# Generic G471METx
+GenG4.menu.pnum.GENERIC_G471METX=Generic G471METx
+GenG4.menu.pnum.GENERIC_G471METX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G471METX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471METX.build.board=GENERIC_G471METX
+GenG4.menu.pnum.GENERIC_G471METX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471METX.build.variant=STM32G4xx/G471M(C-E)T
+
+# Generic G471QCTx
+GenG4.menu.pnum.GENERIC_G471QCTX=Generic G471QCTx
+GenG4.menu.pnum.GENERIC_G471QCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G471QCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471QCTX.build.board=GENERIC_G471QCTX
+GenG4.menu.pnum.GENERIC_G471QCTX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471QCTX.build.variant=STM32G4xx/G471Q(C-E)T
+
+# Generic G471QETx
+GenG4.menu.pnum.GENERIC_G471QETX=Generic G471QETx
+GenG4.menu.pnum.GENERIC_G471QETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G471QETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471QETX.build.board=GENERIC_G471QETX
+GenG4.menu.pnum.GENERIC_G471QETX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471QETX.build.variant=STM32G4xx/G471Q(C-E)T
+
+# Generic G471RCTx
+GenG4.menu.pnum.GENERIC_G471RCTX=Generic G471RCTx
+GenG4.menu.pnum.GENERIC_G471RCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G471RCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471RCTX.build.board=GENERIC_G471RCTX
+GenG4.menu.pnum.GENERIC_G471RCTX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471RCTX.build.variant=STM32G4xx/G471R(C-E)T
+
+# Generic G471RETx
+GenG4.menu.pnum.GENERIC_G471RETX=Generic G471RETx
+GenG4.menu.pnum.GENERIC_G471RETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G471RETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471RETX.build.board=GENERIC_G471RETX
+GenG4.menu.pnum.GENERIC_G471RETX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471RETX.build.variant=STM32G4xx/G471R(C-E)T
+
+# Generic G471VCHx
+GenG4.menu.pnum.GENERIC_G471VCHX=Generic G471VCHx
+GenG4.menu.pnum.GENERIC_G471VCHX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G471VCHX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471VCHX.build.board=GENERIC_G471VCHX
+GenG4.menu.pnum.GENERIC_G471VCHX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471VCHX.build.variant=STM32G4xx/G471V(C-E)(H-I-T)
+
+# Generic G471VEHx
+GenG4.menu.pnum.GENERIC_G471VEHX=Generic G471VEHx
+GenG4.menu.pnum.GENERIC_G471VEHX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G471VEHX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471VEHX.build.board=GENERIC_G471VEHX
+GenG4.menu.pnum.GENERIC_G471VEHX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471VEHX.build.variant=STM32G4xx/G471V(C-E)(H-I-T)
+
+# Generic G471VCIx
+GenG4.menu.pnum.GENERIC_G471VCIX=Generic G471VCIx
+GenG4.menu.pnum.GENERIC_G471VCIX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G471VCIX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471VCIX.build.board=GENERIC_G471VCIX
+GenG4.menu.pnum.GENERIC_G471VCIX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471VCIX.build.variant=STM32G4xx/G471V(C-E)(H-I-T)
+
+# Generic G471VEIx
+GenG4.menu.pnum.GENERIC_G471VEIX=Generic G471VEIx
+GenG4.menu.pnum.GENERIC_G471VEIX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G471VEIX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471VEIX.build.board=GENERIC_G471VEIX
+GenG4.menu.pnum.GENERIC_G471VEIX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471VEIX.build.variant=STM32G4xx/G471V(C-E)(H-I-T)
+
+# Generic G471VCTx
+GenG4.menu.pnum.GENERIC_G471VCTX=Generic G471VCTx
+GenG4.menu.pnum.GENERIC_G471VCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G471VCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471VCTX.build.board=GENERIC_G471VCTX
+GenG4.menu.pnum.GENERIC_G471VCTX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471VCTX.build.variant=STM32G4xx/G471V(C-E)(H-I-T)
+
+# Generic G471VETx
+GenG4.menu.pnum.GENERIC_G471VETX=Generic G471VETx
+GenG4.menu.pnum.GENERIC_G471VETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G471VETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G471VETX.build.board=GENERIC_G471VETX
+GenG4.menu.pnum.GENERIC_G471VETX.build.product_line=STM32G471xx
+GenG4.menu.pnum.GENERIC_G471VETX.build.variant=STM32G4xx/G471V(C-E)(H-I-T)
+
+# Generic G473CBTx
+GenG4.menu.pnum.GENERIC_G473CBTX=Generic G473CBTx
+GenG4.menu.pnum.GENERIC_G473CBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G473CBTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473CBTX.build.board=GENERIC_G473CBTX
+GenG4.menu.pnum.GENERIC_G473CBTX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473CBTX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
+
+# Generic G473CCTx
+GenG4.menu.pnum.GENERIC_G473CCTX=Generic G473CCTx
+GenG4.menu.pnum.GENERIC_G473CCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G473CCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473CCTX.build.board=GENERIC_G473CCTX
+GenG4.menu.pnum.GENERIC_G473CCTX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473CCTX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
+
+# Generic G473CETx
+GenG4.menu.pnum.GENERIC_G473CETX=Generic G473CETx
+GenG4.menu.pnum.GENERIC_G473CETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G473CETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473CETX.build.board=GENERIC_G473CETX
+GenG4.menu.pnum.GENERIC_G473CETX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473CETX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
+
+# Generic G473MBTx
+GenG4.menu.pnum.GENERIC_G473MBTX=Generic G473MBTx
+GenG4.menu.pnum.GENERIC_G473MBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G473MBTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473MBTX.build.board=GENERIC_G473MBTX
+GenG4.menu.pnum.GENERIC_G473MBTX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473MBTX.build.variant=STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET
+
+# Generic G473MCTx
+GenG4.menu.pnum.GENERIC_G473MCTX=Generic G473MCTx
+GenG4.menu.pnum.GENERIC_G473MCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G473MCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473MCTX.build.board=GENERIC_G473MCTX
+GenG4.menu.pnum.GENERIC_G473MCTX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473MCTX.build.variant=STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET
+
+# Generic G473METx
+GenG4.menu.pnum.GENERIC_G473METX=Generic G473METx
+GenG4.menu.pnum.GENERIC_G473METX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G473METX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473METX.build.board=GENERIC_G473METX
+GenG4.menu.pnum.GENERIC_G473METX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473METX.build.variant=STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET
+
+# Generic G473PBIx
+GenG4.menu.pnum.GENERIC_G473PBIX=Generic G473PBIx
+GenG4.menu.pnum.GENERIC_G473PBIX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G473PBIX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473PBIX.build.board=GENERIC_G473PBIX
+GenG4.menu.pnum.GENERIC_G473PBIX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473PBIX.build.variant=STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI
+
+# Generic G473PCIx
+GenG4.menu.pnum.GENERIC_G473PCIX=Generic G473PCIx
+GenG4.menu.pnum.GENERIC_G473PCIX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G473PCIX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473PCIX.build.board=GENERIC_G473PCIX
+GenG4.menu.pnum.GENERIC_G473PCIX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473PCIX.build.variant=STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI
+
+# Generic G473PEIx
+GenG4.menu.pnum.GENERIC_G473PEIX=Generic G473PEIx
+GenG4.menu.pnum.GENERIC_G473PEIX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G473PEIX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473PEIX.build.board=GENERIC_G473PEIX
+GenG4.menu.pnum.GENERIC_G473PEIX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473PEIX.build.variant=STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI
+
 # Generic G473RBTx
 GenG4.menu.pnum.GENERIC_G473RBTX=Generic G473RBTx
 GenG4.menu.pnum.GENERIC_G473RBTX.upload.maximum_size=131072
@@ -4727,6 +5815,150 @@ GenG4.menu.pnum.GENERIC_G473RETX.build.board=GENERIC_G473RETX
 GenG4.menu.pnum.GENERIC_G473RETX.build.product_line=STM32G473xx
 GenG4.menu.pnum.GENERIC_G473RETX.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET
 
+# Generic G473QBTx
+GenG4.menu.pnum.GENERIC_G473QBTX=Generic G473QBTx
+GenG4.menu.pnum.GENERIC_G473QBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G473QBTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473QBTX.build.board=GENERIC_G473QBTX
+GenG4.menu.pnum.GENERIC_G473QBTX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473QBTX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET
+
+# Generic G473QCTx
+GenG4.menu.pnum.GENERIC_G473QCTX=Generic G473QCTx
+GenG4.menu.pnum.GENERIC_G473QCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G473QCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473QCTX.build.board=GENERIC_G473QCTX
+GenG4.menu.pnum.GENERIC_G473QCTX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473QCTX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET
+
+# Generic G473QETx
+GenG4.menu.pnum.GENERIC_G473QETX=Generic G473QETx
+GenG4.menu.pnum.GENERIC_G473QETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G473QETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473QETX.build.board=GENERIC_G473QETX
+GenG4.menu.pnum.GENERIC_G473QETX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473QETX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET
+
+# Generic G473VBHx
+GenG4.menu.pnum.GENERIC_G473VBHX=Generic G473VBHx
+GenG4.menu.pnum.GENERIC_G473VBHX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G473VBHX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473VBHX.build.board=GENERIC_G473VBHX
+GenG4.menu.pnum.GENERIC_G473VBHX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473VBHX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G473VCHx
+GenG4.menu.pnum.GENERIC_G473VCHX=Generic G473VCHx
+GenG4.menu.pnum.GENERIC_G473VCHX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G473VCHX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473VCHX.build.board=GENERIC_G473VCHX
+GenG4.menu.pnum.GENERIC_G473VCHX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473VCHX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G473VEHx
+GenG4.menu.pnum.GENERIC_G473VEHX=Generic G473VEHx
+GenG4.menu.pnum.GENERIC_G473VEHX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G473VEHX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473VEHX.build.board=GENERIC_G473VEHX
+GenG4.menu.pnum.GENERIC_G473VEHX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473VEHX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G473VBTx
+GenG4.menu.pnum.GENERIC_G473VBTX=Generic G473VBTx
+GenG4.menu.pnum.GENERIC_G473VBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G473VBTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473VBTX.build.board=GENERIC_G473VBTX
+GenG4.menu.pnum.GENERIC_G473VBTX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473VBTX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G473VCTx
+GenG4.menu.pnum.GENERIC_G473VCTX=Generic G473VCTx
+GenG4.menu.pnum.GENERIC_G473VCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G473VCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473VCTX.build.board=GENERIC_G473VCTX
+GenG4.menu.pnum.GENERIC_G473VCTX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473VCTX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G473VETx
+GenG4.menu.pnum.GENERIC_G473VETX=Generic G473VETx
+GenG4.menu.pnum.GENERIC_G473VETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G473VETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G473VETX.build.board=GENERIC_G473VETX
+GenG4.menu.pnum.GENERIC_G473VETX.build.product_line=STM32G473xx
+GenG4.menu.pnum.GENERIC_G473VETX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G474CBTx
+GenG4.menu.pnum.GENERIC_G474CBTX=Generic G474CBTx
+GenG4.menu.pnum.GENERIC_G474CBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G474CBTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474CBTX.build.board=GENERIC_G474CBTX
+GenG4.menu.pnum.GENERIC_G474CBTX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474CBTX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
+
+# Generic G474CCTx
+GenG4.menu.pnum.GENERIC_G474CCTX=Generic G474CCTx
+GenG4.menu.pnum.GENERIC_G474CCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G474CCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474CCTX.build.board=GENERIC_G474CCTX
+GenG4.menu.pnum.GENERIC_G474CCTX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474CCTX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
+
+# Generic G474CETx
+GenG4.menu.pnum.GENERIC_G474CETX=Generic G474CETx
+GenG4.menu.pnum.GENERIC_G474CETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G474CETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474CETX.build.board=GENERIC_G474CETX
+GenG4.menu.pnum.GENERIC_G474CETX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474CETX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
+
+# Generic G474MBTx
+GenG4.menu.pnum.GENERIC_G474MBTX=Generic G474MBTx
+GenG4.menu.pnum.GENERIC_G474MBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G474MBTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474MBTX.build.board=GENERIC_G474MBTX
+GenG4.menu.pnum.GENERIC_G474MBTX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474MBTX.build.variant=STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET
+
+# Generic G474MCTx
+GenG4.menu.pnum.GENERIC_G474MCTX=Generic G474MCTx
+GenG4.menu.pnum.GENERIC_G474MCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G474MCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474MCTX.build.board=GENERIC_G474MCTX
+GenG4.menu.pnum.GENERIC_G474MCTX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474MCTX.build.variant=STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET
+
+# Generic G474METx
+GenG4.menu.pnum.GENERIC_G474METX=Generic G474METx
+GenG4.menu.pnum.GENERIC_G474METX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G474METX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474METX.build.board=GENERIC_G474METX
+GenG4.menu.pnum.GENERIC_G474METX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474METX.build.variant=STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET
+
+# Generic G474PBIx
+GenG4.menu.pnum.GENERIC_G474PBIX=Generic G474PBIx
+GenG4.menu.pnum.GENERIC_G474PBIX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G474PBIX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474PBIX.build.board=GENERIC_G474PBIX
+GenG4.menu.pnum.GENERIC_G474PBIX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474PBIX.build.variant=STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI
+
+# Generic G474PCIx
+GenG4.menu.pnum.GENERIC_G474PCIX=Generic G474PCIx
+GenG4.menu.pnum.GENERIC_G474PCIX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G474PCIX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474PCIX.build.board=GENERIC_G474PCIX
+GenG4.menu.pnum.GENERIC_G474PCIX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474PCIX.build.variant=STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI
+
+# Generic G474PEIx
+GenG4.menu.pnum.GENERIC_G474PEIX=Generic G474PEIx
+GenG4.menu.pnum.GENERIC_G474PEIX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G474PEIX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474PEIX.build.board=GENERIC_G474PEIX
+GenG4.menu.pnum.GENERIC_G474PEIX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474PEIX.build.variant=STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI
+
 # Generic G474RBTx
 GenG4.menu.pnum.GENERIC_G474RBTX=Generic G474RBTx
 GenG4.menu.pnum.GENERIC_G474RBTX.upload.maximum_size=131072
@@ -4751,6 +5983,102 @@ GenG4.menu.pnum.GENERIC_G474RETX.build.board=GENERIC_G474RETX
 GenG4.menu.pnum.GENERIC_G474RETX.build.product_line=STM32G474xx
 GenG4.menu.pnum.GENERIC_G474RETX.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET
 
+# Generic G474QBTx
+GenG4.menu.pnum.GENERIC_G474QBTX=Generic G474QBTx
+GenG4.menu.pnum.GENERIC_G474QBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G474QBTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474QBTX.build.board=GENERIC_G474QBTX
+GenG4.menu.pnum.GENERIC_G474QBTX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474QBTX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET
+
+# Generic G474QCTx
+GenG4.menu.pnum.GENERIC_G474QCTX=Generic G474QCTx
+GenG4.menu.pnum.GENERIC_G474QCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G474QCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474QCTX.build.board=GENERIC_G474QCTX
+GenG4.menu.pnum.GENERIC_G474QCTX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474QCTX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET
+
+# Generic G474QETx
+GenG4.menu.pnum.GENERIC_G474QETX=Generic G474QETx
+GenG4.menu.pnum.GENERIC_G474QETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G474QETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474QETX.build.board=GENERIC_G474QETX
+GenG4.menu.pnum.GENERIC_G474QETX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474QETX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET
+
+# Generic G474VBHx
+GenG4.menu.pnum.GENERIC_G474VBHX=Generic G474VBHx
+GenG4.menu.pnum.GENERIC_G474VBHX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G474VBHX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474VBHX.build.board=GENERIC_G474VBHX
+GenG4.menu.pnum.GENERIC_G474VBHX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474VBHX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G474VCHx
+GenG4.menu.pnum.GENERIC_G474VCHX=Generic G474VCHx
+GenG4.menu.pnum.GENERIC_G474VCHX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G474VCHX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474VCHX.build.board=GENERIC_G474VCHX
+GenG4.menu.pnum.GENERIC_G474VCHX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474VCHX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G474VEHx
+GenG4.menu.pnum.GENERIC_G474VEHX=Generic G474VEHx
+GenG4.menu.pnum.GENERIC_G474VEHX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G474VEHX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474VEHX.build.board=GENERIC_G474VEHX
+GenG4.menu.pnum.GENERIC_G474VEHX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474VEHX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G474VBTx
+GenG4.menu.pnum.GENERIC_G474VBTX=Generic G474VBTx
+GenG4.menu.pnum.GENERIC_G474VBTX.upload.maximum_size=131072
+GenG4.menu.pnum.GENERIC_G474VBTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474VBTX.build.board=GENERIC_G474VBTX
+GenG4.menu.pnum.GENERIC_G474VBTX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474VBTX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G474VCTx
+GenG4.menu.pnum.GENERIC_G474VCTX=Generic G474VCTx
+GenG4.menu.pnum.GENERIC_G474VCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G474VCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474VCTX.build.board=GENERIC_G474VCTX
+GenG4.menu.pnum.GENERIC_G474VCTX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474VCTX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G474VETx
+GenG4.menu.pnum.GENERIC_G474VETX=Generic G474VETx
+GenG4.menu.pnum.GENERIC_G474VETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G474VETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G474VETX.build.board=GENERIC_G474VETX
+GenG4.menu.pnum.GENERIC_G474VETX.build.product_line=STM32G474xx
+GenG4.menu.pnum.GENERIC_G474VETX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G483CETx
+GenG4.menu.pnum.GENERIC_G483CETX=Generic G483CETx
+GenG4.menu.pnum.GENERIC_G483CETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G483CETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G483CETX.build.board=GENERIC_G483CETX
+GenG4.menu.pnum.GENERIC_G483CETX.build.product_line=STM32G483xx
+GenG4.menu.pnum.GENERIC_G483CETX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
+
+# Generic G483METx
+GenG4.menu.pnum.GENERIC_G483METX=Generic G483METx
+GenG4.menu.pnum.GENERIC_G483METX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G483METX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G483METX.build.board=GENERIC_G483METX
+GenG4.menu.pnum.GENERIC_G483METX.build.product_line=STM32G483xx
+GenG4.menu.pnum.GENERIC_G483METX.build.variant=STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET
+
+# Generic G483PEIx
+GenG4.menu.pnum.GENERIC_G483PEIX=Generic G483PEIx
+GenG4.menu.pnum.GENERIC_G483PEIX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G483PEIX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G483PEIX.build.board=GENERIC_G483PEIX
+GenG4.menu.pnum.GENERIC_G483PEIX.build.product_line=STM32G483xx
+GenG4.menu.pnum.GENERIC_G483PEIX.build.variant=STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI
+
 # Generic G483RETx
 GenG4.menu.pnum.GENERIC_G483RETX=Generic G483RETx
 GenG4.menu.pnum.GENERIC_G483RETX.upload.maximum_size=524288
@@ -4759,6 +6087,62 @@ GenG4.menu.pnum.GENERIC_G483RETX.build.board=GENERIC_G483RETX
 GenG4.menu.pnum.GENERIC_G483RETX.build.product_line=STM32G483xx
 GenG4.menu.pnum.GENERIC_G483RETX.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET
 
+# Generic G483QETx
+GenG4.menu.pnum.GENERIC_G483QETX=Generic G483QETx
+GenG4.menu.pnum.GENERIC_G483QETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G483QETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G483QETX.build.board=GENERIC_G483QETX
+GenG4.menu.pnum.GENERIC_G483QETX.build.product_line=STM32G483xx
+GenG4.menu.pnum.GENERIC_G483QETX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET
+
+# Generic G483VEHx
+GenG4.menu.pnum.GENERIC_G483VEHX=Generic G483VEHx
+GenG4.menu.pnum.GENERIC_G483VEHX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G483VEHX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G483VEHX.build.board=GENERIC_G483VEHX
+GenG4.menu.pnum.GENERIC_G483VEHX.build.product_line=STM32G483xx
+GenG4.menu.pnum.GENERIC_G483VEHX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G483VETx
+GenG4.menu.pnum.GENERIC_G483VETX=Generic G483VETx
+GenG4.menu.pnum.GENERIC_G483VETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G483VETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G483VETX.build.board=GENERIC_G483VETX
+GenG4.menu.pnum.GENERIC_G483VETX.build.product_line=STM32G483xx
+GenG4.menu.pnum.GENERIC_G483VETX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G484CETx
+GenG4.menu.pnum.GENERIC_G484CETX=Generic G484CETx
+GenG4.menu.pnum.GENERIC_G484CETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G484CETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G484CETX.build.board=GENERIC_G484CETX
+GenG4.menu.pnum.GENERIC_G484CETX.build.product_line=STM32G484xx
+GenG4.menu.pnum.GENERIC_G484CETX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
+
+# Generic G484METx
+GenG4.menu.pnum.GENERIC_G484METX=Generic G484METx
+GenG4.menu.pnum.GENERIC_G484METX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G484METX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G484METX.build.board=GENERIC_G484METX
+GenG4.menu.pnum.GENERIC_G484METX.build.product_line=STM32G484xx
+GenG4.menu.pnum.GENERIC_G484METX.build.variant=STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET
+
+# Generic G484PEIx
+GenG4.menu.pnum.GENERIC_G484PEIX=Generic G484PEIx
+GenG4.menu.pnum.GENERIC_G484PEIX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G484PEIX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G484PEIX.build.board=GENERIC_G484PEIX
+GenG4.menu.pnum.GENERIC_G484PEIX.build.product_line=STM32G484xx
+GenG4.menu.pnum.GENERIC_G484PEIX.build.variant=STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI
+
+# Generic G484QETx
+GenG4.menu.pnum.GENERIC_G484QETX=Generic G484QETx
+GenG4.menu.pnum.GENERIC_G484QETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G484QETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G484QETX.build.board=GENERIC_G484QETX
+GenG4.menu.pnum.GENERIC_G484QETX.build.product_line=STM32G484xx
+GenG4.menu.pnum.GENERIC_G484QETX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET
+
 # Generic G484RETx
 GenG4.menu.pnum.GENERIC_G484RETX=Generic G484RETx
 GenG4.menu.pnum.GENERIC_G484RETX.upload.maximum_size=524288
@@ -4767,6 +6151,93 @@ GenG4.menu.pnum.GENERIC_G484RETX.build.board=GENERIC_G484RETX
 GenG4.menu.pnum.GENERIC_G484RETX.build.product_line=STM32G484xx
 GenG4.menu.pnum.GENERIC_G484RETX.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET
 
+# Generic G484VEHx
+GenG4.menu.pnum.GENERIC_G484VEHX=Generic G484VEHx
+GenG4.menu.pnum.GENERIC_G484VEHX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G484VEHX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G484VEHX.build.board=GENERIC_G484VEHX
+GenG4.menu.pnum.GENERIC_G484VEHX.build.product_line=STM32G484xx
+GenG4.menu.pnum.GENERIC_G484VEHX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G484VETx
+GenG4.menu.pnum.GENERIC_G484VETX=Generic G484VETx
+GenG4.menu.pnum.GENERIC_G484VETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G484VETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G484VETX.build.board=GENERIC_G484VETX
+GenG4.menu.pnum.GENERIC_G484VETX.build.product_line=STM32G484xx
+GenG4.menu.pnum.GENERIC_G484VETX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)
+
+# Generic G484QETx
+GenG4.menu.pnum.GENERIC_G484QETX=Generic G484QETx
+GenG4.menu.pnum.GENERIC_G484QETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G484QETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G484QETX.build.board=GENERIC_G484QETX
+GenG4.menu.pnum.GENERIC_G484QETX.build.product_line=STM32G484xx
+GenG4.menu.pnum.GENERIC_G484QETX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET
+
+# Generic G491CCTx
+GenG4.menu.pnum.GENERIC_G491CCTX=Generic G491CCTx
+GenG4.menu.pnum.GENERIC_G491CCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G491CCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G491CCTX.build.board=GENERIC_G491CCTX
+GenG4.menu.pnum.GENERIC_G491CCTX.build.product_line=STM32G491xx
+GenG4.menu.pnum.GENERIC_G491CCTX.build.variant=STM32G4xx/G491C(C-E)T_G4A1CET
+
+# Generic G491CETx
+GenG4.menu.pnum.GENERIC_G491CETX=Generic G491CETx
+GenG4.menu.pnum.GENERIC_G491CETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G491CETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G491CETX.build.board=GENERIC_G491CETX
+GenG4.menu.pnum.GENERIC_G491CETX.build.product_line=STM32G491xx
+GenG4.menu.pnum.GENERIC_G491CETX.build.variant=STM32G4xx/G491C(C-E)T_G4A1CET
+
+# Generic G491KCUx
+GenG4.menu.pnum.GENERIC_G491KCUX=Generic G491KCUx
+GenG4.menu.pnum.GENERIC_G491KCUX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G491KCUX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G491KCUX.build.board=GENERIC_G491KCUX
+GenG4.menu.pnum.GENERIC_G491KCUX.build.product_line=STM32G491xx
+GenG4.menu.pnum.GENERIC_G491KCUX.build.variant=STM32G4xx/G491K(C-E)U_G4A1KEU
+
+# Generic G491KEUx
+GenG4.menu.pnum.GENERIC_G491KEUX=Generic G491KEUx
+GenG4.menu.pnum.GENERIC_G491KEUX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G491KEUX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G491KEUX.build.board=GENERIC_G491KEUX
+GenG4.menu.pnum.GENERIC_G491KEUX.build.product_line=STM32G491xx
+GenG4.menu.pnum.GENERIC_G491KEUX.build.variant=STM32G4xx/G491K(C-E)U_G4A1KEU
+
+# Generic G491MCSx
+GenG4.menu.pnum.GENERIC_G491MCSX=Generic G491MCSx
+GenG4.menu.pnum.GENERIC_G491MCSX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G491MCSX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G491MCSX.build.board=GENERIC_G491MCSX
+GenG4.menu.pnum.GENERIC_G491MCSX.build.product_line=STM32G491xx
+GenG4.menu.pnum.GENERIC_G491MCSX.build.variant=STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)
+
+# Generic G491MESx
+GenG4.menu.pnum.GENERIC_G491MESX=Generic G491MESx
+GenG4.menu.pnum.GENERIC_G491MESX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G491MESX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G491MESX.build.board=GENERIC_G491MESX
+GenG4.menu.pnum.GENERIC_G491MESX.build.product_line=STM32G491xx
+GenG4.menu.pnum.GENERIC_G491MESX.build.variant=STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)
+
+# Generic G491MCTx
+GenG4.menu.pnum.GENERIC_G491MCTX=Generic G491MCTx
+GenG4.menu.pnum.GENERIC_G491MCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G491MCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G491MCTX.build.board=GENERIC_G491MCTX
+GenG4.menu.pnum.GENERIC_G491MCTX.build.product_line=STM32G491xx
+GenG4.menu.pnum.GENERIC_G491MCTX.build.variant=STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)
+
+# Generic G491METx
+GenG4.menu.pnum.GENERIC_G491METX=Generic G491METx
+GenG4.menu.pnum.GENERIC_G491METX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G491METX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G491METX.build.board=GENERIC_G491METX
+GenG4.menu.pnum.GENERIC_G491METX.build.product_line=STM32G491xx
+GenG4.menu.pnum.GENERIC_G491METX.build.variant=STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)
 
 # Generic G491RCIx
 GenG4.menu.pnum.GENERIC_G491RCIX=Generic G491RCIx
@@ -4808,6 +6279,22 @@ GenG4.menu.pnum.GENERIC_G491REYX.build.board=GENERIC_G491REYX
 GenG4.menu.pnum.GENERIC_G491REYX.build.product_line=STM32G491xx
 GenG4.menu.pnum.GENERIC_G491REYX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)
 
+# Generic G491VCTx
+GenG4.menu.pnum.GENERIC_G491VCTX=Generic G491VCTx
+GenG4.menu.pnum.GENERIC_G491VCTX.upload.maximum_size=262144
+GenG4.menu.pnum.GENERIC_G491VCTX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G491VCTX.build.board=GENERIC_G491VCTX
+GenG4.menu.pnum.GENERIC_G491VCTX.build.product_line=STM32G491xx
+GenG4.menu.pnum.GENERIC_G491VCTX.build.variant=STM32G4xx/G491V(C-E)T_G4A1VET
+
+# Generic G491VETx
+GenG4.menu.pnum.GENERIC_G491VETX=Generic G491VETx
+GenG4.menu.pnum.GENERIC_G491VETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G491VETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G491VETX.build.board=GENERIC_G491VETX
+GenG4.menu.pnum.GENERIC_G491VETX.build.product_line=STM32G491xx
+GenG4.menu.pnum.GENERIC_G491VETX.build.variant=STM32G4xx/G491V(C-E)T_G4A1VET
+
 # Generic G4A1REIx
 GenG4.menu.pnum.GENERIC_G4A1REIX=Generic G4A1REIx
 GenG4.menu.pnum.GENERIC_G4A1REIX.upload.maximum_size=524288
@@ -4816,6 +6303,38 @@ GenG4.menu.pnum.GENERIC_G4A1REIX.build.board=GENERIC_G4A1REIX
 GenG4.menu.pnum.GENERIC_G4A1REIX.build.product_line=STM32G4A1xx
 GenG4.menu.pnum.GENERIC_G4A1REIX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)
 
+# Generic G4A1CETx
+GenG4.menu.pnum.GENERIC_G4A1CETX=Generic G4A1CETx
+GenG4.menu.pnum.GENERIC_G4A1CETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G4A1CETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G4A1CETX.build.board=GENERIC_G4A1CETX
+GenG4.menu.pnum.GENERIC_G4A1CETX.build.product_line=STM32G4A1xx
+GenG4.menu.pnum.GENERIC_G4A1CETX.build.variant=STM32G4xx/G491C(C-E)T_G4A1CET
+
+# Generic G4A1KEUx
+GenG4.menu.pnum.GENERIC_G4A1KEUX=Generic G4A1KEUx
+GenG4.menu.pnum.GENERIC_G4A1KEUX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G4A1KEUX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G4A1KEUX.build.board=GENERIC_G4A1KEUX
+GenG4.menu.pnum.GENERIC_G4A1KEUX.build.product_line=STM32G4A1xx
+GenG4.menu.pnum.GENERIC_G4A1KEUX.build.variant=STM32G4xx/G491K(C-E)U_G4A1KEU
+
+# Generic G4A1MESx
+GenG4.menu.pnum.GENERIC_G4A1MESX=Generic G4A1MESx
+GenG4.menu.pnum.GENERIC_G4A1MESX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G4A1MESX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G4A1MESX.build.board=GENERIC_G4A1MESX
+GenG4.menu.pnum.GENERIC_G4A1MESX.build.product_line=STM32G4A1xx
+GenG4.menu.pnum.GENERIC_G4A1MESX.build.variant=STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)
+
+# Generic G4A1METx
+GenG4.menu.pnum.GENERIC_G4A1METX=Generic G4A1METx
+GenG4.menu.pnum.GENERIC_G4A1METX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G4A1METX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G4A1METX.build.board=GENERIC_G4A1METX
+GenG4.menu.pnum.GENERIC_G4A1METX.build.product_line=STM32G4A1xx
+GenG4.menu.pnum.GENERIC_G4A1METX.build.variant=STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)
+
 # Generic G4A1RETx
 GenG4.menu.pnum.GENERIC_G4A1RETX=Generic G4A1RETx
 GenG4.menu.pnum.GENERIC_G4A1RETX.upload.maximum_size=524288
@@ -4832,6 +6351,14 @@ GenG4.menu.pnum.GENERIC_G4A1REYX.build.board=GENERIC_G4A1REYX
 GenG4.menu.pnum.GENERIC_G4A1REYX.build.product_line=STM32G4A1xx
 GenG4.menu.pnum.GENERIC_G4A1REYX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)
 
+# Generic G4A1VETx
+GenG4.menu.pnum.GENERIC_G4A1VETX=Generic G4A1VETx
+GenG4.menu.pnum.GENERIC_G4A1VETX.upload.maximum_size=524288
+GenG4.menu.pnum.GENERIC_G4A1VETX.upload.maximum_data_size=131072
+GenG4.menu.pnum.GENERIC_G4A1VETX.build.board=GENERIC_G4A1VETX
+GenG4.menu.pnum.GENERIC_G4A1VETX.build.product_line=STM32G4A1xx
+GenG4.menu.pnum.GENERIC_G4A1VETX.build.variant=STM32G4xx/G491V(C-E)T_G4A1VET
+
 
 
 # Upload menu
@@ -6786,6 +8313,18 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg
 3dprinter.menu.pnum.ARMED_V1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
 3dprinter.menu.pnum.ARMED_V1.build.cmsis_lib_gcc=arm_cortexM4lf_math
 
+# Big Tree Tech EBB42_V1_1 board
+3dprinter.menu.pnum.EBB42_V1_1=Big Tree Tech EBB42 V1.1
+3dprinter.menu.pnum.EBB42_V1_1.upload.maximum_size=131072
+3dprinter.menu.pnum.EBB42_V1_1.upload.maximum_data_size=147456
+3dprinter.menu.pnum.EBB42_V1_1.build.mcu=cortex-m0plus
+3dprinter.menu.pnum.EBB42_V1_1.build.board=EBB42_V1_1
+3dprinter.menu.pnum.EBB42_V1_1.build.series=STM32G0xx
+3dprinter.menu.pnum.EBB42_V1_1.build.product_line=STM32G0B1xx
+3dprinter.menu.pnum.EBB42_V1_1.build.variant=STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)
+3dprinter.menu.pnum.EBB42_V1_1.build.cmsis_lib_gcc=arm_cortexM0l_math
+3dprinter.menu.pnum.EBB42_V1_1.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0
+
 # REMRAM_V1 board
 3dprinter.menu.pnum.REMRAM_V1=RemRam v1
 3dprinter.menu.pnum.REMRAM_V1.upload.maximum_size=2097152
diff --git a/variants/STM32G0xx/G030J6M/generic_clock.c b/variants/STM32G0xx/G030J6M/generic_clock.c
index 800308262e..a01071f898 100644
--- a/variants/STM32G0xx/G030J6M/generic_clock.c
+++ b/variants/STM32G0xx/G030J6M/generic_clock.c
@@ -20,8 +20,41 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G030J6M/ldscript.ld b/variants/STM32G0xx/G030J6M/ldscript.ld
new file mode 100644
index 0000000000..1dfd35f111
--- /dev/null
+++ b/variants/STM32G0xx/G030J6M/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G030J6Mx Device from STM32G0 series
+**                      32Kbytes FLASH
+**                      8Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/generic_clock.c b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/generic_clock.c
index b109dba65f..af2708bd07 100644
--- a/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/generic_clock.c
+++ b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/generic_clock.c
@@ -24,8 +24,42 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/ldscript.ld b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/ldscript.ld
new file mode 100644
index 0000000000..4a2deb9832
--- /dev/null
+++ b/variants/STM32G0xx/G031C(4-6-8)(T-U)_G041C(6-8)(T-U)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G031C4Tx Device from STM32G0 series
+**                      16Kbytes FLASH
+**                      8Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/generic_clock.c b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/generic_clock.c
index aa2832df5a..b3a5dfd57a 100644
--- a/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/generic_clock.c
+++ b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/generic_clock.c
@@ -22,8 +22,42 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/ldscript.ld b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/ldscript.ld
new file mode 100644
index 0000000000..8edfc3ed26
--- /dev/null
+++ b/variants/STM32G0xx/G031G(4-6-8)U_G041G(6-8)U/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G031G4Ux Device from STM32G0 series
+**                      16Kbytes FLASH
+**                      8Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G050C(6-8)T/generic_clock.c b/variants/STM32G0xx/G050C(6-8)T/generic_clock.c
index fa7147d05b..abce35c5b6 100644
--- a/variants/STM32G0xx/G050C(6-8)T/generic_clock.c
+++ b/variants/STM32G0xx/G050C(6-8)T/generic_clock.c
@@ -20,8 +20,41 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G050C(6-8)T/ldscript.ld b/variants/STM32G0xx/G050C(6-8)T/ldscript.ld
new file mode 100644
index 0000000000..0019dea4ba
--- /dev/null
+++ b/variants/STM32G0xx/G050C(6-8)T/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G050C6Tx Device from STM32G0 series
+**                      32Kbytes FLASH
+**                      18Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G050F6P/generic_clock.c b/variants/STM32G0xx/G050F6P/generic_clock.c
index a52771f7fb..97a09a0140 100644
--- a/variants/STM32G0xx/G050F6P/generic_clock.c
+++ b/variants/STM32G0xx/G050F6P/generic_clock.c
@@ -20,8 +20,41 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G050F6P/ldscript.ld b/variants/STM32G0xx/G050F6P/ldscript.ld
new file mode 100644
index 0000000000..7422a55e86
--- /dev/null
+++ b/variants/STM32G0xx/G050F6P/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G050F6Px Device from STM32G0 series
+**                      32Kbytes FLASH
+**                      18Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G050K(6-8)T/generic_clock.c b/variants/STM32G0xx/G050K(6-8)T/generic_clock.c
index efa488c221..0acb7c9ed5 100644
--- a/variants/STM32G0xx/G050K(6-8)T/generic_clock.c
+++ b/variants/STM32G0xx/G050K(6-8)T/generic_clock.c
@@ -20,8 +20,41 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G050K(6-8)T/ldscript.ld b/variants/STM32G0xx/G050K(6-8)T/ldscript.ld
new file mode 100644
index 0000000000..fe6e885c85
--- /dev/null
+++ b/variants/STM32G0xx/G050K(6-8)T/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G050K6Tx Device from STM32G0 series
+**                      32Kbytes FLASH
+**                      18Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/generic_clock.c b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/generic_clock.c
index fb99a376d1..413775e85b 100644
--- a/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/generic_clock.c
+++ b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/generic_clock.c
@@ -23,8 +23,42 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/ldscript.ld b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/ldscript.ld
new file mode 100644
index 0000000000..4fc9328ca5
--- /dev/null
+++ b/variants/STM32G0xx/G051C(6-8)(T-U)_G061C(6-8)(T-U)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G051C6Tx Device from STM32G0 series
+**                      32Kbytes FLASH
+**                      18Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/generic_clock.c b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/generic_clock.c
index 6e38b4dc33..5dd32dcad0 100644
--- a/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/generic_clock.c
+++ b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/generic_clock.c
@@ -22,8 +22,42 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/ldscript.ld b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/ldscript.ld
new file mode 100644
index 0000000000..33d1109a11
--- /dev/null
+++ b/variants/STM32G0xx/G051F6P_G051F8(P-Y)_G061F6P_G061F8(P-Y)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G051F6Px Device from STM32G0 series
+**                      32Kbytes FLASH
+**                      18Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/generic_clock.c b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/generic_clock.c
index 71c9831909..9456aa919a 100644
--- a/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/generic_clock.c
+++ b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/generic_clock.c
@@ -21,8 +21,42 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/ldscript.ld b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/ldscript.ld
new file mode 100644
index 0000000000..7d801b1610
--- /dev/null
+++ b/variants/STM32G0xx/G051G(6-8)U_G061G(6-8)U/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G051G6Ux Device from STM32G0 series
+**                      32Kbytes FLASH
+**                      18Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/generic_clock.c b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/generic_clock.c
index 36532f4efd..ec47321c55 100644
--- a/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/generic_clock.c
+++ b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/generic_clock.c
@@ -23,8 +23,42 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/ldscript.ld b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/ldscript.ld
new file mode 100644
index 0000000000..0a590e71f0
--- /dev/null
+++ b/variants/STM32G0xx/G051K(6-8)(T-U)_G061K(6-8)(T-U)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G051K6Tx Device from STM32G0 series
+**                      32Kbytes FLASH
+**                      18Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G071EBY_G081EBY/generic_clock.c b/variants/STM32G0xx/G071EBY_G081EBY/generic_clock.c
index 918f1dd4a5..ccd1f68f37 100644
--- a/variants/STM32G0xx/G071EBY_G081EBY/generic_clock.c
+++ b/variants/STM32G0xx/G071EBY_G081EBY/generic_clock.c
@@ -20,8 +20,42 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G071EBY_G081EBY/ldscript.ld b/variants/STM32G0xx/G071EBY_G081EBY/ldscript.ld
new file mode 100644
index 0000000000..c1ce1e0ebe
--- /dev/null
+++ b/variants/STM32G0xx/G071EBY_G081EBY/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G071EBYx Device from STM32G0 series
+**                      128Kbytes FLASH
+**                      36Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/generic_clock.c b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/generic_clock.c
index 87d5d66755..252d2d0d72 100644
--- a/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/generic_clock.c
+++ b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/generic_clock.c
@@ -21,8 +21,42 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/ldscript.ld b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/ldscript.ld
new file mode 100644
index 0000000000..16ba265495
--- /dev/null
+++ b/variants/STM32G0xx/G071G(6-8-B)U_G081GBU/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G081GBUx Device from STM32G0 series
+**                      128Kbytes FLASH
+**                      36Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/generic_clock.c b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/generic_clock.c
index a8034201fc..be825a2ea2 100644
--- a/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/generic_clock.c
+++ b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/generic_clock.c
@@ -23,8 +23,42 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/ldscript.ld b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/ldscript.ld
new file mode 100644
index 0000000000..1d65d9e460
--- /dev/null
+++ b/variants/STM32G0xx/G071K(6-8-B)(T-U)_G081KB(T-U)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G071K8Tx Device from STM32G0 series
+**                      64Kbytes FLASH
+**                      36Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G0B0CET/generic_clock.c b/variants/STM32G0xx/G0B0CET/generic_clock.c
index 8be3bf6fdf..879550021d 100644
--- a/variants/STM32G0xx/G0B0CET/generic_clock.c
+++ b/variants/STM32G0xx/G0B0CET/generic_clock.c
@@ -20,8 +20,42 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 9;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV3;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV3;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G0B0CET/ldscript.ld b/variants/STM32G0xx/G0B0CET/ldscript.ld
new file mode 100644
index 0000000000..5108535fbf
--- /dev/null
+++ b/variants/STM32G0xx/G0B0CET/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G0B0CETx Device from STM32G0 series
+**                      512Kbytes FLASH
+**                      144Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G0B0RET/generic_clock.c b/variants/STM32G0xx/G0B0RET/generic_clock.c
index c8ee10bc80..700dc8bcb4 100644
--- a/variants/STM32G0xx/G0B0RET/generic_clock.c
+++ b/variants/STM32G0xx/G0B0RET/generic_clock.c
@@ -20,8 +20,42 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 9;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV3;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV3;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G0B0RET/ldscript.ld b/variants/STM32G0xx/G0B0RET/ldscript.ld
new file mode 100644
index 0000000000..d475078239
--- /dev/null
+++ b/variants/STM32G0xx/G0B0RET/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G0B0RETx Device from STM32G0 series
+**                      512Kbytes FLASH
+**                      144Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G0B0VET/generic_clock.c b/variants/STM32G0xx/G0B0VET/generic_clock.c
index ae205b01d8..7f53a17a13 100644
--- a/variants/STM32G0xx/G0B0VET/generic_clock.c
+++ b/variants/STM32G0xx/G0B0VET/generic_clock.c
@@ -20,8 +20,42 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 9;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV3;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV3;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G0B0VET/ldscript.ld b/variants/STM32G0xx/G0B0VET/ldscript.ld
new file mode 100644
index 0000000000..53552800e9
--- /dev/null
+++ b/variants/STM32G0xx/G0B0VET/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G0B0VETx Device from STM32G0 series
+**                      512Kbytes FLASH
+**                      144Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/generic_clock.c b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/generic_clock.c
index 73bcd6eb60..546c1c55a6 100644
--- a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/generic_clock.c
+++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/generic_clock.c
@@ -24,8 +24,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/ldscript.ld b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/ldscript.ld
new file mode 100644
index 0000000000..ce97a9f4ae
--- /dev/null
+++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G0B1CBTx Device from STM32G0 series
+**                      128Kbytes FLASH
+**                      144Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/variant_EBB42_V1_1.cpp b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/variant_EBB42_V1_1.cpp
new file mode 100644
index 0000000000..b59d34f7b6
--- /dev/null
+++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/variant_EBB42_V1_1.cpp
@@ -0,0 +1,138 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2021, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+#if defined(ARDUINO_EBB42_V1_1)
+#include "pins_arduino.h"
+
+// Pin number
+const PinName digitalPin[] = {
+  PA_0,   // D0/A0
+  PA_1,   // D1/A1
+  PA_2,   // D2/A2
+  PA_3,   // D3/A3
+  PA_4,   // D4/A4
+  PA_5,   // D5/A5
+  PA_6,   // D6/A6
+  PA_7,   // D7/A7
+  PA_8,   // D8
+  PA_9,   // D9
+  PA_10,  // D10
+  PA_11,  // D11
+  PA_12,  // D12
+  PA_13,  // D13
+  PA_14,  // D14
+  PA_15,  // D15
+  PB_0,   // D16/A8
+  PB_1,   // D17/A9
+  PB_2,   // D18/A10
+  PB_3,   // D19
+  PB_4,   // D20
+  PB_5,   // D21
+  PB_6,   // D22
+  PB_7,   // D23
+  PB_8,   // D24
+  PB_9,   // D25
+  PB_10,  // D26/A11
+  PB_11,  // D27/A12
+  PB_12,  // D28/A13
+  PB_13,  // D29
+  PB_14,  // D30
+  PB_15,  // D31
+  PC_6,   // D32
+  PC_7,   // D33
+  PC_13,  // D34
+  PC_14,  // D35
+  PC_15,  // D36
+  PD_0,   // D37
+  PD_1,   // D38
+  PD_2,   // D39
+  PD_3,   // D40
+  PF_0,   // D41
+  PF_1,   // D42
+  PF_2,   // D43
+  PA_9_R, // D44
+  PA_10_R // D45
+};
+
+// Analog (Ax) pin number array
+const uint32_t analogInputPin[] = {
+  0,  // A0,  PA0
+  1,  // A1,  PA1
+  2,  // A2,  PA2
+  3,  // A3,  PA3
+  4,  // A4,  PA4
+  5,  // A5,  PA5
+  6,  // A6,  PA6
+  7,  // A7,  PA7
+  16, // A8,  PB0
+  17, // A9,  PB1
+  18, // A10, PB2
+  26, // A11, PB10
+  27, // A12, PB11
+  28  // A13, PB12
+};
+
+// ----------------------------------------------------------------------------
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  * @brief  System Clock Configuration
+  * @param  None
+  * @retval None
+  */
+WEAK void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 16;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
+}
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ARDUINO_EBB42_V1_1 */
diff --git a/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/variant_EBB42_V1_1.h b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/variant_EBB42_V1_1.h
new file mode 100644
index 0000000000..ff75bc1e48
--- /dev/null
+++ b/variants/STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U)/variant_EBB42_V1_1.h
@@ -0,0 +1,198 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ *        STM32 pins number
+ *----------------------------------------------------------------------------*/
+#define PA0                     PIN_A0
+#define PA1                     PIN_A1
+#define PA2                     PIN_A2
+#define PA3                     PIN_A3
+#define PA4                     PIN_A4
+#define PA5                     PIN_A5
+#define PA6                     PIN_A6
+#define PA7                     PIN_A7
+#define PA8                     8
+#define PA9                     9
+#define PA10                    10
+#define PA11                    11
+#define PA12                    12
+#define PA13                    13
+#define PA14                    14
+#define PA15                    15
+#define PB0                     PIN_A8
+#define PB1                     PIN_A9
+#define PB2                     PIN_A10
+#define PB3                     19
+#define PB4                     20
+#define PB5                     21
+#define PB6                     22
+#define PB7                     23
+#define PB8                     24
+#define PB9                     25
+#define PB10                    PIN_A11
+#define PB11                    PIN_A12
+#define PB12                    PIN_A13
+#define PB13                    29
+#define PB14                    30
+#define PB15                    31
+#define PC6                     32
+#define PC7                     33
+#define PC13                    34
+#define PC14                    35
+#define PC15                    36
+#define PD0                     37
+#define PD1                     38
+#define PD2                     39
+#define PD3                     40
+#define PF0                     41
+#define PF1                     42
+#define PF2                     43
+#define PA9_R                   44
+#define PA10_R                  45
+
+// Alternate pins number
+#define PA1_ALT1                (PA1    | ALT1)
+#define PA2_ALT1                (PA2    | ALT1)
+#define PA3_ALT1                (PA3    | ALT1)
+#define PA4_ALT1                (PA4    | ALT1)
+#define PA6_ALT1                (PA6    | ALT1)
+#define PA6_ALT2                (PA6    | ALT2)
+#define PA7_ALT1                (PA7    | ALT1)
+#define PA7_ALT2                (PA7    | ALT2)
+#define PA7_ALT3                (PA7    | ALT3)
+#define PA9_ALT1                (PA9    | ALT1)
+#define PA9_R_ALT1              (PA9_R  | ALT1)
+#define PA10_ALT1               (PA10   | ALT1)
+#define PA10_R_ALT1             (PA10_R | ALT1)
+#define PA14_ALT1               (PA14   | ALT1)
+#define PA15_ALT1               (PA15   | ALT1)
+#define PB0_ALT1                (PB0    | ALT1)
+#define PB1_ALT1                (PB1    | ALT1)
+#define PB1_ALT2                (PB1    | ALT2)
+#define PB3_ALT1                (PB3    | ALT1)
+#define PB4_ALT1                (PB4    | ALT1)
+#define PB5_ALT1                (PB5    | ALT1)
+#define PB6_ALT1                (PB6    | ALT1)
+#define PB6_ALT2                (PB6    | ALT2)
+#define PB7_ALT1                (PB7    | ALT1)
+#define PB8_ALT1                (PB8    | ALT1)
+#define PB9_ALT1                (PB9    | ALT1)
+#define PB13_ALT1               (PB13   | ALT1)
+#define PB14_ALT1               (PB14   | ALT1)
+#define PB15_ALT1               (PB15   | ALT1)
+#define PB15_ALT2               (PB15   | ALT2)
+#define PC6_ALT1                (PC6    | ALT1)
+#define PC7_ALT1                (PC7    | ALT1)
+
+#define NUM_DIGITAL_PINS        46
+#define NUM_REMAP_PINS          2
+#define NUM_ANALOG_INPUTS       14
+
+// On-board LED pin number
+#ifndef LED_BUILTIN
+  #define LED_BUILTIN           PNUM_NOT_DEFINED
+#endif
+
+// On-board user button
+#ifndef USER_BTN
+  #define USER_BTN              PNUM_NOT_DEFINED
+#endif
+
+// SPI definitions
+#ifndef PIN_SPI_SS
+  #define PIN_SPI_SS            PA4
+#endif
+#ifndef PIN_SPI_SS1
+  #define PIN_SPI_SS1           PA15
+#endif
+#ifndef PIN_SPI_SS2
+  #define PIN_SPI_SS2           PB0
+#endif
+#ifndef PIN_SPI_SS3
+  #define PIN_SPI_SS3           PNUM_NOT_DEFINED
+#endif
+#ifndef PIN_SPI_MOSI
+  #define PIN_SPI_MOSI          PA2
+#endif
+#ifndef PIN_SPI_MISO
+  #define PIN_SPI_MISO          PA6
+#endif
+#ifndef PIN_SPI_SCK
+  #define PIN_SPI_SCK           PA1
+#endif
+
+// I2C definitions
+#ifndef PIN_WIRE_SDA
+  #define PIN_WIRE_SDA          PA6
+#endif
+#ifndef PIN_WIRE_SCL
+  #define PIN_WIRE_SCL          PA7
+#endif
+
+// Timer Definitions
+// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+  #define TIMER_TONE            TIM6
+#endif
+#ifndef TIMER_SERVO
+  #define TIMER_SERVO           TIM7
+#endif
+
+// UART Definitions
+#ifndef SERIAL_UART_INSTANCE
+  #define SERIAL_UART_INSTANCE  4
+#endif
+
+// Default pin used for generic 'Serial' instance
+// Mandatory for Firmata
+#ifndef PIN_SERIAL_RX
+  #define PIN_SERIAL_RX         PA1
+#endif
+#ifndef PIN_SERIAL_TX
+  #define PIN_SERIAL_TX         PA0
+#endif
+
+// Extra HAL modules
+#if !defined(HAL_DAC_MODULE_DISABLED)
+  #define HAL_DAC_MODULE_ENABLED
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+  // These serial port names are intended to allow libraries and architecture-neutral
+  // sketches to automatically default to the correct port name for a particular type
+  // of use.  For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+  // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+  //
+  // SERIAL_PORT_MONITOR        Port which normally prints to the Arduino Serial Monitor
+  //
+  // SERIAL_PORT_USBVIRTUAL     Port which is USB virtual serial
+  //
+  // SERIAL_PORT_LINUXBRIDGE    Port which connects to a Linux system via Bridge library
+  //
+  // SERIAL_PORT_HARDWARE       Hardware serial port, physical RX & TX pins.
+  //
+  // SERIAL_PORT_HARDWARE_OPEN  Hardware serial ports which are open for use.  Their RX & TX
+  //                            pins are NOT connected to anything by default.
+  #ifndef SERIAL_PORT_MONITOR
+    #define SERIAL_PORT_MONITOR   Serial
+  #endif
+  #ifndef SERIAL_PORT_HARDWARE
+    #define SERIAL_PORT_HARDWARE  Serial
+  #endif
+#endif
diff --git a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/generic_clock.c b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/generic_clock.c
index 937e0b0f85..2d43af93f0 100644
--- a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/generic_clock.c
+++ b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/generic_clock.c
@@ -24,8 +24,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/ldscript.ld b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/ldscript.ld
new file mode 100644
index 0000000000..df89cee1cb
--- /dev/null
+++ b/variants/STM32G0xx/G0B1K(B-C-E)(T-U)_G0C1K(C-E)(T-U)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G0B1KBTx Device from STM32G0 series
+**                      128Kbytes FLASH
+**                      144Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/generic_clock.c b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/generic_clock.c
index 808386da53..3129584ca6 100644
--- a/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/generic_clock.c
+++ b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/generic_clock.c
@@ -22,8 +22,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/ldscript.ld b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/ldscript.ld
new file mode 100644
index 0000000000..58bb455351
--- /dev/null
+++ b/variants/STM32G0xx/G0B1M(B-C-E)T_G0C1M(C-E)T/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G0B1MBTx Device from STM32G0 series
+**                      128Kbytes FLASH
+**                      144Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G0B1NEY_G0C1NEY/generic_clock.c b/variants/STM32G0xx/G0B1NEY_G0C1NEY/generic_clock.c
index 4f03c763f6..a664bf1fd4 100644
--- a/variants/STM32G0xx/G0B1NEY_G0C1NEY/generic_clock.c
+++ b/variants/STM32G0xx/G0B1NEY_G0C1NEY/generic_clock.c
@@ -20,8 +20,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G0B1NEY_G0C1NEY/ldscript.ld b/variants/STM32G0xx/G0B1NEY_G0C1NEY/ldscript.ld
new file mode 100644
index 0000000000..9436f0ea35
--- /dev/null
+++ b/variants/STM32G0xx/G0B1NEY_G0C1NEY/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G0B1NEYx Device from STM32G0 series
+**                      512Kbytes FLASH
+**                      144Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/generic_clock.c b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/generic_clock.c
index e7bac9a3d8..dcd887fbee 100644
--- a/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/generic_clock.c
+++ b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/generic_clock.c
@@ -24,8 +24,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/ldscript.ld b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/ldscript.ld
new file mode 100644
index 0000000000..9ef7f823f0
--- /dev/null
+++ b/variants/STM32G0xx/G0B1V(B-C-E)(I-T)_G0C1V(C-E)(I-T)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G0B1VBIx Device from STM32G0 series
+**                      128Kbytes FLASH
+**                      144Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/generic_clock.c b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/generic_clock.c
index 6056ba9585..6341219850 100644
--- a/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/generic_clock.c
+++ b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/generic_clock.c
@@ -21,8 +21,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/ldscript.ld b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/ldscript.ld
new file mode 100644
index 0000000000..a1b53d35a0
--- /dev/null
+++ b/variants/STM32G4xx/G431C(6-8-B)T_G441CBT/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G431C6Tx Device from STM32G4 series
+**                      32Kbytes FLASH
+**                      32Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/generic_clock.c b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/generic_clock.c
index 4a45677b78..cbc88f3d27 100644
--- a/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/generic_clock.c
+++ b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/generic_clock.c
@@ -21,8 +21,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/ldscript.ld b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/ldscript.ld
new file mode 100644
index 0000000000..f32a2e7982
--- /dev/null
+++ b/variants/STM32G4xx/G431M(6-8-B)T_G441MBT/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G431M6Tx Device from STM32G4 series
+**                      32Kbytes FLASH
+**                      32Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/generic_clock.c b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/generic_clock.c
index 2d91f649e9..c458aa2515 100644
--- a/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/generic_clock.c
+++ b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/generic_clock.c
@@ -21,8 +21,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/ldscript.ld b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/ldscript.ld
new file mode 100644
index 0000000000..afa44871d3
--- /dev/null
+++ b/variants/STM32G4xx/G431V(6-8-B)T_G441VBT/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G431V6Tx Device from STM32G4 series
+**                      32Kbytes FLASH
+**                      32Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G471C(C-E)T/generic_clock.c b/variants/STM32G4xx/G471C(C-E)T/generic_clock.c
index 48c524d917..0b74cc53f4 100644
--- a/variants/STM32G4xx/G471C(C-E)T/generic_clock.c
+++ b/variants/STM32G4xx/G471C(C-E)T/generic_clock.c
@@ -20,8 +20,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G471C(C-E)T/ldscript.ld b/variants/STM32G4xx/G471C(C-E)T/ldscript.ld
new file mode 100644
index 0000000000..5dc45798ab
--- /dev/null
+++ b/variants/STM32G4xx/G471C(C-E)T/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G471CCTx Device from STM32G4 series
+**                      256Kbytes FLASH
+**                      128Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G471M(C-E)T/generic_clock.c b/variants/STM32G4xx/G471M(C-E)T/generic_clock.c
index 4a8e538d15..606210f81f 100644
--- a/variants/STM32G4xx/G471M(C-E)T/generic_clock.c
+++ b/variants/STM32G4xx/G471M(C-E)T/generic_clock.c
@@ -20,8 +20,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G471M(C-E)T/ldscript.ld b/variants/STM32G4xx/G471M(C-E)T/ldscript.ld
new file mode 100644
index 0000000000..d552ca64e1
--- /dev/null
+++ b/variants/STM32G4xx/G471M(C-E)T/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G471MCTx Device from STM32G4 series
+**                      256Kbytes FLASH
+**                      128Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G471Q(C-E)T/generic_clock.c b/variants/STM32G4xx/G471Q(C-E)T/generic_clock.c
index ef0f51b453..6b950f4e34 100644
--- a/variants/STM32G4xx/G471Q(C-E)T/generic_clock.c
+++ b/variants/STM32G4xx/G471Q(C-E)T/generic_clock.c
@@ -20,8 +20,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G471Q(C-E)T/ldscript.ld b/variants/STM32G4xx/G471Q(C-E)T/ldscript.ld
new file mode 100644
index 0000000000..2242a813a2
--- /dev/null
+++ b/variants/STM32G4xx/G471Q(C-E)T/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld (debug in RAM dedicated)
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G471QCTx Device from STM32G4 series
+**                      256Kbytes FLASH
+**                      128Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G471R(C-E)T/generic_clock.c b/variants/STM32G4xx/G471R(C-E)T/generic_clock.c
index ea3813ef6d..1ef4f86ca2 100644
--- a/variants/STM32G4xx/G471R(C-E)T/generic_clock.c
+++ b/variants/STM32G4xx/G471R(C-E)T/generic_clock.c
@@ -20,8 +20,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G471R(C-E)T/ldscript.ld b/variants/STM32G4xx/G471R(C-E)T/ldscript.ld
new file mode 100644
index 0000000000..981f26bcb6
--- /dev/null
+++ b/variants/STM32G4xx/G471R(C-E)T/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G471RCTx Device from STM32G4 series
+**                      256Kbytes FLASH
+**                      128Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G471V(C-E)(H-I-T)/generic_clock.c b/variants/STM32G4xx/G471V(C-E)(H-I-T)/generic_clock.c
index d0cd7a04ba..c48fad793c 100644
--- a/variants/STM32G4xx/G471V(C-E)(H-I-T)/generic_clock.c
+++ b/variants/STM32G4xx/G471V(C-E)(H-I-T)/generic_clock.c
@@ -22,8 +22,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G471V(C-E)(H-I-T)/ldscript.ld b/variants/STM32G4xx/G471V(C-E)(H-I-T)/ldscript.ld
new file mode 100644
index 0000000000..ac9ec8adeb
--- /dev/null
+++ b/variants/STM32G4xx/G471V(C-E)(H-I-T)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G471VCHx Device from STM32G4 series
+**                      256Kbytes FLASH
+**                      128Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/generic_clock.c b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/generic_clock.c
index 59d2d0de53..084f46c9f4 100644
--- a/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/generic_clock.c
+++ b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/generic_clock.c
@@ -23,8 +23,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/ldscript.ld b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/ldscript.ld
new file mode 100644
index 0000000000..f715f98c76
--- /dev/null
+++ b/variants/STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G473CBTx Device from STM32G4 series
+**                      128Kbytes FLASH
+**                      128Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/generic_clock.c b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/generic_clock.c
index 559a08119d..3469e446c2 100644
--- a/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/generic_clock.c
+++ b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/generic_clock.c
@@ -23,8 +23,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/ldscript.ld b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/ldscript.ld
new file mode 100644
index 0000000000..6e97736e73
--- /dev/null
+++ b/variants/STM32G4xx/G473M(B-C-E)T_G474M(B-C-E)T_G483MET_G484MET/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G473MBTx Device from STM32G4 series
+**                      128Kbytes FLASH
+**                      128Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/generic_clock.c b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/generic_clock.c
index 823815a8ef..a40fafdba1 100644
--- a/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/generic_clock.c
+++ b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/generic_clock.c
@@ -23,8 +23,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/ldscript.ld b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/ldscript.ld
new file mode 100644
index 0000000000..53b52eda4a
--- /dev/null
+++ b/variants/STM32G4xx/G473P(B-C-E)I_G474P(B-C-E)I_G483PEI_G484PEI/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G473PBIx Device from STM32G4 series
+**                      128Kbytes FLASH
+**                      128Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET/generic_clock.c b/variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET/generic_clock.c
index b63ab3baab..67568c131c 100644
--- a/variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET/generic_clock.c
+++ b/variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET/generic_clock.c
@@ -23,8 +23,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET/ldscript.ld b/variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET/ldscript.ld
new file mode 100644
index 0000000000..573a1eae4f
--- /dev/null
+++ b/variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G473QBTx Device from STM32G4 series
+**                      128Kbytes FLASH
+**                      128Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/generic_clock.c b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/generic_clock.c
index f934bab798..19cc3eec9d 100644
--- a/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/generic_clock.c
+++ b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/generic_clock.c
@@ -27,8 +27,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/ldscript.ld b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/ldscript.ld
new file mode 100644
index 0000000000..7f2560b13b
--- /dev/null
+++ b/variants/STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G473VBHx Device from STM32G4 series
+**                      128Kbytes FLASH
+**                      128Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G491C(C-E)T_G4A1CET/generic_clock.c b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/generic_clock.c
index c8a34e70ed..3f878953fb 100644
--- a/variants/STM32G4xx/G491C(C-E)T_G4A1CET/generic_clock.c
+++ b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/generic_clock.c
@@ -21,8 +21,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G491C(C-E)T_G4A1CET/ldscript.ld b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/ldscript.ld
new file mode 100644
index 0000000000..01e036356b
--- /dev/null
+++ b/variants/STM32G4xx/G491C(C-E)T_G4A1CET/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G491CCTx Device from STM32G4 series
+**                      256Kbytes FLASH
+**                      112Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/generic_clock.c b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/generic_clock.c
index 68da5e4ecc..b6d0ec56f3 100644
--- a/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/generic_clock.c
+++ b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/generic_clock.c
@@ -21,8 +21,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/ldscript.ld b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/ldscript.ld
new file mode 100644
index 0000000000..4b8c9a8648
--- /dev/null
+++ b/variants/STM32G4xx/G491K(C-E)U_G4A1KEU/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G491KCUx Device from STM32G4 series
+**                      256Kbytes FLASH
+**                      112Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/generic_clock.c b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/generic_clock.c
index f19f21b1d1..147446f237 100644
--- a/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/generic_clock.c
+++ b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/generic_clock.c
@@ -22,8 +22,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/ldscript.ld b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/ldscript.ld
new file mode 100644
index 0000000000..3aa627662f
--- /dev/null
+++ b/variants/STM32G4xx/G491M(C-E)(S-T)_G4A1ME(S-T)/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G491MCSx Device from STM32G4 series
+**                      256Kbytes FLASH
+**                      112Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32G4xx/G491V(C-E)T_G4A1VET/generic_clock.c b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/generic_clock.c
index 7f8bd7c184..c1f94276b5 100644
--- a/variants/STM32G4xx/G491V(C-E)T_G4A1VET/generic_clock.c
+++ b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/generic_clock.c
@@ -21,8 +21,43 @@
   */
 WEAK void SystemClock_Config(void)
 {
-  /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+  RCC_OscInitTypeDef RCC_OscInitStruct = {};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+    Error_Handler();
+  }
 }
 
 #endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32G4xx/G491V(C-E)T_G4A1VET/ldscript.ld b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/ldscript.ld
new file mode 100644
index 0000000000..08e6ab9d25
--- /dev/null
+++ b/variants/STM32G4xx/G491V(C-E)T_G4A1VET/ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+** @brief       : Linker script for STM32G491VCTx Device from STM32G4 series
+**                      256Kbytes FLASH
+**                      112Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = LD_MAX_DATA_SIZE
+  FLASH    (rx)    : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}