From 165bfbdca2bcc5d5b3a41a57395204ad2a6d5142 Mon Sep 17 00:00:00 2001 From: Alexandre Bourdiol Date: Fri, 8 Apr 2022 14:33:27 +0200 Subject: [PATCH 1/2] system(F4) update STM32F4xx HAL Drivers to v1.8.0 Included in STM32CubeF4 FW v1.27.0 Signed-off-by: Alexandre Bourdiol --- .../Inc/Legacy/stm32_hal_legacy.h | 156 +- .../Inc/Legacy/stm32f4xx_hal_can_legacy.h | 30 +- .../Inc/Legacy/stm32f4xx_hal_eth_legacy.h | 2209 + .../Inc/stm32_assert_template.h | 12 +- .../STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h | 12 +- .../Inc/stm32f4xx_hal_adc.h | 12 +- .../Inc/stm32f4xx_hal_adc_ex.h | 12 +- .../Inc/stm32f4xx_hal_can.h | 14 +- .../Inc/stm32f4xx_hal_cec.h | 14 +- .../Inc/stm32f4xx_hal_conf_template.h | 13 +- .../Inc/stm32f4xx_hal_cortex.h | 13 +- .../Inc/stm32f4xx_hal_crc.h | 13 +- .../Inc/stm32f4xx_hal_cryp.h | 12 +- .../Inc/stm32f4xx_hal_cryp_ex.h | 12 +- .../Inc/stm32f4xx_hal_dac.h | 12 +- .../Inc/stm32f4xx_hal_dac_ex.h | 12 +- .../Inc/stm32f4xx_hal_dcmi.h | 14 +- .../Inc/stm32f4xx_hal_dcmi_ex.h | 14 +- .../Inc/stm32f4xx_hal_def.h | 12 +- .../Inc/stm32f4xx_hal_dfsdm.h | 21 +- .../Inc/stm32f4xx_hal_dma.h | 12 +- .../Inc/stm32f4xx_hal_dma2d.h | 23 +- .../Inc/stm32f4xx_hal_dma_ex.h | 12 +- .../Inc/stm32f4xx_hal_dsi.h | 284 +- .../Inc/stm32f4xx_hal_eth.h | 2550 +- .../Inc/stm32f4xx_hal_exti.h | 12 +- .../Inc/stm32f4xx_hal_flash.h | 13 +- .../Inc/stm32f4xx_hal_flash_ex.h | 13 +- .../Inc/stm32f4xx_hal_flash_ramfunc.h | 13 +- .../Inc/stm32f4xx_hal_fmpi2c.h | 27 +- .../Inc/stm32f4xx_hal_fmpi2c_ex.h | 13 +- .../Inc/stm32f4xx_hal_fmpsmbus.h | 35 +- .../Inc/stm32f4xx_hal_fmpsmbus_ex.h | 17 +- .../Inc/stm32f4xx_hal_gpio.h | 12 +- .../Inc/stm32f4xx_hal_gpio_ex.h | 12 +- .../Inc/stm32f4xx_hal_hash.h | 12 +- .../Inc/stm32f4xx_hal_hash_ex.h | 12 +- .../Inc/stm32f4xx_hal_hcd.h | 13 +- .../Inc/stm32f4xx_hal_i2c.h | 12 +- .../Inc/stm32f4xx_hal_i2c_ex.h | 12 +- .../Inc/stm32f4xx_hal_i2s.h | 12 +- .../Inc/stm32f4xx_hal_i2s_ex.h | 12 +- .../Inc/stm32f4xx_hal_irda.h | 20 +- .../Inc/stm32f4xx_hal_iwdg.h | 13 +- .../Inc/stm32f4xx_hal_lptim.h | 19 +- .../Inc/stm32f4xx_hal_ltdc.h | 111 +- .../Inc/stm32f4xx_hal_ltdc_ex.h | 13 +- .../Inc/stm32f4xx_hal_mmc.h | 28 +- .../Inc/stm32f4xx_hal_nand.h | 159 +- .../Inc/stm32f4xx_hal_nor.h | 150 +- .../Inc/stm32f4xx_hal_pccard.h | 70 +- .../Inc/stm32f4xx_hal_pcd.h | 43 +- .../Inc/stm32f4xx_hal_pcd_ex.h | 17 +- .../Inc/stm32f4xx_hal_pwr.h | 14 +- .../Inc/stm32f4xx_hal_pwr_ex.h | 14 +- .../Inc/stm32f4xx_hal_qspi.h | 41 +- .../Inc/stm32f4xx_hal_rcc.h | 13 +- .../Inc/stm32f4xx_hal_rcc_ex.h | 13 +- .../Inc/stm32f4xx_hal_rng.h | 12 +- .../Inc/stm32f4xx_hal_rtc.h | 457 +- .../Inc/stm32f4xx_hal_rtc_ex.h | 614 +- .../Inc/stm32f4xx_hal_sai.h | 14 +- .../Inc/stm32f4xx_hal_sai_ex.h | 12 +- .../Inc/stm32f4xx_hal_sd.h | 13 +- .../Inc/stm32f4xx_hal_sdram.h | 88 +- .../Inc/stm32f4xx_hal_smartcard.h | 20 +- .../Inc/stm32f4xx_hal_smbus.h | 12 +- .../Inc/stm32f4xx_hal_spdifrx.h | 98 +- .../Inc/stm32f4xx_hal_spi.h | 15 +- .../Inc/stm32f4xx_hal_sram.h | 162 +- .../Inc/stm32f4xx_hal_tim.h | 65 +- .../Inc/stm32f4xx_hal_tim_ex.h | 15 +- .../Inc/stm32f4xx_hal_uart.h | 20 +- .../Inc/stm32f4xx_hal_usart.h | 26 +- .../Inc/stm32f4xx_hal_wwdg.h | 15 +- .../Inc/stm32f4xx_ll_adc.h | 16 +- .../Inc/stm32f4xx_ll_bus.h | 13 +- .../Inc/stm32f4xx_ll_cortex.h | 13 +- .../Inc/stm32f4xx_ll_crc.h | 13 +- .../Inc/stm32f4xx_ll_dac.h | 12 +- .../Inc/stm32f4xx_ll_dma.h | 18 +- .../Inc/stm32f4xx_ll_dma2d.h | 13 +- .../Inc/stm32f4xx_ll_exti.h | 12 +- .../Inc/stm32f4xx_ll_fmc.h | 1061 +- .../Inc/stm32f4xx_ll_fmpi2c.h | 15 +- .../Inc/stm32f4xx_ll_fsmc.h | 747 +- .../Inc/stm32f4xx_ll_gpio.h | 12 +- .../Inc/stm32f4xx_ll_i2c.h | 12 +- .../Inc/stm32f4xx_ll_iwdg.h | 13 +- .../Inc/stm32f4xx_ll_lptim.h | 27 +- .../Inc/stm32f4xx_ll_pwr.h | 14 +- .../Inc/stm32f4xx_ll_rcc.h | 13 +- .../Inc/stm32f4xx_ll_rng.h | 12 +- .../Inc/stm32f4xx_ll_rtc.h | 390 +- .../Inc/stm32f4xx_ll_sdmmc.h | 34 +- .../Inc/stm32f4xx_ll_spi.h | 12 +- .../Inc/stm32f4xx_ll_system.h | 28 +- .../Inc/stm32f4xx_ll_tim.h | 14 +- .../Inc/stm32f4xx_ll_usart.h | 12 +- .../Inc/stm32f4xx_ll_usb.h | 44 +- .../Inc/stm32f4xx_ll_utils.h | 13 +- .../Inc/stm32f4xx_ll_wwdg.h | 13 +- .../Drivers/STM32F4xx_HAL_Driver/License.md | 4 +- system/Drivers/STM32F4xx_HAL_Driver/README.md | 8 +- .../STM32F4xx_HAL_Driver/Release_Notes.html | 63609 +++------------- .../Src/Legacy/stm32f4xx_hal_can.c | 40 +- .../Src/Legacy/stm32f4xx_hal_eth.c | 2307 + .../STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c | 29 +- .../Src/stm32f4xx_hal_adc.c | 49 +- .../Src/stm32f4xx_hal_adc_ex.c | 24 +- .../Src/stm32f4xx_hal_can.c | 26 +- .../Src/stm32f4xx_hal_cec.c | 25 +- .../Src/stm32f4xx_hal_cortex.c | 13 +- .../Src/stm32f4xx_hal_crc.c | 24 +- .../Src/stm32f4xx_hal_cryp.c | 47 +- .../Src/stm32f4xx_hal_cryp_ex.c | 27 +- .../Src/stm32f4xx_hal_dac.c | 23 +- .../Src/stm32f4xx_hal_dac_ex.c | 23 +- .../Src/stm32f4xx_hal_dcmi.c | 23 +- .../Src/stm32f4xx_hal_dcmi_ex.c | 23 +- .../Src/stm32f4xx_hal_dfsdm.c | 24 +- .../Src/stm32f4xx_hal_dma.c | 22 +- .../Src/stm32f4xx_hal_dma2d.c | 46 +- .../Src/stm32f4xx_hal_dma_ex.c | 12 +- .../Src/stm32f4xx_hal_dsi.c | 97 +- .../Src/stm32f4xx_hal_eth.c | 3967 +- .../Src/stm32f4xx_hal_exti.c | 28 +- .../Src/stm32f4xx_hal_flash.c | 13 +- .../Src/stm32f4xx_hal_flash_ex.c | 13 +- .../Src/stm32f4xx_hal_flash_ramfunc.c | 13 +- .../Src/stm32f4xx_hal_fmpi2c.c | 407 +- .../Src/stm32f4xx_hal_fmpi2c_ex.c | 25 +- .../Src/stm32f4xx_hal_fmpsmbus.c | 109 +- .../Src/stm32f4xx_hal_fmpsmbus_ex.c | 25 +- .../Src/stm32f4xx_hal_gpio.c | 55 +- .../Src/stm32f4xx_hal_hash.c | 58 +- .../Src/stm32f4xx_hal_hash_ex.c | 25 +- .../Src/stm32f4xx_hal_hcd.c | 101 +- .../Src/stm32f4xx_hal_i2c.c | 30 +- .../Src/stm32f4xx_hal_i2c_ex.c | 24 +- .../Src/stm32f4xx_hal_i2s.c | 25 +- .../Src/stm32f4xx_hal_i2s_ex.c | 23 +- .../Src/stm32f4xx_hal_irda.c | 73 +- .../Src/stm32f4xx_hal_iwdg.c | 27 +- .../Src/stm32f4xx_hal_lptim.c | 115 +- .../Src/stm32f4xx_hal_ltdc.c | 122 +- .../Src/stm32f4xx_hal_ltdc_ex.c | 24 +- .../Src/stm32f4xx_hal_mmc.c | 460 +- .../Src/stm32f4xx_hal_msp_template.c | 12 +- .../Src/stm32f4xx_hal_nand.c | 2478 +- .../Src/stm32f4xx_hal_nor.c | 1256 +- .../Src/stm32f4xx_hal_pccard.c | 274 +- .../Src/stm32f4xx_hal_pcd.c | 233 +- .../Src/stm32f4xx_hal_pcd_ex.c | 55 +- .../Src/stm32f4xx_hal_pwr.c | 14 +- .../Src/stm32f4xx_hal_pwr_ex.c | 14 +- .../Src/stm32f4xx_hal_qspi.c | 230 +- .../Src/stm32f4xx_hal_rcc.c | 13 +- .../Src/stm32f4xx_hal_rcc_ex.c | 13 +- .../Src/stm32f4xx_hal_rng.c | 25 +- .../Src/stm32f4xx_hal_rtc.c | 1267 +- .../Src/stm32f4xx_hal_rtc_ex.c | 968 +- .../Src/stm32f4xx_hal_sai.c | 24 +- .../Src/stm32f4xx_hal_sai_ex.c | 23 +- .../Src/stm32f4xx_hal_sd.c | 27 +- .../Src/stm32f4xx_hal_sdram.c | 826 +- .../Src/stm32f4xx_hal_smartcard.c | 42 +- .../Src/stm32f4xx_hal_smbus.c | 24 +- .../Src/stm32f4xx_hal_spdifrx.c | 190 +- .../Src/stm32f4xx_hal_spi.c | 29 +- .../Src/stm32f4xx_hal_sram.c | 740 +- .../Src/stm32f4xx_hal_tim.c | 43 +- .../Src/stm32f4xx_hal_tim_ex.c | 29 +- ...tm32f4xx_hal_timebase_rtc_alarm_template.c | 24 +- ...m32f4xx_hal_timebase_rtc_wakeup_template.c | 24 +- .../Src/stm32f4xx_hal_timebase_tim_template.c | 13 +- .../Src/stm32f4xx_hal_uart.c | 72 +- .../Src/stm32f4xx_hal_usart.c | 124 +- .../Src/stm32f4xx_hal_wwdg.c | 26 +- .../Src/stm32f4xx_ll_adc.c | 12 +- .../Src/stm32f4xx_ll_crc.c | 16 +- .../Src/stm32f4xx_ll_dac.c | 12 +- .../Src/stm32f4xx_ll_dma.c | 12 +- .../Src/stm32f4xx_ll_dma2d.c | 14 +- .../Src/stm32f4xx_ll_exti.c | 12 +- .../Src/stm32f4xx_ll_fmc.c | 1216 +- .../Src/stm32f4xx_ll_fmpi2c.c | 13 +- .../Src/stm32f4xx_ll_fsmc.c | 741 +- .../Src/stm32f4xx_ll_gpio.c | 12 +- .../Src/stm32f4xx_ll_i2c.c | 12 +- .../Src/stm32f4xx_ll_lptim.c | 21 +- .../Src/stm32f4xx_ll_pwr.c | 14 +- .../Src/stm32f4xx_ll_rcc.c | 13 +- .../Src/stm32f4xx_ll_rng.c | 39 +- .../Src/stm32f4xx_ll_rtc.c | 59 +- .../Src/stm32f4xx_ll_sdmmc.c | 183 +- .../Src/stm32f4xx_ll_spi.c | 12 +- .../Src/stm32f4xx_ll_tim.c | 12 +- .../Src/stm32f4xx_ll_usart.c | 12 +- .../Src/stm32f4xx_ll_usb.c | 194 +- .../Src/stm32f4xx_ll_utils.c | 13 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 202 files changed, 27761 insertions(+), 67048 deletions(-) create mode 100644 system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_eth_legacy.h create mode 100644 system/Drivers/STM32F4xx_HAL_Driver/Src/Legacy/stm32f4xx_hal_eth.c diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index ae83378c19..1cfd19b94a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -105,6 +104,12 @@ extern "C" { #if defined(STM32H7) #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ /** * @} */ @@ -214,10 +219,20 @@ extern "C" { * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ /** * @} */ +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ /** * @} */ @@ -252,6 +267,13 @@ extern "C" { #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID @@ -394,6 +416,10 @@ extern "C" { #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ /** * @} */ @@ -542,6 +568,7 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ + /** * @} */ @@ -637,6 +664,20 @@ extern "C" { #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#endif /* STM32U5 */ /** * @} */ @@ -874,9 +915,19 @@ extern "C" { #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + #if defined(STM32U5) #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U #endif /* STM32U5 */ /** * @} @@ -1216,6 +1267,10 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif /** * @} */ @@ -1646,6 +1701,79 @@ extern "C" { #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + /** * @} */ @@ -3404,7 +3532,21 @@ extern "C" { #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE #endif + /** * @} */ @@ -3474,6 +3616,7 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + /** * @} */ @@ -3836,5 +3979,4 @@ extern "C" { #endif /* STM32_HAL_LEGACY */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h index fd809622a6..715d61f994 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h @@ -6,29 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -780,6 +763,3 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); #endif #endif /* __STM32F4xx_HAL_CAN_LEGACY_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_eth_legacy.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_eth_legacy.h new file mode 100644 index 0000000000..ab84a468b0 --- /dev/null +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_eth_legacy.h @@ -0,0 +1,2209 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_eth_legacy.h + * @author MCD Application Team + * @brief Header file of ETH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_ETH_LEGACY_H +#define __STM32F4xx_HAL_ETH_LEGACY_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup ETH + * @{ + */ + +/** @addtogroup ETH_Private_Macros + * @{ + */ +#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) +#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ + ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) +#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ + ((SPEED) == ETH_SPEED_100M)) +#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ + ((MODE) == ETH_MODE_HALFDUPLEX)) +#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ + ((MODE) == ETH_RXINTERRUPT_MODE)) +#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ + ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) +#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ + ((MODE) == ETH_MEDIA_INTERFACE_RMII)) +#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ + ((CMD) == ETH_WATCHDOG_DISABLE)) +#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ + ((CMD) == ETH_JABBER_DISABLE)) +#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_40BIT)) +#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ + ((CMD) == ETH_CARRIERSENCE_DISABLE)) +#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ + ((CMD) == ETH_RECEIVEOWN_DISABLE)) +#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ + ((CMD) == ETH_LOOPBACKMODE_DISABLE)) +#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ + ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) +#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ + ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) +#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ + ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) +#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ + ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ + ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ + ((LIMIT) == ETH_BACKOFFLIMIT_1)) +#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ + ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) +#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ + ((CMD) == ETH_RECEIVEAll_DISABLE)) +#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ + ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ + ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) +#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ + ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ + ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) +#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ + ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) +#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ + ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) +#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ + ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) +#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ + ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ + ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ + ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) +#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ + ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ + ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) +#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) +#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ + ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) +#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ + ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ + ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ + ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) +#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ + ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) +#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ + ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) +#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ + ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) +#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ + ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) +#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) +#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ + ((ADDRESS) == ETH_MAC_ADDRESS1) || \ + ((ADDRESS) == ETH_MAC_ADDRESS2) || \ + ((ADDRESS) == ETH_MAC_ADDRESS3)) +#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ + ((ADDRESS) == ETH_MAC_ADDRESS2) || \ + ((ADDRESS) == ETH_MAC_ADDRESS3)) +#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ + ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) +#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) +#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ + ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) +#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ + ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) +#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ + ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) +#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ + ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) +#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) +#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ + ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) +#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ + ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) +#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ + ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ + ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ + ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) +#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ + ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) +#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ + ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) +#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ + ((CMD) == ETH_FIXEDBURST_DISABLE)) +#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) +#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) +#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) +#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ + ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ + ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ + ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ + ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) +#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ + ((FLAG) == ETH_DMATXDESC_IC) || \ + ((FLAG) == ETH_DMATXDESC_LS) || \ + ((FLAG) == ETH_DMATXDESC_FS) || \ + ((FLAG) == ETH_DMATXDESC_DC) || \ + ((FLAG) == ETH_DMATXDESC_DP) || \ + ((FLAG) == ETH_DMATXDESC_TTSE) || \ + ((FLAG) == ETH_DMATXDESC_TER) || \ + ((FLAG) == ETH_DMATXDESC_TCH) || \ + ((FLAG) == ETH_DMATXDESC_TTSS) || \ + ((FLAG) == ETH_DMATXDESC_IHE) || \ + ((FLAG) == ETH_DMATXDESC_ES) || \ + ((FLAG) == ETH_DMATXDESC_JT) || \ + ((FLAG) == ETH_DMATXDESC_FF) || \ + ((FLAG) == ETH_DMATXDESC_PCE) || \ + ((FLAG) == ETH_DMATXDESC_LCA) || \ + ((FLAG) == ETH_DMATXDESC_NC) || \ + ((FLAG) == ETH_DMATXDESC_LCO) || \ + ((FLAG) == ETH_DMATXDESC_EC) || \ + ((FLAG) == ETH_DMATXDESC_VF) || \ + ((FLAG) == ETH_DMATXDESC_CC) || \ + ((FLAG) == ETH_DMATXDESC_ED) || \ + ((FLAG) == ETH_DMATXDESC_UF) || \ + ((FLAG) == ETH_DMATXDESC_DB)) +#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ + ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) +#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ + ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ + ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ + ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) +#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) +#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ + ((FLAG) == ETH_DMARXDESC_AFM) || \ + ((FLAG) == ETH_DMARXDESC_ES) || \ + ((FLAG) == ETH_DMARXDESC_DE) || \ + ((FLAG) == ETH_DMARXDESC_SAF) || \ + ((FLAG) == ETH_DMARXDESC_LE) || \ + ((FLAG) == ETH_DMARXDESC_OE) || \ + ((FLAG) == ETH_DMARXDESC_VLAN) || \ + ((FLAG) == ETH_DMARXDESC_FS) || \ + ((FLAG) == ETH_DMARXDESC_LS) || \ + ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ + ((FLAG) == ETH_DMARXDESC_LC) || \ + ((FLAG) == ETH_DMARXDESC_FT) || \ + ((FLAG) == ETH_DMARXDESC_RWT) || \ + ((FLAG) == ETH_DMARXDESC_RE) || \ + ((FLAG) == ETH_DMARXDESC_DBE) || \ + ((FLAG) == ETH_DMARXDESC_CE) || \ + ((FLAG) == ETH_DMARXDESC_MAMPCE)) +#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ + ((BUFFER) == ETH_DMARXDESC_BUFFER2)) +#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ + ((FLAG) == ETH_PMT_FLAG_MPR)) +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) +#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ + ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ + ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ + ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ + ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ + ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ + ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ + ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ + ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ + ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ + ((FLAG) == ETH_DMA_FLAG_T)) +#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) +#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ + ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ + ((IT) == ETH_MAC_IT_PMT)) +#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ + ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ + ((FLAG) == ETH_MAC_FLAG_PMT)) +#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) +#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ + ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ + ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ + ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ + ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ + ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ + ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ + ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ + ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) +#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ + ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) +#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ + ((IT) != 0x00U)) +#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ + ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ + ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) +#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ + ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Private_Defines + * @{ + */ +/* Delay to wait when writing to some Ethernet registers */ +#define ETH_REG_WRITE_DELAY 0x00000001U + +/* ETHERNET Errors */ +#define ETH_SUCCESS 0U +#define ETH_ERROR 1U + +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U + +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U + +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U + +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U + +/* ETHERNET DMA Rx descriptors Frame length Shift */ +#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U + +/* ETHERNET MAC address offsets */ +#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ + +/* ETHERNET MACMIIAR register Mask */ +#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U + +/* ETHERNET MACCR register Mask */ +#define ETH_MACCR_CLEAR_MASK 0xFF20810FU + +/* ETHERNET MACFCR register Mask */ +#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U + +/* ETHERNET DMAOMR register Mask */ +#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U + +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8U + +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U + /** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ETH_Exported_Types ETH Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ + HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ + HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ + HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ + HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +}HAL_ETH_StateTypeDef; + +/** + * @brief ETH Init Structure definition + */ + +typedef struct +{ + uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex). + This parameter can be a value of @ref ETH_AutoNegotiation */ + + uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. + This parameter can be a value of @ref ETH_Speed */ + + uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref ETH_Duplex_Mode */ + + uint16_t PhyAddress; /*!< Ethernet PHY address. + This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ + + uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ + + uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. + This parameter can be a value of @ref ETH_Rx_Mode */ + + uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. + This parameter can be a value of @ref ETH_Checksum_Mode */ + + uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface. + This parameter can be a value of @ref ETH_Media_Interface */ + +} ETH_InitTypeDef; + + + /** + * @brief ETH MAC Configuration Structure definition + */ + +typedef struct +{ + uint32_t Watchdog; /*!< Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref ETH_Watchdog */ + + uint32_t Jabber; /*!< Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref ETH_Jabber */ + + uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. + This parameter can be a value of @ref ETH_Inter_Frame_Gap */ + + uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. + This parameter can be a value of @ref ETH_Carrier_Sense */ + + uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode. + This parameter can be a value of @ref ETH_Receive_Own */ + + uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. + This parameter can be a value of @ref ETH_Loop_Back_Mode */ + + uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. + This parameter can be a value of @ref ETH_Checksum_Offload */ + + uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a collision occurs (Half-Duplex mode). + This parameter can be a value of @ref ETH_Retry_Transmission */ + + uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. + This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ + + uint32_t BackOffLimit; /*!< Selects the BackOff limit value. + This parameter can be a value of @ref ETH_Back_Off_Limit */ + + uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). + This parameter can be a value of @ref ETH_Deferral_Check */ + + uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). + This parameter can be a value of @ref ETH_Receive_All */ + + uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + + uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + This parameter can be a value of @ref ETH_Pass_Control_Frames */ + + uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. + This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ + + uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + + uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + + uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. + This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ + + uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. + This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ + + uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ + + uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ + + uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */ + + uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. + This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ + + uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame. + This parameter can be a value of @ref ETH_Pause_Low_Threshold */ + + uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address). + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + + uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + + uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + + uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering. + This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ + + uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ + +} ETH_MACInitTypeDef; + +/** + * @brief ETH DMA Configuration Structure definition + */ + +typedef struct +{ + uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. + This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ + + uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. + This parameter can be a value of @ref ETH_Receive_Store_Forward */ + + uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. + This parameter can be a value of @ref ETH_Flush_Received_Frame */ + + uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + + uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. + This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ + + uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. + This parameter can be a value of @ref ETH_Forward_Error_Frames */ + + uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ + + uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. + This parameter can be a value of @ref ETH_Receive_Threshold_Control */ + + uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. + This parameter can be a value of @ref ETH_Second_Frame_Operate */ + + uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. + This parameter can be a value of @ref ETH_Address_Aligned_Beats */ + + uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. + This parameter can be a value of @ref ETH_Fixed_Burst */ + + uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. + This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ + + uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. + This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ + + uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. + This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ + + uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) + This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ + + uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. + This parameter can be a value of @ref ETH_DMA_Arbitration */ +} ETH_DMAInitTypeDef; + + +/** + * @brief ETH DMA Descriptors data structure definition + */ + +typedef struct +{ + __IO uint32_t Status; /*!< Status */ + + uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ + + uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ + + uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ + + /*!< Enhanced ETHERNET DMA PTP Descriptors */ + uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ + + uint32_t Reserved1; /*!< Reserved */ + + uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ + + uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ + +} ETH_DMADescTypeDef; + +/** + * @brief Received Frame Informations structure definition + */ +typedef struct +{ + ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ + + ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ + + uint32_t SegCount; /*!< Segment count */ + + uint32_t length; /*!< Frame length */ + + uint32_t buffer; /*!< Frame buffer */ + +} ETH_DMARxFrameInfos; + +/** + * @brief ETH Handle Structure definition + */ + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +typedef struct __ETH_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ +{ + ETH_TypeDef *Instance; /*!< Register base address */ + + ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ + + uint32_t LinkStatus; /*!< Ethernet link status */ + + ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ + + ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ + + ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ + + __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ + + HAL_LockTypeDef Lock; /*!< ETH Lock */ + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + + void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */ + void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */ + void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< DMA Error Callback */ + void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */ + void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */ + +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +} ETH_HandleTypeDef; + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ETH Callback ID enumeration definition + */ +typedef enum +{ + HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ + HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ + HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ + HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ + HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ + +}HAL_ETH_CallbackIDTypeDef; + +/** + * @brief HAL ETH Callback pointer definition + */ +typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */ + +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ETH_Exported_Constants ETH Exported Constants + * @{ + */ + +/** @defgroup ETH_Buffers_setting ETH Buffers setting + * @{ + */ +#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4U /*!< Ethernet CRC */ +#define ETH_EXTRA 2U /*!< Extra bytes in some cases */ +#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ +#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ +#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ + + /* Ethernet driver receive buffers are organized in a chained linked-list, when + an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO + to the driver receive buffers memory. + + Depending on the size of the received ethernet packet and the size of + each ethernet driver receive buffer, the received packet can take one or more + ethernet driver receive buffer. + + In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE + and the total count of the driver receive buffers ETH_RXBUFNB. + + The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as + example, they can be reconfigured in the application layer to fit the application + needs */ + +/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet + packet */ +#ifndef ETH_RX_BUF_SIZE + #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ +#ifndef ETH_RXBUFNB + #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ +#endif + + + /* Ethernet driver transmit buffers are organized in a chained linked-list, when + an ethernet packet is transmitted, Tx-DMA will transfer the packet from the + driver transmit buffers memory to the TxFIFO. + + Depending on the size of the Ethernet packet to be transmitted and the size of + each ethernet driver transmit buffer, the packet to be transmitted can take + one or more ethernet driver transmit buffer. + + In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE + and the total count of the driver transmit buffers ETH_TXBUFNB. + + The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as + example, they can be reconfigured in the application layer to fit the application + needs */ + +/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet + packet */ +#ifndef ETH_TX_BUF_SIZE + #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ +#ifndef ETH_TXBUFNB + #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ +#endif + + /** + * @} + */ + +/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor + * @{ + */ + +/* + DMA Tx Descriptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | + ----------------------------------------------------------------------------------------------- +*/ + +/** + * @brief Bit definition of TDES0 register: DMA Tx descriptor status register + */ +#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ +#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ +#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ +#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ +#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ +#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ +#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ +#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ +#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ +#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ +#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ +#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ +#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ +#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ +#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ +#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ +#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ +#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ + +/** + * @brief Bit definition of TDES1 register + */ +#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ +#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ + +/** + * @brief Bit definition of TDES2 register + */ +#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of TDES3 register + */ +#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ + + /*--------------------------------------------------------------------------------------------- + TDES6 | Transmit Time Stamp Low [31:0] | + ----------------------------------------------------------------------------------------------- + TDES7 | Transmit Time Stamp High [31:0] | + ----------------------------------------------------------------------------------------------*/ + +/* Bit definition of TDES6 register */ + #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ + +/* Bit definition of TDES7 register */ + #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ + +/** + * @} + */ +/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor + * @{ + */ + +/* + DMA Rx Descriptor + -------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- +*/ + +/** + * @brief Bit definition of RDES0 register: DMA Rx descriptor status register + */ +#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ +#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ +#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ +#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ +#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ +#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ +#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ +#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ +#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ +#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/** + * @brief Bit definition of RDES1 register + */ +#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ +#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ +#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ +#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ +#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ + +/** + * @brief Bit definition of RDES2 register + */ +#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of RDES3 register + */ +#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ + +/*--------------------------------------------------------------------------------------------------------------------- + RDES4 | Reserved[31:15] | Extended Status [14:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES5 | Reserved[31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES6 | Receive Time Stamp Low [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES7 | Receive Time Stamp High [31:0] | + --------------------------------------------------------------------------------------------------------------------*/ + +/* Bit definition of RDES4 register */ +#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ +#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ +#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ + #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */ + #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */ + #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */ + #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */ + #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ + #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ + #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ +#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ +#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ +#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ +#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ +#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ + #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */ + #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */ + #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */ + +/* Bit definition of RDES6 register */ +#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ + +/* Bit definition of RDES7 register */ +#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ +/** + * @} + */ + /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation + * @{ + */ +#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U +#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U + +/** + * @} + */ +/** @defgroup ETH_Speed ETH Speed + * @{ + */ +#define ETH_SPEED_10M 0x00000000U +#define ETH_SPEED_100M 0x00004000U + +/** + * @} + */ +/** @defgroup ETH_Duplex_Mode ETH Duplex Mode + * @{ + */ +#define ETH_MODE_FULLDUPLEX 0x00000800U +#define ETH_MODE_HALFDUPLEX 0x00000000U +/** + * @} + */ +/** @defgroup ETH_Rx_Mode ETH Rx Mode + * @{ + */ +#define ETH_RXPOLLING_MODE 0x00000000U +#define ETH_RXINTERRUPT_MODE 0x00000001U +/** + * @} + */ + +/** @defgroup ETH_Checksum_Mode ETH Checksum Mode + * @{ + */ +#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U +#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U +/** + * @} + */ + +/** @defgroup ETH_Media_Interface ETH Media Interface + * @{ + */ +#define ETH_MEDIA_INTERFACE_MII 0x00000000U +#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) +/** + * @} + */ + +/** @defgroup ETH_Watchdog ETH Watchdog + * @{ + */ +#define ETH_WATCHDOG_ENABLE 0x00000000U +#define ETH_WATCHDOG_DISABLE 0x00800000U +/** + * @} + */ + +/** @defgroup ETH_Jabber ETH Jabber + * @{ + */ +#define ETH_JABBER_ENABLE 0x00000000U +#define ETH_JABBER_DISABLE 0x00400000U +/** + * @} + */ + +/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap + * @{ + */ +#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ +#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ +#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ +#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ +#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ +#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ +#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ +#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ +/** + * @} + */ + +/** @defgroup ETH_Carrier_Sense ETH Carrier Sense + * @{ + */ +#define ETH_CARRIERSENCE_ENABLE 0x00000000U +#define ETH_CARRIERSENCE_DISABLE 0x00010000U +/** + * @} + */ + +/** @defgroup ETH_Receive_Own ETH Receive Own + * @{ + */ +#define ETH_RECEIVEOWN_ENABLE 0x00000000U +#define ETH_RECEIVEOWN_DISABLE 0x00002000U +/** + * @} + */ + +/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode + * @{ + */ +#define ETH_LOOPBACKMODE_ENABLE 0x00001000U +#define ETH_LOOPBACKMODE_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Checksum_Offload ETH Checksum Offload + * @{ + */ +#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U +#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Retry_Transmission ETH Retry Transmission + * @{ + */ +#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U +#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U +/** + * @} + */ + +/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip + * @{ + */ +#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U +#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit + * @{ + */ +#define ETH_BACKOFFLIMIT_10 0x00000000U +#define ETH_BACKOFFLIMIT_8 0x00000020U +#define ETH_BACKOFFLIMIT_4 0x00000040U +#define ETH_BACKOFFLIMIT_1 0x00000060U +/** + * @} + */ + +/** @defgroup ETH_Deferral_Check ETH Deferral Check + * @{ + */ +#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U +#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Receive_All ETH Receive All + * @{ + */ +#define ETH_RECEIVEALL_ENABLE 0x80000000U +#define ETH_RECEIVEAll_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter + * @{ + */ +#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U +#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U +#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames + * @{ + */ +#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ +#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ +/** + * @} + */ + +/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception + * @{ + */ +#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U +#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U +/** + * @} + */ + +/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter + * @{ + */ +#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U +#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U +/** + * @} + */ + +/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode + * @{ + */ +#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U +#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter + * @{ + */ +#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U +#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U +#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U +#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U +/** + * @} + */ + +/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter + * @{ + */ +#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U +#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U +#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause + * @{ + */ +#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U +#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U +/** + * @} + */ + +/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold + * @{ + */ +#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ +/** + * @} + */ + +/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect + * @{ + */ +#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U +#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control + * @{ + */ +#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U +#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control + * @{ + */ +#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U +#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison + * @{ + */ +#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U +#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses ETH MAC addresses + * @{ + */ +#define ETH_MAC_ADDRESS0 0x00000000U +#define ETH_MAC_ADDRESS1 0x00000008U +#define ETH_MAC_ADDRESS2 0x00000010U +#define ETH_MAC_ADDRESS3 0x00000018U +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA + * @{ + */ +#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U +#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes + * @{ + */ +#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ +/** + * @} + */ + +/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame + * @{ + */ +#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U +#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U +/** + * @} + */ + +/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward + * @{ + */ +#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U +#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame + * @{ + */ +#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U +#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U +/** + * @} + */ + +/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward + * @{ + */ +#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U +#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control + * @{ + */ +#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ +/** + * @} + */ + +/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames + * @{ + */ +#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U +#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames + * @{ + */ +#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U +#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control + * @{ + */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ +/** + * @} + */ + +/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate + * @{ + */ +#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U +#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats + * @{ + */ +#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U +#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Fixed_Burst ETH Fixed Burst + * @{ + */ +#define ETH_FIXEDBURST_ENABLE 0x00010000U +#define ETH_FIXEDBURST_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length + * @{ + */ +#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ +/** + * @} + */ + +/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length + * @{ + */ +#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format + * @{ + */ +#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U +#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration + * @{ + */ +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U +#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment + * @{ + */ +#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ +#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control + * @{ + */ +#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ +#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ +#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers + * @{ + */ +#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ +#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ +/** + * @} + */ + +/** @defgroup ETH_PMT_Flags ETH PMT Flags + * @{ + */ +#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ +/** + * @} + */ + +/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts + * @{ + */ +#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ +/** + * @} + */ + +/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts + * @{ + */ +#define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ +/** + * @} + */ + +/** @defgroup ETH_MAC_Flags ETH MAC Flags + * @{ + */ +#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ +#define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Flags ETH DMA Flags + * @{ + */ +#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ +#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ +#define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ +#define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ +#define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ +#define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ +#define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ +/** + * @} + */ + +/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts + * @{ + */ +#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ +#define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts + * @{ + */ +#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ +#define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ +#define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ +#define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ +#define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ +#define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ +#define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ +#define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ +#define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ +#define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ +/** + * @} + */ + +/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state + * @{ + */ +#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ +#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ +#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ +#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ +#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ + +/** + * @} + */ + + +/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state + * @{ + */ +#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ +#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ +#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ +#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ +#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ + +/** + * @} + */ + +/** @defgroup ETH_DMA_overflow ETH DMA overflow + * @{ + */ +#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ +#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ +/** + * @} + */ + +/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP + * @{ + */ +#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ETH_Exported_Macros ETH Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +/** @brief Reset ETH handle state + * @param __HANDLE__ specifies the ETH handle. + * @retval None + */ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_ETH_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) +#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag of TDES0 to check. + * @retval the ETH_DMATxDescFlag (SET or RESET). + */ +#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) + +/** + * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag of RDES0 to check. + * @retval the ETH_DMATxDescFlag (SET or RESET). + */ +#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) + +/** + * @brief Enables the specified DMA Rx Desc receive interrupt. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) + +/** + * @brief Disables the specified DMA Rx Desc receive interrupt. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) + +/** + * @brief Set the specified DMA Rx Desc Own bit. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) + +/** + * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * @param __HANDLE__ ETH Handle + * @retval The Transmit descriptor collision counter value. + */ +#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) + +/** + * @brief Set the specified DMA Tx Desc Own bit. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) + +/** + * @brief Enables the specified DMA Tx Desc Transmit interrupt. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) + +/** + * @brief Disables the specified DMA Tx Desc Transmit interrupt. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) + +/** + * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * @param __HANDLE__ ETH Handle + * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. + * This parameter can be one of the following values: + * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass + * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum + * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present + * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header + * @retval None + */ +#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) + +/** + * @brief Enables the DMA Tx Desc CRC. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) + +/** + * @brief Disables the DMA Tx Desc CRC. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) + +/** + * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) + +/** + * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) + +/** + * @brief Enables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @retval None + */ +#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @retval None + */ +#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) + +/** + * @brief Initiate a Pause Control Frame (Full-duplex only). + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) + +/** + * @brief Checks whether the ETHERNET flow control busy bit is set or not. + * @param __HANDLE__ ETH Handle + * @retval The new state of flow control busy status bit (SET or RESET). + */ +#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) + +/** + * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) + +/** + * @brief Disables the MAC BackPressure operation activation (Half-duplex only). + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) + +/** + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag + * @arg ETH_MAC_FLAG_MMCR : MMC receive flag + * @arg ETH_MAC_FLAG_MMC : MMC flag + * @arg ETH_MAC_FLAG_PMT : PMT flag + * @retval The state of ETHERNET MAC flag. + */ +#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Enables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be + * enabled @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be + * disabled. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) + +/** + * @brief Clears the ETHERNET DMA IT pending bit. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. +* @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags + * @retval The new state of ETH_DMA_FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags + * @retval The new state of ETH_DMA_FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) + +/** + * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * @param __HANDLE__ ETH Handle + * @param __OVERFLOW__ specifies the DMA overflow flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter + * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter + * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). + */ +#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) + +/** + * @brief Set the DMA Receive status watchdog timer register value + * @param __HANDLE__ ETH Handle + * @param __VALUE__ DMA Receive status watchdog timer register value + * @retval None + */ +#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) + +/** + * @brief Enables any unicast packet filtered by the MAC address + * recognition to be a wake-up frame. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) + +/** + * @brief Disables any unicast packet filtered by the MAC address + * recognition to be a wake-up frame. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) + +/** + * @brief Enables the MAC Wake-Up Frame Detection. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) + +/** + * @brief Disables the MAC Wake-Up Frame Detection. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) + +/** + * @brief Enables the MAC Magic Packet Detection. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) + +/** + * @brief Disables the MAC Magic Packet Detection. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) + +/** + * @brief Enables the MAC Power Down. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) + +/** + * @brief Disables the MAC Power Down. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) + +/** + * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * @param __HANDLE__ ETH Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset + * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MPR : Magic Packet Received + * @retval The new state of ETHERNET PMT Flag (SET or RESET). + */ +#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) + +/** + * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ + (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) + +/** + * @brief Enables the MMC Counter Freeze. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) + +/** + * @brief Disables the MMC Counter Freeze. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) + +/** + * @brief Enables the MMC Reset On Read. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) + +/** + * @brief Disables the MMC Reset On Read. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) + +/** + * @brief Enables the MMC Counter Stop Rollover. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) + +/** + * @brief Disables the MMC Counter Stop Rollover. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) + +/** + * @brief Resets the MMC Counters. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) + +/** + * @brief Enables the specified ETHERNET MMC Rx interrupts. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value + * @retval None + */ +#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) +/** + * @brief Disables the specified ETHERNET MMC Rx interrupts. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value + * @retval None + */ +#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) +/** + * @brief Enables the specified ETHERNET MMC Tx interrupts. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @retval None + */ +#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET MMC Tx interrupts. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @retval None + */ +#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) + +/** + * @brief Enables the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Disables the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Enable event on ETH External event line. + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Disable event on ETH External event line + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Get flag of the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Clear flag of the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Enables rising edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP + +/** + * @brief Disables the rising edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Enables falling edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Disables falling edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Enables rising/falling edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ + EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ + }while(0U) + +/** + * @brief Disables rising/falling edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ + EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ + }while(0U) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup ETH_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ + +/** @addtogroup ETH_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); +HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* IO operation functions ****************************************************/ + +/** @addtogroup ETH_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); +/* Communication with PHY functions*/ +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); +/* Callback in non blocking modes (Interrupt) */ +void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ + +/** @addtogroup ETH_Exported_Functions_Group3 + * @{ + */ + +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ + +/** @addtogroup ETH_Exported_Functions_Group4 + * @{ + */ +HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ + STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_ETH_LEGACY_H */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32_assert_template.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32_assert_template.h index 4711b65d8f..8cbab0136f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32_assert_template.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32_assert_template.h @@ -8,13 +8,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -54,4 +53,3 @@ #endif /* __STM32_ASSERT_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h index fb8eb2ab0b..a5303ed292 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -295,4 +294,3 @@ void HAL_DisableMemorySwappingBank(void); #endif /* __STM32F4xx_HAL_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h index 408f2a0b9b..072ea91f05 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -897,4 +896,3 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); #endif /*__STM32F4xx_ADC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h index f0c2f74765..b0a4eb724d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -406,4 +405,3 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ #endif /*__STM32F4xx_ADC_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h index 062abd6925..aa4a40d0bc 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -843,6 +842,3 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); #endif #endif /* STM32F4xx_HAL_CAN_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h index 9041577369..9d6c226a74 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -105,7 +104,7 @@ typedef struct uint16_t OwnAddress; /*!< Own addresses configuration This parameter can be a value of @ref CEC_OWN_ADDRESS */ - uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */ + uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */ } CEC_InitTypeDef; @@ -791,4 +790,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); #endif /* STM32F4xxHAL_CEC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h index 36a5cba6a4..7c5f1152df 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h @@ -8,13 +8,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -498,4 +497,4 @@ #endif /* __STM32F4xx_HAL_CONF_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h index 028ea5e6a0..ab92803036 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -407,4 +405,3 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __STM32F4xx_HAL_CORTEX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h index bbd58a581a..41edbe381c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -180,5 +179,3 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); #endif #endif /* STM32F4xx_HAL_CRC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h index f74264af28..ff3aad1488 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -682,4 +681,3 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); #endif /* __STM32F4xx_HAL_CRYP_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h index 251e94b1da..dd12742e06 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -141,4 +140,3 @@ void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp); #endif /* __STM32F4xx_HAL_CRYP_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h index abd85449b6..a79ca73a17 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -479,4 +478,3 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); #endif /* STM32F4xx_HAL_DAC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h index 03159d4fe5..db10990297 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -204,4 +203,3 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); #endif /* STM32F4xx_HAL_DAC_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi.h index d3f61d357e..bd7e3908cb 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -563,5 +561,3 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); #endif #endif /* __STM32F4xx_HAL_DCMI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi_ex.h index c241c7b590..6b77c86dba 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dcmi_ex.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -208,5 +206,3 @@ typedef struct #endif #endif /* __STM32F4xx_HAL_DCMI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h index a5f57b0549..59720256c6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -208,4 +207,3 @@ typedef enum #endif /* ___STM32F4xx_HAL_DEF */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h index ca0a40a835..ad39ff6cb2 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dfsdm.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -59,7 +58,7 @@ typedef struct { FunctionalState Activation; /*!< Output clock enable/disable */ uint32_t Selection; /*!< Output clock is system clock or audio clock. - This parameter can be a value of @ref DFSDM_Channel_OuputClock */ + This parameter can be a value of @ref DFSDM_Channel_OutputClock */ uint32_t Divider; /*!< Output clock divider. This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ }DFSDM_Channel_OutputClockTypeDef; @@ -333,11 +332,11 @@ typedef struct * @{ */ -/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection +/** @defgroup DFSDM_Channel_OutputClock DFSDM channel output clock selection * @{ */ -#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */ -#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ +#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for output clock is system clock */ +#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for output clock is audio clock */ /** * @} */ @@ -1140,5 +1139,3 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source); #endif #endif /* __STM32F4xx_HAL_DFSDM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h index 9423ab5df6..987af2c1c3 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -801,4 +800,3 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #endif /* __STM32F4xx_HAL_DMA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h index e45d9451b1..896714137b 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma2d.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -279,15 +278,6 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointe * @} */ -/** @defgroup DMA2D_Aliases DMA2D API Aliases - * @{ - */ -#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort - for compatibility with legacy code */ -/** - * @} - */ - #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) /** * @brief HAL DMA2D common Callback ID enumeration definition @@ -646,6 +636,3 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #endif #endif /* STM32F4xx_HAL_DMA2D_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h index 7691536f47..dc8a22017b 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -101,4 +100,3 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre #endif /*__STM32F4xx_HAL_DMA_EX_H*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h index 716dea17da..6da96681c3 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dsi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -40,6 +39,9 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ +/** @defgroup DSI_Exported_Types DSI Exported Types + * @{ + */ /** * @brief DSI Init Structure definition */ @@ -61,14 +63,14 @@ typedef struct */ typedef struct { - uint32_t PLLNDIV; /*!< PLL Loop Division Factor - This parameter must be a value between 10 and 125 */ + uint32_t PLLNDIV; /*!< PLL Loop Division Factor + This parameter must be a value between 10 and 125 */ - uint32_t PLLIDF; /*!< PLL Input Division Factor - This parameter can be any value of @ref DSI_PLL_IDF */ + uint32_t PLLIDF; /*!< PLL Input Division Factor + This parameter can be any value of @ref DSI_PLL_IDF */ - uint32_t PLLODF; /*!< PLL Output Division Factor - This parameter can be any value of @ref DSI_PLL_ODF */ + uint32_t PLLODF; /*!< PLL Output Division Factor + This parameter can be any value of @ref DSI_PLL_ODF */ } DSI_PLLInitTypeDef; @@ -346,6 +348,9 @@ typedef enum typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */ #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DSI_Exported_Constants DSI Exported Constants @@ -700,8 +705,8 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE -#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ - DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ +#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ + DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ DSI_FLOW_CONTROL_EOTP_TX) /** * @} @@ -841,18 +846,18 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @{ */ #define HAL_DSI_ERROR_NONE 0U -#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ -#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ -#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ -#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ -#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ -#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ -#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ -#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ -#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ -#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ +#define HAL_DSI_ERROR_ACK 0x00000001U /*!< Acknowledge errors */ +#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ +#define HAL_DSI_ERROR_TX 0x00000004U /*!< Transmission error */ +#define HAL_DSI_ERROR_RX 0x00000008U /*!< Reception error */ +#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ +#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ +#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ +#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ +#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ +#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) -#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ +#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ /** * @} @@ -912,6 +917,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @} */ + /** * @} */ @@ -955,11 +961,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ - /* Delay after an DSI Host disabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + /* Delay after an DSI Host disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -968,11 +974,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - /* Delay after an DSI warpper enabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -981,11 +987,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - /* Delay after an DSI warpper disabling*/ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper disabling*/ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -994,11 +1000,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - /* Delay after an DSI PLL enabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -1007,11 +1013,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - /* Delay after an DSI PLL disabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -1033,11 +1039,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ - /* Delay after an DSI regulator disabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + /* Delay after an DSI regulator disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -1121,23 +1127,41 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to /** @defgroup DSI_Exported_Functions DSI Exported Functions * @{ */ +/** @defgroup DSI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); - -void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); -void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); -void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); -void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); - +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, pDSI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup DSI_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); +void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); +/** + * @} + */ +/** @defgroup DSI_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); @@ -1190,40 +1214,28 @@ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, Functional HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); -uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); -HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); -HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); /** * @} */ -/* Private types -------------------------------------------------------------*/ -/** @defgroup DSI_Private_Types DSI Private Types +/** @defgroup DSI_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * @{ */ +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); /** * @} */ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup DSI_Private_Defines DSI Private Defines - * @{ - */ - /** * @} */ +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/** @defgroup DSI_Private_Variables DSI Private Variables - * @{ - */ - -/** - * @} - */ - /* Private constants ---------------------------------------------------------*/ /** @defgroup DSI_Private_Constants DSI Private Constants * @{ @@ -1249,45 +1261,73 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); ((ODF) == DSI_PLL_OUT_DIV2) || \ ((ODF) == DSI_PLL_OUT_DIV4) || \ ((ODF) == DSI_PLL_OUT_DIV8)) -#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) -#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) +#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\ + || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) +#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE)\ + || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) -#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) -#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) -#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) -#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) +#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\ + || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) +#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\ + || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) +#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\ + || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) +#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\ + || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ ((VideoModeType) == DSI_VID_MODE_BURST)) -#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) +#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL)\ + || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) -#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) +#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE)\ + || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) -#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE)) +#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE)\ + || ((LPVActive) == DSI_LP_VACT_ENABLE)) #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) -#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) -#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) +#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\ + || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) +#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\ + || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) -#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE)) -#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE)) -#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING)) -#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) -#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) -#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) -#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) -#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) -#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) -#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) -#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) -#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE)) -#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) -#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) -#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) -#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE)) -#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) +#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE)\ + || ((TEPolarity) == DSI_TE_FALLING_EDGE)) +#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE)\ + || ((AutomaticRefresh) == DSI_AR_ENABLE)) +#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING)\ + || ((VSPolarity) == DSI_VSYNC_RISING)) +#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\ + || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\ + || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\ + || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) +#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\ + || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) +#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\ + || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) +#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\ + || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) +#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\ + || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) +#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\ + || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) +#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE)\ + || ((LP_GLW) == DSI_LP_GLW_ENABLE)) +#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\ + || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) +#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\ + || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) +#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\ + || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) +#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE)\ + || ((LP_DLW) == DSI_LP_DLW_ENABLE)) +#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\ + || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ @@ -1299,10 +1339,14 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) -#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY)) +#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || \ + ((CommDelay) == DSI_SLEW_RATE_LPTX) || \ + ((CommDelay) == DSI_HS_DELAY)) #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) -#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) -#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) +#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS)\ + || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) +#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || \ + ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ ((Timing) == DSI_TLPX_CLK ) || \ ((Timing) == DSI_THS_EXIT ) || \ @@ -1317,24 +1361,6 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); * @} */ -/* Private functions prototypes ----------------------------------------------*/ -/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes - * @{ - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DSI_Private_Functions DSI Private Functions - * @{ - */ - -/** - * @} - */ - /** * @} */ @@ -1349,5 +1375,3 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); #endif #endif /* STM32F4xx_HAL_DSI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h index 057d70216e..af84bcb421 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h @@ -6,30 +6,30 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_ETH_H -#define __STM32F4xx_HAL_ETH_H +#ifndef STM32F4xx_HAL_ETH_H +#define STM32F4xx_HAL_ETH_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" +#if defined(ETH) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ @@ -38,609 +38,557 @@ * @{ */ -/** @addtogroup ETH_Private_Macros - * @{ - */ -#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) -#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ - ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) -#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ - ((SPEED) == ETH_SPEED_100M)) -#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ - ((MODE) == ETH_MODE_HALFDUPLEX)) -#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ - ((MODE) == ETH_RXINTERRUPT_MODE)) -#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ - ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) -#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ - ((MODE) == ETH_MEDIA_INTERFACE_RMII)) -#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ - ((CMD) == ETH_WATCHDOG_DISABLE)) -#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ - ((CMD) == ETH_JABBER_DISABLE)) -#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_40BIT)) -#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ - ((CMD) == ETH_CARRIERSENCE_DISABLE)) -#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ - ((CMD) == ETH_RECEIVEOWN_DISABLE)) -#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ - ((CMD) == ETH_LOOPBACKMODE_DISABLE)) -#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ - ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) -#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ - ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) -#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ - ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) -#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_1)) -#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ - ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) -#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ - ((CMD) == ETH_RECEIVEAll_DISABLE)) -#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ - ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ - ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) -#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ - ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ - ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) -#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ - ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) -#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ - ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) -#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ - ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) -#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) -#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ - ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ - ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) -#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) -#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ - ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) -#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) -#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ - ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) -#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ - ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) -#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ - ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) -#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ - ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) -#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) -#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ - ((ADDRESS) == ETH_MAC_ADDRESS1) || \ - ((ADDRESS) == ETH_MAC_ADDRESS2) || \ - ((ADDRESS) == ETH_MAC_ADDRESS3)) -#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ - ((ADDRESS) == ETH_MAC_ADDRESS2) || \ - ((ADDRESS) == ETH_MAC_ADDRESS3)) -#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ - ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) -#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) -#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ - ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) -#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ - ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) -#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ - ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) -#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ - ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) -#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) -#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ - ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) -#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ - ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) -#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) -#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ - ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) -#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ - ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) -#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ - ((CMD) == ETH_FIXEDBURST_DISABLE)) -#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) -#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) -#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) -#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ - ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) -#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ - ((FLAG) == ETH_DMATXDESC_IC) || \ - ((FLAG) == ETH_DMATXDESC_LS) || \ - ((FLAG) == ETH_DMATXDESC_FS) || \ - ((FLAG) == ETH_DMATXDESC_DC) || \ - ((FLAG) == ETH_DMATXDESC_DP) || \ - ((FLAG) == ETH_DMATXDESC_TTSE) || \ - ((FLAG) == ETH_DMATXDESC_TER) || \ - ((FLAG) == ETH_DMATXDESC_TCH) || \ - ((FLAG) == ETH_DMATXDESC_TTSS) || \ - ((FLAG) == ETH_DMATXDESC_IHE) || \ - ((FLAG) == ETH_DMATXDESC_ES) || \ - ((FLAG) == ETH_DMATXDESC_JT) || \ - ((FLAG) == ETH_DMATXDESC_FF) || \ - ((FLAG) == ETH_DMATXDESC_PCE) || \ - ((FLAG) == ETH_DMATXDESC_LCA) || \ - ((FLAG) == ETH_DMATXDESC_NC) || \ - ((FLAG) == ETH_DMATXDESC_LCO) || \ - ((FLAG) == ETH_DMATXDESC_EC) || \ - ((FLAG) == ETH_DMATXDESC_VF) || \ - ((FLAG) == ETH_DMATXDESC_CC) || \ - ((FLAG) == ETH_DMATXDESC_ED) || \ - ((FLAG) == ETH_DMATXDESC_UF) || \ - ((FLAG) == ETH_DMATXDESC_DB)) -#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ - ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) -#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) -#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) -#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ - ((FLAG) == ETH_DMARXDESC_AFM) || \ - ((FLAG) == ETH_DMARXDESC_ES) || \ - ((FLAG) == ETH_DMARXDESC_DE) || \ - ((FLAG) == ETH_DMARXDESC_SAF) || \ - ((FLAG) == ETH_DMARXDESC_LE) || \ - ((FLAG) == ETH_DMARXDESC_OE) || \ - ((FLAG) == ETH_DMARXDESC_VLAN) || \ - ((FLAG) == ETH_DMARXDESC_FS) || \ - ((FLAG) == ETH_DMARXDESC_LS) || \ - ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ - ((FLAG) == ETH_DMARXDESC_LC) || \ - ((FLAG) == ETH_DMARXDESC_FT) || \ - ((FLAG) == ETH_DMARXDESC_RWT) || \ - ((FLAG) == ETH_DMARXDESC_RE) || \ - ((FLAG) == ETH_DMARXDESC_DBE) || \ - ((FLAG) == ETH_DMARXDESC_CE) || \ - ((FLAG) == ETH_DMARXDESC_MAMPCE)) -#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ - ((BUFFER) == ETH_DMARXDESC_BUFFER2)) -#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ - ((FLAG) == ETH_PMT_FLAG_MPR)) -#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) -#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ - ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ - ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ - ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ - ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ - ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ - ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ - ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ - ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ - ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ - ((FLAG) == ETH_DMA_FLAG_T)) -#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) -#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ - ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ - ((IT) == ETH_MAC_IT_PMT)) -#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ - ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ - ((FLAG) == ETH_MAC_FLAG_PMT)) -#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) -#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ - ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ - ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ - ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ - ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ - ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ - ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ - ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ - ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) -#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ - ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) -#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ - ((IT) != 0x00U)) -#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ - ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ - ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) -#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ - ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) - -/** - * @} - */ - -/** @addtogroup ETH_Private_Defines - * @{ - */ -/* Delay to wait when writing to some Ethernet registers */ -#define ETH_REG_WRITE_DELAY 0x00000001U - -/* ETHERNET Errors */ -#define ETH_SUCCESS 0U -#define ETH_ERROR 1U - -/* ETHERNET DMA Tx descriptors Collision Count Shift */ -#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U - -/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ -#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U - -/* ETHERNET DMA Rx descriptors Frame Length Shift */ -#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U - -/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ -#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U - -/* ETHERNET DMA Rx descriptors Frame length Shift */ -#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U - -/* ETHERNET MAC address offsets */ -#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ -#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ - -/* ETHERNET MACMIIAR register Mask */ -#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U - -/* ETHERNET MACCR register Mask */ -#define ETH_MACCR_CLEAR_MASK 0xFF20810FU - -/* ETHERNET MACFCR register Mask */ -#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U - -/* ETHERNET DMAOMR register Mask */ -#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U - -/* ETHERNET Remote Wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8U - -/* ETHERNET Missed frames counter Shift */ -#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U - /** - * @} - */ - /* Exported types ------------------------------------------------------------*/ +#ifndef ETH_TX_DESC_CNT +#define ETH_TX_DESC_CNT 4U +#endif /* ETH_TX_DESC_CNT */ + +#ifndef ETH_RX_DESC_CNT +#define ETH_RX_DESC_CNT 4U +#endif /* ETH_RX_DESC_CNT */ + + +/*********************** Descriptors struct def section ************************/ /** @defgroup ETH_Exported_Types ETH Exported Types * @{ */ /** - * @brief HAL State structures definition + * @brief ETH DMA Descriptor structure definition */ -typedef enum +typedef struct { - HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ - HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ - HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ - HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ - HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ - HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ - HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ -}HAL_ETH_StateTypeDef; + __IO uint32_t DESC0; + __IO uint32_t DESC1; + __IO uint32_t DESC2; + __IO uint32_t DESC3; + __IO uint32_t DESC4; + __IO uint32_t DESC5; + __IO uint32_t DESC6; + __IO uint32_t DESC7; + uint32_t BackupAddr0; /* used to store rx buffer 1 address */ + uint32_t BackupAddr1; /* used to store rx buffer 2 address */ +} ETH_DMADescTypeDef; +/** + * + */ /** - * @brief ETH Init Structure definition + * @brief ETH Buffers List structure definition + */ +typedef struct __ETH_BufferTypeDef +{ + uint8_t *buffer; /*State = HAL_ETH_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else -#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) +#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ + } while(0) #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ -/** - * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag of TDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ -#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) - -/** - * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag of RDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ -#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) - -/** - * @brief Enables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) - -/** - * @brief Disables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) - -/** - * @brief Set the specified DMA Rx Desc Own bit. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) - -/** - * @brief Returns the specified ETHERNET DMA Tx Desc collision count. - * @param __HANDLE__ ETH Handle - * @retval The Transmit descriptor collision counter value. - */ -#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) - -/** - * @brief Set the specified DMA Tx Desc Own bit. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) - -/** - * @brief Enables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) - -/** - * @brief Disables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) - -/** - * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. - * @param __HANDLE__ ETH Handle - * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. - * This parameter can be one of the following values: - * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass - * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) - -/** - * @brief Enables the DMA Tx Desc CRC. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) - -/** - * @brief Disables the DMA Tx Desc CRC. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) - -/** - * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) - -/** - * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) - -/** - * @brief Enables the specified ETHERNET MAC interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ -#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) - -/** - * @brief Disables the specified ETHERNET MAC interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ -#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) - -/** - * @brief Initiate a Pause Control Frame (Full-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) - -/** - * @brief Checks whether the ETHERNET flow control busy bit is set or not. - * @param __HANDLE__ ETH Handle - * @retval The new state of flow control busy status bit (SET or RESET). - */ -#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) - -/** - * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) - -/** - * @brief Disables the MAC BackPressure operation activation (Half-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) - -/** - * @brief Checks whether the specified ETHERNET MAC flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag - * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag - * @arg ETH_MAC_FLAG_MMCR : MMC receive flag - * @arg ETH_MAC_FLAG_MMC : MMC flag - * @arg ETH_MAC_FLAG_PMT : PMT flag - * @retval The state of ETHERNET MAC flag. - */ -#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) - /** * @brief Enables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be * enabled @ref ETH_DMA_Interrupts * @retval None */ -#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) +#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \ + |= (__INTERRUPT__)) /** * @brief Disables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be * disabled. @ref ETH_DMA_Interrupts * @retval None */ -#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) - -/** - * @brief Clears the ETHERNET DMA IT pending bit. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) - -/** - * @brief Checks whether the specified ETHERNET DMA flag is set or not. -* @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Checks whether the specified ETHERNET DMA flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) - -/** - * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __OVERFLOW__ specifies the DMA overflow flag to check. - * This parameter can be one of the following values: - * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter - * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter - * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). - */ -#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) - -/** - * @brief Set the DMA Receive status watchdog timer register value - * @param __HANDLE__ ETH Handle - * @param __VALUE__ DMA Receive status watchdog timer register value - * @retval None - */ -#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) - -/** - * @brief Enables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) - -/** - * @brief Disables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) - -/** - * @brief Enables the MAC Wake-Up Frame Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) - -/** - * @brief Disables the MAC Wake-Up Frame Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) - -/** - * @brief Enables the MAC Magic Packet Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) - -/** - * @brief Disables the MAC Magic Packet Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) - -/** - * @brief Enables the MAC Power Down. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) - -/** - * @brief Disables the MAC Power Down. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) - -/** - * @brief Checks whether the specified ETHERNET PMT flag is set or not. - * @param __HANDLE__ ETH Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset - * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received - * @arg ETH_PMT_FLAG_MPR : Magic Packet Received - * @retval The new state of ETHERNET PMT Flag (SET or RESET). - */ -#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) - -/** - * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ - (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) - -/** - * @brief Enables the MMC Counter Freeze. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) - -/** - * @brief Disables the MMC Counter Freeze. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) +#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \ + &= ~(__INTERRUPT__)) /** - * @brief Enables the MMC Reset On Read. - * @param __HANDLE__ ETH Handle. - * @retval None + * @brief Gets the ETHERNET DMA IT source enabled or disabled. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts + * @retval The ETH DMA IT Source enabled or disabled */ -#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) +#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMAIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) /** - * @brief Disables the MMC Reset On Read. - * @param __HANDLE__ ETH Handle. - * @retval None + * @brief Gets the ETHERNET DMA IT pending bit. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts + * @retval The state of ETH DMA IT (SET or RESET) */ -#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) +#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMASR &\ + (__INTERRUPT__)) == (__INTERRUPT__)) /** - * @brief Enables the MMC Counter Stop Rollover. - * @param __HANDLE__ ETH Handle. + * @brief Clears the ETHERNET DMA IT pending bit. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts * @retval None */ -#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) +#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR = (__INTERRUPT__)) /** - * @brief Disables the MMC Counter Stop Rollover. - * @param __HANDLE__ ETH Handle. - * @retval None + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags + * @retval The state of ETH DMA FLAG (SET or RESET). */ -#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) +#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &\ + ( __FLAG__)) == ( __FLAG__)) /** - * @brief Resets the MMC Counters. - * @param __HANDLE__ ETH Handle. - * @retval None + * @brief Clears the specified ETHERNET DMA flag. + * @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags + * @retval The state of ETH DMA FLAG (SET or RESET). */ -#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) +#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__)) /** - * @brief Enables the specified ETHERNET MMC Rx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) -/** - * @brief Disables the specified ETHERNET MMC Rx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) -/** - * @brief Enables the specified ETHERNET MMC Tx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @brief Enables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * enabled @ref ETH_MAC_Interrupts * @retval None */ -#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) +#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \ + |= (__INTERRUPT__)) /** - * @brief Disables the specified ETHERNET MMC Tx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @brief Disables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * enabled @ref ETH_MAC_Interrupts * @retval None */ -#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) +#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \ + &= ~(__INTERRUPT__)) /** - * @brief Enables the ETH External interrupt line. - * @retval None + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts + * @retval The state of ETH MAC IT (SET or RESET). */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACSR &\ + ( __INTERRUPT__)) == ( __INTERRUPT__)) -/** - * @brief Disables the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) +/*!< External interrupt line 19 Connected to the ETH wakeup EXTI Line */ +#define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00080000U) /** - * @brief Enable event on ETH External event line. + * @brief Enable the ETH WAKEUP Exti Line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. + * @arg ETH_WAKEUP_EXTI_LINE * @retval None. */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI->IMR |= (__EXTI_LINE__)) /** - * @brief Disable event on ETH External event line - * @retval None. + * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval EXTI ETH WAKEUP Line Status. */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) /** - * @brief Get flag of the ETH External interrupt line. - * @retval None + * @brief Clear the ETH WAKEUP Exti flag. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. */ -#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) -/** - * @brief Clear flag of the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) /** - * @brief Enables rising edge trigger to the ETH External interrupt line. + * @brief enable rising edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR &= ~(__EXTI_LINE__)); \ + (EXTI->RTSR |= (__EXTI_LINE__)) /** - * @brief Disables the rising edge trigger to the ETH External interrupt line. + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR &= ~(__EXTI_LINE__));\ + (EXTI->FTSR |= (__EXTI_LINE__)) /** - * @brief Enables falling edge trigger to the ETH External interrupt line. + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR |= (__EXTI_LINE__));\ + (EXTI->FTSR |= (__EXTI_LINE__)) /** - * @brief Disables falling edge trigger to the ETH External interrupt line. + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) -/** - * @brief Enables rising/falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ - EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ - }while(0U) +#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->PTPTSCR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->PTPTSCR |= (__FLAG__)) /** - * @brief Disables rising/falling edge trigger to the ETH External interrupt line. - * @retval None + * @} */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - }while(0U) -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP -/** - * @} - */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup ETH_Exported_Functions * @{ */ -/* Initialization and de-initialization functions ****************************/ - /** @addtogroup ETH_Exported_Functions_Group1 * @{ */ +/* Initialization and de initialization functions **********************************/ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); -HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); + /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, + pETH_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ /** * @} */ -/* IO operation functions ****************************************************/ /** @addtogroup ETH_Exported_Functions_Group2 * @{ */ -HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); -/* Communication with PHY functions*/ -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); -void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); -/* Callback in non blocking modes (Interrupt) */ -void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff); +HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, + pETH_rxAllocateCallbackTypeDef rxAllocateCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode); +HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth); + +#ifdef HAL_ETH_USE_PTP +HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); +HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); +HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); +HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); +HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, + ETH_TimeTypeDef *timeoffset); +HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth); +#endif /* HAL_ETH_USE_PTP */ + +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout); +HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig); + +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t RegValue); +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t *pRegValue); + +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); +void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxAllocateCallback(uint8_t **buff); +void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length); +void HAL_ETH_TxFreeCallback(uint32_t *buff); +void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp); /** * @} */ -/* Peripheral Control functions **********************************************/ - /** @addtogroup ETH_Exported_Functions_Group3 * @{ */ +/* Peripheral Control functions **********************************************/ +/* MAC & DMA Configuration APIs **********************************************/ +HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); + +/* MAC VLAN Processing APIs ************************************************/ +void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, + uint32_t VLANIdentifier); + +/* MAC L2 Packet Filtering APIs **********************************************/ +HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); +HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr); + +/* MAC Power Down APIs *****************************************************/ +void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig); +void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); -HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); -HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); /** * @} */ -/* Peripheral State functions ************************************************/ - /** @addtogroup ETH_Exported_Functions_Group4 * @{ */ +/* Peripheral State functions **************************************************/ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); /** * @} */ @@ -2200,14 +2136,12 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ - STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#endif /* ETH */ #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_ETH_H */ +#endif /* STM32F4xx_HAL_ETH_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h index 857011236b..b18a2287a1 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS.Clause * ****************************************************************************** */ @@ -365,4 +364,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); #endif /* STM32f4xx_HAL_EXTI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h index d40fb9880d..c2d0bf4930 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -425,4 +423,3 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #endif /* __STM32F4xx_HAL_FLASH_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h index 4df2675746..63dcc9a2dd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -1063,4 +1061,3 @@ void FLASH_FlushCaches(void); #endif /* __STM32F4xx_HAL_FLASH_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h index ecb522c707..014b109670 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -76,4 +74,3 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void); #endif /* __STM32F4xx_FLASH_RAMFUNC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h index b7f370a8f4..400b923ebb 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -277,7 +276,7 @@ typedef enum typedef void (*pFMPI2C_CallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c); /*!< pointer to an FMPI2C callback function */ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, - uint16_t AddrMatchCode); + uint16_t AddrMatchCode); /*!< pointer to an FMPI2C Address Match callback function */ #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ @@ -621,13 +620,13 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout); + uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout); + uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout); + uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout); + uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, @@ -783,9 +782,9 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); FMPI2C_CR2_RD_WRN))) #define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) \ - >> 16U)) + >> 16U)) #define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) \ - >> 16U)) + >> 16U)) #define FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) #define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)) #define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)) @@ -836,5 +835,3 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); #endif /* STM32F4xx_HAL_FMPI2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h index 6a5df0b1a1..8b90f40752 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -149,5 +148,3 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #endif #endif /* STM32F4xx_HAL_FMPI2C_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h index 9d5e0307ed..6d1ff4b19c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -373,9 +372,9 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus #define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE #define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE #define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | \ - FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) #define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | \ - FMPSMBUS_IT_RXI) + FMPSMBUS_IT_RXI) #define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI) #define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI) /** @@ -623,11 +622,11 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus #define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \ - FMPI2C_CR1_PECEN))) + FMPI2C_CR1_PECEN))) #define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ - FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ - FMPI2C_CR2_RD_WRN))) + FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ + FMPI2C_CR2_RD_WRN))) #define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? \ (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ @@ -677,13 +676,13 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, - pFMPSMBUS_CallbackTypeDef pCallback); + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, + pFMPSMBUS_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - pFMPSMBUS_AddrCallbackTypeDef pCallback); + pFMPSMBUS_AddrCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ /** @@ -710,9 +709,9 @@ HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, */ /******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, - uint8_t *pData, uint16_t Size, uint32_t XferOptions); + uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, - uint8_t *pData, uint16_t Size, uint32_t XferOptions); + uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress); HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); @@ -789,5 +788,3 @@ uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus); #endif /* STM32F4xx_HAL_FMPSMBUS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h index d5439e7ce8..001dc54733 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -105,9 +104,9 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @{ */ #define IS_FMPSMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SCL)) == \ - FMPSMBUS_FASTMODEPLUS_SCL) || \ + FMPSMBUS_FASTMODEPLUS_SCL) || \ (((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == \ - FMPSMBUS_FASTMODEPLUS_SDA)) + FMPSMBUS_FASTMODEPLUS_SDA)) /** * @} */ @@ -135,5 +134,3 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #endif #endif /* STM32F4xx_HAL_FMPSMBUS_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h index fec558979f..412319f91b 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -324,4 +323,3 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); #endif /* __STM32F4xx_HAL_GPIO_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h index 8997e86c8a..716c839d18 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1589,4 +1588,3 @@ #endif /* __STM32F4xx_HAL_GPIO_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h index 3b73282edf..9a93fbbc06 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -633,4 +632,3 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, #endif /* STM32F4xx_HAL_HASH_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash_ex.h index 0a9844c0ae..91e65dca2a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -174,4 +173,3 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 #endif /* STM32F4xx_HAL_HASH_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h index 6025e032c2..9cd148626c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -315,5 +314,3 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); #endif #endif /* STM32F4xx_HAL_HCD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h index 9a622b82b3..9a7a67efb9 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -740,4 +739,3 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #endif /* __STM32F4xx_HAL_I2C_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h index 6864d83519..31ad99c3a2 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -114,4 +113,3 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ #endif /* __STM32F4xx_HAL_I2C_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h index 1e9676f868..66cee01b26 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -617,4 +616,3 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); #endif /* STM32F4xx_HAL_I2S_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h index 10335f49f4..3aaa45b76e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -182,4 +181,3 @@ void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s); #endif /* STM32F4xx_HAL_I2S_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h index 4d83abc22d..0d1c5f15a3 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_irda.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -145,7 +144,7 @@ typedef struct IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ @@ -560,11 +559,11 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD * @{ */ /* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); @@ -681,4 +680,3 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); #endif /* __STM32F4xx_HAL_IRDA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h index 32f5ff027a..5273730c14 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -219,5 +218,3 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); #endif #endif /* STM32F4xx_HAL_IWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h index 80ea203720..7a41ee9da0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -819,11 +818,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL) +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ + ((__AUTORELOAD__) <= 0x0000FFFFUL)) #define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) -#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL) +#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ + ((__PERIOD__) <= 0x0000FFFFUL)) #define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) @@ -854,5 +855,3 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim); #endif #endif /* STM32F4xx_HAL_LPTIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h index 0cab8446ef..ab951d3ea7 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -80,28 +79,36 @@ typedef struct This parameter can be one of value of @ref LTDC_PC_POLARITY */ uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. - This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height. - This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. - This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ uint32_t AccumulatedActiveH; /*!< configures the accumulated active height. - This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ uint32_t TotalWidth; /*!< configures the total width. - This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ uint32_t TotalHeigh; /*!< configures the total height. - This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ } LTDC_InitTypeDef; @@ -112,25 +119,31 @@ typedef struct typedef struct { uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t WindowY0; /*!< Configures the Window vertical Start Position. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x7FF. */ uint32_t PixelFormat; /*!< Specifies the pixel format. This parameter can be one of value of @ref LTDC_Pixelformat */ uint32_t Alpha; /*!< Specifies the constant alpha used for blending. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF. */ uint32_t Alpha0; /*!< Configures the default alpha value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF. */ uint32_t BlendingFactor1; /*!< Select the blending factor 1. This parameter can be one of value of @ref LTDC_BlendingFactor1 */ @@ -141,10 +154,12 @@ typedef struct uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ uint32_t ImageWidth; /*!< Configures the color frame buffer line length. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x1FFF. */ uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ } LTDC_LayerCfgTypeDef; @@ -400,7 +415,7 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer * @retval None */ #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) -#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->State = HAL_LTDC_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ @@ -430,7 +445,8 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). * @retval None. */ -#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN) +#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ + |= (uint32_t)LTDC_LxCR_LEN) /** * @brief Disable the LTDC Layer. @@ -439,7 +455,8 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). * @retval None. */ -#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN) +#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ + &= ~(uint32_t)LTDC_LxCR_LEN) /** * @brief Reload immediately all LTDC Layers. @@ -545,7 +562,8 @@ void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, + pLTDC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ @@ -583,9 +601,12 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType); -HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, + uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); @@ -621,12 +642,18 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); /** @defgroup LTDC_Private_Macros LTDC Private Macros * @{ */ -#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__))))) +#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(\ + ((uint32_t)((__HANDLE__)->Instance))\ + + 0x84U + (0x80U*(__LAYER__))))) #define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) -#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) -#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) -#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) -#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) +#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL)\ + || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) +#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL)\ + || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) +#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL)\ + || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) +#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\ + || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) #define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC) #define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC) #define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC) @@ -642,10 +669,14 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA)) #define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \ ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA)) -#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) +#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) #define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA) #define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION) #define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION) @@ -655,7 +686,8 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); #define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER) #define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER) #define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU) -#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) +#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \ + ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) /** * @} */ @@ -685,4 +717,3 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); #endif /* STM32F4xx_HAL_LTDC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h index 37a5fdf47a..b9c39e49ae 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_ltdc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -82,5 +81,3 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD #endif #endif /* STM32F4xx_HAL_LTDC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h index 03b928b38b..5355001be6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_mmc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -145,6 +144,8 @@ typedef struct uint32_t CID[4U]; /*!< MMC card identification number table */ + uint32_t Ext_CSD[128]; + #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); @@ -334,10 +335,12 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); /** * @brief */ -#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */ -#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */ -#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */ -#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */ +#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */ +#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */ +#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */ +#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */ +#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */ +#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */ #define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U /** * @} @@ -636,6 +639,7 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); /** * @} */ @@ -649,7 +653,7 @@ uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); * @} */ -/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management +/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management * @{ */ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc); @@ -741,5 +745,3 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); #endif /* SDIO */ #endif /* STM32F4xx_HAL_MMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h index 7395751c70..26f650256f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h @@ -6,35 +6,32 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_NAND_H -#define __STM32F4xx_HAL_NAND_H +#ifndef STM32F4xx_HAL_NAND_H +#define STM32F4xx_HAL_NAND_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -/* Includes ------------------------------------------------------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) - #include "stm32f4xx_ll_fsmc.h" -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - #include "stm32f4xx_ll_fmc.h" -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ - STM32F479xx */ +/* Includes ------------------------------------------------------------------*/ +#if defined(FSMC_Bank2_3) +#include "stm32f4xx_ll_fsmc.h" +#else +#include "stm32f4xx_ll_fmc.h" +#endif /* FSMC_Bank2_3 */ /** @addtogroup STM32F4xx_HAL_Driver * @{ @@ -44,10 +41,6 @@ * @{ */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - /* Exported typedef ----------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /** @defgroup NAND_Exported_Types NAND Exported Types @@ -63,7 +56,7 @@ typedef enum HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ -}HAL_NAND_StateTypeDef; +} HAL_NAND_StateTypeDef; /** * @brief NAND Memory electronic signature Structure definition @@ -79,20 +72,20 @@ typedef struct uint8_t Third_Id; uint8_t Fourth_Id; -}NAND_IDTypeDef; +} NAND_IDTypeDef; /** * @brief NAND Memory address Structure definition */ typedef struct { - uint16_t Page; /*!< NAND memory Page address */ + uint16_t Page; /*!< NAND memory Page address */ - uint16_t Plane; /*!< NAND memory Plane address */ + uint16_t Plane; /*!< NAND memory Zone address */ - uint16_t Block; /*!< NAND memory Block address */ + uint16_t Block; /*!< NAND memory Block address */ -}NAND_AddressTypeDef; +} NAND_AddressTypeDef; /** * @brief NAND Memory info Structure definition @@ -100,10 +93,10 @@ typedef struct typedef struct { uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes - for 8 bits adressing or words for 16 bits addressing */ + for 8 bits addressing or words for 16 bits addressing */ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes - for 8 bits adressing or words for 16 bits addressing */ + for 8 bits addressing or words for 16 bits addressing */ uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ @@ -111,7 +104,7 @@ typedef struct uint32_t PlaneNbr; /*!< NAND memory number of planes */ - uint32_t PlaneSize; /*!< NAND memory plane size measured in number of blocks */ + uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This parameter is mandatory for some NAND parts after the read @@ -119,7 +112,7 @@ typedef struct Example: Toshiba THTH58BYG3S0HBAI6. This parameter could be ENABLE or DISABLE Please check the Read Mode sequnece in the NAND device datasheet */ -}NAND_DeviceConfigTypeDef; +} NAND_DeviceConfigTypeDef; /** * @brief NAND handle Structure definition @@ -141,10 +134,10 @@ typedef struct NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */ - void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */ - void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */ -#endif + void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ + void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ + void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ } NAND_HandleTypeDef; #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) @@ -156,23 +149,23 @@ typedef enum HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ -}HAL_NAND_CallbackIDTypeDef; +} HAL_NAND_CallbackIDTypeDef; /** * @brief HAL NAND Callback pointer definition */ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} */ /* Exported constants --------------------------------------------------------*/ -/* Exported macros ------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ /** @defgroup NAND_Exported_Macros NAND Exported Macros - * @{ - */ + * @{ + */ /** @brief Reset NAND handle state * @param __HANDLE__ specifies the NAND handle. @@ -186,7 +179,7 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); } while(0) #else #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} @@ -202,8 +195,8 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); */ /* Initialization/de-initialization functions ********************************/ -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, + FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); @@ -226,26 +219,34 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); /* IO operation functions ****************************************************/ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); - -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /* NAND callback registering/unregistering */ -HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, + pNAND_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} @@ -269,6 +270,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, */ /* NAND State functions *******************************************************/ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); +uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); /** * @} */ @@ -283,12 +285,16 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); /** @defgroup NAND_Private_Constants NAND Private Constants * @{ */ -#define NAND_DEVICE1 0x70000000U -#define NAND_DEVICE2 0x80000000U -#define NAND_WRITE_TIMEOUT 0x01000000U +#if defined(FMC_Bank2_3) +#define NAND_DEVICE1 0x70000000UL +#define NAND_DEVICE2 0x80000000UL +#else +#define NAND_DEVICE 0x80000000UL +#endif +#define NAND_WRITE_TIMEOUT 0x01000000UL -#define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */ -#define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */ +#define CMD_AREA (1UL<<16U) /* A16 = CLE high */ +#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ #define NAND_CMD_AREA_A ((uint8_t)0x00) #define NAND_CMD_AREA_B ((uint8_t)0x01) @@ -305,12 +311,12 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); #define NAND_CMD_RESET ((uint8_t)0xFF) /* NAND memory status */ -#define NAND_VALID_ADDRESS 0x00000100U -#define NAND_INVALID_ADDRESS 0x00000200U -#define NAND_TIMEOUT_ERROR 0x00000400U -#define NAND_BUSY 0x00000000U -#define NAND_ERROR 0x00000001U -#define NAND_READY 0x00000040U +#define NAND_VALID_ADDRESS 0x00000100UL +#define NAND_INVALID_ADDRESS 0x00000200UL +#define NAND_TIMEOUT_ERROR 0x00000400UL +#define NAND_BUSY 0x00000000UL +#define NAND_ERROR 0x00000001UL +#define NAND_READY 0x00000040UL /** * @} */ @@ -323,11 +329,14 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); /** * @brief NAND memory address computation. * @param __ADDRESS__ NAND memory address. - * @param __HANDLE__ NAND handle. + * @param __HANDLE__ NAND handle. * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ - (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) + (((__ADDRESS__)->Block + \ + (((__ADDRESS__)->Plane) * \ + ((__HANDLE__)->Config.PlaneSize))) * \ + ((__HANDLE__)->Config.BlockSize))) /** * @brief NAND memory Column address computation. @@ -351,19 +360,17 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); * @param __ADDRESS__ NAND memory address. * @retval NAND Column address cycling value. */ -#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */ +#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ - STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ - STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ + /** * @} */ @@ -372,10 +379,10 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); * @} */ +#endif /* FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3 */ + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_NAND_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_NAND_H */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nor.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nor.h index f668085b36..cc7f1b5e50 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nor.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nor.h @@ -6,35 +6,32 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_NOR_H -#define __STM32F4xx_HAL_NOR_H +#ifndef STM32F4xx_HAL_NOR_H +#define STM32F4xx_HAL_NOR_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -/* Includes ------------------------------------------------------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) - #include "stm32f4xx_ll_fsmc.h" -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#if defined(FMC_Bank1) || defined(FSMC_Bank1) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - #include "stm32f4xx_ll_fmc.h" -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/* Includes ------------------------------------------------------------------*/ +#if defined(FSMC_Bank1) +#include "stm32f4xx_ll_fsmc.h" +#else +#include "stm32f4xx_ll_fmc.h" +#endif /* FMC_Bank1 */ /** @addtogroup STM32F4xx_HAL_Driver * @{ @@ -44,11 +41,6 @@ * @{ */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) - /* Exported typedef ----------------------------------------------------------*/ /** @defgroup NOR_Exported_Types NOR Exported Types * @{ @@ -64,7 +56,7 @@ typedef enum HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */ -}HAL_NOR_StateTypeDef; +} HAL_NOR_StateTypeDef; /** * @brief FMC NOR Status typedef @@ -75,7 +67,7 @@ typedef enum HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT -}HAL_NOR_StatusTypeDef; +} HAL_NOR_StatusTypeDef; /** * @brief FMC NOR ID typedef @@ -92,7 +84,7 @@ typedef struct These codes can be accessed by performing read operations with specific control signals and addresses set.They can also be accessed by issuing an Auto Select command */ -}NOR_IDTypeDef; +} NOR_IDTypeDef; /** * @brief FMC NOR CFI typedef @@ -110,7 +102,7 @@ typedef struct uint16_t CFI_3; uint16_t CFI_4; -}NOR_CFITypeDef; +} NOR_CFITypeDef; /** * @brief NOR handle Structure definition @@ -132,10 +124,12 @@ typedef struct __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ + uint32_t CommandSet; /*!< NOR algorithm command set and control */ + #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */ - void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */ -#endif + void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */ + void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */ +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ } NOR_HandleTypeDef; #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) @@ -146,19 +140,19 @@ typedef enum { HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */ HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */ -}HAL_NOR_CallbackIDTypeDef; +} HAL_NOR_CallbackIDTypeDef; /** * @brief HAL NOR Callback pointer definition */ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ /* Exported constants --------------------------------------------------------*/ -/* Exported macros ------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ /** @defgroup NOR_Exported_Macros NOR Exported Macros * @{ */ @@ -174,21 +168,23 @@ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); } while(0) #else #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup NOR_Exported_Functions - * @{ - */ +/** @addtogroup NOR_Exported_Functions NOR Exported Functions + * @{ + */ + +/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ -/** @addtogroup NOR_Exported_Functions_Group1 - * @{ - */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming); HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); @@ -197,17 +193,20 @@ void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); * @} */ -/** @addtogroup NOR_Exported_Functions_Group2 - * @{ - */ +/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions + * @{ + */ + /* I/O operation functions ***************************************************/ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); @@ -215,16 +214,18 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) /* NOR callback registering/unregistering */ -HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, + pNOR_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ -/** @addtogroup NOR_Exported_Functions_Group3 - * @{ - */ +/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions + * @{ + */ + /* NOR Control functions *****************************************************/ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); @@ -232,9 +233,10 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); * @} */ -/** @addtogroup NOR_Exported_Functions_Group4 - * @{ - */ +/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions + * @{ + */ + /* NOR State functions ********************************************************/ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); @@ -272,10 +274,10 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres #define NOR_MEMORY_16B ((uint8_t)0x01) /* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 0x60000000U -#define NOR_MEMORY_ADRESS2 0x64000000U -#define NOR_MEMORY_ADRESS3 0x68000000U -#define NOR_MEMORY_ADRESS4 0x6C000000U +#define NOR_MEMORY_ADRESS1 (0x60000000U) +#define NOR_MEMORY_ADRESS2 (0x64000000U) +#define NOR_MEMORY_ADRESS3 (0x68000000U) +#define NOR_MEMORY_ADRESS4 (0x6C000000U) /** * @} */ @@ -286,29 +288,31 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres */ /** * @brief NOR memory address shifting. - * @param __NOR_ADDRESS__ NOR base address - * @param NOR_MEMORY_WIDTH NOR memory width - * @param ADDRESS NOR memory address + * @param __NOR_ADDRESS NOR base address + * @param __NOR_MEMORY_WIDTH_ NOR memory width + * @param __ADDRESS__ NOR memory address * @retval NOR shifted address value */ -#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_16B)? ((uint32_t)((__NOR_ADDRESS__) + (2U * (ADDRESS)))):\ - ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS)))) +#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ + ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ + ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ + ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) /** * @brief NOR memory write data to specified address. - * @param ADDRESS NOR memory address - * @param DATA Data to write + * @param __ADDRESS__ NOR memory address + * @param __DATA__ Data to write * @retval None */ -#define NOR_WRITE(ADDRESS, DATA) (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA)) +#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \ + (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \ + __DSB(); \ + } while(0) /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ - STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ - STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ + /** * @} */ @@ -317,10 +321,10 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @} */ +#endif /* FMC_Bank1 || FSMC_Bank1 */ + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_NOR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_NOR_H */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pccard.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pccard.h index fa47bc25f9..47fbb262ff 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pccard.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pccard.h @@ -6,41 +6,37 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_PCCARD_H -#define __STM32F4xx_HAL_PCCARD_H +#ifndef STM32F4xx_HAL_PCCARD_H +#define STM32F4xx_HAL_PCCARD_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -/* Includes ------------------------------------------------------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) - #include "stm32f4xx_ll_fsmc.h" -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#if defined(FMC_Bank4) || defined(FSMC_Bank4) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - #include "stm32f4xx_ll_fmc.h" -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +/* Includes ------------------------------------------------------------------*/ +#if defined(FSMC_Bank4) +#include "stm32f4xx_ll_fsmc.h" +#else +#include "stm32f4xx_ll_fmc.h" +#endif /* FSMC_Bank4 */ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - /** @addtogroup PCCARD * @{ */ @@ -59,7 +55,7 @@ typedef enum HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */ HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */ HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */ -}HAL_PCCARD_StateTypeDef; +} HAL_PCCARD_StateTypeDef; typedef enum { @@ -67,7 +63,7 @@ typedef enum HAL_PCCARD_STATUS_ONGOING, HAL_PCCARD_STATUS_ERROR, HAL_PCCARD_STATUS_TIMEOUT -}HAL_PCCARD_StatusTypeDef; +} HAL_PCCARD_StatusTypeDef; /** * @brief FMC_PCCARD handle Structure definition @@ -87,9 +83,9 @@ typedef struct HAL_LockTypeDef Lock; /*!< PCCARD Lock */ #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp Init callback */ - void (* MspDeInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp DeInit callback */ - void (* ItCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD IT callback */ + void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */ + void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */ + void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */ #endif } PCCARD_HandleTypeDef; @@ -102,7 +98,7 @@ typedef enum HAL_PCCARD_MSP_INIT_CB_ID = 0x00U, /*!< PCCARD MspInit Callback ID */ HAL_PCCARD_MSP_DEINIT_CB_ID = 0x01U, /*!< PCCARD MspDeInit Callback ID */ HAL_PCCARD_IT_CB_ID = 0x02U /*!< PCCARD IT Callback ID */ -}HAL_PCCARD_CallbackIDTypeDef; +} HAL_PCCARD_CallbackIDTypeDef; /** * @brief HAL PCCARD Callback pointer definition @@ -144,7 +140,8 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard); * @{ */ /* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming); +HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, + FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming); HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard); @@ -157,8 +154,10 @@ void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard); */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus); -HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus); -HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus); +HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus); +HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus); HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus); HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard); @@ -166,8 +165,10 @@ void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard); #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) /* PCCARD callback registering/unregistering */ -HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId); +HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, + pPCCARD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, + HAL_PCCARD_CallbackIDTypeDef CallbackId); #endif /** * @} @@ -270,18 +271,15 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard); * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ - STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - /** * @} */ +#endif /* FMC_Bank4 || FSMC_Bank4 */ + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_PCCARD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_PCCARD_H */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h index e28285d475..92488b2fe7 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -107,6 +106,7 @@ typedef struct uint32_t Setup[12]; /*!< Setup packet buffer */ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; + uint32_t FrameNumber; /*!< Store Current Frame number */ uint32_t lpm_active; /*!< Enable or disable the Link Power Management . @@ -290,12 +290,10 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType * @} */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, - HAL_PCD_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, - HAL_PCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); @@ -317,14 +315,10 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, - pPCD_BcdCallbackTypeDef pCallback); - +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, - pPCD_LpmCallbackTypeDef pCallback); - +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /** @@ -364,22 +358,17 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint16_t ep_mps, uint8_t ep_type); - +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint8_t *pBuf, uint32_t len); - -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint8_t *pBuf, uint32_t len); - - +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode); uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); /** @@ -468,5 +457,3 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #endif #endif /* STM32F4xx_HAL_PCD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h index 71e9a2c18b..72ded2b6ca 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -23,7 +22,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -83,9 +82,7 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /* STM32F4xx_HAL_PCD_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h index 1a4b27bab5..3b9ad5a390 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -427,5 +425,3 @@ void HAL_PWR_DisableSEVOnPend(void); #endif /* __STM32F4xx_HAL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h index e461bff84c..68d49b50aa 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -340,5 +338,3 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t #endif /* __STM32F4xx_HAL_PWR_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h index 97e9324f34..56287af6ce 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -457,7 +456,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); * @{ */ /** @brief Reset QSPI handle state. - * @param __HANDLE__ : QSPI handle. + * @param __HANDLE__ QSPI handle. * @retval None */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) @@ -471,20 +470,20 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #endif /** @brief Enable the QSPI peripheral. - * @param __HANDLE__ : specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable the QSPI peripheral. - * @param __HANDLE__ : specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enable the specified QSPI interrupt. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -497,8 +496,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @brief Disable the specified QSPI interrupt. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -510,8 +509,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Check whether the specified QSPI interrupt source is enabled or not. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -524,8 +523,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** * @brief Check whether the selected QSPI flag is set or not. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __FLAG__ : specifies the QSPI flag to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Timeout flag @@ -538,8 +537,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag @@ -742,12 +741,10 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3 * @} */ -#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ +#endif /* defined(QUADSPI) */ #ifdef __cplusplus } #endif #endif /* STM32F4xx_HAL_QSPI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h index 2eeff3482e..dcf5814451 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -1459,4 +1457,3 @@ void HAL_RCC_CSSCallback(void); #endif /* __STM32F4xx_HAL_RCC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h index eac10feb63..dbcc98cd29 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -7111,4 +7109,3 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); #endif /* __STM32F4xx_HAL_RCC_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h index cde48592e3..7d4dca1ebd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -360,4 +359,3 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); #endif /* STM32F4xx_HAL_RNG_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h index 9afa8a1407..24affc5428 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h @@ -6,26 +6,26 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_RTC_H -#define __STM32F4xx_HAL_RTC_H +#ifndef STM32F4xx_HAL_RTC_H +#define STM32F4xx_HAL_RTC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ + #include "stm32f4xx_hal_def.h" /** @addtogroup STM32F4xx_HAL_Driver @@ -37,6 +37,7 @@ */ /* Exported types ------------------------------------------------------------*/ + /** @defgroup RTC_Exported_Types RTC Exported Types * @{ */ @@ -51,7 +52,7 @@ typedef enum HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ -}HAL_RTCStateTypeDef; +} HAL_RTCStateTypeDef; /** * @brief RTC Configuration Structure definition @@ -65,7 +66,7 @@ typedef struct This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFFU */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FFF */ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. This parameter can be a value of @ref RTC_Output_selection_Definitions */ @@ -75,7 +76,7 @@ typedef struct uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ -}RTC_InitTypeDef; +} RTC_InitTypeDef; /** * @brief RTC Time structure definition @@ -83,8 +84,8 @@ typedef struct typedef struct { uint8_t Hours; /*!< Specifies the RTC Time Hour. - This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. - This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ + This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected + This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ uint8_t Minutes; /*!< Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ @@ -95,22 +96,22 @@ typedef struct uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ - uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. + uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity */ uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content - corresponding to Synchronous pre-scaler factor value (PREDIV_S) + corresponding to Synchronous prescaler factor value (PREDIV_S) This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function */ - uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time, - please use HAL_RTC_DST_xxx functions */ + uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight + Saving Time, please use HAL_RTC_DST_xxx functions */ - uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time, - please use HAL_RTC_DST_xxx functions */ -}RTC_TimeTypeDef; + uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight + Saving Time, please use HAL_RTC_DST_xxx functions */ +} RTC_TimeTypeDef; /** * @brief RTC Date structure definition @@ -129,7 +130,7 @@ typedef struct uint8_t Year; /*!< Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ -}RTC_DateTypeDef; +} RTC_DateTypeDef; /** * @brief RTC Alarm structure definition @@ -145,7 +146,7 @@ typedef struct This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. @@ -153,7 +154,7 @@ typedef struct uint32_t Alarm; /*!< Specifies the alarm . This parameter can be a value of @ref RTC_Alarms_Definitions */ -}RTC_AlarmTypeDef; +} RTC_AlarmTypeDef; /** * @brief RTC Handle Structure definition @@ -162,7 +163,7 @@ typedef struct typedef struct __RTC_HandleTypeDef #else typedef struct -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ { RTC_TypeDef *Instance; /*!< Register base address */ @@ -173,25 +174,27 @@ typedef struct __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */ + void (* AlarmAEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ - void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */ + void (* AlarmBEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ - void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */ + void (* TimeStampEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Timestamp Event callback */ - void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */ + void (* WakeUpTimerEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ - void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */ + void (* Tamper1EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ - void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */ +#if defined(RTC_TAMPER2_SUPPORT) + void (* Tamper2EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ +#endif /* RTC_TAMPER2_SUPPORT */ - void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */ + void (* MspInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ - void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */ + void (* MspDeInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ -}RTC_HandleTypeDef; +} RTC_HandleTypeDef; #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) /** @@ -199,20 +202,22 @@ typedef struct */ typedef enum { - HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */ - HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01u, /*!< RTC Alarm B Event Callback ID */ - HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02u, /*!< RTC TimeStamp Event Callback ID */ - HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03u, /*!< RTC Wake-Up Timer Event Callback ID */ - HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */ - HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05u, /*!< RTC Tamper 2 Callback ID */ - HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */ - HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */ -}HAL_RTC_CallbackIDTypeDef; + HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */ + HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */ + HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC Timestamp Event Callback ID */ + HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC Wakeup Timer Event Callback ID */ + HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */ +#if defined(RTC_TAMPER2_SUPPORT) + HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */ +#endif /* RTC_TAMPER2_SUPPORT */ + HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */ + HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */ +} HAL_RTC_CallbackIDTypeDef; /** * @brief HAL RTC Callback pointer definition */ -typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */ +typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */ #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ /** @@ -220,6 +225,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup RTC_Exported_Constants RTC Exported Constants * @{ */ @@ -228,7 +234,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_HOURFORMAT_24 0x00000000U -#define RTC_HOURFORMAT_12 0x00000040U +#define RTC_HOURFORMAT_12 RTC_CR_FMT /** * @} */ @@ -237,9 +243,9 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_OUTPUT_DISABLE 0x00000000U -#define RTC_OUTPUT_ALARMA 0x00200000U -#define RTC_OUTPUT_ALARMB 0x00400000U -#define RTC_OUTPUT_WAKEUP 0x00600000U +#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 +#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 +#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL /** * @} */ @@ -248,7 +254,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_OUTPUT_POLARITY_HIGH 0x00000000U -#define RTC_OUTPUT_POLARITY_LOW 0x00100000U +#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL /** * @} */ @@ -257,7 +263,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U -#define RTC_OUTPUT_TYPE_PUSHPULL 0x00040000U +#define RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE /** * @} */ @@ -266,7 +272,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_HOURFORMAT12_AM ((uint8_t)0x00) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) +#define RTC_HOURFORMAT12_PM ((uint8_t)0x01) /** * @} */ @@ -274,8 +280,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions * @{ */ -#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U -#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U +#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H +#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H #define RTC_DAYLIGHTSAVING_NONE 0x00000000U /** * @} @@ -285,7 +291,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_STOREOPERATION_RESET 0x00000000U -#define RTC_STOREOPERATION_SET 0x00040000U +#define RTC_STOREOPERATION_SET RTC_CR_BKP /** * @} */ @@ -293,16 +299,15 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions * @{ */ -#define RTC_FORMAT_BIN 0x00000000U -#define RTC_FORMAT_BCD 0x00000001U +#define RTC_FORMAT_BIN 0x00000000U +#define RTC_FORMAT_BCD 0x00000001U /** * @} */ -/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions +/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format) * @{ */ -/* Coded in BCD format */ #define RTC_MONTH_JANUARY ((uint8_t)0x01) #define RTC_MONTH_FEBRUARY ((uint8_t)0x02) #define RTC_MONTH_MARCH ((uint8_t)0x03) @@ -337,7 +342,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /** * @} */ @@ -350,7 +355,10 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to #define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 #define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 #define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL 0x80808080U +#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | \ + RTC_ALARMMASK_HOURS | \ + RTC_ALARMMASK_MINUTES | \ + RTC_ALARMMASK_SECONDS) /** * @} */ @@ -367,39 +375,38 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 0x01000000U /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 0x02000000U /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 0x03000000U /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 0x04000000U /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 0x05000000U /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 0x06000000U /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 0x07000000U /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 0x08000000U /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 0x09000000U /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 0x0A000000U /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 0x0B000000U /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 0x0C000000U /*!< SS[14:12] are don't care in Alarm - comparison.Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 0x0D000000U /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 0x0E000000U /*!< SS[14] is don't care in Alarm - comparison.Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_NONE 0x0F000000U /*!< SS[14:0] are compared and must match - to activate alarm. */ +/*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ +#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U +/*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 +/*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 +/*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) +/*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 +/*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) +/*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) +/*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) +/*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 +/*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) +/*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) +/*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) +/*!< SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) +/*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) +/*!< SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) +/*!< SS[14:0] are compared and must match to activate alarm. */ +#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /** * @} */ @@ -407,13 +414,10 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions * @{ */ -#define RTC_IT_TS 0x00008000U -#define RTC_IT_WUT 0x00004000U -#define RTC_IT_ALRB 0x00002000U -#define RTC_IT_ALRA 0x00001000U -#define RTC_IT_TAMP 0x00000004U /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 0x00020000U -#define RTC_IT_TAMP2 0x00040000U +#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */ +#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */ +#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */ +#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */ /** * @} */ @@ -421,21 +425,23 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Flags_Definitions RTC Flags Definitions * @{ */ -#define RTC_FLAG_RECALPF 0x00010000U -#define RTC_FLAG_TAMP2F 0x00004000U -#define RTC_FLAG_TAMP1F 0x00002000U -#define RTC_FLAG_TSOVF 0x00001000U -#define RTC_FLAG_TSF 0x00000800U -#define RTC_FLAG_WUTF 0x00000400U -#define RTC_FLAG_ALRBF 0x00000200U -#define RTC_FLAG_ALRAF 0x00000100U -#define RTC_FLAG_INITF 0x00000040U -#define RTC_FLAG_RSF 0x00000020U -#define RTC_FLAG_INITS 0x00000010U -#define RTC_FLAG_SHPF 0x00000008U -#define RTC_FLAG_WUTWF 0x00000004U -#define RTC_FLAG_ALRBWF 0x00000002U -#define RTC_FLAG_ALRAWF 0x00000001U +#define RTC_FLAG_RECALPF RTC_ISR_RECALPF /*!< Recalibration pending flag */ +#if defined(RTC_TAMPER2_SUPPORT) +#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F /*!< Tamper 2 event flag */ +#endif /* RTC_TAMPER2_SUPPORT */ +#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F /*!< Tamper 1 event flag */ +#define RTC_FLAG_TSOVF RTC_ISR_TSOVF /*!< Timestamp overflow flag */ +#define RTC_FLAG_TSF RTC_ISR_TSF /*!< Timestamp event flag */ +#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Wakeup timer event flag */ +#define RTC_FLAG_ALRBF RTC_ISR_ALRBF /*!< Alarm B event flag */ +#define RTC_FLAG_ALRAF RTC_ISR_ALRAF /*!< Alarm A event flag */ +#define RTC_FLAG_INITF RTC_ISR_INITF /*!< RTC in initialization mode flag */ +#define RTC_FLAG_RSF RTC_ISR_RSF /*!< Register synchronization flag */ +#define RTC_FLAG_INITS RTC_ISR_INITS /*!< RTC initialization status flag */ +#define RTC_FLAG_SHPF RTC_ISR_SHPF /*!< Shift operation pending flag */ +#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< WUTR register write allowance flag */ +#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF /*!< ALRMBR register write allowance flag */ +#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF /*!< ALRMAR register write allowance flag */ /** * @} */ @@ -444,7 +450,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ + /** @defgroup RTC_Exported_Macros RTC Exported Macros * @{ */ @@ -454,11 +461,11 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @retval None */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ - (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL;\ - (__HANDLE__)->MspDeInitCallback = NULL;\ - }while(0u) +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_RTC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) #else #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ @@ -468,21 +475,20 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->WPR = 0xCAU; \ - (__HANDLE__)->Instance->WPR = 0x53U; \ - } while(0U) +#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) do { \ + (__HANDLE__)->Instance->WPR = 0xCAU; \ + (__HANDLE__)->Instance->WPR = 0x53U; \ + } while(0U) /** * @brief Enable the write protection for RTC registers. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->WPR = 0xFFU; \ - } while(0U) +#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) do { \ + (__HANDLE__)->Instance->WPR = 0xFFU; \ + } while(0U) + /** * @brief Enable the RTC ALARMA peripheral. @@ -527,9 +533,9 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @brief Disable the RTC Alarm interrupt. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt + * This parameter can be any combination of the following values: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt * @retval None */ #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) @@ -543,25 +549,25 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @arg RTC_IT_ALRB: Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) /** * @brief Get the selected RTC Alarm's flag status. * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC Alarm Flag to check. * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF - * @arg RTC_FLAG_ALRAWF - * @arg RTC_FLAG_ALRBWF + * @arg RTC_FLAG_ALRAF: Alarm A interrupt flag + * @arg RTC_FLAG_ALRAWF: Alarm A 'write allowed' flag + * @arg RTC_FLAG_ALRBF: Alarm B interrupt flag + * @arg RTC_FLAG_ALRBWF: Alarm B 'write allowed' flag * @retval None */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) /** * @brief Clear the RTC Alarm's pending flags. * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled. + * @param __FLAG__ specifies the RTC Alarm flag to be cleared. * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRBF @@ -569,7 +575,6 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to */ #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. @@ -579,86 +584,88 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @arg RTC_IT_ALRB: Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) /** - * @brief Enable interrupt on the RTC Alarm associated Exti line. + * @brief Enable interrupt on the RTC Alarm associated EXTI line. * @retval None */ #define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Disable interrupt on the RTC Alarm associated Exti line. + * @brief Disable interrupt on the RTC Alarm associated EXTI line. * @retval None */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) +#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Enable event on the RTC Alarm associated Exti line. + * @brief Enable event on the RTC Alarm associated EXTI line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) +#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Disable event on the RTC Alarm associated Exti line. + * @brief Disable event on the RTC Alarm associated EXTI line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) +#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Enable falling edge trigger on the RTC Alarm associated Exti line. + * @brief Enable falling edge trigger on the RTC Alarm associated EXTI line. * @retval None. */ #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Disable falling edge trigger on the RTC Alarm associated Exti line. + * @brief Disable falling edge trigger on the RTC Alarm associated EXTI line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) +#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Enable rising edge trigger on the RTC Alarm associated Exti line. + * @brief Enable rising edge trigger on the RTC Alarm associated EXTI line. * @retval None. */ #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Disable rising edge trigger on the RTC Alarm associated Exti line. + * @brief Disable rising edge trigger on the RTC Alarm associated EXTI line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @brief Enable rising & falling edge trigger on the RTC Alarm associated EXTI line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\ +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ } while(0U) /** - * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @brief Disable rising & falling edge trigger on the RTC Alarm associated EXTI line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();\ - __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\ +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ } while(0U) /** - * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. + * @brief Check whether the RTC Alarm associated EXTI line interrupt flag is set or not. * @retval Line Status. */ #define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Clear the RTC Alarm associated Exti line flag. + * @brief Clear the RTC Alarm associated EXTI line flag. * @retval None. */ #define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Generate a Software interrupt on RTC Alarm associated Exti line. + * @brief Generate a Software interrupt on RTC Alarm associated EXTI line. * @retval None. */ #define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT) @@ -666,10 +673,11 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @} */ -/* Include RTC HAL Extension module */ +/* Include RTC HAL Extended module */ #include "stm32f4xx_hal_rtc_ex.h" /* Exported functions --------------------------------------------------------*/ + /** @addtogroup RTC_Exported_Functions * @{ */ @@ -680,8 +688,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -700,11 +708,6 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); /** * @} */ @@ -717,9 +720,9 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); /** * @} */ @@ -728,7 +731,14 @@ void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); + +/* RTC Daylight Saving Time functions *****************************************/ +void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); /** * @} */ @@ -749,28 +759,38 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ + /** @defgroup RTC_Private_Constants RTC Private Constants * @{ */ /* Masks Definition */ -#define RTC_TR_RESERVED_MASK 0x007F7F7FU -#define RTC_DR_RESERVED_MASK 0x00FFFF3FU +#define RTC_TR_RESERVED_MASK ((uint32_t)(RTC_TR_HT | RTC_TR_HU | \ + RTC_TR_MNT | RTC_TR_MNU | \ + RTC_TR_ST | RTC_TR_SU | \ + RTC_TR_PM)) +#define RTC_DR_RESERVED_MASK ((uint32_t)(RTC_DR_YT | RTC_DR_YU | \ + RTC_DR_MT | RTC_DR_MU | \ + RTC_DR_DT | RTC_DR_DU | \ + RTC_DR_WDU)) #define RTC_INIT_MASK 0xFFFFFFFFU -#define RTC_RSF_MASK 0xFFFFFF5FU -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ - RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ - RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ - RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \ - RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) +#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF)) +#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \ + RTC_FLAG_ALRAF | RTC_FLAG_ALRAWF | \ + RTC_FLAG_ALRBF | RTC_FLAG_ALRBWF | \ + RTC_FLAG_WUTF | RTC_FLAG_WUTWF | \ + RTC_FLAG_RECALPF | RTC_FLAG_SHPF | \ + RTC_FLAG_TSF | RTC_FLAG_TSOVF | \ + RTC_FLAG_RSF | RTC_TAMPER_FLAGS_MASK)) -#define RTC_TIMEOUT_VALUE 1000 +#define RTC_TIMEOUT_VALUE 1000U -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */ /** * @} */ /* Private macros ------------------------------------------------------------*/ + /** @defgroup RTC_Private_Macros RTC Private Macros * @{ */ @@ -780,31 +800,42 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); */ #define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ ((FORMAT) == RTC_HOURFORMAT_24)) + #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ ((OUTPUT) == RTC_OUTPUT_WAKEUP)) + #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ ((POL) == RTC_OUTPUT_POLARITY_LOW)) + #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) + #define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU) #define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU) + +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) #define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) #define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) -#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) +#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \ + ((PM) == RTC_HOURFORMAT12_PM)) + #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) + #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ ((OPERATION) == RTC_STOREOPERATION_SET)) + #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) + #define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) #define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) #define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) + #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ @@ -812,7 +843,9 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U)) + #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ @@ -820,27 +853,31 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) -#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET) + +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ((uint32_t)~RTC_ALARMMASK_ALL)) == 0U) + #define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU) - -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ + +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS) + +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ ((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) /** * @} @@ -851,12 +888,14 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); */ /* Private functions ---------------------------------------------------------*/ + /** @defgroup RTC_Private_Functions RTC Private Functions * @{ */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); -uint8_t RTC_ByteToBcd2(uint8_t Value); -uint8_t RTC_Bcd2ToByte(uint8_t Value); +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc); +uint8_t RTC_ByteToBcd2(uint8_t number); +uint8_t RTC_Bcd2ToByte(uint8_t number); /** * @} */ @@ -873,6 +912,4 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value); } #endif -#endif /* __STM32F4xx_HAL_RTC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_RTC_H */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h index 8312c23cd0..ff5f14d498 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h @@ -2,30 +2,30 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc_ex.h * @author MCD Application Team - * @brief Header file of RTC HAL Extension module. + * @brief Header file of RTC HAL Extended module. ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_RTC_EX_H -#define __STM32F4xx_HAL_RTC_EX_H +#ifndef STM32F4xx_HAL_RTC_EX_H +#define STM32F4xx_HAL_RTC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ + #include "stm32f4xx_hal_def.h" /** @addtogroup STM32F4xx_HAL_Driver @@ -37,6 +37,7 @@ */ /* Exported types ------------------------------------------------------------*/ + /** @defgroup RTCEx_Exported_Types RTCEx Exported Types * @{ */ @@ -47,13 +48,13 @@ typedef struct { uint32_t Tamper; /*!< Specifies the Tamper Pin. - This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_Pin_Definitions */ uint32_t PinSelection; /*!< Specifies the Tamper Pin. - This parameter can be a value of @ref RTCEx_Tamper_Pins_Selection */ + This parameter can be a value of @ref RTCEx_Tamper_Pin_Selection */ uint32_t Trigger; /*!< Specifies the Tamper Trigger. - This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ uint32_t Filter; /*!< Specifies the RTC Filter Tamper. This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ @@ -65,21 +66,22 @@ typedef struct This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp . - This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_Pull_Up_Definitions */ uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ -}RTC_TamperTypeDef; +} RTC_TamperTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants * @{ */ -/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions +/** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definitions * @{ */ #define RTC_BKP_DR0 0x00000000U @@ -106,196 +108,207 @@ typedef struct * @} */ -/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC TimeStamp Edges Definitions +/** @defgroup RTCEx_Timestamp_Edges_Definitions RTCEx Timestamp Edges Definitions * @{ */ #define RTC_TIMESTAMPEDGE_RISING 0x00000000U -#define RTC_TIMESTAMPEDGE_FALLING 0x00000008U +#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE /** * @} */ -/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions +/** @defgroup RTCEx_Timestamp_Pin_Selection RTC Timestamp Pin Selection * @{ */ -#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E +#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U +#if defined(RTC_AF2_SUPPORT) +#define RTC_TIMESTAMPPIN_POS1 RTC_TAFCR_TSINSEL +#endif /* RTC_AF2_SUPPORT */ +/** + * @} + */ -#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx) +/** @defgroup RTCEx_Tamper_Pin_Definitions RTCEx Tamper Pins Definitions + * @{ + */ +#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_TAMPER_2 RTC_TAFCR_TAMP2E -#endif +#endif /* RTC_TAMPER2_SUPPORT */ /** * @} */ -/** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection +/** @defgroup RTCEx_Tamper_Pin_Selection RTC tamper Pins Selection * @{ */ - #define RTC_TAMPERPIN_DEFAULT 0x00000000U - -#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx) -#define RTC_TAMPERPIN_POS1 0x00010000U -#endif +#if defined(RTC_AF2_SUPPORT) +#define RTC_TAMPERPIN_POS1 RTC_TAFCR_TAMP1INSEL +#endif /* RTC_AF2_SUPPORT */ /** * @} */ -/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection +/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions * @{ */ -#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U - -#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx) -#define RTC_TIMESTAMPPIN_POS1 0x00020000U -#endif +#define RTC_IT_TAMP RTC_TAFCR_TAMPIE /*!< Enable global Tamper Interrupt */ /** * @} */ -/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions +/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Triggers Definitions * @{ */ #define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U -#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U +#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG #define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE #define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE /** * @} */ -/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions +/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions * @{ */ -#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ +#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ -#define RTC_TAMPERFILTER_2SAMPLE 0x00000800U /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE 0x00001000U /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE 0x00001800U /*!< Tamper is activated after 8 - consecutive samples at the active level. */ +#define RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_MASK RTC_TAFCR_TAMPFLT /*!< Masking all bits except those of + field TAMPFLT */ /** * @} */ -/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions +/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions * @{ */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 0x00000100U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 0x00000200U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 0x00000300U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 0x00000400U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 0x00000500U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 0x00000600U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 0x00000700U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 RTC_TAFCR_TAMPFREQ /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK RTC_TAFCR_TAMPFREQ /*!< Masking all bits except those of + field TAMPFREQ */ /** * @} */ -/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions +/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions * @{ */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK 0x00002000U /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK 0x00004000U /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK 0x00006000U /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK RTC_TAFCR_TAMPPRCH /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_MASK RTC_TAFCR_TAMPPRCH /*!< Masking all bits except those of + field TAMPPRCH */ /** * @} */ -/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions +/** @defgroup RTCEx_Tamper_Pull_Up_Definitions RTCEx Tamper Pull Up Definitions * @{ */ -#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_DISABLE RTC_TAFCR_TAMPPUDIS /*!< Tamper pins are not pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_MASK RTC_TAFCR_TAMPPUDIS /*!< Masking all bits except bit TAMPPUDIS */ /** * @} */ -/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions +/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStamp On Tamper Detection Definitions * @{ */ -#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAFCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_MASK RTC_TAFCR_TAMPTS /*!< Masking all bits except bit TAMPTS */ /** * @} */ -/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wake-up Timer Definitions +/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions * @{ */ #define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 0x00000001U -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 0x00000002U -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 0x00000003U -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS 0x00000004U -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS 0x00000006U +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2) /** * @} */ -/** @defgroup RTCEx_Digital_Calibration_Definitions RTC Digital Calib Definitions +/** @defgroup RTCEx_Coarse_Calibration_Definitions RTCEx Coarse Calib Definitions * @{ */ #define RTC_CALIBSIGN_POSITIVE 0x00000000U -#define RTC_CALIBSIGN_NEGATIVE 0x00000080U +#define RTC_CALIBSIGN_NEGATIVE RTC_CALIBR_DCS /** * @} */ -/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions +/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth Calib Period Definitions * @{ */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC 0x00002000U /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC 0x00004000U /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 8s, else 2exp18 RTCCLK seconds */ +#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, smooth calibration + period is 32s, otherwise 2^20 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, smooth calibration + period is 16s, otherwise 2^19 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, smooth calibration + period is 8s, otherwise 2^18 RTCCLK pulses */ /** * @} */ -/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions +/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth Calib Plus Pulses Definitions * @{ */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET 0x00008000U /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0] - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0] */ +#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0] + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0] */ /** * @} */ -/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions +/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions * @{ */ #define RTC_SHIFTADD1S_RESET 0x00000000U -#define RTC_SHIFTADD1S_SET 0x80000000U +#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S /** * @} */ - - /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions +/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output Selection Definitions * @{ */ #define RTC_CALIBOUTPUT_512HZ 0x00000000U -#define RTC_CALIBOUTPUT_1HZ 0x00080000U +#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL /** * @} */ @@ -304,13 +317,15 @@ typedef struct * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ + /** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros * @{ */ -/* ---------------------------------WAKEUPTIMER---------------------------------*/ -/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer +/* ---------------------------------WAKEUPTIMER-------------------------------*/ + +/** @defgroup RTCEx_WakeUp_Timer RTCEx WakeUp Timer * @{ */ @@ -322,152 +337,154 @@ typedef struct #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) /** - * @brief Disable the RTC Wake-up Timer peripheral. + * @brief Disable the RTC Wakeup Timer peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) /** - * @brief Enable the RTC WakeUpTimer interrupt. + * @brief Enable the RTC Wakeup Timer interrupt. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt sources to be enabled or disabled. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt + * @arg RTC_IT_WUT: Wakeup Timer interrupt * @retval None */ #define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) /** - * @brief Disable the RTC WakeUpTimer interrupt. + * @brief Disable the RTC Wakeup Timer interrupt. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt sources to be enabled or disabled. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt + * @arg RTC_IT_WUT: Wakeup Timer interrupt * @retval None */ #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) /** - * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. + * @brief Check whether the specified RTC Wakeup Timer interrupt has occurred or not. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. + * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt to check. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt + * @arg RTC_IT_WUT: Wakeup Timer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) /** - * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @brief Check whether the specified RTC Wakeup timer interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. + * @param __INTERRUPT__ specifies the RTC Wakeup timer interrupt sources to check. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) /** - * @brief Get the selected RTC WakeUpTimer's flag status. + * @brief Get the selected RTC Wakeup Timer's flag status. * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC WakeUpTimer Flag to check. + * @param __FLAG__ specifies the RTC Wakeup Timer flag to check. * This parameter can be: - * @arg RTC_FLAG_WUTF - * @arg RTC_FLAG_WUTWF + * @arg RTC_FLAG_WUTF: Wakeup Timer interrupt flag + * @arg RTC_FLAG_WUTWF: Wakeup Timer 'write allowed' flag * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) /** - * @brief Clear the RTC Wake Up timer's pending flags. + * @brief Clear the RTC Wakeup timer's pending flags. * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled. + * @param __FLAG__ specifies the RTC Wakeup Timer Flag to clear. * This parameter can be: - * @arg RTC_FLAG_WUTF + * @arg RTC_FLAG_WUTF: Wakeup Timer interrupt Flag * @retval None */ #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) /** - * @brief Enable interrupt on the RTC Wake-up Timer associated Exti line. + * @brief Enable interrupt on the RTC Wakeup Timer associated EXTI line. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Disable interrupt on the RTC Wake-up Timer associated Exti line. + * @brief Disable interrupt on the RTC Wakeup Timer associated EXTI line. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Enable event on the RTC Wake-up Timer associated Exti line. + * @brief Enable event on the RTC Wakeup Timer associated EXTI line. * @retval None. */ #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Disable event on the RTC Wake-up Timer associated Exti line. + * @brief Disable event on the RTC Wakeup Timer associated EXTI line. * @retval None. */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Enable falling edge trigger on the RTC Wake-up Timer associated Exti line. + * @brief Enable falling edge trigger on the RTC Wakeup Timer associated EXTI line. * @retval None. */ #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Disable falling edge trigger on the RTC Wake-up Timer associated Exti line. + * @brief Disable falling edge trigger on the RTC Wakeup Timer associated EXTI line. * @retval None. */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Enable rising edge trigger on the RTC Wake-up Timer associated Exti line. + * @brief Enable rising edge trigger on the RTC Wakeup Timer associated EXTI line. * @retval None. */ #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Disable rising edge trigger on the RTC Wake-up Timer associated Exti line. + * @brief Disable rising edge trigger on the RTC Wakeup Timer associated EXTI line. * @retval None. */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line. + * @brief Enable rising & falling edge trigger on the RTC Wakeup Timer associated EXTI line. * @retval None. */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \ } while(0U) /** - * @brief Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line. + * @brief Disable rising & falling edge trigger on the RTC Wakeup Timer associated EXTI line. * This parameter can be: * @retval None. */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\ - __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \ } while(0U) /** - * @brief Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not. + * @brief Check whether the RTC Wakeup Timer associated EXTI line interrupt flag is set or not. * @retval Line Status. */ #define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Clear the RTC Wake-up Timer associated Exti line flag. + * @brief Clear the RTC Wakeup Timer associated EXTI line flag. * @retval None. */ #define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Generate a Software interrupt on the RTC Wake-up Timer associated Exti line. + * @brief Generate a Software interrupt on the RTC Wakeup Timer associated EXTI line. * @retval None. */ #define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) @@ -477,28 +494,29 @@ typedef struct */ /* ---------------------------------TIMESTAMP---------------------------------*/ -/** @defgroup RTCEx_Timestamp RTC Timestamp + +/** @defgroup RTCEx_Timestamp RTCEx Timestamp * @{ */ /** - * @brief Enable the RTC TimeStamp peripheral. + * @brief Enable the RTC Timestamp peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) /** - * @brief Disable the RTC TimeStamp peripheral. + * @brief Disable the RTC Timestamp peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) /** - * @brief Enable the RTC TimeStamp interrupt. + * @brief Enable the RTC Timestamp interrupt. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * @param __INTERRUPT__ specifies the RTC Timestamp interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -506,9 +524,9 @@ typedef struct #define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) /** - * @brief Disable the RTC TimeStamp interrupt. + * @brief Disable the RTC Timestamp interrupt. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * @param __INTERRUPT__ specifies the RTC Timestamp interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -516,42 +534,43 @@ typedef struct #define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) /** - * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. + * @brief Check whether the specified RTC Timestamp interrupt has occurred or not. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check. + * @param __INTERRUPT__ specifies the RTC Timestamp interrupt to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) /** - * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. + * @brief Check whether the specified RTC Timestamp interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. + * @param __INTERRUPT__ specifies the RTC Timestamp interrupt source to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) /** - * @brief Get the selected RTC TimeStamp's flag status. + * @brief Get the selected RTC Timestamp's flag status. * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC TimeStamp flag to check. + * @param __FLAG__ specifies the RTC Timestamp flag to check. * This parameter can be: - * @arg RTC_FLAG_TSF - * @arg RTC_FLAG_TSOVF + * @arg RTC_FLAG_TSF: Timestamp interrupt flag + * @arg RTC_FLAG_TSOVF: Timestamp overflow flag * @retval None */ -#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) /** - * @brief Clear the RTC Time Stamp's pending flags. + * @brief Clear the RTC Timestamp's pending flags. * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TSF + * @param __FLAG__ specifies the RTC Timestamp flag to clear. + * This parameter can be: + * @arg RTC_FLAG_TSF: Timestamp interrupt flag + * @arg RTC_FLAG_TSOVF: Timestamp overflow flag * @retval None */ #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) @@ -561,7 +580,8 @@ typedef struct */ /* ---------------------------------TAMPER------------------------------------*/ -/** @defgroup RTCEx_Tamper RTC Tamper + +/** @defgroup RTCEx_Tamper RTCEx Tamper * @{ */ @@ -579,7 +599,7 @@ typedef struct */ #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E)) -#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx) +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Enable the RTC Tamper2 input detection. * @param __HANDLE__ specifies the RTC handle. @@ -593,47 +613,70 @@ typedef struct * @retval None */ #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E)) -#endif +#endif /* RTC_TAMPER2_SUPPORT */ + +/** + * @brief Enable the RTC Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP: Tamper global interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP: Tamper global interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__)) /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. * This parameter can be: - * @arg RTC_IT_TAMP1 - * @arg RTC_IT_TAMP2 + * @arg RTC_IT_TAMP1: Tamper 1 interrupt + * @arg RTC_IT_TAMP2: Tamper 2 interrupt + * @note RTC_IT_TAMP2 is not applicable to all devices. * @retval None */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. * This parameter can be: - * @arg RTC_IT_TAMP: Tamper interrupt + * @arg RTC_IT_TAMP: Tamper global interrupt * @retval None */ -#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) /** * @brief Get the selected RTC Tamper's flag status. * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled. + * @param __FLAG__ specifies the RTC Tamper flag to be checked. * This parameter can be: - * @arg RTC_FLAG_TAMP1F - * @arg RTC_FLAG_TAMP2F + * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag + * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag + * @note RTC_FLAG_TAMP2F is not applicable to all devices. * @retval None */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) /** * @brief Clear the RTC Tamper's pending flags. * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC Tamper Flag to clear. * This parameter can be: - * @arg RTC_FLAG_TAMP1F - * @arg RTC_FLAG_TAMP2F + * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag + * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag + * @note RTC_FLAG_TAMP2F is not applicable to all devices. * @retval None */ #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) @@ -647,84 +690,86 @@ typedef struct */ /** - * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line. + * @brief Enable interrupt on the RTC Tamper and Timestamp associated EXTI line. * @retval None */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line. + * @brief Disable interrupt on the RTC Tamper and Timestamp associated EXTI line. * @retval None */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Enable event on the RTC Tamper and Timestamp associated Exti line. + * @brief Enable event on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Disable event on the RTC Tamper and Timestamp associated Exti line. + * @brief Disable event on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();\ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \ } while(0U) /** - * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. * This parameter can be: * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();\ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \ } while(0U) /** - * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not. + * @brief Check whether the RTC Tamper and Timestamp associated EXTI line interrupt flag is set or not. * @retval Line Status. */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Clear the RTC Tamper and Timestamp associated Exti line flag. + * @brief Clear the RTC Tamper and Timestamp associated EXTI line flag. * @retval None. */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line + * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated EXTI line * @retval None. */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) @@ -732,8 +777,9 @@ typedef struct * @} */ -/* ------------------------------Calibration----------------------------------*/ -/** @defgroup RTCEx_Calibration RTC Calibration +/* ------------------------------CALIBRATION----------------------------------*/ + +/** @defgroup RTCEx_Calibration RTCEx Calibration * @{ */ @@ -784,10 +830,10 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. * This parameter can be: - * @arg RTC_FLAG_SHPF + * @arg RTC_FLAG_SHPF: Shift pending flag * @retval None */ -#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) /** * @} */ @@ -797,6 +843,7 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ + /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions * @{ */ @@ -804,23 +851,27 @@ typedef struct /** @addtogroup RTCEx_Exported_Functions_Group1 * @{ */ -/* RTC TimeStamp and Tamper functions *****************************************/ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +/* RTC Timestamp and Tamper functions *****************************************/ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin); HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +#if defined(RTC_TAMPER2_SUPPORT) +void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); +#endif /* RTC_TAMPER2_SUPPORT */ +void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#if defined(RTC_TAMPER2_SUPPORT) HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#endif /* RTC_TAMPER2_SUPPORT */ /** * @} */ @@ -828,13 +879,13 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ /** @addtogroup RTCEx_Exported_Functions_Group2 * @{ */ -/* RTC Wake-up functions ******************************************************/ +/* RTC Wakeup functions ******************************************************/ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); /** * @} @@ -843,13 +894,13 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /** @addtogroup RTCEx_Exported_Functions_Group3 * @{ */ -/* Extension Control functions ************************************************/ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +/* Extended Control functions ************************************************/ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value); HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue); +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); @@ -864,7 +915,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); /** @addtogroup RTCEx_Exported_Functions_Group4 * @{ */ -/* Extension RTC features functions *******************************************/ +/* Extended RTC features functions *******************************************/ void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); /** @@ -878,16 +929,37 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ + +/** @defgroup RTCEx_Private_Constants RTCEx Private Constants + * @{ + */ +#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_MR21 /*!< External interrupt line 21 Connected to the RTC Tamper and Timestamp event */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */ +/** + * @} + */ + /** @defgroup RTCEx_Private_Constants RTCEx Private Constants * @{ */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */ +/* Masks Definition */ +#if defined(RTC_TAMPER2_SUPPORT) +#define RTC_TAMPER_ENABLE_BITS_MASK ((uint32_t) (RTC_TAMPER_1 | \ + RTC_TAMPER_2)) + +#define RTC_TAMPER_FLAGS_MASK ((uint32_t) (RTC_FLAG_TAMP1F | \ + RTC_FLAG_TAMP2F)) +#else /* RTC_TAMPER2_SUPPORT */ +#define RTC_TAMPER_ENABLE_BITS_MASK RTC_TAMPER_1 + +#define RTC_TAMPER_FLAGS_MASK RTC_FLAG_TAMP1F +#endif /* RTC_TAMPER2_SUPPORT */ /** * @} */ /* Private macros ------------------------------------------------------------*/ + /** @defgroup RTCEx_Private_Macros RTCEx Private Macros * @{ */ @@ -895,56 +967,45 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters * @{ */ -#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ - ((BKP) == RTC_BKP_DR1) || \ - ((BKP) == RTC_BKP_DR2) || \ - ((BKP) == RTC_BKP_DR3) || \ - ((BKP) == RTC_BKP_DR4) || \ - ((BKP) == RTC_BKP_DR5) || \ - ((BKP) == RTC_BKP_DR6) || \ - ((BKP) == RTC_BKP_DR7) || \ - ((BKP) == RTC_BKP_DR8) || \ - ((BKP) == RTC_BKP_DR9) || \ - ((BKP) == RTC_BKP_DR10) || \ - ((BKP) == RTC_BKP_DR11) || \ - ((BKP) == RTC_BKP_DR12) || \ - ((BKP) == RTC_BKP_DR13) || \ - ((BKP) == RTC_BKP_DR14) || \ - ((BKP) == RTC_BKP_DR15) || \ - ((BKP) == RTC_BKP_DR16) || \ - ((BKP) == RTC_BKP_DR17) || \ - ((BKP) == RTC_BKP_DR18) || \ - ((BKP) == RTC_BKP_DR19)) +#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER) + #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E ))) == 0x00U) && ((TAMPER) != (uint32_t)RESET)) -#else -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E | RTC_TAFCR_TAMP2E))) == 0x00U) && ((TAMPER) != (uint32_t)RESET)) -#endif +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)~RTC_TAMPER_ENABLE_BITS_MASK)) == 0x00U) && ((TAMPER) != 0U)) -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -#define IS_RTC_TAMPER_PIN(PIN) ((PIN) == RTC_TAMPERPIN_DEFAULT) -#else +#if defined(RTC_AF2_SUPPORT) #define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_DEFAULT) || \ ((PIN) == RTC_TAMPERPIN_POS1)) -#endif +#else /* RTC_AF2_SUPPORT */ +#define IS_RTC_TAMPER_PIN(PIN) ((PIN) == RTC_TAMPERPIN_DEFAULT) +#endif /* RTC_AF2_SUPPORT */ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -#define IS_RTC_TIMESTAMP_PIN(PIN) ((PIN) == RTC_TIMESTAMPPIN_DEFAULT) -#else +#if defined(RTC_AF2_SUPPORT) #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT) || \ ((PIN) == RTC_TIMESTAMPPIN_POS1)) -#endif -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ +#else /* RTC_AF2_SUPPORT */ +#define IS_RTC_TIMESTAMP_PIN(PIN) ((PIN) == RTC_TIMESTAMPPIN_DEFAULT) +#endif /* RTC_AF2_SUPPORT */ + +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) + #define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) + +#define IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(FILTER, TRIGGER) \ + ( ( ((FILTER) != RTC_TAMPERFILTER_DISABLE) \ + && ( ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) \ + || ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))) \ + || ( ((FILTER) == RTC_TAMPERFILTER_DISABLE) \ + && ( ((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) \ + || ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE)))) + #define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ @@ -953,14 +1014,18 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) + #define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) -#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ - ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + #define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) + +#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ @@ -968,7 +1033,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU) +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT) + #define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \ ((SIGN) == RTC_CALIBSIGN_NEGATIVE)) @@ -977,13 +1043,17 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) + #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU) +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM) + #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ ((SEL) == RTC_SHIFTADD1S_SET)) -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU) + +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS) + #define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) /** @@ -1006,6 +1076,4 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t } #endif -#endif /* __STM32F4xx_HAL_RTC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_RTC_EX_H */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h index 0307f92333..6c23f93c15 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -118,7 +117,7 @@ typedef struct uint32_t TriState; /*!< Specifies the companding mode type. This parameter can be a value of @ref SAI_TRIState_Management */ - /* This part of the structure is automatically filled if your are using the high level intialisation + /* This part of the structure is automatically filled if your are using the high level initialisation function HAL_SAI_InitProtocol */ uint32_t Protocol; /*!< Specifies the SAI Block protocol. @@ -894,4 +893,3 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #endif /* __STM32F4xx_HAL_SAI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h index fbd44979de..c6fdd56612 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sai_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -113,4 +112,3 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai); #endif /* __STM32F4xx_HAL_SAI_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h index 0ee1052e17..d2f0403bbb 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -757,5 +756,3 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); #endif /* STM32F4xx_HAL_SD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h index 1ab41a0924..3d450a0387 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sdram.h @@ -6,27 +6,25 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_SDRAM_H -#define __STM32F4xx_HAL_SDRAM_H +#ifndef STM32F4xx_HAL_SDRAM_H +#define STM32F4xx_HAL_SDRAM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined(FMC_Bank5_6) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_ll_fmc.h" @@ -40,6 +38,7 @@ */ /* Exported typedef ----------------------------------------------------------*/ + /** @defgroup SDRAM_Exported_Types SDRAM Exported Types * @{ */ @@ -78,12 +77,12 @@ typedef struct DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp Init callback */ - void (* MspDeInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp DeInit callback */ - void (* RefreshErrorCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Refresh Error callback */ - void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SDRAM DMA Xfer Complete callback */ - void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SDRAM DMA Xfer Error callback */ -#endif + void (* MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp Init callback */ + void (* MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp DeInit callback */ + void (* RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Refresh Error callback */ + void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Error callback */ +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } SDRAM_HandleTypeDef; #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) @@ -97,20 +96,21 @@ typedef enum HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */ HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */ HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */ -}HAL_SDRAM_CallbackIDTypeDef; +} HAL_SDRAM_CallbackIDTypeDef; /** * @brief HAL SDRAM Callback pointer definition */ typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram); typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ + /** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros * @{ */ @@ -127,12 +127,13 @@ typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); } while(0) #else #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /** * @} */ /* Exported functions --------------------------------------------------------*/ + /** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions * @{ */ @@ -151,6 +152,7 @@ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram); void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram); void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); + /** * @} */ @@ -159,22 +161,32 @@ void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); * @{ */ /* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); - -HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); + +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) /* SDRAM callback registering/unregistering */ -HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId); -HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback); -#endif +HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_DmaCallbackTypeDef pCallback); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /** * @} @@ -186,10 +198,12 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL /* SDRAM Control functions *****************************************************/ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram); HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram); -HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, + uint32_t Timeout); HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate); HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber); uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); + /** * @} */ @@ -211,16 +225,14 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - /** * @} */ +#endif /* FMC_Bank5_6 */ + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_SDRAM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_SDRAM_H */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h index 36f16c757c..135f40261e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -157,7 +156,7 @@ typedef struct __SMARTCARD_HandleTypeDef SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ @@ -643,11 +642,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, * @{ */ /* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); /* Transfer Abort functions */ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc); @@ -754,4 +753,3 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); #endif /* __STM32F4xx_HAL_SMARTCARD_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h index 056a600d17..ea92afa30c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smbus.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -730,4 +729,3 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); #endif /* __STM32F4xx_HAL_SMBUS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spdifrx.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spdifrx.h index 73e30d2283..7ea04aa900 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spdifrx.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spdifrx.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -22,7 +21,7 @@ #define STM32F4xx_HAL_SPDIFRX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -124,7 +123,7 @@ typedef enum typedef struct __SPDIFRX_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ { SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */ @@ -168,8 +167,8 @@ typedef struct void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed callback */ void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */ void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */ - void (* MspInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp Init callback */ - void (* MspDeInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp DeInit callback */ + void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp Init callback */ + void (* MspDeInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp DeInit callback */ #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ } SPDIFRX_HandleTypeDef; @@ -190,12 +189,12 @@ typedef enum HAL_SPDIFRX_ERROR_CB_ID = 0x04U, /*!< SPDIFRX error callback */ HAL_SPDIFRX_MSPINIT_CB_ID = 0x05U, /*!< SPDIFRX Msp Init callback ID */ HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U /*!< SPDIFRX Msp DeInit callback ID */ -}HAL_SPDIFRX_CallbackIDTypeDef; +} HAL_SPDIFRX_CallbackIDTypeDef; /** * @brief HAL SPDIFRX Callback pointer definition */ -typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< pointer to an SPDIFRX callback function */ +typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback function */ #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ /* Exported constants --------------------------------------------------------*/ @@ -268,8 +267,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< */ /** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask -* @{ -*/ + * @{ + */ #define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U) #define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK) /** @@ -369,10 +368,10 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< */ #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\ - (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL;\ - (__HANDLE__)->MspDeInitCallback = NULL;\ - }while(0) + (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0) #else #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET) #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ @@ -411,7 +410,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< * @retval None */ #define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) -#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__))) +#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR\ + &= (uint16_t)(~(__INTERRUPT__))) /** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled. * @param __HANDLE__ specifies the SPDIFRX Handle. @@ -426,7 +426,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< * @arg SPDIFRX_IT_IFEIE * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified SPDIFRX flag is set or not. * @param __HANDLE__ specifies the SPDIFRX Handle. @@ -443,7 +444,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< * @arg SPDIFRX_FLAG_TERR * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\ + & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit. * @param __HANDLE__ specifies the USART Handle. @@ -472,15 +474,17 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< */ /* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif); -HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif); +HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif); void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif); void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif); HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, + pSPDIFRX_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, + HAL_SPDIFRX_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ /** * @} @@ -490,9 +494,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, * @{ */ /* I/O operation functions ***************************************************/ - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); @@ -518,8 +524,8 @@ void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif); * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif); -uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif); +HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif); +uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif); /** * @} */ @@ -535,39 +541,39 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif); * @{ */ #define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \ - ((INPUT) == SPDIFRX_INPUT_IN2) || \ - ((INPUT) == SPDIFRX_INPUT_IN3) || \ - ((INPUT) == SPDIFRX_INPUT_IN0)) + ((INPUT) == SPDIFRX_INPUT_IN2) || \ + ((INPUT) == SPDIFRX_INPUT_IN3) || \ + ((INPUT) == SPDIFRX_INPUT_IN0)) #define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \ - ((RET) == SPDIFRX_MAXRETRIES_3) || \ - ((RET) == SPDIFRX_MAXRETRIES_15) || \ - ((RET) == SPDIFRX_MAXRETRIES_63)) + ((RET) == SPDIFRX_MAXRETRIES_3) || \ + ((RET) == SPDIFRX_MAXRETRIES_15) || \ + ((RET) == SPDIFRX_MAXRETRIES_63)) #define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \ - ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF)) + ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF)) #define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \ - ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF)) + ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF)) #define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \ - ((VAL) == SPDIFRX_VALIDITYMASK_ON)) + ((VAL) == SPDIFRX_VALIDITYMASK_ON)) #define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \ - ((VAL) == SPDIFRX_PARITYERRORMASK_ON)) + ((VAL) == SPDIFRX_PARITYERRORMASK_ON)) #define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \ - ((CHANNEL) == SPDIFRX_CHANNEL_B)) + ((CHANNEL) == SPDIFRX_CHANNEL_B)) #define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \ - ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \ - ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS)) + ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \ + ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS)) #define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \ - ((MODE) == SPDIFRX_STEREOMODE_ENABLE)) + ((MODE) == SPDIFRX_STEREOMODE_ENABLE)) #define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \ - ((VAL) == SPDIFRX_CHANNELSTATUS_OFF)) + ((VAL) == SPDIFRX_CHANNELSTATUS_OFF)) /** * @} @@ -595,6 +601,4 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif); #endif -#endif /* __STM32F4xx_HAL_SPDIFRX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_SPDIFRX_H */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h index f2e07c2c0f..d7997a317b 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -656,7 +655,8 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** @@ -727,4 +727,3 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #endif /* STM32F4xx_HAL_SPI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h index 67cfa63e11..e135aa1378 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sram.h @@ -6,46 +6,36 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_SRAM_H -#define __STM32F4xx_HAL_SRAM_H +#ifndef STM32F4xx_HAL_SRAM_H +#define STM32F4xx_HAL_SRAM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -/* Includes ------------------------------------------------------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) - #include "stm32f4xx_ll_fsmc.h" -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - #include "stm32f4xx_ll_fmc.h" -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +#if defined(FMC_Bank1) || defined(FSMC_Bank1) +/* Includes ------------------------------------------------------------------*/ +#if defined(FSMC_Bank1) +#include "stm32f4xx_ll_fsmc.h" +#else +#include "stm32f4xx_ll_fmc.h" +#endif /* FSMC_Bank1 */ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) - /** @addtogroup SRAM * @{ */ @@ -90,11 +80,11 @@ typedef struct DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */ - void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */ - void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */ - void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */ -#endif + void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ + void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ + void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } SRAM_HandleTypeDef; #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) @@ -107,14 +97,14 @@ typedef enum HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ -}HAL_SRAM_CallbackIDTypeDef; +} HAL_SRAM_CallbackIDTypeDef; /** * @brief HAL SRAM Callback pointer definition */ typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} */ @@ -125,6 +115,7 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); /** @defgroup SRAM_Exported_Macros SRAM Exported Macros * @{ */ + /** @brief Reset SRAM handle state * @param __HANDLE__ SRAM handle * @retval None @@ -137,69 +128,89 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); } while(0) #else #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} */ + /* Exported functions --------------------------------------------------------*/ +/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions + * @{ + */ -/** @addtogroup SRAM_Exported_Functions - * @{ - */ +/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ -/** @addtogroup SRAM_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming); HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); +void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); +void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); /** * @} */ -/** @addtogroup SRAM_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions *****************************************************/ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions + * @{ + */ + +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); + +void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); + #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) /* SRAM callback registering/unregistering */ -HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); -HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback); -#endif +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + /** * @} */ -/** @addtogroup SRAM_Exported_Functions_Group3 - * @{ - */ -/* SRAM Control functions ******************************************************/ +/** @addtogroup SRAM_Exported_Functions_Group3 Control functions + * @{ + */ + +/* SRAM Control functions ****************************************************/ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); + /** * @} */ -/** @addtogroup SRAM_Exported_Functions_Group4 - * @{ - */ -/* SRAM State functions *********************************************************/ +/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions + * @{ + */ + +/* SRAM State functions ******************************************************/ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); + /** * @} */ @@ -208,25 +219,18 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); * @} */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ /** * @} */ + +#endif /* FMC_Bank1 || FSMC_Bank1 */ + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_SRAM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_SRAM_H */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h index 2322bf0999..8c81414fad 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -706,6 +705,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ @@ -740,16 +748,16 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ -#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ -#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ -#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ -#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ -#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ /** * @} */ @@ -1527,6 +1535,17 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ }while(0) +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + /** * @} */ @@ -1640,15 +1659,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to ((__CHANNEL__) == TIM_CHANNEL_3)) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ @@ -1724,13 +1743,13 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF)) #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -2125,5 +2144,3 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim); #endif #endif /* STM32F4xx_HAL_TIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h index 737fdc4e5e..39fb500f67 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -329,7 +328,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ -/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); @@ -353,5 +352,3 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); #endif /* STM32F4xx_HAL_TIM_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h index 14526e816b..c5f5d3e348 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -153,7 +152,7 @@ typedef struct __UART_HandleTypeDef UART_InitTypeDef Init; /*!< UART communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ uint16_t TxXferSize; /*!< UART Tx Transfer size */ @@ -720,11 +719,11 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); */ /* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); @@ -883,4 +882,3 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa #endif /* __STM32F4xx_HAL_UART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h index 83615ed219..b64e95dc0c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -102,7 +101,7 @@ typedef struct __USART_HandleTypeDef USART_InitTypeDef Init; /*!< Usart communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */ uint16_t TxXferSize; /*!< Usart Tx Transfer size */ @@ -510,17 +509,17 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ * @{ */ /* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); @@ -647,4 +646,3 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); #endif /* __STM32F4xx_HAL_USART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_wwdg.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_wwdg.h index 017b34df4b..ab8b1ead41 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_wwdg.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_wwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -184,7 +183,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt @@ -297,5 +296,3 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg); #endif #endif /* STM32F4xx_HAL_WWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h index 1fd89cbe07..44e8af28d3 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -4395,7 +4394,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_MST) == (LL_ADC_FLAG_EOCS_MST)); } /** @@ -4468,7 +4467,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_ /** * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. - * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS + * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_JEOS * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). @@ -4778,4 +4777,3 @@ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); #endif /* __STM32F4xx_LL_ADC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h index 66da28fe24..5083c10dc1 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h @@ -23,14 +23,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -2105,4 +2103,3 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) #endif /* __STM32F4xx_LL_BUS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h index eddcc97aea..d478e13019 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h @@ -22,14 +22,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -637,4 +635,3 @@ __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) #endif /* __STM32F4xx_LL_CORTEX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h index 2d05b67949..0a280062b8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -200,5 +199,3 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); #endif #endif /* STM32F4xx_LL_CRC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h index 98bf40b71c..ea1500ba58 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1454,4 +1453,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); #endif /* STM32F4xx_LL_DAC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h index 561c40f1ee..5169d3b819 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -2730,7 +2729,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) } /** - * @brief Check if Half transfer interrup is enabled. + * @brief Check if Half transfer interrupt is enabled. * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: @@ -2770,7 +2769,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Strea } /** - * @brief Check if Transfer complete interrup is enabled. + * @brief Check if Transfer complete interrupt is enabled. * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: @@ -2810,7 +2809,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stre } /** - * @brief Check if FIFO error interrup is enabled. + * @brief Check if FIFO error interrupt is enabled. * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: @@ -2867,4 +2866,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); #endif /* __STM32F4xx_LL_DMA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h index a783d058af..64c57b0ee4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1900,5 +1899,3 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb #endif #endif /* STM32F4xx_LL_DMA2D_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h index c816e266ef..65ab691840 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS.Clause * ****************************************************************************** */ @@ -953,4 +952,3 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); #endif /* __STM32F4xx_LL_EXTI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h index 0d78bf393d..3dc863d46c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h @@ -6,23 +6,22 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_FMC_H -#define __STM32F4xx_LL_FMC_H +#ifndef STM32F4xx_LL_FMC_H +#define STM32F4xx_LL_FMC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -35,81 +34,266 @@ /** @addtogroup FMC_LL * @{ */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/* Private types -------------------------------------------------------------*/ -/** @defgroup FMC_LL_Private_Types FMC Private Types + +/** @addtogroup FMC_LL_Private_Macros + * @{ + */ +#if defined(FMC_Bank1) + +#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ + ((__BANK__) == FMC_NORSRAM_BANK2) || \ + ((__BANK__) == FMC_NORSRAM_BANK3) || \ + ((__BANK__) == FMC_NORSRAM_BANK4)) +#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) +#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) +#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) +#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ + ((__SIZE__) == FMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FMC_PAGE_SIZE_512) || \ + ((__SIZE__) == FMC_PAGE_SIZE_1024)) +#if defined(FMC_BCR1_WFDIS) +#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ + ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) +#endif /* FMC_BCR1_WFDIS */ +#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ + ((__MODE__) == FMC_ACCESS_MODE_B) || \ + ((__MODE__) == FMC_ACCESS_MODE_C) || \ + ((__MODE__) == FMC_ACCESS_MODE_D)) +#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) +#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) +#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \ + ((__MODE__) == FMC_WRAP_MODE_ENABLE)) +#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) +#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) +#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) +#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) +#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) +#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) +#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FMC_WRITE_BURST_ENABLE)) +#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ + ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) +#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) +#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) +#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) +#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) +#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) +#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) + +#endif /* FMC_Bank1 */ +#if (defined(FMC_Bank3) || defined(FMC_Bank2_3)) + +#if defined(FMC_Bank2_3) +#define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK2) || \ + ((__BANK__) == FMC_NAND_BANK3)) +#else +#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) +#endif /* FMC_Bank2_3 */ +#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ + ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE)) +#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16)) +#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ + ((__STATE__) == FMC_NAND_ECC_ENABLE)) + +#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) +#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) +#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) +#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) + +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ +#if defined(FMC_Bank4) +#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE) + +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) + +#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32)) +#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ + ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) +#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) +#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ + ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) +#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) +#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) +#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) +#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) +#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) +#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U)) +#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U) +#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U) +#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) +#define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \ + ((__BANK__) == FMC_SDRAM_BANK2)) +#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11)) +#define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \ + ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \ + ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13)) +#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ + ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4)) +#define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \ + ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \ + ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3)) + +#endif /* FMC_Bank5_6 */ + +/** + * @} + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types * @{ */ +#if defined(FMC_Bank1) +#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef +#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef +#endif /* FMC_Bank1 */ +#if defined(FMC_Bank2_3) +#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef +#else +#define FMC_NAND_TypeDef FMC_Bank3_TypeDef +#endif /* FMC_Bank2_3 */ +#if defined(FMC_Bank4) +#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) +#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef +#endif /* FMC_Bank5_6 */ + +#if defined(FMC_Bank1) +#define FMC_NORSRAM_DEVICE FMC_Bank1 +#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E +#endif /* FMC_Bank1 */ +#if defined(FMC_Bank2_3) +#define FMC_NAND_DEVICE FMC_Bank2_3 +#else +#define FMC_NAND_DEVICE FMC_Bank3 +#endif /* FMC_Bank2_3 */ +#if defined(FMC_Bank4) +#define FMC_PCCARD_DEVICE FMC_Bank4 +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) +#define FMC_SDRAM_DEVICE FMC_Bank5_6 +#endif /* FMC_Bank5_6 */ + +#if defined(FMC_Bank1) /** * @brief FMC NORSRAM Configuration Structure definition */ typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of @ref FMC_Wrap_Mode - This mode is not available for the STM32F446/467/479xx devices */ + This mode is not available for the STM32F446/467/479xx devices */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. This parameter can be a value of @ref FMC_Write_FIFO - This mode is available only for the STM32F446/469/479xx devices */ + This mode is available only for the STM32F446/469/479xx devices */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ -}FMC_NORSRAM_InitTypeDef; + This parameter can be a value of @ref FMC_Page_Size */ +} FMC_NORSRAM_InitTypeDef; /** * @brief FMC NORSRAM Timing parameters structure definition @@ -119,60 +303,63 @@ typedef struct uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between Min_Data = 1 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between Min_Data = 1 and Max_Data = 255. @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed - NOR Flash memories. */ + NOR Flash memories. */ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is only used for multiplexed NOR Flash memories. */ + @note This parameter is only used for multiplexed NOR Flash memories. */ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of - HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. + HCLK cycles. This parameter can be a value between Min_Data = 2 and + Max_Data = 16. @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM - accesses. */ + accesses. */ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories - with synchronous burst mode enable */ + - It may assume a value between Min_Data = 2 and Max_Data = 17 + in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ -}FMC_NORSRAM_TimingTypeDef; + This parameter can be a value of @ref FMC_Access_Mode */ +} FMC_NORSRAM_TimingTypeDef; +#endif /* FMC_Bank1 */ +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) /** * @brief FMC NAND Configuration Structure definition */ typedef struct { uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. - This parameter can be a value of @ref FMC_NAND_Bank */ + This parameter can be a value of @ref FMC_NAND_Bank */ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. - This parameter can be any value of @ref FMC_Wait_feature */ + This parameter can be any value of @ref FMC_Wait_feature */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FMC_NAND_Data_Width */ + This parameter can be any value of @ref FMC_NAND_Data_Width */ uint32_t EccComputation; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FMC_ECC */ + This parameter can be any value of @ref FMC_ECC */ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FMC_ECC_Page_Size */ + This parameter can be any value of @ref FMC_ECC_Page_Size */ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. @@ -181,10 +368,12 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ -}FMC_NAND_InitTypeDef; +} FMC_NAND_InitTypeDef; +#endif +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) /** - * @brief FMC NAND/PCCARD Timing parameters structure definition + * @brief FMC NAND Timing parameters structure definition */ typedef struct { @@ -192,35 +381,37 @@ typedef struct the command assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address (and data for write access) after the command de-assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the data bus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ -}FMC_NAND_PCC_TimingTypeDef; + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ +} FMC_NAND_PCC_TimingTypeDef; +#endif /* FMC_Bank3 || FMC_Bank2_3 */ +#if defined(FMC_Bank4) /** - * @brief FMC NAND Configuration Structure definition + * @brief FMC PCCARD Configuration Structure definition */ typedef struct { uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. - This parameter can be any value of @ref FMC_Wait_feature */ + This parameter can be any value of @ref FMC_Wait_feature */ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. @@ -230,7 +421,9 @@ typedef struct delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ }FMC_PCCARD_InitTypeDef; +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) /** * @brief FMC SDRAM Configuration Structure definition */ @@ -267,7 +460,7 @@ typedef struct uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ -}FMC_SDRAM_InitTypeDef; +} FMC_SDRAM_InitTypeDef; /** * @brief FMC SDRAM Timing parameters structure definition @@ -301,7 +494,7 @@ typedef struct uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ -}FMC_SDRAM_TimingTypeDef; +} FMC_SDRAM_TimingTypeDef; /** * @brief SDRAM command parameters structure definition @@ -316,28 +509,32 @@ typedef struct uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued in auto refresh mode. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + This parameter can be a value between Min_Data = 1 and Max_Data = 15 */ + uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ -}FMC_SDRAM_CommandTypeDef; +} FMC_SDRAM_CommandTypeDef; +#endif /* FMC_Bank5_6 */ /** * @} */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup FMC_LL_Private_Constants FMC Private Constants +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants * @{ */ +#if defined(FMC_Bank1) /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller * @{ */ + /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank * @{ */ -#define FMC_NORSRAM_BANK1 0x00000000U -#define FMC_NORSRAM_BANK2 0x00000002U -#define FMC_NORSRAM_BANK3 0x00000004U -#define FMC_NORSRAM_BANK4 0x00000006U +#define FMC_NORSRAM_BANK1 (0x00000000U) +#define FMC_NORSRAM_BANK2 (0x00000002U) +#define FMC_NORSRAM_BANK3 (0x00000004U) +#define FMC_NORSRAM_BANK4 (0x00000006U) /** * @} */ @@ -345,8 +542,8 @@ typedef struct /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing * @{ */ -#define FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U -#define FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U +#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) /** * @} */ @@ -354,9 +551,9 @@ typedef struct /** @defgroup FMC_Memory_Type FMC Memory Type * @{ */ -#define FMC_MEMORY_TYPE_SRAM 0x00000000U -#define FMC_MEMORY_TYPE_PSRAM 0x00000004U -#define FMC_MEMORY_TYPE_NOR 0x00000008U +#define FMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FMC_MEMORY_TYPE_NOR (0x00000008U) /** * @} */ @@ -364,9 +561,9 @@ typedef struct /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width * @{ */ -#define FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U -#define FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U -#define FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) /** * @} */ @@ -374,8 +571,8 @@ typedef struct /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access * @{ */ -#define FMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U -#define FMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) /** * @} */ @@ -383,8 +580,8 @@ typedef struct /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode * @{ */ -#define FMC_BURST_ACCESS_MODE_DISABLE 0x00000000U -#define FMC_BURST_ACCESS_MODE_ENABLE 0x00000100U +#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) /** * @} */ @@ -392,19 +589,18 @@ typedef struct /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity * @{ */ -#define FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U -#define FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U +#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) /** * @} */ /** @defgroup FMC_Wrap_Mode FMC Wrap Mode + * @note This mode is not available for the STM32F446/469/479xx devices * @{ */ -/** @note This mode is not available for the STM32F446/469/479xx devices - */ -#define FMC_WRAP_MODE_DISABLE 0x00000000U -#define FMC_WRAP_MODE_ENABLE 0x00000400U +#define FMC_WRAP_MODE_DISABLE (0x00000000U) +#define FMC_WRAP_MODE_ENABLE (0x00000400U) /** * @} */ @@ -412,8 +608,8 @@ typedef struct /** @defgroup FMC_Wait_Timing FMC Wait Timing * @{ */ -#define FMC_WAIT_TIMING_BEFORE_WS 0x00000000U -#define FMC_WAIT_TIMING_DURING_WS 0x00000800U +#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) +#define FMC_WAIT_TIMING_DURING_WS (0x00000800U) /** * @} */ @@ -421,8 +617,8 @@ typedef struct /** @defgroup FMC_Write_Operation FMC Write Operation * @{ */ -#define FMC_WRITE_OPERATION_DISABLE 0x00000000U -#define FMC_WRITE_OPERATION_ENABLE 0x00001000U +#define FMC_WRITE_OPERATION_DISABLE (0x00000000U) +#define FMC_WRITE_OPERATION_ENABLE (0x00001000U) /** * @} */ @@ -430,8 +626,8 @@ typedef struct /** @defgroup FMC_Wait_Signal FMC Wait Signal * @{ */ -#define FMC_WAIT_SIGNAL_DISABLE 0x00000000U -#define FMC_WAIT_SIGNAL_ENABLE 0x00002000U +#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) /** * @} */ @@ -439,8 +635,8 @@ typedef struct /** @defgroup FMC_Extended_Mode FMC Extended Mode * @{ */ -#define FMC_EXTENDED_MODE_DISABLE 0x00000000U -#define FMC_EXTENDED_MODE_ENABLE 0x00004000U +#define FMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FMC_EXTENDED_MODE_ENABLE (0x00004000U) /** * @} */ @@ -448,8 +644,8 @@ typedef struct /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait * @{ */ -#define FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U -#define FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U +#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) /** * @} */ @@ -457,39 +653,42 @@ typedef struct /** @defgroup FMC_Page_Size FMC Page Size * @{ */ -#define FMC_PAGE_SIZE_NONE 0x00000000U -#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0) -#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1) -#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1)) -#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2) +#define FMC_PAGE_SIZE_NONE (0x00000000U) +#define FMC_PAGE_SIZE_128 FMC_BCR1_CPSIZE_0 +#define FMC_PAGE_SIZE_256 FMC_BCR1_CPSIZE_1 +#define FMC_PAGE_SIZE_512 (FMC_BCR1_CPSIZE_0\ + | FMC_BCR1_CPSIZE_1) +#define FMC_PAGE_SIZE_1024 FMC_BCR1_CPSIZE_2 /** * @} */ -/** @defgroup FMC_Write_FIFO FMC Write FIFO - * @note These values are available only for the STM32F446/469/479xx devices. +/** @defgroup FMC_Write_Burst FMC Write Burst * @{ */ -#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) -#define FMC_WRITE_FIFO_ENABLE 0x00000000U +#define FMC_WRITE_BURST_DISABLE (0x00000000U) +#define FMC_WRITE_BURST_ENABLE (0x00080000U) /** * @} */ -/** @defgroup FMC_Write_Burst FMC Write Burst +/** @defgroup FMC_Continous_Clock FMC Continuous Clock * @{ */ -#define FMC_WRITE_BURST_DISABLE 0x00000000U -#define FMC_WRITE_BURST_ENABLE 0x00080000U +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) /** * @} */ -/** @defgroup FMC_Continous_Clock FMC Continuous Clock +#if defined(FMC_BCR1_WFDIS) +/** @defgroup FMC_Write_FIFO FMC Write FIFO + * @note These values are available only for the STM32F446/469/479xx devices. * @{ */ -#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U -#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U +#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS +#define FMC_WRITE_FIFO_ENABLE (0x00000000U) +#endif /* FMC_BCR1_WFDIS */ /** * @} */ @@ -497,10 +696,10 @@ typedef struct /** @defgroup FMC_Access_Mode FMC Access Mode * @{ */ -#define FMC_ACCESS_MODE_A 0x00000000U -#define FMC_ACCESS_MODE_B 0x10000000U -#define FMC_ACCESS_MODE_C 0x20000000U -#define FMC_ACCESS_MODE_D 0x30000000U +#define FMC_ACCESS_MODE_A (0x00000000U) +#define FMC_ACCESS_MODE_B (0x10000000U) +#define FMC_ACCESS_MODE_C (0x20000000U) +#define FMC_ACCESS_MODE_D (0x30000000U) /** * @} */ @@ -508,6 +707,9 @@ typedef struct /** * @} */ +#endif /* FMC_Bank1 */ + +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller * @{ @@ -515,8 +717,10 @@ typedef struct /** @defgroup FMC_NAND_Bank FMC NAND Bank * @{ */ -#define FMC_NAND_BANK2 0x00000010U -#define FMC_NAND_BANK3 0x00000100U +#if defined(FMC_Bank2_3) +#define FMC_NAND_BANK2 (0x00000010U) +#endif +#define FMC_NAND_BANK3 (0x00000100U) /** * @} */ @@ -524,8 +728,8 @@ typedef struct /** @defgroup FMC_Wait_feature FMC Wait feature * @{ */ -#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U -#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) /** * @} */ @@ -533,8 +737,10 @@ typedef struct /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type * @{ */ -#define FMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U -#define FMC_PCR_MEMORY_TYPE_NAND 0x00000008U +#if defined(FMC_Bank4) +#define FMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) +#endif /* FMC_Bank4 */ +#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) /** * @} */ @@ -542,8 +748,8 @@ typedef struct /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width * @{ */ -#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U -#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) /** * @} */ @@ -551,8 +757,8 @@ typedef struct /** @defgroup FMC_ECC FMC ECC * @{ */ -#define FMC_NAND_ECC_DISABLE 0x00000000U -#define FMC_NAND_ECC_ENABLE 0x00000040U +#define FMC_NAND_ECC_DISABLE (0x00000000U) +#define FMC_NAND_ECC_ENABLE (0x00000040U) /** * @} */ @@ -560,12 +766,12 @@ typedef struct /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size * @{ */ -#define FMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U -#define FMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U -#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U -#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U -#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U -#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) +#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) +#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) +#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) +#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) +#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) /** * @} */ @@ -573,15 +779,17 @@ typedef struct /** * @} */ +#endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */ +#if defined(FMC_Bank5_6) /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller * @{ */ /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank * @{ */ -#define FMC_SDRAM_BANK1 0x00000000U -#define FMC_SDRAM_BANK2 0x00000001U +#define FMC_SDRAM_BANK1 (0x00000000U) +#define FMC_SDRAM_BANK2 (0x00000001U) /** * @} */ @@ -589,10 +797,10 @@ typedef struct /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number * @{ */ -#define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000U -#define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001U -#define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002U -#define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003U +#define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U) +#define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U) +#define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U) +#define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U) /** * @} */ @@ -600,9 +808,9 @@ typedef struct /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number * @{ */ -#define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000U -#define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004U -#define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008U +#define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U) +#define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U) +#define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U) /** * @} */ @@ -610,9 +818,9 @@ typedef struct /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width * @{ */ -#define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000U -#define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010U -#define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020U +#define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U) /** * @} */ @@ -620,8 +828,8 @@ typedef struct /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number * @{ */ -#define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000U -#define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040U +#define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U) +#define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U) /** * @} */ @@ -629,9 +837,9 @@ typedef struct /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency * @{ */ -#define FMC_SDRAM_CAS_LATENCY_1 0x00000080U -#define FMC_SDRAM_CAS_LATENCY_2 0x00000100U -#define FMC_SDRAM_CAS_LATENCY_3 0x00000180U +#define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U) +#define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U) +#define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U) /** * @} */ @@ -639,9 +847,8 @@ typedef struct /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection * @{ */ -#define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000U -#define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200U - +#define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U) +#define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U) /** * @} */ @@ -649,9 +856,9 @@ typedef struct /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period * @{ */ -#define FMC_SDRAM_CLOCK_DISABLE 0x00000000U -#define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800U -#define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00U +#define FMC_SDRAM_CLOCK_DISABLE (0x00000000U) +#define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U) +#define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U) /** * @} */ @@ -659,8 +866,8 @@ typedef struct /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst * @{ */ -#define FMC_SDRAM_RBURST_DISABLE 0x00000000U -#define FMC_SDRAM_RBURST_ENABLE 0x00001000U +#define FMC_SDRAM_RBURST_DISABLE (0x00000000U) +#define FMC_SDRAM_RBURST_ENABLE (0x00001000U) /** * @} */ @@ -668,9 +875,9 @@ typedef struct /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay * @{ */ -#define FMC_SDRAM_RPIPE_DELAY_0 0x00000000U -#define FMC_SDRAM_RPIPE_DELAY_1 0x00002000U -#define FMC_SDRAM_RPIPE_DELAY_2 0x00004000U +#define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U) +#define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U) +#define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U) /** * @} */ @@ -678,13 +885,13 @@ typedef struct /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode * @{ */ -#define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000U -#define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001U -#define FMC_SDRAM_CMD_PALL 0x00000002U -#define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003U -#define FMC_SDRAM_CMD_LOAD_MODE 0x00000004U -#define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005U -#define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006U +#define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U) +#define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U) +#define FMC_SDRAM_CMD_PALL (0x00000002U) +#define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U) +#define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U) +#define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U) +#define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U) /** * @} */ @@ -692,9 +899,9 @@ typedef struct /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target * @{ */ -#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 -#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 -#define FMC_SDRAM_CMD_TARGET_BANK1_2 0x00000018U +#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 +#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 +#define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U) /** * @} */ @@ -702,9 +909,9 @@ typedef struct /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status * @{ */ -#define FMC_SDRAM_NORMAL_MODE 0x00000000U -#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 -#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 +#define FMC_SDRAM_NORMAL_MODE (0x00000000U) +#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 +#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 /** * @} */ @@ -713,54 +920,41 @@ typedef struct * @} */ -/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition +#endif /* FMC_Bank5_6 */ + +/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition * @{ */ -#define FMC_IT_RISING_EDGE 0x00000008U -#define FMC_IT_LEVEL 0x00000010U -#define FMC_IT_FALLING_EDGE 0x00000020U -#define FMC_IT_REFRESH_ERROR 0x00004000U +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) +#define FMC_IT_RISING_EDGE (0x00000008U) +#define FMC_IT_LEVEL (0x00000010U) +#define FMC_IT_FALLING_EDGE (0x00000020U) +#endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */ +#if defined(FMC_Bank5_6) +#define FMC_IT_REFRESH_ERROR (0x00004000U) +#endif /* FMC_Bank5_6 */ /** * @} */ -/** @defgroup FMC_LL_Flag_definition FMC Flag definition +/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition * @{ */ -#define FMC_FLAG_RISING_EDGE 0x00000001U -#define FMC_FLAG_LEVEL 0x00000002U -#define FMC_FLAG_FALLING_EDGE 0x00000004U -#define FMC_FLAG_FEMPT 0x00000040U +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) +#define FMC_FLAG_RISING_EDGE (0x00000001U) +#define FMC_FLAG_LEVEL (0x00000002U) +#define FMC_FLAG_FALLING_EDGE (0x00000004U) +#define FMC_FLAG_FEMPT (0x00000040U) +#endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */ +#if defined(FMC_Bank5_6) #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE +#endif /* FMC_Bank5_6 */ /** * @} */ -/** @defgroup FMC_LL_Alias_definition FMC Alias definition - * @{ - */ -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - #define FMC_NAND_TypeDef FMC_Bank3_TypeDef -#else - #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef - #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef -#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ - #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef - #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef - #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef - - -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - #define FMC_NAND_DEVICE FMC_Bank3 -#else - #define FMC_NAND_DEVICE FMC_Bank2_3 - #define FMC_PCCARD_DEVICE FMC_Bank4 -#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ - #define FMC_NORSRAM_DEVICE FMC_Bank1 - #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E - #define FMC_SDRAM_DEVICE FMC_Bank5_6 /** * @} */ @@ -770,21 +964,23 @@ typedef struct */ /* Private macro -------------------------------------------------------------*/ -/** @defgroup FMC_LL_Private_Macros FMC Private Macros +/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros * @{ */ - +#if defined(FMC_Bank1) /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros - * @brief macros to handle NOR device enable/disable and read/write operations - * @{ - */ + * @brief macros to handle NOR device enable/disable and read/write operations + * @{ + */ + /** * @brief Enable the NORSRAM device access. * @param __INSTANCE__ FMC_NORSRAM Instance * @param __BANK__ FMC_NORSRAM Bank * @retval None */ -#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN) +#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + |= FMC_BCR1_MBKEN) /** * @brief Disable the NORSRAM device access. @@ -792,59 +988,64 @@ typedef struct * @param __BANK__ FMC_NORSRAM Bank * @retval None */ -#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN) +#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + &= ~FMC_BCR1_MBKEN) + /** * @} */ +#endif /* FMC_Bank1 */ +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros - * @brief macros to handle NAND device enable/disable - * @{ - */ -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** - * @brief Enable the NAND device access. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @retval None + * @brief macros to handle NAND device enable/disable + * @{ */ -#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) -/** - * @brief Disable the NAND device access. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @retval None - */ -#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN) -#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ /** * @brief Enable the NAND device access. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank + * @param __BANK__ FMC_NAND Bank * @retval None */ +#if defined(FMC_Bank2_3) +#if defined (FMC_PCR_PBKEN) +#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) +#else #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \ - ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN)) + ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN)) +#endif /* FMC_PCR_PBKEN */ +#else +#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) +#endif /* FMC_Bank2_3 */ /** * @brief Disable the NAND device access. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank + * @param __BANK__ FMC_NAND Bank * @retval None */ -#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \ - ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN)) +#if defined(FMC_Bank2_3) +#if defined (FMC_PCR_PBKEN) +#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) +#else +#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCR2_PBKEN): \ + CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCR3_PBKEN)) +#endif /* FMC_PCR_PBKEN */ +#else +#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) +#endif /* FMC_Bank2_3 */ -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ /** * @} */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#endif /* FMC_Bank3 || FMC_Bank2_3 */ + +#if defined(FMC_Bank4) /** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros - * @brief macros to handle SRAM read/write operations - * @{ - */ + * @brief macros to handle PCCARD read/write operations + * @{ + */ /** * @brief Enable the PCCARD device access. * @param __INSTANCE__ FMC_PCCARD Instance @@ -861,70 +1062,18 @@ typedef struct /** * @} */ -#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ - -/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros - * @brief macros to handle FMC flags and interrupts - * @{ - */ -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** - * @brief Enable the NAND device interrupt. - * @param __INSTANCE__ FMC_NAND instance - * @param __BANK__ FMC_NAND Bank - * @param __INTERRUPT__ FMC_NAND interrupt - * This parameter can be any combination of the following values: - * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. - * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. - * @retval None - */ -#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) -/** - * @brief Disable the NAND device interrupt. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @param __INTERRUPT__ FMC_NAND interrupt - * This parameter can be any combination of the following values: - * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. - * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. - * @retval None +#endif +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) +/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt + * @brief macros to handle NAND interrupts + * @{ */ -#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) -/** - * @brief Get flag status of the NAND device. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @param __FLAG__ FMC_NAND flag - * This parameter can be any combination of the following values: - * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) -/** - * @brief Clear flag status of the NAND device. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @param __FLAG__ FMC_NAND flag - * This parameter can be any combination of the following values: - * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. - * @retval None - */ -#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) -#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ /** * @brief Enable the NAND device interrupt. * @param __INSTANCE__ FMC_NAND instance - * @param __BANK__ FMC_NAND Bank + * @param __BANK__ FMC_NAND Bank * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. @@ -932,13 +1081,17 @@ typedef struct * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None */ +#if defined(FMC_Bank2_3) #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) + ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) +#else +#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) +#endif /* FMC_Bank2_3 */ /** * @brief Disable the NAND device interrupt. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank + * @param __BANK__ FMC_NAND Bank * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. @@ -946,14 +1099,18 @@ typedef struct * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None */ +#if defined(FMC_Bank2_3) #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) + ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) +#else +#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) +#endif /* FMC_Bank2_3 */ /** * @brief Get flag status of the NAND device. * @param __INSTANCE__ FMC_NAND Instance * @param __BANK__ FMC_NAND Bank - * @param __FLAG__ FMC_NAND flag + * @param __FLAG__ FMC_NAND flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. @@ -961,13 +1118,18 @@ typedef struct * @arg FMC_FLAG_FEMPT: FIFO empty flag. * @retval The state of FLAG (SET or RESET). */ +#if defined(FMC_Bank2_3) #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ - (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) + (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) +#else +#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) +#endif /* FMC_Bank2_3 */ + /** * @brief Clear flag status of the NAND device. * @param __INSTANCE__ FMC_NAND Instance * @param __BANK__ FMC_NAND Bank - * @param __FLAG__ FMC_NAND flag + * @param __FLAG__ FMC_NAND flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. @@ -975,11 +1137,24 @@ typedef struct * @arg FMC_FLAG_FEMPT: FIFO empty flag. * @retval None */ +#if defined(FMC_Bank2_3) #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ - ((__INSTANCE__)->SR3 &= ~(__FLAG__))) -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ + ((__INSTANCE__)->SR3 &= ~(__FLAG__))) +#else +#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) +#endif /* FMC_Bank2_3 */ + +/** + * @} + */ +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ + +#if defined(FMC_Bank4) +/** @defgroup FMC_LL_PCCARD_Interrupt FMC PCCARD Interrupt + * @brief macros to handle PCCARD interrupts + * @{ + */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /** * @brief Enable the PCCARD device interrupt. * @param __INSTANCE__ FMC_PCCARD instance @@ -1029,11 +1204,21 @@ typedef struct * @retval None */ #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) -#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ + +/** + * @} + */ +#endif + +#if defined(FMC_Bank5_6) +/** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt + * @brief macros to handle SDRAM interrupts + * @{ + */ /** * @brief Enable the SDRAM device interrupt. - * @param __INSTANCE__ FMC_SDRAM instance + * @param __INSTANCE__ FMC_SDRAM instance * @param __INTERRUPT__ FMC_SDRAM interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error @@ -1043,7 +1228,7 @@ typedef struct /** * @brief Disable the SDRAM device interrupt. - * @param __INSTANCE__ FMC_SDRAM instance + * @param __INSTANCE__ FMC_SDRAM instance * @param __INTERRUPT__ FMC_SDRAM interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error @@ -1054,7 +1239,7 @@ typedef struct /** * @brief Get flag status of the SDRAM device. * @param __INSTANCE__ FMC_SDRAM instance - * @param __FLAG__ FMC_SDRAM flag + * @param __FLAG__ FMC_SDRAM flag * This parameter can be any combination of the following values: * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. @@ -1066,207 +1251,17 @@ typedef struct /** * @brief Clear flag status of the SDRAM device. * @param __INSTANCE__ FMC_SDRAM instance - * @param __FLAG__ FMC_SDRAM flag + * @param __FLAG__ FMC_SDRAM flag * This parameter can be any combination of the following values: * @arg FMC_SDRAM_FLAG_REFRESH_ERROR * @retval None */ #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) + /** * @} */ - -/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros - * @{ - */ -#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \ - ((BANK) == FMC_NORSRAM_BANK2) || \ - ((BANK) == FMC_NORSRAM_BANK3) || \ - ((BANK) == FMC_NORSRAM_BANK4)) - -#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) - -#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) - -#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) - -#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ - ((__MODE__) == FMC_ACCESS_MODE_B) || \ - ((__MODE__) == FMC_ACCESS_MODE_C) || \ - ((__MODE__) == FMC_ACCESS_MODE_D)) - -#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \ - ((BANK) == FMC_NAND_BANK3)) - -#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ - ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE)) - -#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ - ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16)) - -#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \ - ((STATE) == FMC_NAND_ECC_ENABLE)) - -#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) - -#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U) - -#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U) - -#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U) - -#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U) - -#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U) - -#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U) - -#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) - -#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) - -#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) - -#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE) - -#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) - -#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) -#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \ - ((__MODE__) == FMC_WRAP_MODE_ENABLE)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - -#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) - -#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) - -#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) - -#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) - -#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) - -#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FMC_WRITE_BURST_ENABLE)) - -#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ - ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) - -#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) - -#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) - -#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) - -#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) - -#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) - -#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U)) - -#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \ - ((BANK) == FMC_SDRAM_BANK2)) - -#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ - ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ - ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ - ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11)) - -#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \ - ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \ - ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13)) - -#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ - ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ - ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32)) - -#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ - ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4)) - - -#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \ - ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \ - ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3)) - -#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \ - ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \ - ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3)) - -#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \ - ((RBURST) == FMC_SDRAM_RBURST_ENABLE)) - - -#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \ - ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \ - ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2)) - -#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U)) - -#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U)) - -#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U)) - -#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U)) - -#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U)) - -#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U)) - -#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U)) - -#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \ - ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \ - ((COMMAND) == FMC_SDRAM_CMD_PALL) || \ - ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ - ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \ - ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ - ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE)) - -#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \ - ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \ - ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2)) - -#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U)) - -#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U) - -#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U) - -#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE) - -#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ - ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) - -#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \ - ((SIZE) == FMC_PAGE_SIZE_128) || \ - ((SIZE) == FMC_PAGE_SIZE_256) || \ - ((SIZE) == FMC_PAGE_SIZE_512) || \ - ((SIZE) == FMC_PAGE_SIZE_1024)) - -#if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \ - ((FIFO) == FMC_WRITE_FIFO_ENABLE)) -#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ - +#endif /* FMC_Bank5_6 */ /** * @} */ @@ -1280,16 +1275,22 @@ typedef struct * @{ */ +#if defined(FMC_Bank1) /** @defgroup FMC_LL_NORSRAM NOR SRAM * @{ */ /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode); +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); /** * @} */ @@ -1305,7 +1306,9 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic /** * @} */ +#endif /* FMC_Bank1 */ +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) /** @defgroup FMC_LL_NAND NAND * @{ */ @@ -1313,8 +1316,10 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic * @{ */ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -1325,15 +1330,17 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); - +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout); /** * @} */ /** * @} */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ + +#if defined(FMC_Bank4) /** @defgroup FMC_LL_PCCARD PCCARD * @{ */ @@ -1341,9 +1348,12 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u * @{ */ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init); -HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device); /** * @} @@ -1351,8 +1361,9 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device); /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) /** @defgroup FMC_LL_SDRAM SDRAM * @{ */ @@ -1360,7 +1371,8 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device); * @{ */ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); -HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} @@ -1371,9 +1383,11 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); -HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, + uint32_t AutoRefreshNumber); uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} @@ -1381,12 +1395,12 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t B /** * @} */ +#endif /* FMC_Bank5_6 */ /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ @@ -1394,10 +1408,9 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t B /** * @} */ + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_LL_FMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_LL_FMC_H */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h index dd08b77c36..dcc001605e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1229,7 +1228,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) { return ((READ_BIT(FMPI2Cx->TIMEOUTR, (FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN)) == \ - (ClockTimeout)) ? 1UL : 0UL); + (ClockTimeout)) ? 1UL : 0UL); } /** @@ -2233,5 +2232,3 @@ void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct); #endif #endif /* STM32F4xx_LL_FMPI2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h index 15664d2447..8b0ceb75f9 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h @@ -6,23 +6,22 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_FSMC_H -#define __STM32F4xx_LL_FSMC_H +#ifndef STM32F4xx_LL_FSMC_H +#define STM32F4xx_LL_FSMC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -36,147 +35,266 @@ * @{ */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) -/* Private types -------------------------------------------------------------*/ -/** @defgroup FSMC_LL_Private_Types FSMC Private Types +/** @addtogroup FSMC_LL_Private_Macros * @{ */ +#if defined(FSMC_Bank1) + +#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ + ((__BANK__) == FSMC_NORSRAM_BANK2) || \ + ((__BANK__) == FSMC_NORSRAM_BANK3) || \ + ((__BANK__) == FSMC_NORSRAM_BANK4)) +#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) +#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) +#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) +#define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \ + ((__SIZE__) == FSMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FSMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FSMC_PAGE_SIZE_512) || \ + ((__SIZE__) == FSMC_PAGE_SIZE_1024)) +#if defined(FSMC_BCR1_WFDIS) +#define IS_FSMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FSMC_WRITE_FIFO_DISABLE) || \ + ((__FIFO__) == FSMC_WRITE_FIFO_ENABLE)) +#endif /* FSMC_BCR1_WFDIS */ +#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ + ((__MODE__) == FSMC_ACCESS_MODE_B) || \ + ((__MODE__) == FSMC_ACCESS_MODE_C) || \ + ((__MODE__) == FSMC_ACCESS_MODE_D)) +#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) +#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) +#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ + ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) +#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) +#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) +#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) +#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) +#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) +#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) +#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ + ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) +#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) +#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) +#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) +#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) +#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) +#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) + +#endif /* FSMC_Bank1 */ +#if defined(FSMC_Bank2_3) + +#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \ + ((__BANK__) == FSMC_NAND_BANK3)) +#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ + ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) +#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) +#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \ + ((__STATE__) == FSMC_NAND_ECC_ENABLE)) + +#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) +#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) +#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) +#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) + +#endif /* FSMC_Bank2_3 */ +#if defined(FSMC_Bank4) +#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) + +#endif /* FSMC_Bank4 */ /** - * @brief FSMC NORSRAM Configuration Structure definition + * @} + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types + * @{ + */ + +#if defined(FSMC_Bank1) +#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef +#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef +#endif /* FSMC_Bank1 */ +#if defined(FSMC_Bank2_3) +#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef +#endif /* FSMC_Bank2_3 */ +#if defined(FSMC_Bank4) +#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef +#endif /* FSMC_Bank4 */ + +#if defined(FSMC_Bank1) +#define FSMC_NORSRAM_DEVICE FSMC_Bank1 +#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E +#endif /* FSMC_Bank1 */ +#if defined(FSMC_Bank2_3) +#define FSMC_NAND_DEVICE FSMC_Bank2_3 +#endif /* FSMC_Bank2_3 */ +#if defined(FSMC_Bank4) +#define FSMC_PCCARD_DEVICE FSMC_Bank4 +#endif /* FSMC_Bank4 */ + +#if defined(FSMC_Bank1) +/** + * @brief FSMC NORSRAM Configuration Structure definition */ typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FSMC_Memory_Type */ + This parameter can be a value of @ref FSMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of @ref FSMC_Wrap_Mode - This mode is available only for the STM32F405/407/4015/417xx devices */ + This mode is available only for the STM32F405/407/4015/417xx devices */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ + This parameter can be a value of @ref FSMC_Wait_Timing */ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ + This parameter can be a value of @ref FSMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ + This parameter can be a value of @ref FSMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ + This parameter can be a value of @ref FSMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ + This parameter can be a value of @ref FSMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ + This parameter can be a value of @ref FSMC_Write_Burst */ - uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock - This mode is available only for the STM32F412Vx/Zx/Rx devices */ + uint32_t ContinuousClock; /*!< Enables or disables the FSMC clock output to external memory devices. + This parameter is only enabled through the FSMC_BCR1 register, + and don't care through FSMC_BCR2..4 registers. + This parameter can be a value of @ref FSMC_Continous_Clock + This mode is available only for the STM32F412Vx/Zx/Rx devices */ - uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO - This mode is available only for the STM32F412Vx/Vx devices */ + uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FSMC controller. + This parameter is only enabled through the FSMC_BCR1 register, + and don't care through FSMC_BCR2..4 registers. + This parameter can be a value of @ref FSMC_Write_FIFO + This mode is available only for the STM32F412Vx/Vx devices */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ -}FSMC_NORSRAM_InitTypeDef; + This parameter can be a value of @ref FSMC_Page_Size */ +} FSMC_NORSRAM_InitTypeDef; /** - * @brief FSMC NORSRAM Timing parameters structure definition + * @brief FSMC NORSRAM Timing parameters structure definition */ typedef struct { uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between Min_Data = 1 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between Min_Data = 1 and Max_Data = 255. @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed - NOR Flash memories. */ + NOR Flash memories. */ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is only used for multiplexed NOR Flash memories. */ + @note This parameter is only used for multiplexed NOR Flash memories. */ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of - HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. + HCLK cycles. This parameter can be a value between Min_Data = 2 and + Max_Data = 16. @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM - accesses. */ + accesses. */ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories - with synchronous burst mode enable */ + - It may assume a value between Min_Data = 2 and Max_Data = 17 + in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ - -}FSMC_NORSRAM_TimingTypeDef; + This parameter can be a value of @ref FSMC_Access_Mode */ +} FSMC_NORSRAM_TimingTypeDef; +#endif /* FSMC_Bank1 */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#if defined(FSMC_Bank2_3) /** - * @brief FSMC NAND Configuration Structure definition + * @brief FSMC NAND Configuration Structure definition */ typedef struct { uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ + This parameter can be a value of @ref FSMC_NAND_Bank */ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. - This parameter can be any value of @ref FSMC_Wait_feature */ + This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_NAND_Data_Width */ + This parameter can be any value of @ref FSMC_NAND_Data_Width */ uint32_t EccComputation; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ + This parameter can be any value of @ref FSMC_ECC */ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ + This parameter can be any value of @ref FSMC_ECC_Page_Size */ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. @@ -185,11 +303,12 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ +} FSMC_NAND_InitTypeDef; +#endif -}FSMC_NAND_InitTypeDef; - +#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) /** - * @brief FSMC NAND/PCCARD Timing parameters structure definition + * @brief FSMC NAND Timing parameters structure definition */ typedef struct { @@ -197,36 +316,37 @@ typedef struct the command assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address (and data for write access) after the command de-assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the data bus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - -}FSMC_NAND_PCC_TimingTypeDef; + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ +} FSMC_NAND_PCC_TimingTypeDef; +#endif /* FSMC_Bank2_3 */ +#if defined(FSMC_Bank4) /** - * @brief FSMC NAND Configuration Structure definition + * @brief FSMC PCCARD Configuration Structure definition */ typedef struct { uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. - This parameter can be any value of @ref FSMC_Wait_feature */ + This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. @@ -235,28 +355,30 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - }FSMC_PCCARD_InitTypeDef; +#endif /* FSMC_Bank4 */ + /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants * @{ */ +#if defined(FSMC_Bank1) /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller * @{ */ + /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank * @{ */ -#define FSMC_NORSRAM_BANK1 0x00000000U -#define FSMC_NORSRAM_BANK2 0x00000002U -#define FSMC_NORSRAM_BANK3 0x00000004U -#define FSMC_NORSRAM_BANK4 0x00000006U +#define FSMC_NORSRAM_BANK1 (0x00000000U) +#define FSMC_NORSRAM_BANK2 (0x00000002U) +#define FSMC_NORSRAM_BANK3 (0x00000004U) +#define FSMC_NORSRAM_BANK4 (0x00000006U) /** * @} */ @@ -264,8 +386,8 @@ typedef struct /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing * @{ */ -#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U -#define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U +#define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) /** * @} */ @@ -273,19 +395,19 @@ typedef struct /** @defgroup FSMC_Memory_Type FSMC Memory Type * @{ */ -#define FSMC_MEMORY_TYPE_SRAM 0x00000000U -#define FSMC_MEMORY_TYPE_PSRAM 0x00000004U -#define FSMC_MEMORY_TYPE_NOR 0x00000008U +#define FSMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FSMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FSMC_MEMORY_TYPE_NOR (0x00000008U) /** * @} */ -/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width +/** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width * @{ */ -#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U -#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U -#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U +#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) /** * @} */ @@ -293,8 +415,8 @@ typedef struct /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access * @{ */ -#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U -#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U +#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) /** * @} */ @@ -302,8 +424,8 @@ typedef struct /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode * @{ */ -#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U -#define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U +#define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) /** * @} */ @@ -311,8 +433,8 @@ typedef struct /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity * @{ */ -#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U -#define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U +#define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) /** * @} */ @@ -321,8 +443,8 @@ typedef struct * @note These values are available only for the STM32F405/415/407/417xx devices. * @{ */ -#define FSMC_WRAP_MODE_DISABLE 0x00000000U -#define FSMC_WRAP_MODE_ENABLE 0x00000400U +#define FSMC_WRAP_MODE_DISABLE (0x00000000U) +#define FSMC_WRAP_MODE_ENABLE (0x00000400U) /** * @} */ @@ -330,8 +452,8 @@ typedef struct /** @defgroup FSMC_Wait_Timing FSMC Wait Timing * @{ */ -#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U -#define FSMC_WAIT_TIMING_DURING_WS 0x00000800U +#define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) +#define FSMC_WAIT_TIMING_DURING_WS (0x00000800U) /** * @} */ @@ -339,8 +461,8 @@ typedef struct /** @defgroup FSMC_Write_Operation FSMC Write Operation * @{ */ -#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U -#define FSMC_WRITE_OPERATION_ENABLE 0x00001000U +#define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) +#define FSMC_WRITE_OPERATION_ENABLE (0x00001000U) /** * @} */ @@ -348,8 +470,8 @@ typedef struct /** @defgroup FSMC_Wait_Signal FSMC Wait Signal * @{ */ -#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U -#define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U +#define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U) /** * @} */ @@ -357,8 +479,8 @@ typedef struct /** @defgroup FSMC_Extended_Mode FSMC Extended Mode * @{ */ -#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U -#define FSMC_EXTENDED_MODE_ENABLE 0x00004000U +#define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FSMC_EXTENDED_MODE_ENABLE (0x00004000U) /** * @} */ @@ -366,8 +488,8 @@ typedef struct /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait * @{ */ -#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U -#define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U +#define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) /** * @} */ @@ -375,40 +497,43 @@ typedef struct /** @defgroup FSMC_Page_Size FSMC Page Size * @{ */ -#define FSMC_PAGE_SIZE_NONE 0x00000000U -#define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0) -#define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1) -#define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1)) -#define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2) +#define FSMC_PAGE_SIZE_NONE (0x00000000U) +#define FSMC_PAGE_SIZE_128 FSMC_BCR1_CPSIZE_0 +#define FSMC_PAGE_SIZE_256 FSMC_BCR1_CPSIZE_1 +#define FSMC_PAGE_SIZE_512 (FSMC_BCR1_CPSIZE_0\ + | FSMC_BCR1_CPSIZE_1) +#define FSMC_PAGE_SIZE_1024 FSMC_BCR1_CPSIZE_2 /** * @} */ -/** @defgroup FSMC_Write_FIFO FSMC Write FIFO - * @note These values are available only for the STM32F412Vx/Zx/Rx devices. +/** @defgroup FSMC_Write_Burst FSMC Write Burst * @{ */ -#define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS) -#define FSMC_WRITE_FIFO_ENABLE 0x00000000U +#define FSMC_WRITE_BURST_DISABLE (0x00000000U) +#define FSMC_WRITE_BURST_ENABLE (0x00080000U) /** * @} */ -/** @defgroup FSMC_Write_Burst FSMC Write Burst +/** @defgroup FSMC_Continous_Clock FSMC Continuous Clock + * @note These values are available only for the STM32F412Vx/Zx/Rx devices. * @{ */ -#define FSMC_WRITE_BURST_DISABLE 0x00000000U -#define FSMC_WRITE_BURST_ENABLE 0x00080000U +#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) +#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) /** * @} */ -/** @defgroup FSMC_Continous_Clock FSMC Continous Clock +#if defined(FSMC_BCR1_WFDIS) +/** @defgroup FSMC_Write_FIFO FSMC Write FIFO * @note These values are available only for the STM32F412Vx/Zx/Rx devices. * @{ */ -#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U -#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U +#define FSMC_WRITE_FIFO_DISABLE FSMC_BCR1_WFDIS +#define FSMC_WRITE_FIFO_ENABLE (0x00000000U) +#endif /* FSMC_BCR1_WFDIS */ /** * @} */ @@ -416,26 +541,31 @@ typedef struct /** @defgroup FSMC_Access_Mode FSMC Access Mode * @{ */ -#define FSMC_ACCESS_MODE_A 0x00000000U -#define FSMC_ACCESS_MODE_B 0x10000000U -#define FSMC_ACCESS_MODE_C 0x20000000U -#define FSMC_ACCESS_MODE_D 0x30000000U +#define FSMC_ACCESS_MODE_A (0x00000000U) +#define FSMC_ACCESS_MODE_B (0x10000000U) +#define FSMC_ACCESS_MODE_C (0x20000000U) +#define FSMC_ACCESS_MODE_D (0x30000000U) /** * @} */ + /** * @} */ +#endif /* FSMC_Bank1 */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller +#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) + +/** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller * @{ */ /** @defgroup FSMC_NAND_Bank FSMC NAND Bank * @{ */ -#define FSMC_NAND_BANK2 0x00000010U -#define FSMC_NAND_BANK3 0x00000100U +#if defined(FSMC_Bank2_3) +#define FSMC_NAND_BANK2 (0x00000010U) +#endif +#define FSMC_NAND_BANK3 (0x00000100U) /** * @} */ @@ -443,8 +573,8 @@ typedef struct /** @defgroup FSMC_Wait_feature FSMC Wait feature * @{ */ -#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U -#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U +#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) +#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) /** * @} */ @@ -452,8 +582,10 @@ typedef struct /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type * @{ */ -#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U -#define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U +#if defined(FSMC_Bank4) +#define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) +#endif /* FSMC_Bank4 */ +#define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U) /** * @} */ @@ -461,8 +593,8 @@ typedef struct /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width * @{ */ -#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U -#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U +#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) +#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) /** * @} */ @@ -470,8 +602,8 @@ typedef struct /** @defgroup FSMC_ECC FSMC ECC * @{ */ -#define FSMC_NAND_ECC_DISABLE 0x00000000U -#define FSMC_NAND_ECC_ENABLE 0x00000040U +#define FSMC_NAND_ECC_DISABLE (0x00000000U) +#define FSMC_NAND_ECC_ENABLE (0x00000040U) /** * @} */ @@ -479,38 +611,43 @@ typedef struct /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size * @{ */ -#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U -#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U -#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U -#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U -#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U -#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U +#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) +#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) +#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) +#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) +#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) +#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) /** * @} */ + /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#endif /* FSMC_Bank2_3 || FSMC_Bank4 */ + -/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition +/** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition * @{ */ -#define FSMC_IT_RISING_EDGE 0x00000008U -#define FSMC_IT_LEVEL 0x00000010U -#define FSMC_IT_FALLING_EDGE 0x00000020U -#define FSMC_IT_REFRESH_ERROR 0x00004000U +#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) +#define FSMC_IT_RISING_EDGE (0x00000008U) +#define FSMC_IT_LEVEL (0x00000010U) +#define FSMC_IT_FALLING_EDGE (0x00000020U) +#endif /* FSMC_Bank2_3 || FSMC_Bank4 */ /** * @} */ -/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition +/** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition * @{ */ -#define FSMC_FLAG_RISING_EDGE 0x00000001U -#define FSMC_FLAG_LEVEL 0x00000002U -#define FSMC_FLAG_FALLING_EDGE 0x00000004U -#define FSMC_FLAG_FEMPT 0x00000040U +#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) +#define FSMC_FLAG_RISING_EDGE (0x00000001U) +#define FSMC_FLAG_LEVEL (0x00000002U) +#define FSMC_FLAG_FALLING_EDGE (0x00000004U) +#define FSMC_FLAG_FEMPT (0x00000040U) +#endif /* FSMC_Bank2_3 || FSMC_Bank4 */ /** * @} */ @@ -518,19 +655,8 @@ typedef struct /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition * @{ */ -#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef -#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef -#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#define FSMC_NORSRAM_DEVICE FSMC_Bank1 -#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -#define FSMC_NAND_DEVICE FSMC_Bank2_3 -#define FSMC_PCCARD_DEVICE FSMC_Bank4 -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#define FMC_WRITE_OPERATION_DISABLE FSMC_WRITE_OPERATION_DISABLE +#define FMC_WRITE_OPERATION_ENABLE FSMC_WRITE_OPERATION_ENABLE #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16 @@ -620,89 +746,105 @@ typedef struct * @} */ +/** + * @} + */ + /* Private macro -------------------------------------------------------------*/ -/** @defgroup FSMC_LL_Private_Macros FSMC Private Macros +/** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros + * @{ + */ +#if defined(FSMC_Bank1) +/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros + * @brief macros to handle NOR device enable/disable and read/write operations * @{ */ -/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros - * @brief macros to handle NOR device enable/disable and read/write operations - * @{ - */ /** * @brief Enable the NORSRAM device access. * @param __INSTANCE__ FSMC_NORSRAM Instance * @param __BANK__ FSMC_NORSRAM Bank - * @retval none + * @retval None */ -#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN) +#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + |= FSMC_BCR1_MBKEN) /** * @brief Disable the NORSRAM device access. * @param __INSTANCE__ FSMC_NORSRAM Instance * @param __BANK__ FSMC_NORSRAM Bank - * @retval none + * @retval None */ -#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN) +#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + &= ~FSMC_BCR1_MBKEN) + /** * @} */ +#endif /* FSMC_Bank1 */ +#if defined(FSMC_Bank2_3) /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros - * @brief macros to handle NAND device enable/disable - * @{ - */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) + * @brief macros to handle NAND device enable/disable + * @{ + */ + /** * @brief Enable the NAND device access. * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank - * @retval none + * @param __BANK__ FSMC_NAND Bank + * @retval None */ #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \ - ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) + ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) /** * @brief Disable the NAND device access. * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank - * @retval none + * @param __BANK__ FSMC_NAND Bank + * @retval None */ -#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \ - ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN)) +#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN): \ + CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN)) + /** * @} */ +#endif /* FSMC_Bank2_3 */ -/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros - * @brief macros to handle SRAM read/write operations +#if defined(FSMC_Bank4) +/** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros + * @brief macros to handle PCCARD read/write operations * @{ */ /** * @brief Enable the PCCARD device access. * @param __INSTANCE__ FSMC_PCCARD Instance - * @retval none + * @retval None */ #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN) /** * @brief Disable the PCCARD device access. * @param __INSTANCE__ FSMC_PCCARD Instance - * @retval none + * @retval None */ #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN) /** * @} */ -/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros - * @brief macros to handle FSMC flags and interrupts - * @{ - */ +#endif +#if defined(FSMC_Bank2_3) +/** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt + * @brief macros to handle NAND interrupts + * @{ + */ + /** * @brief Enable the NAND device interrupt. - * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank + * @param __INSTANCE__ FSMC_NAND instance + * @param __BANK__ FSMC_NAND Bank * @param __INTERRUPT__ FSMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. @@ -711,12 +853,12 @@ typedef struct * @retval None */ #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) + ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) /** * @brief Disable the NAND device interrupt. - * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank * @param __INTERRUPT__ FSMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. @@ -725,7 +867,7 @@ typedef struct * @retval None */ #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) + ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) /** * @brief Get flag status of the NAND device. @@ -740,13 +882,13 @@ typedef struct * @retval The state of FLAG (SET or RESET). */ #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ - (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) + (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) /** * @brief Clear flag status of the NAND device. * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank - * @param __FLAG__ FSMC_NAND flag + * @param __BANK__ FSMC_NAND Bank + * @param __FLAG__ FSMC_NAND flag * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. @@ -755,11 +897,22 @@ typedef struct * @retval None */ #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ - ((__INSTANCE__)->SR3 &= ~(__FLAG__))) + ((__INSTANCE__)->SR3 &= ~(__FLAG__))) + +/** + * @} + */ +#endif /* FSMC_Bank2_3 */ + +#if defined(FSMC_Bank4) +/** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt + * @brief macros to handle PCCARD interrupts + * @{ + */ /** * @brief Enable the PCCARD device interrupt. - * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __INSTANCE__ FSMC_PCCARD instance * @param __INTERRUPT__ FSMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. @@ -771,7 +924,7 @@ typedef struct /** * @brief Disable the PCCARD device interrupt. - * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __INSTANCE__ FSMC_PCCARD instance * @param __INTERRUPT__ FSMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. @@ -783,151 +936,39 @@ typedef struct /** * @brief Get flag status of the PCCARD device. - * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __INSTANCE__ FSMC_PCCARD instance * @param __FLAG__ FSMC_PCCARD flag * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT: FIFO empty flag. + * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. * @retval The state of FLAG (SET or RESET). */ #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) /** * @brief Clear flag status of the PCCARD device. - * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __INSTANCE__ FSMC_PCCARD instance * @param __FLAG__ FSMC_PCCARD flag * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT: FIFO empty flag. + * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. * @retval None */ #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) + /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros - * @{ - */ -#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ - ((__BANK__) == FSMC_NORSRAM_BANK2) || \ - ((__BANK__) == FSMC_NORSRAM_BANK3) || \ - ((__BANK__) == FSMC_NORSRAM_BANK4)) - -#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) - -#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) - -#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) - -#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ - ((__MODE__) == FSMC_ACCESS_MODE_B) || \ - ((__MODE__) == FSMC_ACCESS_MODE_C) || \ - ((__MODE__) == FSMC_ACCESS_MODE_D)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \ - ((BANK) == FSMC_NAND_BANK3)) - -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ - ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) - -#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ - ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) - -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \ - ((STATE) == FSMC_NAND_ECC_ENABLE)) - -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) - -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) - -#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) - -#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE) - -#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE) - -#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) - -#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) - -#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ - ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) - -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) - -#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) - -#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) - -#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) - -#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) - -#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) - -#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) - -#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) - -#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) - -#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) - -#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) - -#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ - ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) - -#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U)) - -#define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \ - ((SIZE) == FSMC_PAGE_SIZE_128) || \ - ((SIZE) == FSMC_PAGE_SIZE_256) || \ - ((SIZE) == FSMC_PAGE_SIZE_512) || \ - ((SIZE) == FSMC_PAGE_SIZE_1024)) - -#define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \ - ((FIFO) == FSMC_WRITE_FIFO_ENABLE)) +#endif /** * @} */ + /** * @} */ @@ -937,17 +978,22 @@ typedef struct * @{ */ +#if defined(FSMC_Bank1) /** @defgroup FSMC_LL_NORSRAM NOR SRAM * @{ */ - /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); -HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode); +HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); /** * @} */ @@ -963,8 +1009,9 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Dev /** * @} */ +#endif /* FSMC_Bank1 */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#if defined(FSMC_Bank2_3) /** @defgroup FSMC_LL_NAND NAND * @{ */ @@ -972,8 +1019,10 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Dev * @{ */ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -984,14 +1033,17 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); +HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout); /** * @} */ /** * @} */ +#endif /* FSMC_Bank2_3 */ +#if defined(FSMC_Bank4) /** @defgroup FSMC_LL_PCCARD PCCARD * @{ */ @@ -999,9 +1051,12 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, * @{ */ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); /** * @} @@ -1009,12 +1064,12 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#endif /* FSMC_Bank4 */ + /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ /** * @} @@ -1028,6 +1083,4 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); } #endif -#endif /* __STM32F4xx_LL_FSMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_LL_FSMC_H */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h index 76e9170a0d..6bee7fd15e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -980,4 +979,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); #endif /* __STM32F4xx_LL_GPIO_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h index 5a46babfdc..babba6bf9d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1889,4 +1888,3 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); #endif /* __STM32F4xx_LL_I2C_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_iwdg.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_iwdg.h index 2f1b844a9c..4158363d1c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_iwdg.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_iwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -301,5 +300,3 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) #endif #endif /* STM32F4xx_LL_IWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h index a91bf920d0..9495e019f2 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -353,7 +352,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *const LPTIMx) { return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } @@ -399,7 +398,7 @@ __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t Upda * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD */ -__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *const LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); } @@ -414,7 +413,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) * @note autoreload value be strictly greater than the compare value. * @rmtoll ARR ARR LL_LPTIM_SetAutoReload * @param LPTIMx Low-Power Timer instance - * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF * @retval None */ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload) @@ -426,9 +425,9 @@ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t Auto * @brief Get actual auto reload value * @rmtoll ARR ARR LL_LPTIM_GetAutoReload * @param LPTIMx Low-Power Timer instance - * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *const LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); } @@ -470,7 +469,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval Counter value */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *const LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); } @@ -498,7 +497,7 @@ __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t Cou * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *const LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); } @@ -1377,5 +1376,3 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) #endif #endif /* STM32F4xx_LL_LPTIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h index 69d463e25f..ae415e9ed3 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -985,5 +983,3 @@ ErrorStatus LL_PWR_DeInit(void); #endif #endif /* __STM32F4xx_LL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h index 209e7790d2..59a4dbac99 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -7096,4 +7094,3 @@ uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); #endif /* __STM32F4xx_LL_RCC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rng.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rng.h index c142717b0c..151cb4a728 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rng.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rng.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -334,4 +333,3 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); #endif /* __STM32F4xx_LL_RNG_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rtc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rtc.h index c4f9422565..180cc15f14 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rtc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rtc.h @@ -6,20 +6,19 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_RTC_H -#define __STM32F4xx_LL_RTC_H +#ifndef STM32F4xx_LL_RTC_H +#define STM32F4xx_LL_RTC_H #ifdef __cplusplus extern "C" { @@ -46,7 +45,7 @@ extern "C" { */ /* Masks Definition */ #define RTC_INIT_MASK 0xFFFFFFFFU -#define RTC_RSF_MASK 0xFFFFFF5FU +#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF)) /* Write protection defines */ #define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU) @@ -168,7 +167,7 @@ typedef struct This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B. This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A - or @ref LL_RTC_ALMB_SetMask() for ALARM B + or @ref LL_RTC_ALMB_SetMask() for ALARM B. */ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay. @@ -205,8 +204,8 @@ typedef struct /** @defgroup RTC_LL_EC_FORMAT FORMAT * @{ */ -#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */ -#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */ +#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */ /** * @} */ @@ -236,8 +235,9 @@ typedef struct * @{ */ #define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF -#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F +#if defined(RTC_TAMPER2_SUPPORT) #define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F +#endif /* RTC_TAMPER2_SUPPORT */ #define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F #define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF #define LL_RTC_ISR_TSF RTC_ISR_TSF @@ -330,16 +330,6 @@ typedef struct * @} */ -/** @defgroup RTC_LL_EC_PIN PIN - * @{ - */ -#define LL_RTC_PIN_PC13 RTC_TAFCR_PC13MODE /*!< PC13 is forced to push-pull output if all RTC alternate functions are disabled */ -#define LL_RTC_PIN_PC14 RTC_TAFCR_PC14MODE /*!< PC14 is forced to push-pull output if LSE is disabled */ -#define LL_RTC_PIN_PC15 RTC_TAFCR_PC15MODE /*!< PC15 is forced to push-pull output if LSE is disabled */ -/** - * @} - */ - /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN * @{ */ @@ -392,11 +382,11 @@ typedef struct /** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK * @{ */ -#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/ +#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B */ #define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */ -#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */ -#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */ -#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */ #define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */ /** * @} @@ -440,29 +430,6 @@ typedef struct * @} */ -/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK - * @{ - */ -#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAFCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ -#if defined(RTC_TAMPER2_SUPPORT) -#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAFCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ -#endif /* RTC_TAMPER2_SUPPORT */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE - * @{ - */ -#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAFCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ -#if defined(RTC_TAMPER2_SUPPORT) -#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAFCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */ -#endif /* RTC_TAMPER2_SUPPORT */ -/** - * @} - */ - -#if defined(RTC_TAFCR_TAMPPRCH) /** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION * @{ */ @@ -473,9 +440,7 @@ typedef struct /** * @} */ -#endif /* RTC_TAFCR_TAMPPRCH */ -#if defined(RTC_TAFCR_TAMPFLT) /** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER * @{ */ @@ -486,9 +451,7 @@ typedef struct /** * @} */ -#endif /* RTC_TAFCR_TAMPFLT */ -#if defined(RTC_TAFCR_TAMPFREQ) /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER * @{ */ @@ -503,14 +466,13 @@ typedef struct /** * @} */ -#endif /* RTC_TAFCR_TAMPFREQ */ /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL * @{ */ -#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ #if defined(RTC_TAMPER2_SUPPORT) -#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ #endif /* RTC_TAMPER2_SUPPORT */ /** * @} @@ -537,7 +499,6 @@ typedef struct #define LL_RTC_BKP_DR2 0x00000002U #define LL_RTC_BKP_DR3 0x00000003U #define LL_RTC_BKP_DR4 0x00000004U -#if RTC_BKP_NUMBER > 5 #define LL_RTC_BKP_DR5 0x00000005U #define LL_RTC_BKP_DR6 0x00000006U #define LL_RTC_BKP_DR7 0x00000007U @@ -549,14 +510,10 @@ typedef struct #define LL_RTC_BKP_DR13 0x0000000DU #define LL_RTC_BKP_DR14 0x0000000EU #define LL_RTC_BKP_DR15 0x0000000FU -#endif /* RTC_BKP_NUMBER > 5 */ - -#if RTC_BKP_NUMBER > 16 #define LL_RTC_BKP_DR16 0x00000010U #define LL_RTC_BKP_DR17 0x00000011U #define LL_RTC_BKP_DR18 0x00000012U #define LL_RTC_BKP_DR19 0x00000013U -#endif /* RTC_BKP_NUMBER > 16 */ /** * @} */ @@ -605,7 +562,7 @@ typedef struct #define LL_RTC_TimeStampPin_Default 0x00000000U /*!< Use RTC_AF1 as TIMESTAMP */ #if defined(RTC_AF2_SUPPORT) #define LL_RTC_TimeStampPin_Pos1 RTC_TAFCR_TSINSEL /*!< Use RTC_AF2 as TIMESTAMP */ -#endif +#endif /* RTC_AF2_SUPPORT */ /** * @} */ @@ -616,7 +573,7 @@ typedef struct #define LL_RTC_TamperPin_Default 0x00000000U /*!< Use RTC_AF1 as TAMPER1 */ #if defined(RTC_AF2_SUPPORT) #define LL_RTC_TamperPin_Pos1 RTC_TAFCR_TAMP1INSEL /*!< Use RTC_AF2 as TAMPER1 */ -#endif +#endif /* RTC_AF2_SUPPORT */ /** * @} */ @@ -837,8 +794,6 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) /** * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) * @note Used only when RTC_ALARM is mapped on PC13 - * @note If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the - * PC13 output data * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_SetAlarmOutputType * @param RTCx RTC Instance * @param Output This parameter can be one of the following values: @@ -854,8 +809,6 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Outpu /** * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output) * @note used only when RTC_ALARM is mapped on PC13 - * @note If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the - * PC13 output data * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_GetAlarmOutputType * @param RTCx RTC Instance * @retval Returned value can be one of the following values: @@ -867,76 +820,6 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE)); } -/** - * @brief Enable push-pull output on PC13, PC14 and/or PC15 - * @note PC13 forced to push-pull output if all RTC alternate functions are disabled - * @note PC14 and PC15 forced to push-pull output if LSE is disabled - * @rmtoll TAFCR PC13MODE LL_RTC_EnablePushPullMode\n - * @rmtoll TAFCR PC14MODE LL_RTC_EnablePushPullMode\n - * @rmtoll TAFCR PC15MODE LL_RTC_EnablePushPullMode - * @param RTCx RTC Instance - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_PIN_PC13 - * @arg @ref LL_RTC_PIN_PC14 - * @arg @ref LL_RTC_PIN_PC15 - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnablePushPullMode(RTC_TypeDef *RTCx, uint32_t PinMask) -{ - SET_BIT(RTCx->TAFCR, PinMask); -} - -/** - * @brief Disable push-pull output on PC13, PC14 and/or PC15 - * @note PC13, PC14 and/or PC15 are controlled by the GPIO configuration registers. - * Consequently PC13, PC14 and/or PC15 are floating in Standby mode. - * @rmtoll TAFCR PC13MODE LL_RTC_DisablePushPullMode\n - * TAFCR PC14MODE LL_RTC_DisablePushPullMode\n - * TAFCR PC15MODE LL_RTC_DisablePushPullMode - * @param RTCx RTC Instance - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_PIN_PC13 - * @arg @ref LL_RTC_PIN_PC14 - * @arg @ref LL_RTC_PIN_PC15 - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisablePushPullMode(RTC_TypeDef* RTCx, uint32_t PinMask) -{ - CLEAR_BIT(RTCx->TAFCR, PinMask); -} - -/** - * @brief Set PC14 and/or PC15 to high level. - * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode) - * @rmtoll TAFCR PC14VALUE LL_RTC_SetOutputPin\n - * TAFCR PC15VALUE LL_RTC_SetOutputPin - * @param RTCx RTC Instance - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_PIN_PC14 - * @arg @ref LL_RTC_PIN_PC15 - * @retval None - */ -__STATIC_INLINE void LL_RTC_SetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask) -{ - SET_BIT(RTCx->TAFCR, (PinMask >> 1)); -} - -/** - * @brief Set PC14 and/or PC15 to low level. - * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode) - * @rmtoll TAFCR PC14VALUE LL_RTC_ResetOutputPin\n - * TAFCR PC15VALUE LL_RTC_ResetOutputPin - * @param RTCx RTC Instance - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_PIN_PC14 - * @arg @ref LL_RTC_PIN_PC15 - * @retval None - */ -__STATIC_INLINE void LL_RTC_ResetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask) -{ - CLEAR_BIT(RTCx->TAFCR, (PinMask >> 1)); -} - /** * @brief Enable initialization mode * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) @@ -1023,7 +906,7 @@ __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)); + return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL); } /** @@ -1229,7 +1112,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU))>> RTC_TR_MNU_Pos); + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); } /** @@ -1290,12 +1173,12 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp = 0U; + uint32_t temp; - temp = Format12_24 | \ - (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ + temp = Format12_24 | \ + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \ - (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp); } @@ -1318,12 +1201,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, */ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); - return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ - (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ - ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos))); + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU))); } /** @@ -1358,7 +1236,7 @@ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)); + return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL); } /** @@ -1386,17 +1264,18 @@ __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) } /** - * @brief Get Sub second value in the synchronous prescaler counter. + * @brief Get subseconds value in the synchronous prescaler counter. * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar * SubSeconds value in second fraction ratio with time unit following * generic formula: - * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * ==> Seconds fraction ratio * time_unit = + * [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit * This conversion can be performed only if no shift operation is pending * (ie. SHFP=0) when PREDIV_S >= SS. * @rmtoll SSR SS LL_RTC_TIME_GetSubSecond * @param RTCx RTC Instance - * @retval Sub second value (number between 0 and 65535) + * @retval Subseconds value (number between 0 and 65535) */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) { @@ -1550,7 +1429,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) { - return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)))>> RTC_DR_MU_Pos); + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); } /** @@ -1620,12 +1499,12 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year) { - register uint32_t temp = 0U; + uint32_t temp; - temp = (WeekDay << RTC_DR_WDU_Pos) | \ - (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ + temp = ( WeekDay << RTC_DR_WDU_Pos) | \ + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \ - (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp); } @@ -1648,13 +1527,14 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin */ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; + uint32_t temp; temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); - return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ - (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \ - (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \ - ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos))); + + return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ + (((temp & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos) << RTC_OFFSET_DAY) | \ + (((temp & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos) << RTC_OFFSET_MONTH) | \ + ((temp & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos)); } /** @@ -1869,7 +1749,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) { - return (uint32_t)(( READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); } /** @@ -1948,11 +1828,12 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp = 0U; + uint32_t temp; - temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ + temp = Format12_24 | \ + (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ - (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp); } @@ -1976,7 +1857,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) } /** - * @brief Set Alarm A Mask the most-significant bits starting at this bit + * @brief Mask the most-significant bits of the subseconds field starting from + * the bit specified in parameter Mask * @note This register can be written only when ALRAE is reset in RTC_CR register, * or in initialization mode. * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask @@ -1990,7 +1872,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma } /** - * @brief Get Alarm A Mask the most-significant bits starting at this bit + * @brief Get Alarm A subseconds mask * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF @@ -2001,7 +1883,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) } /** - * @brief Set Alarm A Sub seconds value + * @brief Set Alarm A subseconds value * @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond * @param RTCx RTC Instance * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF @@ -2013,7 +1895,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec } /** - * @brief Get Alarm A Sub seconds value + * @brief Get Alarm A subseconds value * @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF @@ -2129,7 +2011,7 @@ __STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) { - MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU), + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU), (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos))); } @@ -2143,7 +2025,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) { - return (uint32_t)(( READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); } /** @@ -2291,10 +2173,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU)); - return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos)); + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); } /** @@ -2317,13 +2196,14 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp = 0U; + uint32_t temp; - temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ + temp = Format12_24 | \ + (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ - (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); - MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); } /** @@ -2345,7 +2225,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx) } /** - * @brief Set Alarm B Mask the most-significant bits starting at this bit + * @brief Mask the most-significant bits of the subseconds field starting from + * the bit specified in parameter Mask * @note This register can be written only when ALRBE is reset in RTC_CR register, * or in initialization mode. * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask @@ -2359,7 +2240,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma } /** - * @brief Get Alarm B Mask the most-significant bits starting at this bit + * @brief Get Alarm B subseconds mask * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF @@ -2370,7 +2251,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) } /** - * @brief Set Alarm B Sub seconds value + * @brief Set Alarm B subseconds value * @rmtoll ALRMBSSR SS LL_RTC_ALMB_SetSubSecond * @param RTCx RTC Instance * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF @@ -2382,7 +2263,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec } /** - * @brief Get Alarm B Sub seconds value + * @brief Get Alarm B subseconds value * @rmtoll ALRMBSSR SS LL_RTC_ALMB_GetSubSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF @@ -2599,7 +2480,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) } /** - * @brief Get time-stamp sub second value + * @brief Get time-stamp subseconds value * @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF @@ -2637,17 +2518,17 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) * @brief Set timestamp Pin * @rmtoll TAFCR TSINSEL LL_RTC_TS_SetPin * @param RTCx RTC Instance - * @param TSPin specifies the RTC TimeStamp Pin. + * @param TSPin specifies the RTC Timestamp Pin. * This parameter can be one of the following values: - * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC TimeStamp. - * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is selected as RTC TimeStamp. (*) + * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC Timestamp Pin. + * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is used as RTC Timestamp Pin. (*) * - * (*) value not defined in all devices. + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE void LL_RTC_TS_SetPin(RTC_TypeDef *RTCx, uint32_t TSPin) { - MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TSINSEL , TSPin); + MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TSINSEL, TSPin); } /** @@ -2655,16 +2536,15 @@ __STATIC_INLINE void LL_RTC_TS_SetPin(RTC_TypeDef *RTCx, uint32_t TSPin) * @rmtoll TAFCR TSINSEL LL_RTC_TS_GetPin * @param RTCx RTC Instance * @retval Returned value can be one of the following values: - * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC TimeStamp Pin. - * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is selected as RTC TimeStamp Pin. (*) + * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC Timestamp Pin. + * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is used as RTC Timestamp Pin. (*) * - * (*) value not defined in all devices. + * (*) value not applicable to all devices. * @retval None */ - __STATIC_INLINE uint32_t LL_RTC_TS_GetPin(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TSINSEL)); + return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TSINSEL)); } /** @@ -2684,7 +2564,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetPin(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TAMPER_1 * @arg @ref LL_RTC_TAMPER_2 (*) * - * (*) value not defined in all devices. + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2701,7 +2581,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) * @arg @ref LL_RTC_TAMPER_1 * @arg @ref LL_RTC_TAMPER_2 (*) * - * (*) value not defined in all devices. + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2709,7 +2589,6 @@ __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) CLEAR_BIT(RTCx->TAFCR, Tamper); } -#if defined(RTC_TAFCR_TAMPPUDIS) /** * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) * @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp @@ -2731,9 +2610,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS); } -#endif /* RTC_TAFCR_TAMPPUDIS */ -#if defined(RTC_TAFCR_TAMPPRCH) /** * @brief Set RTC_TAMPx precharge duration * @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge @@ -2764,9 +2641,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH)); } -#endif /* RTC_TAFCR_TAMPPRCH */ -#if defined(RTC_TAFCR_TAMPFLT) /** * @brief Set RTC_TAMPx filter count * @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_SetFilterCount @@ -2797,9 +2672,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFLT)); } -#endif /* RTC_TAFCR_TAMPFLT */ -#if defined(RTC_TAFCR_TAMPFREQ) /** * @brief Set Tamper sampling frequency * @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq @@ -2838,7 +2711,6 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ)); } -#endif /* RTC_TAFCR_TAMPFREQ */ /** * @brief Enable Active level for Tamper input @@ -2849,7 +2721,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 (*) * - * (*) value not defined in all devices. + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2866,7 +2738,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 (*) * - * (*) value not defined in all devices. + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2880,15 +2752,15 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_ * @param RTCx RTC Instance * @param TamperPin specifies the RTC Tamper Pin. * This parameter can be one of the following values: - * @arg LL_RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper. - * @arg LL_RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper. (*) + * @arg LL_RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper Pin. + * @arg LL_RTC_TamperPin_Pos1: RTC_AF2 is used as RTC Tamper Pin. (*) * - * (*) value not defined in all devices. + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_SetPin(RTC_TypeDef *RTCx, uint32_t TamperPin) { - MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMP1INSEL , TamperPin); + MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMP1INSEL, TamperPin); } /** @@ -2899,13 +2771,13 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetPin(RTC_TypeDef *RTCx, uint32_t TamperPin) * @arg LL_RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper Pin. * @arg LL_RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper Pin. (*) * - * (*) value not defined in all devices. + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPin(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMP1INSEL)); + return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMP1INSEL)); } /** @@ -2948,13 +2820,13 @@ __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)); + return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL); } /** * @brief Select Wakeup clock * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1 + * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1 * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock * @param RTCx RTC Instance * @param WakeupClock This parameter can be one of the following values: @@ -2990,7 +2862,7 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) /** * @brief Set Wakeup auto-reload value - * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR + * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR * @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload * @param RTCx RTC Instance * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF @@ -3050,13 +2922,13 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) { - register uint32_t tmp = 0U; + uint32_t temp; - tmp = (uint32_t)(&(RTCx->BKP0R)); - tmp += (BackupRegister * 4U); + temp = (uint32_t)(&(RTCx->BKP0R)); + temp += (BackupRegister * 4U); /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; + *(__IO uint32_t *)temp = (uint32_t)Data; } /** @@ -3088,13 +2960,13 @@ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe */ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) { - register uint32_t tmp = 0U; + uint32_t temp; - tmp = (uint32_t)(&(RTCx->BKP0R)); - tmp += (BackupRegister * 4U); + temp = (uint32_t)(&(RTCx->BKP0R)); + temp += (BackupRegister * 4U); /* Read the specified register */ - return (*(__IO uint32_t *)tmp); + return (*(__IO uint32_t *)temp); } /** @@ -3115,6 +2987,7 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back * @arg @ref LL_RTC_CALIB_OUTPUT_NONE * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * * @retval None */ __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) @@ -3131,6 +3004,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Freque * @arg @ref LL_RTC_CALIB_OUTPUT_NONE * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * */ __STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) { @@ -3178,7 +3052,7 @@ __STATIC_INLINE void LL_RTC_CAL_DisableCoarseDigital(RTC_TypeDef *RTCx) * @note This Calibration value should be between 0 and 126 when using positive sign with a 4-ppm step. * @retval None */ -__STATIC_INLINE void LL_RTC_CAL_ConfigCoarseDigital(RTC_TypeDef* RTCx, uint32_t Sign, uint32_t Value) +__STATIC_INLINE void LL_RTC_CAL_ConfigCoarseDigital(RTC_TypeDef *RTCx, uint32_t Sign, uint32_t Value) { MODIFY_REG(RTCx->CALIBR, RTC_CALIBR_DCS | RTC_CALIBR_DC, Sign | Value); } @@ -3202,7 +3076,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalValue(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_CALIB_SIGN_POSITIVE * @arg @ref LL_RTC_CALIB_SIGN_NEGATIVE */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalSign(RTC_TypeDef* RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalSign(RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALIBR, RTC_CALIBR_DCS)); } @@ -3210,7 +3084,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalSign(RTC_TypeDef* RTCx) /** * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR + * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR * @rmtoll CALR CALP LL_RTC_CAL_SetPulse * @param RTCx RTC Instance * @param Pulse This parameter can be one of the following values: @@ -3231,11 +3105,11 @@ __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) */ __STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)); + return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL); } /** - * @brief Set the calibration cycle period + * @brief Set smooth calibration cycle period * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR * @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n @@ -3253,7 +3127,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) } /** - * @brief Get the calibration cycle period + * @brief Get smooth calibration cycle period * @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n * CALR CALW16 LL_RTC_CAL_GetPeriod * @param RTCx RTC Instance @@ -3268,7 +3142,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) } /** - * @brief Set Calibration minus + * @brief Set smooth Calibration minus * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR * @rmtoll CALR CALM LL_RTC_CAL_SetMinus @@ -3282,7 +3156,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) } /** - * @brief Get Calibration minus + * @brief Get smooth Calibration minus * @rmtoll CALR CALM LL_RTC_CAL_GetMinus * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF @@ -3308,10 +3182,9 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL); } - #if defined(RTC_TAMPER2_SUPPORT) /** * @brief Get RTC_TAMP2 detection flag @@ -3321,7 +3194,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL); } #endif /* RTC_TAMPER2_SUPPORT */ @@ -3333,7 +3206,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL); } /** @@ -3344,7 +3217,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL); } /** @@ -3355,7 +3228,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL); } /** @@ -3366,7 +3239,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL); } /** @@ -3377,7 +3250,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL); } /** @@ -3388,10 +3261,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL); } - #if defined(RTC_TAMPER2_SUPPORT) /** * @brief Clear RTC_TAMP2 detection flag @@ -3479,7 +3351,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL); } /** @@ -3490,7 +3362,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL); } /** @@ -3512,7 +3384,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL); } /** @@ -3523,7 +3395,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL); } /** @@ -3534,7 +3406,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL); } /** @@ -3545,7 +3417,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL); } /** @@ -3556,7 +3428,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL); } /** @@ -3693,7 +3565,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)); + return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL); } /** @@ -3704,7 +3576,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)); + return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL); } /** @@ -3715,7 +3587,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)); + return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL); } /** @@ -3726,7 +3598,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)); + return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL); } /** @@ -3737,8 +3609,8 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->TAFCR, - RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE)); + return ((READ_BIT(RTCx->TAFCR, + RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE)) ? 1UL : 0UL); } /** @@ -3788,6 +3660,4 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); } #endif -#endif /* __STM32F4xx_LL_RTC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_LL_RTC_H */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h index a2218952ac..35c47e3c04 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1069,8 +1068,14 @@ uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); /* SDMMC Cards mode management functions */ HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode); +/** + * @} + */ /* SDMMC Commands management functions */ +/** @addtogroup HAL_SDMMC_LL_Group4 + * @{ + */ uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize); uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); @@ -1091,13 +1096,26 @@ uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth); uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx); uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx); uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); -uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA); +uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA); uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument); uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx); uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument); uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); +/** + * @} + */ +/* SDMMC Responses management functions *****************************************/ +/** @addtogroup HAL_SDMMC_LL_Group5 + * @{ + */ +uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout); +uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA); +uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx); /** * @} */ @@ -1121,5 +1139,3 @@ uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); #endif #endif /* STM32F4xx_LL_SDMMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h index d7ef2f6b1f..4f3b0306f1 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -2026,4 +2025,3 @@ ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_ #endif /* STM32F4xx_LL_SPI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h index cf34240885..19dfdb935c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h @@ -3,6 +3,18 @@ * @file stm32f4xx_ll_system.h * @author MCD Application Team * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + *Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -16,17 +28,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -767,7 +768,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void) /** * @brief Enables the DFSDM1 or DFSDM2 Delay clock * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN LL_SYSCFG_DFSDM_EnableDelayClock - * @param MCHDLY This paramater can be one of the following values + * @param MCHDLY This parameter can be one of the following values * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN * @retval None @@ -780,7 +781,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY) /** * @brief Disables the DFSDM1 or the DFSDM2 Delay clock * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN LL_SYSCFG_DFSDM1_DisableDelayClock - * @param MCHDLY This paramater can be one of the following values + * @param MCHDLY This parameter can be one of the following values * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN * @retval None @@ -1707,4 +1708,3 @@ __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void) #endif /* __STM32F4xx_LL_SYSTEM_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h index 3f83c98dd9..61148e4e44 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1045,7 +1044,7 @@ typedef struct * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ - (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) /** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. @@ -4092,4 +4091,3 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT #endif #endif /* __STM32F4xx_LL_TIM_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h index 86ee731cb3..e07c232680 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -2520,4 +2519,3 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS #endif /* __STM32F4xx_LL_USART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h index ca78e2a350..a7114cd02a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -23,7 +22,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -80,6 +79,7 @@ typedef enum HC_DATATGLERR } USB_OTG_HCStateTypeDef; + /** * @brief USB Instance Initialization Structure definition */ @@ -131,6 +131,9 @@ typedef struct uint8_t is_stall; /*!< Endpoint stall condition This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t is_iso_incomplete; /*!< Endpoint isoc condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t type; /*!< Endpoint type This parameter can be any value of @ref USB_LL_EP_Type */ @@ -152,6 +155,8 @@ typedef struct uint32_t xfer_len; /*!< Current transfer length */ + uint32_t xfer_size; /*!< requested transfer size */ + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ } USB_OTG_EPTypeDef; @@ -188,7 +193,7 @@ typedef struct uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - uint32_t XferSize; /*!< OTG Channel transfer size. */ + uint32_t XferSize; /*!< OTG Channel transfer size. */ uint32_t xfer_len; /*!< Current transfer length. */ @@ -318,10 +323,10 @@ typedef struct /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define EP_MPS_64 0U -#define EP_MPS_32 1U -#define EP_MPS_16 2U -#define EP_MPS_8 3U +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U /** * @} */ @@ -395,6 +400,12 @@ typedef struct #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U #define GRXSTS_PKTSTS_CH_HALTED 7U +#define TEST_J 1U +#define TEST_K 2U +#define TEST_SE0_NAK 3U +#define TEST_PACKET 4U +#define TEST_FORCE_EN 5U + #define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) @@ -415,6 +426,10 @@ typedef struct #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #define EP_ADDR_MSK 0xFU + +#ifndef USE_USB_DOUBLE_BUFFER +#define USE_USB_DOUBLE_BUFFER 1U +#endif /* USE_USB_DOUBLE_BUFFER */ /** * @} */ @@ -460,6 +475,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); @@ -514,9 +530,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /* STM32F4xx_LL_USB_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h index ac58e8640c..1ea1574729 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h @@ -18,13 +18,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -306,5 +305,3 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa #endif #endif /* __STM32F4xx_LL_UTILS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_wwdg.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_wwdg.h index f20b82dd80..5cbca0d8ff 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_wwdg.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_wwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -315,5 +314,3 @@ __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) #endif #endif /* STM32F4xx_LL_WWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/License.md b/system/Drivers/STM32F4xx_HAL_Driver/License.md index c681658bea..479c4f6826 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/License.md +++ b/system/Drivers/STM32F4xx_HAL_Driver/License.md @@ -1,4 +1,4 @@ -Copyright 2016 STMicroelectronics. +Copyright 2017 STMicroelectronics. All rights reserved. Redistribution and use in source and binary forms, with or without modification, @@ -24,4 +24,4 @@ ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/system/Drivers/STM32F4xx_HAL_Driver/README.md b/system/Drivers/STM32F4xx_HAL_Driver/README.md index 715117c3ed..c345d9be88 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/README.md +++ b/system/Drivers/STM32F4xx_HAL_Driver/README.md @@ -21,13 +21,6 @@ Two models of publication are proposed for the STM32Cube embedded software: This **stm32f4xx_hal_driver** MCU component repository is one element of the STM32CubeF4 MCU embedded software package, providing the **HAL-LL Drivers** part. -## License - -Copyright (c) 2016 STMicroelectronics. - -This software component is licensed by STMicroelectronics under BSD-3-Clause license. You may not use this file except in compliance with the License. -You may obtain a copy of the License [here](https://opensource.org/licenses/BSD-3-Clause). - ## Release note Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32f4xx_hal_driver/blob/master/Release_Notes.html). @@ -48,6 +41,7 @@ Tag v1.7.10| Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.2 (and following, if any, t Tag v1.7.11| Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.0 (and following, if any, till HAL tag) Tag v1.7.12| Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.1 (and following, if any, till HAL tag) Tag v1.7.13| Tag v2.6.7 | Tag v5.4.0_cm4 | Tag v1.26.2 (and following, if any, till HAL tag) +Tag v1.8.0 | Tag v2.6.8 | Tag v5.4.0_cm4 | Tag v1.27.0 (and following, if any, till HAL tag) The full **STM32CubeF4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF4). diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html index 4fafe1b5d5..fb2a057b7d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html @@ -1,162 +1,269 @@ - - - - Release Notes for STM32F4xx HAL Drivers - - -
-
-

 

-
- - 0in 5.4pt 0in 5.4pt" cellspacing="0" cellpadding="0" - border="0" width="900"> - - -
- + Release Notes for STM32F4xx HAL Drivers +
+
+

 

+
+
+ + +
+ - - + - -
-

Back to - Release page

+
+

Back to + Release page
-

+

+

Release - "Times New Roman";color:#3366FF">Release - - Notes for STM32F4xx HAL Drivers

-

Copyright 2017 - STMicroelectronics

-

+ Notes for STM32F4xx HAL Drivers +

Copyright 2017 + STMicroelectronics

+

-

 

- +

 

+
- -
- + +
+ - - - - + @@ -57605,16 +11427,13 @@

-

+

+

Update - New Roman"; color:white">Update + History

V1.8.0 + / 11-February-2022

+
+

Main - History -

+
  • General updates to fix known defects and implementation enhancements.
    • +
  • All source files: update disclaimer to add reference to the new license agreement.
    +
    • +
  • The following changes done on the HAL drivers require an update of the application code based on older HAL versions
    • Rework of HAL Ethernet driver to resolve problems and improve performance (compatibility break). 
    • A new HAL Ethernet driver has been redesigned with new APIs, to bypass limitations with previous HAL Ethernet driver version.
    • The new HAL Ethernet driver is the +recommended version. It is located as usual in +Drivers/STM32F4xx_HAL_Driver/Src and Drivers/STM32F4xx_HAL_Driver/Inc +folders. 
      • It can be enabled through switch HAL_ETH_MODULE_ENABLED in stm32f4xx_hal_conf.h
    • The legacy HAL Ethernet driver is also +present in the release in Drivers/STM32F4xx_HAL_Driver/Src/Legacy and +Drivers/STM32F4xx_HAL_Driver/Inc/Legacy folders for software +compatibility reasons.
      • Its usage is not recommended as +deprecated. It can however be enabled through switch +HAL_ETH_LEGACY_MODULE_ENABLED in stm32f4xx_hal_conf.h
    +

  • HAL + updates

    + +
      + + - "Times New - Roman";color:white">V1.7.13 +
    • HAL ETH update +
        +
      • Entire receive process reworked.
      • Resolve the problem of received data corruption.
      • Implement transmission in interrupt mode.
      • Handle one interrupt for multiple transmitted packets.
      • Implement APIs to handle PTP feature.
      • Implement APIs to handle Timestamp feature.
      • Add support of receive buffer unavailable.
        • +
      • Update HAL_ETH_IRQHandler() to handle receive buffer unavailable.
        • + +
      • +
    • HAL SMBUS update
      • +
        +
      • Update to fix issue of mismatched data +received by master in case of data size to be transmitted by the slave +is greater than the data size to be received by the master.
        • +
          +
        • Add flush on TX register.
          • +
        +
      +
    • HAL TIM update
      • +
        +
      • __LL_TIM_CALC_PSC() macro update to round up the evaluate value when the fractional part of the division is greater than 0.5.
        • +
      + +
    • HAL LPTIM update
      • +
        +
      • Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable()
        • +
      +
    • HAL UART update
      • +
        +
      • Add const qualifier for read only pointers.
        • +
      • Improve header description of UART_WaitOnFlagUntilTimeout() function.
        • +
      • Add a check on the UART parity before enabling the parity error interruption.
        • +
      • Fix typo in UART_IT_TXE bit description.
        +
        • + +
      +
    • HAL IRDA update
      • +
        +
      • Improve header description of IRDA_WaitOnFlagUntilTimeout() function.
        • +
      • Add a check on the IRDA parity before enabling the parity error interrupt.
        • +
      • Add const qualifier for read only pointers.
        • +
      +
    • HAL SMARTCARD update
      • +
        +
      • Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function
        • +
      • Add const qualifier for read only pointers.
        • +
      +
    • HAL NOR update
      • +
        +
      • Apply adequate commands according to the command set field value
        • +
      • command set 1 for Micron JS28F512P33
        • +
      • command set 2 for Micron M29W128G and Cypress S29GL128P
        • +
      • Add new command operations:
        • +
          +
        • NOR_CMD_READ_ARRAY
          • +
        • NOR_CMD_WORD_PROGRAM
          • +
        • NOR_CMD_BUFFERED_PROGRAM
          • +
        • NOR_CMD_CONFIRM
          • +
        • NOR_CMD_BLOCK_ERASE
          • +
        • NOR_CMD_BLOCK_UNLOCK
          • +
        • NOR_CMD_READ_STATUS_REG
          • +
        • NOR_CMD_CLEAR_STATUS_REG
          • +
        +
      • Update some APIs in order to be compliant for memories with different command set, the updated APIs are:
        • +
          +
        • HAL_NOR_Init()
          • +
        • HAL_NOR_Read_ID()
          • +
        • HAL_NOR_ReturnToReadMode()
          • +
        • HAL_NOR_Read()
          • +
        • HAL_NOR_Program()
          • +
        • HAL_NOR_ReadBuffer()
          • +
        • HAL_NOR_ProgramBuffer()
          • +
        • HAL_NOR_Erase_Block()
          • +
        • HAL_NOR_Erase_Chip()
          • +
        • HAL_NOR_GetStatus()
          • +
        +
      • Align HAL_NOR_Init() API with core of the function when write operation is disabled to avoid HardFault.
        • +
      +
    • HAL SDMMC update
      • +
        +
      • Take into account the voltage range in the CMD1 command.
        • +
      • Add new LL function to have correct response for MMC driver.
        • +
      • Update the driver to have all fields correctly initialized.
        • +
      • Add an internal variable to manage the power class and call it before to update speed of bus width.
        • +
      • Add new API to get the value of the Extended CSD register and populate the ExtCSD field of the MMC handle.
        • +
      • In HAL_MMC_InitCard(), call to SDIO_PowerState_ON() moved after +__HAL_MMC_ENABLE() to ensure MMC clock is enabled before the call to +HAL_Delay() from within SDIO_PowerState_ON().
        • +
      +
    • HAL DMA update
      • +
        +
      • Manage the case of an invalid value of CallbackID passed to the HAL_DMA_RegisterCallback() API.
        • +
      +
    • HAL LTDC update
      • +
        +
      • Update HAL_LTDC_DeInit() to fix MCU Hang up during LCD turn OFF.
        • +
      + +
    • HAL I2C update
      • +
        +
      • Update to fix issue detected due to low system frequency execution (HSI).
        • +
      • Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA
        • +
      • Update HAL I2C Master Receive IT process to safe manage data N= 2 and N= 3.
        • +
          +
        • Disable RxNE interrupt if nothing to do.
          • +
        +
      +
    • HAL USART update
      • +
        +
      • Improve header description of USART_WaitOnFlagUntilTimeout() function.
        • +
      • Add a check on the USART parity before enabling the parity error interrupt.
        • +
      • Add const qualifier for read only pointers.
        • +
      +
    • HAL/LL ADC update
      • +
        +
      • Update LL_ADC_IsActiveFlag_MST_EOCS() API to get the appropriate flag.
        • +
      • Better performance by removing multiple volatile reads or writes in interrupt handler.
        • +
      +
    • HAL FMPI2C update
      +
      • +
        +
      • Update to handle errors in polling mode.
        • +
          +
        • Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and correctly manage when error occurs.
          • +
        +
      +
    • HAL EXTI update
      • +
        +
      • Update HAL_EXTI_GetConfigLine() API to fix wrong calculation of GPIOSel value.
        • +
      +
    • HAL QSPI update
      • +
        +
      • Update HAL_QSPI_Abort() and  +HAL_QSPI_Abort_IT() APIs to check on QSPI BUSY flag status before +executing the abort procedure.
        • +
      + +
    • HAL/LL RTC cleanup
      • +
        +
      • Use bits definitions from CMSIS Device header file instead of hard-coded values.
        • +
      • Wrap comments to be 80-character long and correct typos.
        • +
      • Move constants RTC_IT_TAMP. from hal_rtc.h to hal_rtc_ex.h.
        • +
      • Gather all instructions related to exiting the "init" mode into new function RTC_ExitInitMode().
        • +
      • Add +new macro +assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, +sTamper->Trigger)) to check tamper filtering is disabled in case +tamper events are triggered on signal edges.
        • +
      • Rework functions HAL_RTCEx_SetTamper() and HAL_RTCEx_SetTamper_IT() to:
        • +
          +
        • Write in TAFCR register in one single access instead of two.
          • +
        • Avoid modifying user structure sTamper.
          • +
        +
      • Remove functions LL_RTC_EnablePushPullMode() and LL_RTC_DisablePushPullMode() as related to non-supported features.
        • +
      • Remove any reference to non-supported features (e.g., LL_RTC_ISR_TAMP3F).
        • +
      • Remove +useless conditional defines as corresponding features are supported by +all part-numbers (e.g., #if defined(RTC_TAFCR_TAMPPRCH)).
        • +
      +
    • HAL USB OTG update
      • +
        + + +
      • Fix USB_FlushRxFifo() and USB_FlushTxFifo() APIs by adding check on AHB master IDLE state before flushing the USB FIFO
        • +
      • Fix to avoid resetting host channel direction during channel halt
        • +
      • Fix to report correct received amount of data with USB DMA enabled
        • +
      • Fix to avoid compiler optimization on count variable used for USB HAL timeout loop check
        • +
      • Add missing registered callbacks check for HAL_HCD_HC_NotifyURBChange_Callback()
        • +
      • Add new API HAL_PCD_SetTestMode() APIs to handle USB device high speed Test modes
        • +
      • Setting SNAK for EPs not required during device reset
        • +
      • Update USB IRQ handler to enable EP OUT disable
        • +
      • Add support of USB IN/OUT Iso incomplete
        • +
      • Fix USB BCD data contact timeout
        +
        +
        • + +
      +
    +
    • + +

    V1.7.13 / 16-July-2021

    -

    Main +

    Main @@ -164,177 +271,106 @@ Changes

    -
      -
    • +

      • HAL updates

        -
          - - -
        • HAL EXTI +
            +
          • HAL EXTI update -
              -
            • Update +
              • Update HAL_EXTI_GetConfigLine() API to set default configuration value of Trigger and GPIOSel before checking each - corresponding registers.
                • -
              -
              • - - -
            • HAL GPIO + corresponding registers.
            +
            • +
          • HAL GPIO update -
              -
            • Update +
              • Update HAL_GPIO_Init() API to avoid the configuration of PUPDR register when - Analog mode is selected.
                • -
              -
              • - - -
            • HAL DMA + Analog mode is selected.
            +
            • +
          • HAL DMA update -
              -
            • Update +
              • Update HAL_DMA_IRQHandler() API to set the DMA state before unlocking access - to the DMA handle.
                • -
              -
              • - - -
            • HAL/LL ADC + to the DMA handle.
            +
            • +
          • HAL/LL ADC update -
              -
            • Update +
              • Update LL_ADC_DeInit() API to clear missing SQR3 - register.
                • -
              • Update + register.
              • Update LL_ADC_DMA_GetRegAddr() API to prevent unused argument compilation - warning.
                • -
              • Update HAL + warning.
              • Update HAL timeout mechanism to avoid false timeout detection in case of - preemption.
                • -
              -
              • - - -
            • HAL CAN + preemption.
            +
            • +
          • HAL CAN update -
              -
            • Update +
              • Update HAL_CAN_Init() API to be aligned with referance manual and to avoid - timeout error:
                • -
              -
              • - - -
            • HAL/LL + timeout error:
            +
            • +
          • HAL/LL RTC_BKP update -
              -
            • Update +
              • Update __HAL_RTC_�(__HANDLE__, �) macros to access registers through (__HANDLE__)->Instance pointer and avoid �unused variable� - warnings.
                • -
              • Correct month + warnings.
              • Correct month management in - IS_LL_RTC_MONTH() macro.
                • -
              -
              • - - -
            • HAL RNG + IS_LL_RTC_MONTH() macro.
            +
            • +
          • HAL RNG update -
              -
            • Update timeout +
              • Update timeout mechanism to avoid false timeout detection in - case of preemption.
                • -
              -
              • - - -
            • HAL QSPI + case of preemption.
            +
            • +
          • HAL QSPI update -
              -
            • ES0305 +
              • ES0305 workaround disabled for - STM32412xx devices.
                • -
              -
              • - - -
            • HAL I2C + STM32412xx devices.
            +
            • +
          • HAL I2C update -
              -
            • Update +
              • Update HAL_I2C_Mem_Write_DMA() and HAL_I2C_Mem_Read_DMA() APIs to initialize Devaddress, Memaddress and EventCount - parameters.
                • -
              • Update to + parameters.
              • Update to prevent several calls of Start bit: -
                  -
                • Update +
                  • Update I2C_MemoryTransmit_TXE_BTF() API to increment - EventCount.
                    • -
                  -
                  • -
                • Update to + EventCount.
                +
              • Update to avoid I2C interrupt in endless loop: -
                  -
                • Update +
                  • Update HAL_I2C_Master_Transmit_IT(), HAL_I2C_Master_Receive_IT(), @@ -345,226 +381,107 @@ APIs to unlock the I2C peripheral before generating - the start.
                    • -
                  -
                  • -
                • Update to use + the start.
                +
              • Update to use the right macro to clear I2C ADDR flag inside I2C_Slave_ADDR() API as it�s indicated in the - reference manual.
                • -
              • Update + reference manual.
              • Update I2C_IsAcknowledgeFailed() API to avoid I2C in busy state if NACK received after transmitting - register address.
                • -
              • Update + register address.
              • Update HAL_I2C_EV_IRQHandler() and I2C_MasterTransmit_BTF() APIs to correctly manage memory transfers: -
                  -
                • Add check +
                  • Add check on memory mode before calling callbacks - procedures.
                    • -
                  -
                  • -
                -
                • - - -
              • LL USART + procedures.
              +
            +
            • +
          • LL USART update -
              -
            • Handling of +
              • Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART - and LL LPUART)
                • -
              -
              • - - -
            • HAL SMBUS + and LL LPUART)
            +
            • +
          • HAL SMBUS update -
              -
            • Updated +
              • Updated HAL_SMBUS_ER_IRQHandler() API to return the correct error code �SMBUS_FLAG_PECERR� in case of packet error - occurs.
                • -
              -
              • - - -
            • HAL/LL SPI + occurs.
            +
            • +
          • HAL/LL SPI update -
              -
            • Updated to fix - MISRA-C 2012 Rule-13.2.
              • -
            • Update +
              • Updated to fix + MISRA-C 2012 Rule-13.2.
              • Update LL_SPI_TransmitData8() API to avoid casting the - result to 8 bits.
                • -
              -
              • - - -
            • HAL UART + result to 8 bits.
            +
            • +
          • HAL UART update -
              -
            • Fix wrong +
              • Fix wrong comment related to RX pin configuration within - the description section
                • -
              • Correction on + the description section
              • Correction on UART ReceptionType management in case of ReceptionToIdle API are called from RxEvent - callback
                • -
              • Handling of + callback
              • Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART) -
                  -
                • Update CAN +
                  • Update CAN Initialization sequence to set "request initialization" bit before exit from - sleep mode.
                    • -
                  -
                  • -
                -
                • - - -
              • HAL USB + sleep mode.
              +
            +
            • +
          • HAL USB update -
              - -
            • HAL PCD: add +
              • HAL PCD: add fix transfer complete for IN Interrupt transaction in single - buffer mode
                • - -
              • Race condition + buffer mode
              • Race condition in USB PCD control - endpoint receive ISR.
                • -
              -
              • -
            -
            • -
          -

          V1.7.12 - / 26-March-2021

          -

          Main + endpoint receive ISR.

        +
      +

    V1.7.12 + / 26-March-2021

    +

    Main Changes

    -
      -
    • HAL
      • +
        +
      • HAL
          • -
        • HAL/LL - USART update
          • +
        • HAL/LL + USART update
            • -
          • Fix typo in +
          • Fix typo in USART_Receive_IT() and USART_TransmitReceive_IT() APIs to avoid possible @@ -574,70 +491,26 @@
      -

      V1.7.11 - / 12-February-2021

      -

      Main +

      V1.7.11 + / 12-February-2021

      +

      Main Changes

      -
        -
      • General +
          +
        • General updates to fix known defects and - enhancements implementation
          • -
        • implementation
          • +
        • Added - "Times New Roman"">Added - - new HAL + new HAL @@ -648,705 +521,103 @@ to support FMPSMBUS fast Mode Plus.
          • -
        • Removed +
        • Removed �register� keyword to be compliant with new C++ rules:
            • -
          • The register +
          • The register storage class specifier was deprecated in C++11 and removed in C++17.
          -
        • HAL
          • +
        • HAL
            • -
          • HAL update
            • -
          • General +
          • HAL update
            • +
          • General updates to fix known defects and enhancements implementation.
            • -
          • Added new +
          • Added new defines for ARM compiler V6:
              • -
            • __weak
              • -
            • __packed
              • -
            • __NOINLINE
              • +
            • __weak
              • +
            • __packed
              • +
            • __NOINLINE
            -
          • Updated HAL TimeBase - TIM, RTC alarm and RTC WakeUp +
          • Updated HAL TimeBase + TIM, RTC alarm and RTC WakeUp templates for more robustness
              • -
            • Updated Hal_Init_Tick() - API to propoerty +
            • Updated Hal_Init_Tick() + API to propoerty store the priority when using the non-default time base.
            -
          • Updated +
          • Updated PPP_MODULE_ENABLED for FMPSMBUS.
            • -
          • HAL/LL ADC update
            • +
          • HAL/LL ADC update
              • -
            • Updated to +
            • Updated to add include of the LL ADC driver.
              • -
            • Updated the +
            • Updated the following APIs to set status HAL_ADC_STATE_ERROR_INTERNAL and error code HAL_ADC_ERROR_INTERNAL when error occurs:
                • -
              • HAL_ADC_Start()
                • -
              • HAL_ADC_Start_IT()
                • -
              • HAL_ADC_Start_DMA()
                • -
              • HAL_ADCEx_InjectedStart()
                • -
              • HAL_ADCEx_InjectedStart_IT()
                • -
              • HAL_ADCEx_MultiModeStart_DMA()
                • -
              -
            • Updated HAL_ADC_Stop_DMA() - API to check if DMA state is - Busy before calling HAL_DMA_Abort() +
            • HAL_ADC_Start()
              • +
            • HAL_ADC_Start_IT()
              • +
            • HAL_ADC_Start_DMA()
              • +
            • HAL_ADCEx_InjectedStart()
              • +
            • HAL_ADCEx_InjectedStart_IT()
              • +
            • HAL_ADCEx_MultiModeStart_DMA()
              • +
            +
          • Updated HAL_ADC_Stop_DMA() + API to check if DMA state is + Busy before calling HAL_DMA_Abort() API to avoid DMA internal error.
            • -
          • Updated +
          • Updated IS_ADC_CHANNEL to support temperature sensor for:
              • -
            • STM32F411xE
              • -
            • STM32F413xx
              • -
            • STM32F423xx
              • +
            • STM32F411xE
              • +
            • STM32F413xx
              • +
            • STM32F423xx
            -
          • Fixed wrong +
          • Fixed wrong defined values for:
              • -
            • LL_ADC_MULTI_REG_DMA_LIMIT_3
              • -
            • LL_ADC_MULTI_REG_DMA_UNLMT_3
              • +
            • LL_ADC_MULTI_REG_DMA_LIMIT_3
              • +
            • LL_ADC_MULTI_REG_DMA_UNLMT_3
            -
          • Added - __LL_ADC_CALC_VREFANALOG_VOLTAGE() +
          • Added + __LL_ADC_CALC_VREFANALOG_VOLTAGE() macro to evaluate analog reference voltage.
            • -
          • Removed - __LL_ADC_CALC_TEMPERATURE() +
          • Removed + __LL_ADC_CALC_TEMPERATURE() macro for STM32F4x9 devices as the TS_CAL2 is not available.
          -
        • HAL/LL DAC update
          • +
        • HAL/LL DAC update
            • -
          • Added restruction +
          • Added restruction on DAC Channel 2 defines and - parametres.
            • -
          • HAL_DAC_MSPINIT_CB_ID + parametres.
            • +
          • HAL_DAC_MSPINIT_CB_ID @@ -1355,56248 +626,10799 @@ used instead of HAL_DAC_MSP_INIT_CB_ID and HAL_DAC_MSP_DEINIT_CB_ID.
            • -
          • Updated to +
          • Updated to support dual mode:
              • -
            • Added two - new APIs:
              • -
                -
              • HAL_DACEx_DualStart()
                • -
              • HAL_DACEx_DualStop()
                • -
              -
            -
          • Added - position bit definition to - be used instead of - __DAC_MASK_SHIFT macro
            • -
              -
            • __DAC_MASK_SHIFT - - - - macro has been removed.
              • -
            -
          • Updated HAL_DAC_Start_DMA() - API to return HAL_ERROR when - error occurs.
            • -
          • Updated HAL_DAC_Stop_DMA() - API to not return HAL_ERROR - when DAC is already - disabled.
            • -
          -
        • HAL CEC update
          • -
            -
          • Updated HAL_CEC_IRQHandler() - API to avoid appending an - extra byte to the end of a - message.
            • -
          -
        • HAL/LL GPIO update
          • -
            -
          • Updated - IS_GPIO_AF() to - add missing values for - STM32F401xC and STM32F401xE - devices:
            • -
              -
            • GPIO_AF3_TIM9
              • -
            • GPIO_AF3_TIM10
              • -
            • GPIO_AF3_TIM11
              • -
            -
          • Updated - LL/HAL GPIO_TogglePin() - APIs to allow multi Pin�s - toggling.
            • -
          • Updated HAL_GPIO_Init() - API to avoid the - configuration of PUPDR - register when Analog mode is - selected.
            • -
          -
        • HAL/LL RCC update
          • -
            -
          • Updated HAL_RCC_OscConfig() - API to add missing checks - and to don�t return - HAL_ERROR if request repeats - the current PLL - configuration.
            • -
          • Updated - IS_RCC_PLLN_VALUE(VALUE) - macro in case of STM32F411xE - device in order to - be aligned with reference - manual.
            • -
          -
        • HAL SD update
          • -
            -
          • Update - function SD_FindSCR() - to resolve issue of FIFO - blocking when reading.
            • -
          • Update - read/write functions in DMA - mode in - - - - order to - force the DMA direction, - updated functions:
            • -
              -
            • HAL_SD_ReadBlocks_DMA()
              • -
            • HAL_SD_WriteBlocks_DMA()
              • -
            -
          • Add the - block size settings in the - initialization functions and - remove it from read/write - transactions to avoid - repeated and inefficient - reconfiguration, updated - functions:
            • -
              -
            • HAL_SD_InitCard()
              • -
            • HAL_SD_GetCardStatus()
              • -
            • HAL_SD_ConfigWideBusOperation() 
              • -
            • HAL_SD_ReadBlocks()
              • -
            • HAL_SD_WriteBlocks()
              • -
            • HAL_SD_ReadBlocks_IT()
              • -
            • HAL_SD_WriteBlocks_IT()
              • -
            • HAL_SD_ReadBlocks_DMA()
              • -
            • HAL_SD_WriteBlocks_DMA()
              • -
            -
          -
        • HAL MMC update
          • -
            -
          • Add the - block size settings in the - initialization function and - remove it from read/write - transactions to avoid - repeated and inefficient - reconfiguration, updated - functions:
            • -
              -
            • HAL_MMC_InitCard()
              • -
            • HAL_MMC_ReadBlocks()
              • -
            • HAL_MMC_WriteBlocks()
              • -
            • HAL_MMC_ReadBlocks_IT()
              • -
            • HAL_MMC_WriteBlocks_IT()
              • -
            • HAL_MMC_ReadBlocks_DMA()
              • -
            • HAL_MMC_WriteBlocks_DMA()
              • -
            -
          • Update - read/write functions in DMA - mode in - - - - order to - force the DMA direction, - updated functions:
            • -
              -
            • HAL_MMC_ReadBlocks_DMA()
              • -
            • HAL_MMC_WriteBlocks_DMA()
              • -
            -
          • Deploy new - functions MMC_ReadExtCSD() - and SDMMC_CmdSendEXTCSD - () that read and check the - sectors number of the - device in order to resolve - the issue of wrongly reading - big memory size.
            • -
          -
        • HAL NAND - update
          • -
            -
          • Update - functions - HAL_NAND_Read_SpareArea_16b() - and - HAL_NAND_Write_SpareArea_16b() - to fix column address - calculation issue.
            • -
          -
        • LL SDMMC - update
          • -
            -
          • Update the - definition of - SDMMC_DATATIMEOUT constant in - - - - order to - allow the user to redefine - it in his proper - application.
            • -
          • Remove - 'register' storage class - specifier from LL SDMMC - driver.
            • -
          • Deploy new - functions MMC_ReadExtCSD() - and SDMMC_CmdSendEXTCSD - () that read and check the - sectors number of the device - in order to resolve the - issue of wrongly reading big - memory size.
            • -
          -
        • HAL SMBUS update
          • -
            -
          • Support for - Fast Mode Plus to be SMBUS - rev 3 compliant.
            • -
          • Added HAL_FMPSMBUSEx_EnableFastModePlus() - and HAL_FMPSMBUSEx_DisableFastModePlus() - - - - - APIs to manage Fm+.
            • -
          • Updated SMBUS_MasterTransmit_BTF() - , SMBUS_MasterTransmit_TXE() - - - - - and SMBUS_MasterReceive_BTF() - - - - - APIs to allow stop - generation when CurrentXferOptions - is different from - SMBUS_FIRST_FRAME and - SMBUS_NEXT_FRAME.
            • -
          • Updated SMBUS_ITError() - API to correct the twice - call of HAL_SMBUS_ErrorCallback.
            • -
          -
        • HAL SPI update
          • -
            -
          • Updated HAL_SPI_Init() - API
            • -
              -
            • To avoid - setting the BaudRatePrescaler - in case of Slave Motorola - Mode.
              • -
            • Use the bit-mask - for SPI configuration.
              • -
            -
          • Updated - Transmit/Receive processes - in half-duplex mode
            • -
              -
            • Disable - the SPI instance before - setting BDIOE bit.
              • -
            -
          • Fixed wrong - timeout management
            • -
          • Calculate - Timeout based on a software - loop to avoid blocking issue - if Systick - is disabled.
            • -
          -
        • HAL - SPDIFRX update
          • -
            -
          • Remove - 'register' storage class - specifier from HAL SPDIFRX - driver.
            • -
          -
        • HAL I2S update
          • -
            -
          • Updated - I2SEx APIs to correctly - support circular transfers
            • -
              -
            • Updated - I2SEx_TxRxDMACplt() - API to manage DMA circular - mode.
              • -
            -
          • Updated - HAL_I2SEx_TransmitReceive_DMA() - API to set hdmatx - (transfert - callback and half) to NULL.
            • -
          -
        • HAL SAI update
          • -
            -
          • Updated to - avoid the incorrect - left/right synchronization.
            • -
              -
            • Updated HAL_SAI_Transmit_DMA() - API to follow the sequence - described in the reference - manual for slave - transmitter mode.
              • -
            -
          • Updated HAL_SAI_Init() - API to correct the formula - in case of SPDIF is wrong.
            • -
          -
        • HAL CRYP update
          • -
            -
          • Updated HAL_CRYP_SetConfig() - and HAL_CRYP_GetConfig() - - - - - APIs to set/get the - continent of KeyIVConfigSkip - correctly.
            • -
          -
        • HAL EXTI update
          • -
            -
          • __EXTI_LINE__ - - - - is now used instead of - __LINE__ which is a standard - C macro.
            • -
          -
        • HAL DCMI
          • -
            -
          • Support of - HAL callback registration - feature for DCMI extended - driver.
            • -
          -
        • HAL/LL TIM update
          • -
            -
          • Updated HAL_TIMEx_OnePulseN_Start() - and HAL_TIMEx_OnePulseN_Stop() - - - - - APIs (pooling and IT mode) - to take into consideration - all OutputChannel - parameters.
            • -
          • Corrected - reversed description of - TIM_LL_EC_ONEPULSEMODE One - Pulse Mode.
            • -
          • Updated LL_TIM_GetCounterMode() - API to return the correct - counter mode.
            • -
          -
        • HAL/LL - SMARTCARD update
          • -
            -
          • Fixed - invalid initialization of - SMARTCARD configuration by - removing FIFO mode - configuration as it is not - member of SMARTCARD_InitTypeDef - Structure.
            • -
          • Fixed typos - in SMARTCARD State - definition description
            • -
          -
        • HAL/LL IRDA update
          • -
            -
          • Fixed typos - in IRDA State definition - description
            • -
          -
        • LL USART update
          • -
            -
          • Remove - useless check on maximum BRR - value by removing - IS_LL_USART_BRR_MAX() - macro.
            • -
          • Update - USART polling and - interruption processes to - fix issues related to - accesses out of user - specified buffer.
            • -
          -
        • HAL USB update
          • -
            -
          • Enhanced - USB OTG host HAL with USB - DMA is enabled:
            • -
              -
            • fixed - ping and data toggle - issue,
              • -
            • reworked - Channel error report - management
              • -
            -
          -
        -
      -

      V1.7.10 - - - - / 22-October-2020

      -

      Main Changes

      -
        -
      • General - - - - updates to fix known defects.
        • -
      • HAL/LL - - - - I2C update
        • -
      -
        -
          -
        •   Update - to fix hardfault - issue with HAL_I2C_Mem_Write_DMA() - API:
          • -
            -
          •   - Abort the right ongoing DMA - transfer when memory write - access request operation - failed: fix typo �hdmarx� - replaced by �hdmatx�
            • -
          -
        -
      -

      V1.7.9 - - - - / 14-August-2020

      -

      Main Changes

      -
        -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • HAL/LL - - - - I2C update
        • -
      -
        -
          -
        •   Update - HAL_I2C_ER_IRQHandler() - API to fix acknowledge failure - issue with I2C memory IT - processes
          • -
            -
          •   Add - stop condition generation - when NACK occurs.
            • -
          -
        •   Update - I2C_DMAXferCplt(), - - - - - I2C_DMAError() and - I2C_DMAAbort() APIs to fix hardfault - issue when hdmatx - and hdmarx - parameters in i2c handle - aren't initialized (NULL - pointer).
          • -
            -
          •   Add - additional check on - hi2c->hdmtx - and hi2c->hdmarx - before resetting DMA Tx/Rx - complete callbacks
            • -
          -
        •   Update - Sequential transfer APIs to - adjust xfermode - condition.
          • -
            -
          •   - - - - - Replace hi2c->XferCount - < MAX_NBYTE_SIZE by - hi2c->XferCount - <= MAX_NBYTE_SIZE which - corresponds to a case - without reload
            • -
          -
        -
      -
        -
      •  HAL/LL - - - - USB update
        • -
          -
        •   Bug - - - - fix: USB_ReadPMA() - and USB_WritePMA() - - - - - by ensuring 16-bits access to - USB PMA memory
          • -
        •   Bug - - - - fix: correct USB RX count - calculation
          • -
        •   Fix - USB Bulk transfer double - buffer mode
          • -
        •   Remove - register keyword from USB - defined macros as no more - supported by C++ compiler
          • -
        •   Minor - rework on USBD_Start() - and USBD_Stop() - - - - - APIs: stopping device will be - handled by HAL_PCD_DeInit() - - - - - API.
          • -
        •   Remove - non used API for USB device - mode.
          • -
        -
      -

      V1.7.8 - - - - / 12-February-2020

      -

      Main Changes

      -
        -
      • Add - new HAL FMPSMBUS and LL - - - - FMPI2C drivers
        • -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      -
        -
      • Update - - - - HAL CRYP driver to support block - by block decryption without - reinitializes the IV and KEY for - each call.
        • -
      • Improve - - - - code quality by fixing - MisraC-2012 violations
        • -
      • HAL/LL - - - - USB update
        • -
          -
        •  Add - handling USB host babble error - interrupt
          • -
        •  Fix - Enabling ULPI interface for - platforms that integrates USB - HS PHY
          • -
        •  Fix - Host data toggling for IN Iso - transfers
          • -
        •  Ensure - to disable USB EP during - endpoint deactivation
          • -
        -
      • HAL - - - - CRYP update
        • -
          -
        •  Update - HAL CRYP driver to support - block by block decryption - without initializing the IV - and KEY at each call.
          • -
            -
          • Add new - CRYP Handler parameters: "KeyIVConfig" - and "SizesSum"
            • -
          • Add new - CRYP init - parameter: "KeyIVConfigSkip"
            • -
          -
        -
      • HAL - - - - I2S update
        • -
          -
        • Update - HAL_I2S_DMAStop() - API to be more safe
          • -
            -
          • Add a check - on BSY, TXE and RXNE flags - before disabling the I2S
            • -
          -
        • Update - HAL_I2S_DMAStop() - API to fix multi-call transfer - issue(to avoid re-initializing - the I2S for the next - transfer).
          • -
            -
          • Add - __HAL_I2SEXT_FLUSH_RX_DR() - and __HAL_I2S_FLUSH_RX_DR() - macros to flush the - remaining data inside DR - registers.
            • -
          • Add new ErrorCode - define: - HAL_I2S_ERROR_BUSY_LINE_RX
            • -
          -
        -
      -

      V1.7.7 - - - - / 06-December-2019

      -

      Main Changes

      -
        -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • HAL - - - - Generic update
        • -
          -
        • HAL_SetTickFreq(): update to - restore the previous tick - frequency when HAL_InitTick() - - - - - configuration failed.
          • -
        -
      • HAL/LL - - - - GPIO update
        • -
          -
        • Update GPIO - initialization sequence to - - - - avoid unwanted pulse on GPIO Pin's
          • -
        -
      • HAL - - - - EXTI update
        • -
      -
        -
          -
        • General - update to enhance HAL EXTI - driver robustness 
          • -
            -
          • Add - additional assert check on - EXTI config lines
            • -
          • Update to - compute EXTI line mask - before read/write access - to EXTI registers
            -
            -
            • -
          -
        • Update EXTI - callbacks management to be - compliant with reference - manual: only one PR - register for rising and - falling interrupts.
          • -
            -
          • Update - parameters in EXTI_HandleTypeDef - structure: merge HAL - EXTI RisingCallback - and FallingCallback - in only one PendingCallback
            • -
          • Remove - HAL_EXTI_RISING_CB_ID and - HAL_EXTI_FALLING_CB_ID - values from EXTI_CallbackIDTypeDef - enumeration.
            -
            -
            • -
          -
        • Update - HAL_EXTI_IRQHandler() - API to serve interrupts - correctly.
          • -
            -
          • Update to - compute EXTI line mask - before handle - EXTI interrupt.
            • -
          -
        • Update to - support GPIO port - interrupts:
          • -
            -
          • Add new "GPIOSel" - parameter in EXTI_ConfigTypeDef - structure
            • -
          -
        -
      • HAL/LL - - - - RCC update
        • -
          -
        • Update HAL_RCCEx_PeriphCLKConfig() - API to support PLLI2S - configuration for STM32F42xxx - and STM32F43xxx devices
          • -
        • Update the HAL_RCC_ClockConfig() - and HAL_RCC_DeInit() - - - - - API to don't overwrite the - custom tick priority
          • -
        • Fix LL_RCC_DeInit() - failure detected with gcc - compiler and high optimization - level is selected(-03)
          • -
        • Update HAL_RCC_OscConfig() - API to don't return - HAL_ERROR if request repeats - the current PLL configuration
          • -
        -
      • HAL - - - - ADC update
        • -
          -
        • Update LL_ADC_REG_Init() - to fix wrong ADC CR1 register - configuration
          • -
            -
          • The ADC - sequencer length is part - of ADC SQR1 - register not of ADC CR1 - register
            • -
          -
        -
      • HAL - - - - CRYP update
        • -
          -
        • Update HAL_CRYP_Encrypt() - and HAL_CRYP_Decrypt() - - - - - APIs to take into - consideration the datatype fed - to the DIN register (1-, 8-, - 16-, or 32-bit data) when - padding the last block of the - payload, in case the size of - this last block is less than - 128 bits.
          • -
        -
      • HAL - - - - RNG update
        • -
          -
        • Update HAL_RNG_IRQHandler() - API to fix error code - management issue: error code - is assigned - "HAL_RNG_ERROR_CLOCK" in case - of clock error and - "HAL_RNG_ERROR_SEED" in case - of seed error, not the - opposite.
          • -
        -
      • HAL - - - - DFSDM update
        • -
          -
        • Update DFSDM_GetChannelFromInstance() - API to remove unreachable - check condition
          • -
        -
      • HAL - - - - DMA update
        • -
          -
        • Update HAL_DMA_Start_IT() - API to omit the FIFO error
          • -
        -
      • HAL - - - - FLASH update
        • -
          -
        • Update FLASH_Program_DoubleWord() - API to fix with EWARM high - level optimization issue
          • -
        -
      • HAL - - - - QSPI update
        • -
          -
        • Remove Lock - mechanism from HAL_QSPI_Init() - and HAL_QSPI_DeInit() - - - - - APIs
          • -
        -
      • HAL - - - - HASH update
        • -
          -
        • Null pointer - on handler "hhash" - is now checked before - accessing structure member "hhash->Init.DataType" - in the following API:
          • -
            -
          • HAL_HASH_Init()
            • -
          -
        • Following interrupt-based - APIs have been added. - Interrupt mode could allow the - MCU to enter "Sleep" mode - while a data block is being - processed. Please refer to the - "##### How to use this driver - #####" section for details - about their use.
          • -
            -
          • HAL_HASH_SHA1_Accmlt_IT()
            • -
          • HAL_HASH_MD5_Accmlt_IT()
            • -
          • HAL_HASHEx_SHA224_Accmlt_IT()
            • -
          • HAL_HASHEx_SHA256_Accmlt_IT()
            • -
          -
        • Following aliases - have been added (just for - clarity sake) as they - shall be used at the end - of the computation of a - multi-buffers message and not - at the start:
          • -
            -
          • HAL_HASH_SHA1_Accmlt_End() - to be used instead of - HAL_HASH_SHA1_Start()
            • -
          • HAL_HASH_MD5_Accmlt_End() - to be used instead of - HAL_HASH_MD5_Start()
            • -
          • HAL_HASH_SHA1_Accmlt_End_IT() - to be used instead of - HAL_HASH_SHA1_Start_IT()
            • -
          • HAL_HASH_MD5_Accmlt_End_IT() - to be used instead of - HAL_HASH_MD5_Start_IT()
            • -
          • HAL_HASHEx_SHA224_Accmlt_End() - to be used instead of - HAL_HASHEx_SHA224_Start()
            • -
          • HAL_HASHEx_SHA256_Accmlt_End() - to be used instead of - HAL_HASHEx_SHA256_Start()
            • -
          -
        -
      -
        -
          -
            -
          • HAL_HASHEx_SHA224_Accmlt_End_IT() - to be used instead of - HAL_HASHEx_SHA224_Start_IT()
            • -
          • HAL_HASHEx_SHA256_Accmlt_End_IT() - to be used instead of - HAL_HASHEx_SHA256_Start_IT()
            • -
          -
        -
      -
        -
          -
        • MISRAC-2012 - rule R.5.1 (identifiers - shall be distinct in the first - 31 characters) constrained the - naming of the above listed - aliases (e.g. - HAL_HASHEx_SHA256_Accmlt_End() - could not be named - HAL_HASHEx_SHA256_Accumulate_End(). - - - - - Otherwise the name would have - conflicted with - HAL_HASHEx_SHA256_Accumulate_End_IT()). - In - - - - - order to - have aligned names following - APIs have been renamed:
          • -
        -
      -
        -
          -
            -
              -
            • HAL_HASH_MD5_Accumulate() - renamed - HAL_HASH_MD5_Accmlt()
              • -
            • HAL_HASH_SHA1_Accumulate() - renamed - HAL_HASH_SHA1_Accmlt()
              • -
            • HAL_HASHEx_SHA224_Accumulate() - renamed - HAL_HASHEx_SHA224_Accmlt()
              • -
            -
          -
        -
      -
        -
          -
            -
              -
            • HAL_HASHEx_SHA256_Accumulate() - renamed - HAL_HASHEx_SHA256_Accmlt()
              • -
            -
          -
        -
      -
        -
          -
        • HASH handler - state is no more - reset to HAL_HASH_STATE_READY - once DMA has been started - in the following APIs:
          • -
            -
          • HAL_HASH_MD5_Start_DMA()
            • -
          • HAL_HMAC_MD5_Start_DMA()
            • -
          • HAL_HASH_SHA1_Start_DMA()
            • -
          • HAL_HMAC_SHA1_Start_DMA()
            • -
          -
        • HASH phase - state is now set to - HAL_HASH_PHASE_READY once - the digest has been read - in the following APIs:
          • -
            -
          • HASH_IT()
            • -
          • HMAC_Processing()
            • -
          • HASH_Start()
            • -
          • HASH_Finish()
            • -
          -
        • Case of a - large buffer scattered around - in memory each piece of which - is not necessarily a multiple - - - - of 4 bytes in length.
          • -
            -
          • In section - "##### How to use this - driver #####", sub-section - "*** Remarks on message - length ***" added to provide - recommendations to follow in - such case.
            • -
          • No - modification of the driver - as the root-cause is at - design-level.
            • -
          -
        -
      -
        -
      • HAL CAN - - - - update
        • -
          -
        • HAL_CAN_GetRxMessage() update to - get the correct value for the - RTR (type of frame for - the message that will be - transmitted) field in the CAN_RxHeaderTypeDef - structure.
          • -
        -
      • HAL - - - - DCMI update
        • -
          -
        • Add new HAL_DCMI_ConfigSyncUnmask() - API to set embedded - synchronization delimiters - unmasks.
          • -
        -
      • HAL - - - - RTC update
        • -
          -
        • Following IRQ - handlers' implementation has - been aligned with the - STM32Cube firmware - specification (in case of - interrupt lines shared by - multiple events, first check - the IT enable bit is set then - check the IT flag is set too):
          • -
            -
          • HAL_RTC_AlarmIRQHandler()
            • -
          • HAL_RTCEx_WakeUpTimerIRQHandler()
            • -
          • HAL_RTCEx_TamperTimeStampIRQHandler()
            • -
          -
        -
      -
        -
      • HAL - - - - WWDG update
        • -
          -
        • In "##### - WWDG Specific features #####" - descriptive comment section:
          • -
            -
          • Maximal prescaler - value has been corrected (8 - instead of 128).
            • -
          • Maximal APB - frequency has been corrected - (42MHz instead of 56MHz) and - possible timeout values - updated.
            • -
          -
        -
      • HAL - - - - DMA2D update
        • -
      -
        -
          -
        • Add the - following API's to Start DMA2D - CLUT Loading.
          • -
            -
          • HAL_DMA2D_CLUTStartLoad() - Start DMA2D CLUT Loading.
            • -
          • HAL_DMA2D_CLUTStartLoad_IT() - Start DMA2D CLUT Loading - with interrupt enabled.
            • -
          -
        • The following - old wrong services will be - kept in the HAL DCMI driver - for legacy purpose and a - specific Note is added:
          • -
            -
          • HAL_DMA2D_CLUTLoad() - can be replaced with - HAL_DMA2D_CLUTStartLoad()
            • -
          • HAL_DMA2D_CLUTLoad_IT() can - - - - - be replaced with - HAL_DMA2D_CLUTStartLoad_IT()
            • -
          • HAL_DMA2D_ConfigCLUT() - can be omitted as the config - can be performed using - the HAL_DMA2D_CLUTStartLoad() - API.
            • -
          -
        -
      -
        -
      • HAL - - - - SDMMC update
        • -
          -
        • Fix  - typo in "FileFormatGroup" - parameter in the HAL_MMC_CardCSDTypeDef - and HAL_SD_CardCSDTypeDef - structures 
          • -
        • Fix an - improve handle state and - error management
          • -
        • Rename the - defined MMC card capacity type - to be more meaningful:
          • -
            -
          • Update MMC_HIGH_VOLTAGE_CARD to - - - - - MMC LOW_CAPACITY_CARD
            • -
          • Update MMC_DUAL_VOLTAGE_CRAD - to MMC_HIGH_CAPACITY_CARD
            • -
          -
        • Fix - management of peripheral - flags depending on commands - or data transfers
          • -
            -
          • Add new - defines - "SDIO_STATIC_CMD_FLAGS" - and "SDIO_STATIC_DATA_FLAGS" 
            • -
          • Updates HAL - - - - SD and HAL MMC drivers to - manage the new SDIO static - flags.
            -
            -
            • -
          -
        • Due to - limitation SDIO hardware flow - control indicated in Errata - Sheet:
          • -
            -
          • In 4-bits - bus wide mode, do not use - the HAL_SD_WriteBlocks_IT() - or HAL_SD_WriteBlocks() - - - - - APIs otherwise underrun will - occur and it isn't possible - to activate the flow - control.
            • -
          • Use DMA - mode when using 4-bits bus - wide mode or decrease the - SDIO_CK frequency.
            • -
          -
        -
      • HAL - - - - UART update
        • -
          -
        • Update UART - polling processes to handle - efficiently the Lock mechanism
          • -
            -
          •  Move - the process unlock at the - top of the HAL_UART_Receive() - and HAL_UART_Transmit() - - - - - API.
            • -
          -
        • Fix baudrate - calculation error for clock - higher than 172Mhz
          • -
            -
          • Add a - forced cast on - UART_DIV_SAMPLING8() and - UART_DIV_SAMPLING16() - macros.
            • -
          • Remove - useless parenthesis from - UART_DIVFRAQ_SAMPLING8(), - UART_DIVFRAQ_SAMPLING16(), - UART_BRR_SAMPLING8() and - UART_BRR_SAMPLING16() macros - to solve some MISRA - warnings.
            • -
          -
        • Update UART - interruption handler to manage - correctly the overrun interrupt
          • -
            -
          • Add in - the HAL_UART_IRQHandler() - API a check on - USART_CR1_RXNEIE bit when an - overrun interrupt occurs.
            • -
          -
        • Fix baudrate - calculation error UART9 - and UART10
          • -
            -
          • In UART_SetConfig() - API fix UART9 and UART10 - clock source when computing - baudrate - values by adding a check on - these instances and setting - clock sourcePCLK2 instead of - PCLK1.
            • -
          -
        • Update UART_SetConfig() - API
          • -
            -
          • Split - HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() - macros from the - UART_BRR_SAMPLING8() and - UART_BRR_SAMPLING8() - macros 
            • -
          -
        -
      • HAL - - - - USART update
        • -
          -
        • Fix baudrate - calculation error for clock - higher than 172Mhz
          • -
            -
          • Add a - forced cast on USART_DIV() - macro.
            • -
          • Remove - useless parenthesis - from USART_DIVFRAQ() - macro to solve some MISRA - warnings.
            • -
          -
        • Update USART - interruption handler to manage - correctly the overrun interrupt
          • -
            -
          • Add in - the HAL_USART_IRQHandler() - API a check on - USART_CR1_RXNEIE bit when an - overrun interrupt occurs.
            • -
          -
        • Fix baudrate - calculation error UART9 - and UART10
          • -
            -
          • In USART_SetConfig() - API fix UART9 and UART10 - clock source when computing - baudrate - values by adding a check on - these instances and setting - clock sourcePCLK2 instead of - PCLK1.
            • -
          -
        • Update USART_SetConfig() - API
          • -
            -
          • Split - HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() - macros from the USART_BRR() - macro
            • -
          -
        -
      • HAL - - - - IRDA update
        • -
          -
        • Fix baudrate - calculation error for clock - higher than 172Mhz
          • -
            -
          • Add a - forced cast on IRDA_DIV() - macro.
            • -
          • Remove - useless parenthesis - from IRDA_DIVFRAQ() - macro to solve some - MISRA warnings.
            • -
          -
        • Update IRDA - interruption handler to manage - correctly the overrun interrupt
          • -
            -
          • Add in - the HAL_IRDA_IRQHandler() - API a check on - USART_CR1_RXNEIE bit when an - overrun interrupt occurs.
            • -
          -
        • Fix baudrate - calculation error UART9 - and UART10
          • -
            -
          • In IRDA_SetConfig() - API fix UART9 and UART10 - clock source when computing - baudrate - values by adding a check on - these instances and setting - clock sourcePCLK2 instead of - PCLK1.
            • -
          -
        • Update IRDA_SetConfig() - API
          • -
            -
          • Split - HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() - macros from the IRDA_BRR() - macro
            • -
          -
        -
      • HAL - - - - SMARTCARD update
        • -
          -
        • Fix baudrate - calculation error for clock - higher than 172Mhz
          • -
            -
          • Add a - forced cast on SMARTCARD_DIV() - macro.
            • -
          • Remove useless parenthesis - - - - - from SMARTCARD_DIVFRAQ() - macro to solve some - MISRA warnings.
            • -
          -
        • Update - SMARTCARD interruption handler - to manage correctly the - overrun interrupti
          • -
            -
          • Add in - the HAL_SMARTCARD_IRQHandler() - API a check on - USART_CR1_RXNEIE bit when an - overrun interrupt occurs.
            • -
          -
        • Update SMARTCARD_SetConfig() - API
          • -
            -
          • Split - HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() - macros from the - SMARTCARD_BRR() macro
            • -
          -
        -
      • HAL - - - - TIM update
        • -
          -
        • Add new - macros to enable and disable - the fast mode when using the - one pulse mode to output a - waveform with a minimum delay
          • -
            -
          • __HAL_TIM_ENABLE_OCxFAST() - and __HAL_TIM_DISABLE_OCxFAST().
            • -
          -
        • Update - Encoder interface mode to - keep TIM_CCER_CCxNP - bits low
          • -
            -
          • Add TIM_ENCODERINPUTPOLARITY_RISING - - - - - and - TIM_ENCODERINPUTPOLARITY_FALLING - definitions to determine - encoder input polarity.
            • -
          • Add - IS_TIM_ENCODERINPUT_POLARITY() - macro to check the - encoder input polarity.
            • -
          • Update HAL_TIM_Encoder_Init() - API 
            • -
              -
            • Replace - IS_TIM_IC_POLARITY() - macro by - IS_TIM_ENCODERINPUT_POLARITY() - macro.
              • -
            -
          -
        • Update TIM - remapping input configuration - in HAL_TIMEx_RemapConfig() - API
          • -
            -
          • Remove - redundant check on - LPTIM_OR_TIM5_ITR1_RMP bit - and replace it by check on - LPTIM_OR_TIM9_ITR1_RMP bit.
            • -
          -
        • Update HAL_TIMEx_MasterConfigSynchronization() - API to avoid functional errors - and assert fails when using - some TIM instances as input - trigger.
          • -
            -
          • Replace IS_TIM_SYNCHRO_INSTANCE() - macro by - IS_TIM_MASTER_INSTANCE() - macro. 
            • -
          • Add IS_TIM_SLAVE_INSTANCE() - macro to check on - TIM_SMCR_MSM bit.
            • -
          -
        • Add lacking - TIM input remapping definition 
          • -
            -
          • Add - LL_TIM_TIM11_TI1_RMP_SPDIFRX - and - LL_TIM_TIM2_ITR1_RMP_ETH_PTP.
            • -
          • Add lacking - definition for linked - LPTIM_TIM input trigger remapping  
            • -
              -
            • Add - following definitions - - - - - : - LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO, - LL_TIM_TIM9_ITR1_RMP_LPTIM, - - - - LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO, - - - - - LL_TIM_TIM5_ITR1_RMP_LPTIM, - - - - LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO - - - - and - LL_TIM_TIM1_ITR2_RMP_LPTIM.
              • -
            • Add a new - mechanism in LL_TIM_SetRemap() - API to remap TIM1, TIM9, - and TIM5 input - triggers mapped on LPTIM - register. 
              • -
            -
          -
        -
      • HAL - - - - LPTIM update
        • -
          -
        • Add a polling - mechanism to check - on LPTIM_FLAG_XXOK flags - in different API 
          • -
            -
          • Add  - LPTIM_WaitForFlag() API to - wait for flag set.
            • -
          • Perform new - checks on - HAL_LPTIM_STATE_TIMEOUT.
            • -
          -
        • Add lacking - definitions of LPTIM input - trigger remapping and its - related API
          • -
            -
              -
            • LL_LPTIM_INPUT1_SRC_PAD_AF, - - - - - LL_LPTIM_INPUT1_SRC_PAD_PA4, - - - - LL_LPTIM_INPUT1_SRC_PAD_PB9 - - - - and - LL_LPTIM_INPUT1_SRC_TIM_DAC.
              • -
            • Add a new - API LL_LPTIM_SetInput1Src() - to access to the LPTIM_OR - register and remap the - LPTIM input trigger.
              • -
            -
          -
        • Perform a new - check on indirect EXTI23 line - associated to the LPTIM wake - up timer
          • -
            -
          • Condition - the use of the LPTIM Wake-up - Timer associated EXTI - line configuration's - macros by EXTI_IMR_MR23 - bit in different API - - - - :
            • -
              -
            • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE/DDISABLE_FALLING_EDGE()
              • -
            • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()
              • -
            • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() 
              • -
            • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()
              • -
            • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
              • -
            • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
              • -
            • __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()
              • -
            • __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()
              • -
            • __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() 
              • -
            -
          • Update HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop_IT(), - - - - - HAL_LPTIM_Counter_Start_IT() - - - - - and HAL_LPTIM_Counter_Stop_IT() - - - - - API by adding Enable/Disable - rising edge trigger on - the LPTIM Wake-up Timer - Exti - line.
            • -
          • Add - __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() - in the end of the HAL_LPTIM_IRQHandler() - - - - - API conditioned by - EXTI_IMR_MR23 bit.
            • -
          -
        -
      • HAL - - - - I2C update
        • -
          -
        • Update - HAL_I2C_EV_IRQHandler() - API to fix I2C send break - issue 
          • -
            -
          • Add - additional check on - hi2c->hdmatx, - hdmatx->XferCpltCallback, - hi2c->hdmarx, - hdmarx->XferCpltCallback - in I2C_Master_SB() - API to avoid enabling - DMA request when IT - mode is used.
            • -
          -
        • Update - HAL_I2C_ER_IRQHandler() - API to fix acknowledge failure - issue with I2C memory IT - processes
          • -
            -
          •  Add stop - - - - - condition generation when - NACK occurs.
            • -
          -
        • Update - HAL_I2C_Init() - API to force software reset - before setting new I2C - configuration
          • -
        • Update HAL - I2C processes to report ErrorCode - when wrong I2C start condition - occurs
          • -
            -
          •  Add - new ErrorCode - define: HAL_I2C_WRONG_START
            • -
          •  Set ErrorCode - parameter in I2C handle - to HAL_I2C_WRONG_START
            • -
          -
        • Update I2C_DMAXferCplt(), - - - - - I2C_DMAError() and - I2C_DMAAbort() APIs to fix hardfault - issue when hdmatx - and hdmarx parameters - - - - - in i2c handle aren't - initialized (NULL pointer).
          • -
            -
          • Add - additional check on - hi2c->hdmtx - and hi2c->hdmarx - before resetting DMA - Tx/Rx complete callbacks
            • -
          -
        -
      • HAL - - - - FMPI2C update
        • -
          -
        • Fix HAL - FMPI2C slave interrupt - handling issue with I2C - sequential transfers.
          • -
            -
          • Update - FMPI2C_Slave_ISR_IT() - and FMPI2C_Slave_ISR_DMA() - APIs to check on STOP - condition and handle it - before clearing the ADDR - flag
            • -
          -
        -
      • HAL - - - - NAND update
        • -
          -
        • Update - HAL_NAND_Write_Page_8b(), - - - - HAL_NAND_Write_Page_16b() - and  - HAL_NAND_Write_SpareArea_16b() - to manage correctly the time - out condition.
          • -
        -
      • HAL - - - - SAI update
        • -
          -
        • Optimize SAI_DMATxCplt() - and SAI_DMARxCplt() - - - - - APIs to check on "Mode" - parameter instead of CIRC - bit in the CR register.
          • -
        • Remove unused - SAI_FIFO_SIZE define
          • -
        • Update HAL_SAI_Receive_DMA() - programming sequence to be inline - with reference manual
          • -
        -
      -

      V1.7.6 - - - - / 12-April-2019

      -

      Main Changes

      -
        -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • HAL - - - - I2C update
        • -
          -
        • Fix I2C send - break issue in IT processes
          • -
            -
          • Add - additional check on - hi2c->hdmatx - and hi2c->hdmarx to - - - - - avoid the DMA request - enable when IT mode is used.
            • -
          -
        -
      • HAL - - - - SPI update
        • -
          -
        • Update to - implement Erratasheet: - BSY bit may stay high at the - end of a data transfer in - Slave mode
          • -
        -
      • LL - - - - LPTIM update
        • -
          -
        • Fix - compilation errors with LL_LPTIM_WriteReg() - and LL_LPTIM_ReadReg() - - - - - macros
          • -
        -
      • HAL - - - - SDMMC update
        • -
          -
        • Fix - preprocessing compilation - issue with SDIO - STA STBITERR interrupt
          • -
        -
      • HAL/LL - - - - USB update
        • -
          -
        • Updated USB_WritePacket(), - - - - - USB_ReadPacket() - - - - - APIs to prevent compilation - warning with GCC GNU v8.2.0
          • -
        • Rework USB_EPStartXfer() - API to enable the USB endpoint - before unmasking the TX FiFo - empty interrupt in case DMA is - not used
          • -
        • USB HAL_HCD_Init() - and HAL_PCD_Init() - - - - - APIs updated to avoid enabling - USB DMA feature for OTG FS - instance, USB DMA feature is - available only on OTG HS - Instance
          • -
        • Remove - duplicated line in hal_hcd.c - header file comment section -
          • -
        • Rework USB - HAL driver to use instance PCD_SPEED_xxx, - HCD_SPEED_xx - speeds instead of OTG register - Core speed definition during - the instance initialization
          • -
        • Software - Quality improvement with a fix - of CodeSonar - warning on PCD_Port_IRQHandler() - and  HCD_Port_IRQHandler() - - - - - interrupt handlers
          • -
        -
      -

      V1.7.5 - - - - / 08-February-2019

      -

      Main Changes

      -
        -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • General - - - - updates to fix CodeSonar - compilation warnings
        • -
      • General - - - - updates to fix SW4STM32 - compilation errors under Linux
        • -
      • General - - - - updates to fix the user manual - .chm files
        • -
      • Add - support of HAL callback - registration feature
        • -
      -
        -
      • Add - new HAL - - - - EXTI driver
        • -
      • Add - new HAL - - - - SMBUS driver
        • -
      • The - - - - following changes done on the - HAL drivers require an update - on the application code based - on older HAL versions
        • -
          -
        • Rework of HAL - CRYP driver (compatibility - break)
          • -
            -
          • HAL CRYP - driver has been redesigned - with new API's, to bypass - limitations on data - Encryption/Decryption - management present with - previous HAL CRYP driver - version.
            • -
          • The new HAL - CRYP driver is the - recommended version. It is - located as usual in - Drivers/STM32F4xx_HAL_Driver/Src - and - Drivers/STM32f4xx_HAL_Driver/Inc - folders. It can be enabled - through switch - HAL_CRYP_MODULE_ENABLED in - stm32f4xx_hal_conf.h
            • -
          • The legacy - HAL CRYP driver is no longer - supported.
            • -
          -
        • Add new AutoReloadPreload - field in TIM_Base_InitTypeDef - structure to allow the - possibilities to enable or - disable the TIM Auto Reload - Preload.
          • -
        -
      -
        -
      • HAL/LL - - - - Generic update
        • -
          -
        • Add support - of HAL callback - registration feature
          • -
            -
          • The feature - disabled by default is - available for the following - HAL drivers:
            • -
              -
            • ADC, - CAN, CEC, CRYP, DAC, - DCMI, DFSDM, DMA2D, DSI, - ETH, HASH, HCD, I2C, - FMPI2C, SMBUS,
              - UART, USART, IRDA, - SMARTCARD, LPTIM, LTDC, - MMC, NAND, NOR, - PCCARD, PCD, QSPI, RNG,
              -               RTC, - SAI, SD, SDRAM, SRAM, - SPDIFRX, SPI, I2S, TIM, - and WWDG
              • -
            -
          • The feature - may be enabled individually - per HAL PPP driver - by setting the corresponding - definition USE_HAL_PPP_REGISTER_CALLBACKS - - - - - to 1U in - stm32f4xx_hal_conf.h project - configuration file (template - file - stm32f4xx_hal_conf_template.h - available from  - - - - Drivers/STM32F4xx_HAL_Driver/Inc)
            • -
          • Once enabled - - - - , the user - application may resort to HAL_PPP_RegisterCallback() - - - - - to register specific - callback function(s) and - unregister it(them) with HAL_PPP_UnRegisterCallback().
            • -
          -
        • General - updates to fix MISRA 2012 - compilation errors
          • -
            -
          • Replace HAL_GetUID() - API by HAL_GetUIDw0(), - HAL_GetUIDw1() and - HAL_GetUIDw2()
            • -
          • HAL_IS_BIT_SET()/HAL_IS_BIT_CLR() - macros implementation update
            • -
          • "stdio.h" - include updated with "stddef.h"
            • -
          -
        -
      • HAL - - - - GPIO  - - - - update
        • -
          -
        • Add missing - define for SPI3 alternate - function "GPIO_AF5_SPI3" for - STM32F401VE devices
          • -
        • Remove - "GPIO_AF9_TIM14" from defined - alternate function list for - STM32F401xx devices
          • -
        • HAL_GPIO_TogglePin() reentrancy - robustness improvement
          • -
        • HAL_GPIO_DeInit() API update - to avoid potential pending - interrupt after call
          • -
        • Update - GPIO_GET_INDEX() - API for more compliance with - STM32F412Vx/STM32F412Rx/STM32F412Cx - devices
          • -
        • Update - GPIO_BRR registers with - Reference Manual regarding - registers and bit definition - values
          • -
        -
      • HAL - - - - CRYP update
        • -
          -
        • The CRYP_InitTypeDef - is no more - supported, changed by CRYP_ConfigTypedef - to allow changing parameters - using HAL_CRYP_setConfig() - API without reinitialize the - CRYP IP using the HAL_CRYP_Init() - - - - - API
          • -
        • New - parameters added in the CRYP_ConfigTypeDef - structure: B0 and DataWidthUnit
          • -
        • Input data - size parameter is added in the - CRYP_HandleTypeDef - structure
          • -
        • Add new APIs - to manage the CRYP - configuration:
          • -
            -
          •  HAL_CRYP_SetConfig()
            • -
          • HAL_CRYP_GetConfig()
            • -
          -
        • Add new APIs - to manage the Key derivation:
          • -
            -
          • HAL_CRYPEx_EnableAutoKeyDerivation()
            • -
          • HAL_CRYPEx_DisableAutoKeyDerivation()
            • -
          -
        • Add new APIs - to encrypt and decrypt data:
          • -
            -
          • HAL_CRYP_Encypt()
            • -
          • HAL_CRYP_Decypt()
            • -
          • HAL_CRYP_Encypt_IT()
            • -
          • HAL_CRYP_Decypt_IT()
            • -
          • HAL_CRYP_Encypt_DMA()
            • -
          • HAL_CRYP_Decypt_DMA()
            • -
          -
        • Add new APIs - to generate TAG:
          • -
            -
          • HAL_CRYPEx_AESGCM_GenerateAuthTAG()
            • -
          • HAL_CRYPEx_AESCCM_Generago teAuthTAG()
            • -
          -
        -
      • HAL - - - - LPTIM update
        • -
          -
        • Remove - useless LPTIM Wakeup EXTI - related macros from HAL_LPTIM_TimeOut_Start_IT() - API
          • -
        -
      • HAL - - - - I2C update
        • -
          -
        • I2C API - changes for MISRA-C 2012 - compliancy:
          • -
            -
          • Rename - HAL_I2C_Master_Sequential_Transmit_IT() - to - HAL_I2C_Master_Seq_Transmit_IT()
            • -
          • Rename - HAL_I2C_Master_Sequentiel_Receive_IT() - to - HAL_I2C_Master_Seq_Receive_IT()
            • -
          • Rename - HAL_I2C_Slave_Sequentiel_Transmit_IT() - to - HAL_I2C_Slave_Seq_Transmit_IT() -
            • -
          • Rename - HAL_I2C_Slave_Sequentiel_Receive_DMA() - to - HAL_I2C_Slave_Seq_Receive_DMA()
            • -
          -
        • SMBUS defined - flags are removed as not used - by the HAL I2C driver
          • -
            -
          • I2C_FLAG_SMBALERT
            • -
          • I2C_FLAG_TIMEOUT
            • -
          • I2C_FLAG_PECERR
            • -
          • I2C_FLAG_SMBHOST
            • -
          • I2C_FLAG_SMBDEFAULT
            • -
          -
        • Add support - of I2C repeated start feature - in DMA Mode:
          • -
            -
          • With the - following new API's
            • -
              -
            • HAL_I2C_Master_Seq_Transmit_DMA()
              • -
            • HAL_I2C_Master_Seq_Receive_DMA()
              • -
            • HAL_I2C_Slave_Seq_Transmit_DMA()
              • -
            • HAL_I2C_Slave_Seq_Receive_DMA()
              • -
            -
          -
        • Add new I2C - transfer options to easy - manage the sequential transfers
          • -
            -
          • I2C_FIRST_AND_NEXT_FRAME
            • -
          • I2C_LAST_FRAME_NO_STOP
            • -
          • I2C_OTHER_FRAME
            • -
          • I2C_OTHER_AND_LAST_FRAME
            • -
          -
        -
      • HAL - - - - FMPI2C update
        • -
          -
        • I2C API - changes for MISRA-C 2012 - compliancy:
          • -
            -
          • Rename - HAL_FMPI2C_Master_Sequential_Transmit_IT() - to - HAL_FMPI2C_Master_Seq_Transmit_IT()
            • -
          • Rename - HAL_FMPI2C_Master_Sequentiel_Receive_IT() - to - HAL_FMPI2C_Master_Seq_Receive_IT()
            • -
          • Rename - HAL_FMPI2C_Master_Sequentiel_Transmit_DMA() - to - HAL_FMPI2C_Master_Seq_Transmit_DMA() -
            • -
          • Rename - HAL_FMPI2C_Master_Sequentiel_Receive_DMA() - to - HAL_FMPI2C_Master_Seq_Receive_DMA()
            • -
          -
        • Rename - FMPI2C_CR1_DFN to - FMPI2C_CR1_DNF for more - compliance with Reference - Manual regarding registers and - bit definition naming
          • -
        • Add support - of I2C repeated start feature - in DMA Mode:
          • -
            -
          • With the - following new API's
            • -
              -
            • HAL_FMPI2C_Master_Seq_Transmit_DMA()
              • -
            • HAL_FMPI2C_Master_Seq_Receive_DMA()
              • -
            • HAL_FMPI2C_Slave_Seq_Transmit_DMA()
              • -
            • HAL_FMPI2C_Slave_Seq_Receive_DMA()
              • -
            -
          -
        -
      • HAL - - - - FLASH update
        • -
          -
        • Update the FLASH_OB_GetRDP() - API to return the correct RDP - level
          • -
        -
      • HAL  - RCC - update
        • -
          -
        • Remove GPIOD - CLK macros for STM32F412Cx - devices (X = D)
          • -
        • Remove GPIOE - CLK macros for - STM32F412Rx\412Cx devices: (X - = E)
          • -
        • Remove - GPIOF/G CLK macros for - STM32F412Vx\412Rx\412Cx - devices (X= F or G)
          • -
            -
          • __HAL_RCC_GPIOX_CLK_ENABLE()
            • -
          • __HAL_RCC_GPIOX_CLK_DISABLE()
            • -
          • __HAL_RCC_GPIOX_IS_CLK_ENABLED()
            • -
          • __HAL_RCC_GPIOX_IS_CLK_DISABLED()
            • -
          • __HAL_RCC_GPIOX_FORCE_RESET()
            • -
          -
        -
      • HAL - - - - RNG update
        • -
          -
        • Update to - manage RNG error code:
          • -
            -
          • Add ErrorCode - parameter in HAL RNG Handler - structure
            • -
          -
        -
      • LL - - - - ADC update
        • -
          -
        • Add - __LL_ADC_CALC_TEMPERATURE() - helper macro to calculate the - temperature (unit: degree - Celsius) from ADC conversion - data of internal temperature - sensor.
          • -
        • Fix ADC - channels configuration issues - on STM32F413xx/423xx devices
          • -
            -
          • To allow - possibility to switch - between VBAT and TEMPERATURE - channels configurations
            • -
          -
        • HAL_ADC_Start(), HAL_ADC_Start_IT() - - - - - and HAL_ADC_Start_DMA() - - - - - update to prevention from - starting ADC2 or ADC3 once - multimode is enabled
          • -
        -
      • HAL - - - - DFSDM  - - - - update
        • -
          -
        • General - updates to be compliant with - DFSDM bits naming used in - CMSIS files.
          • -
        -
      • HAL - - - - CAN  - - - - update
        • -
          -
        • Update - possible values list for FilterActivation - parameter in CAN_FilterTypeDef - structure
          • -
            -
          • CAN_FILTER_ENABLE - - - - - instead of ENABLE
            • -
          • CAN_FILTER_DISABLE - - - - - instead of DISABLE
            • -
          -
        -
      • HAL - - - - CEC  - - - - update
        • -
          -
        • Update HAL - CEC State management method:
          • -
            -
          • Remove HAL_CEC_StateTypeDef - structure parameters
            • -
          • Add new - defines for CEC states
            • -
          -
        -
      • HAL - - - - DMA  - - - - update
        • -
          -
        • Add clean of - callbacks in HAL_DMA_DeInit() - API
          • -
        -
      • HAL - - - - DMA2D  - - - - update
        • -
          -
        • Remove unused - DMA2D_ColorTypeDef structure - to be compliant with MISRAC - 2012 Rule 2.3
          • -
        • General - update to use dedicated - defines for - DMA2D_BACKGROUND_LAYER and - DMA2D_FOREGROUND_LAYER instead - of numerical values: 0/1.
          • -
        -
      • HAL - - - - DSI  - - - - update
        • -
          -
        • Fix read - multibyte issue: remove extra - call to __HAL_UNLOCK__ from DSI_ShortWrite() - API.
          • -
        -
      -
        -
      • HAL/LL - - - - RTC update
        • -
      -
        -
          -
        • HAL/ LL drivers - optimization
          • -
            -
          • HAL driver: - remove unused variables
            • -
          • LL driver: - getter APIs optimization
            • -
          -
        -
      • HAL - - - - PWR update
        • -
          -
        • Remove the - followings API's as feature - not supported by - STM32F469xx/479xx devices
          • -
            -
          • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
            • -
          • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
            • -
          -
        -
      • HAL - - - - SPI update
        • -
          -
        • Update HAL_SPI_StateTypeDef - structure to add new state: - HAL_SPI_STATE_ABORT
          • -
        -
      • HAL/LL - - - - TIM update
        • -
          -
        • Add new AutoReloadPreload - field in TIM_Base_InitTypeDef - structure
          • -
            -
          • Refer to - the TIM examples to identify - the changes -
            • -
          -
        • Move the - following TIM structures from - stm32f4xx_hal_tim_ex.h into - stm32f4xx_hal_tim.h
          • -
            -
          • TIM_MasterConfigTypeDef
            • -
          • TIM_BreakDeadTimeConfigTypeDef
            • -
          -
        • Add new TIM - Callbacks API's:
          • -
            -
          • HAL_TIM_PeriodElapsedHalfCpltCallback()
            • -
          • HAL_TIM_IC_CaptureHalfCpltCallback()
            • -
          • HAL_TIM_PWM_PulseFinishedHalfCpltCallback()
            • -
          • HAL_TIM_TriggerHalfCpltCallback()
            • -
          -
        • TIM API - changes for MISRA-C 2012 - compliancy:
          • -
            -
          • Rename HAL_TIM_SlaveConfigSynchronization - to HAL_TIM_SlaveConfigSynchro
            • -
          • Rename HAL_TIM_SlaveConfigSynchronization_IT - to HAL_TIM_SlaveConfigSynchro_IT
            • -
          • Rename HAL_TIMEx_ConfigCommutationEvent - to HAL_TIMEx_ConfigCommutEvent
            • -
          • Rename HAL_TIMEx_ConfigCommutationEvent_IT - to HAL_TIMEx_ConfigCommutEvent_IT
            • -
          • Rename HAL_TIMEx_ConfigCommutationEvent_DMA - to HAL_TIMEx_ConfigCommutEvent_DMA
            • -
          • Rename HAL_TIMEx_CommutationCallback - to HAL_TIMEx_CommutCallback
            • -
          • Rename HAL_TIMEx_DMACommutationCplt - to TIMEx_DMACommutationCplt
            • -
          -
        -
      -
        -
      • HAL/LL - - - - USB update
        • -
          -
        • Rework USB - interrupt handler and improve - HS DMA support in Device mode
          • -
        • Fix BCD - handling fr OTG - instance in device mode
          • -
        • cleanup - reference to low speed in - device mode
          • -
        • allow writing - TX FIFO in case of transfer - length is equal to available - space in the TX FIFO
          • -
        • Fix Toggle - OUT interrupt channel in host - mode
          • -
        • Update USB - OTG max number of endpoints (6 - FS and 9 HS instead of 5 and - 8)
          • -
        • Update USB - OTG IP to enable internal - transceiver when starting USB - device after committee BCD negotiation
          • -
        -
      • LL - - - - IWDG update
        • -
          -
        • Update LL - inline macros to use IWDGx - parameter instead of IWDG - instance defined in CMSIS device
          • -
        -
      -

      V1.7.4 - - - - / 02-February-2018

      -

      Main Changes

      -
        -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • HAL update
        • -
          -
        • Update UNUSED() - macro implementation to avoid - GCC warning
          • -
            -
          • The warning - is detected when the UNUSED() - macro is called from C++ - file
            • -
          -
        • Update to - make RAMFUNC define as generic - type instead of HAL_StatusTypdef - type.
          • -
        -
      • HAL - - - - FLASH update
        • -
          -
        • Update - the prototypes of the - following APIs after change on - RAMFUNC defines 
          • -
            -
          • HAL_FLASHEx_StopFlashInterfaceClk()
            • -
          • HAL_FLASHEx_StartFlashInterfaceClk()
            • -
          • HAL_FLASHEx_EnableFlashSleepMode()
            • -
          • HAL_FLASHEx_DisableFlashSleepMode()
            • -
          -
        -
      • HAL - - - - SAI update
        • -
          -
        • Update HAL_SAI_DMAStop() - and HAL_SAI_Abort() - - - - - process to fix the lock/unlock - audio issue
          • -
        -
      -

      V1.7.3 - - - - / 22-December-2017

      -

      Main Changes

      -
        -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • The - - - - following changes done on the - HAL drivers require an update - on the application code based - on older HAL versions
        • -
          -
        • Rework of - HAL CAN driver - (compatibility break) 
          • -
            -
          • A new HAL - CAN driver has been - redesigned with new APIs, to - bypass limitations on CAN - Tx/Rx FIFO management - present with previous HAL - CAN driver version.
            • -
          • The new HAL - CAN driver is the - recommended version. It is - located as usual in - Drivers/STM32F4xx_HAL_Driver/Src - and - Drivers/STM32f4xx_HAL_Driver/Inc - folders. It can be enabled - through switch - HAL_CAN_MODULE_ENABLED in - stm32f4xx_hal_conf.h
            • -
          • The legacy - HAL CAN driver is also - present in the release in - Drivers/STM32F4xx_HAL_Driver/Src/Legacy - - - - and - Drivers/STM32F4xx_HAL_Driver/Inc/Legacy - folders for software - compatibility reasons. Its - usage is not recommended as - deprecated. It can - however be enabled through - switch - HAL_CAN_LEGACY_MODULE_ENABLED - in stm32f4xx_hal_conf.h
            • -
          -
        -
      • HAL update
        • -
          -
        • Update HAL - driver to allow user to change - systick - period to 1ms, 10 ms - or 100 ms :
          • -
            -
          • Add the - following API's - - - - :  
            • -
              -
            • HAL_GetTickPrio(): - Returns a tick priority.
              • -
            • HAL_SetTickFreq(): Sets - new tick frequency.
              • -
            • HAL_GetTickFreq(): - Returns tick frequency.
              • -
            -
          • Add HAL_TickFreqTypeDef - enumeration for the - different Tick Frequencies: - 10 Hz, 100 Hz and 1KHz - (default).
            • -
          -
        -
      • HAL - - - - CAN update
        • -
          -
        • Fields of CAN_InitTypeDef - structure are reworked:
          • -
            -
          • SJW to SyncJumpWidth, - BS1 to TimeSeg1, BS2 to - TimeSeg2, TTCM to TimeTriggeredMode, - ABOM to AutoBusOff, - AWUM to AutoWakeUp, - NART to AutoRetransmission - (inversed), RFLM to ReceiveFifoLocked - and TXFP to TransmitFifoPriority
            • -
          -
        • HAL_CAN_Init() is split - into both HAL_CAN_Init() - - - - - and HAL_CAN_Start() - - - - - API's
          • -
        • HAL_CAN_Transmit() is replaced - by HAL_CAN_AddTxMessage() - - - - - to place Tx Request, then HAL_CAN_GetTxMailboxesFreeLevel() - - - - - for polling until completion.
          • -
        • HAL_CAN_Transmit_IT() is replaced - by HAL_CAN_ActivateNotification() - - - - - to enable transmit IT, then HAL_CAN_AddTxMessage() - - - - - for place Tx request.
          • -
        • HAL_CAN_Receive() is replaced - by HAL_CAN_GetRxFifoFillLevel() - - - - - for polling until reception, - then HAL_CAN_GetRxMessage() - - - - -
          - to get Rx message.
          • -
        • HAL_CAN_Receive_IT() is replaced - by HAL_CAN_ActivateNotification() to - - - - - enable receive IT, then HAL_CAN_GetRxMessage()
          - in the receivecallback - to get Rx message
          • -
        • HAL_CAN_Slepp() is renamed - as HAL_CAN_RequestSleep()
          • -
        • HAL_CAN_TxCpltCallback() is split - into - HAL_CAN_TxMailbox0CompleteCallback(), -HAL_CAN_TxMailbox1CompleteCallback() -and HAL_CAN_TxMailbox2CompleteCallback().
          • -
        • HAL_CAN_RxCpltCallback is split - into HAL_CAN_RxFifo0MsgPendingCallback() - and - HAL_CAN_RxFifo1MsgPendingCallback().
          • -
        • More complete - "How to use the new driver" is - detailed in the driver header - section itself.
          • -
        -
      • HAL - - - - FMPI2C update
        • -
          -
        • Add new - option - FMPI2C_LAST_FRAME_NO_STOP for - the sequential transfer management
          • -
            -
          • This option - allows to manage a restart - condition after several call - of the same master - sequential interface. 
            • -
          -
        -
      • HAL - - - - RCC update
        • -
          -
        • Add new HAL macros
          • -
            -
          • __HAL_RCC_GET_RTC_SOURCE() - allowing to get the RTC - clock source
            • -
          • __HAL_RCC_GET_RTC_HSE_PRESCALER() - allowing to get the HSE - clock divider for RTC - peripheral
            • -
          -
        • Ensure reset - of CIR and CSR registers when - issuing HAL_RCC_DeInit()/LL_RCC_DeInit - functions
          • -
        • Update HAL_RCC_OscConfig() to - - - - - keep backup domain enabled - when configuring - respectively LSE and RTC - clock source
          • -
        • Add new HAL - interfaces allowing to control - the activation or deactivation - of PLLI2S and PLLSAI:
          • -
            -
          • HAL_RCCEx_EnablePLLI2S()
            • -
          • HAL_RCCEx_DisablePLLI2S()
            • -
          • HAL_RCCEx_EnablePLLSAI()
            • -
          • HAL_RCCEx_DisablePLLSAI()
            • -
          -
        -
      -
        -
      • LL - - - - RCC update 
        • -
          -
        • Add new LL - RCC macro
          • -
            -
          • LL_RCC_PLL_SetMainSource() allowing - to configure PLL main clock - source
            • -
          -
        -
      • LL - - - - FMC / LL FSMC update
        • -
          -
        • Add clear of - the PTYP bit to select the - PCARD mode in FMC_PCCARD_Init() - / FSMC_PCCARD_Init()
          • -
        -
      -

      V1.7.2 - - - - / 06-October-2017

      -

      Main Changes

      -
        -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • Fix - compilation warning with - GCC compiler
        • -
      • Remove - - - - Date and version - from header files
        • -
      • Update - - - - HAL drivers to refer to the - new CMSIS bit position - defines instead of usage the - POSITION_VAL() - macro
        • -
      • HAL - - - - Generic update
        • -
          -
        • stm32f4xx_hal_def.h - - - - file changes: 
          • -
            -
          • Update - __weak and __packed defined - values for ARM compiler
            • -
          • Update - __ALIGN_BEGIN and - __ALIGN_END defined values - for ARM compiler
            • -
          -
        • stm32f4xx_ll_system.h - - - - - file: - add LL_SYSCFG_REMAP_SDRAM - define
          • -
        -
      • HAL - - - - ADC update
        • -
          -
        • Fix wrong - definition of ADC channel - temperature sensor for - STM32F413xx and STM32F423xx - devices.
          • -
        -
      • HAL - - - - DMA update
        • -
          -
        • Update values - - - - for the following defines: - DMA_FLAG_FEIF0_4 and - DMA_FLAG_DMEIF0_4 
          • -
        -
      • HAL - - - - DSI update
        • -
          -
        • Fix Extra - warning with SW4STM32 compiler
          • -
        • Fix DSI - display issue when using EWARM - w/ high level optimization 
          • -
        • Fix - MISRAC errors
          • -
        -
      • HAL - - - - FLASH update
        • -
          -
        • HAL_FLASH_Unlock() update to - return state error when the - FLASH is already unlocked
          • -
        -
      • HAL - - - - FMPI2C update
        • -
          -
        • Update - Interface APIs headers to - remove confusing message about - device address
          • -
        • Update - FMPI2C_WaitOnRXNEFlagUntilTimeout() - to resolve a race condition - between STOPF and RXNE Flags
          • -
        • Update - FMPI2C_TransferConfig() - to fix wrong bit management.
          • -
        • Update code - comments to use DMA stream - instead of DMA channel
          • -
        -
      -
        -
      • HAL - - - - PWR update
        • -
          -
        • HAL_PWR_EnableWakeUpPin() update - description to add support of - PWR_WAKEUP_PIN2 and - PWR_WAKEUP_PIN3
          • -
        -
      • HAL - - - - NOR update
        • -
          -
        • Add the - support of STM32F412Rx devices
          • -
        -
      • HAL - - - - I2C update
        • -
          -
        • Update - Interface APIs headers to - remove confusing mesage - about device address
          • -
        • Update - I2C_MasterReceive_RXNE() - and I2C_MasterReceive_BTF() - static APIs to fix bad - Handling of NACK in I2C master - receive process.
          • -
        -
      -
        -
      • HAL - - - - RCC update
        • -
          -
        • Update HAL_RCC_GetOscConfig() - API to:
          • -
            -
          • set PLLR in - the RCC_OscInitStruct
            • -
          • check on - null pointer
            • -
          -
        • Update HAL_RCC_ClockConfig() - API to:
          • -
            -
          • check on - null pointer
            • -
          • optimize code - - - - size by updating the - handling method of the SWS bits
            • -
          • update to use  - - - - - __HAL_FLASH_GET_LATENCY() - - - - flash macro instead of using - direct register access - to LATENCY bits in - FLASH ACR register.
            • -
          -
        • Update HAL_RCC_DeInit() -  and LL_RCC_DeInit() - - - - - APIs to
          • -
            -
          • Be able to - return HAL/LL status
            • -
          • Add checks - for HSI, PLL and PLLI2S -  ready - before modifying RCC CFGR - registers
            • -
          • Clear all - interrupt falgs
            • -
          • Initialize - systick - interrupt period
            • -
          -
        • Update HAL_RCC_GetSysClockFreq() - to avoid risk of rounding - error which may leads to a - wrong returned value. 
          • -
        -
      -

       

      -

       

      -
        -
      • HAL - - - - RNG update
        • -
          -
        • HAL_RNG_Init() remove - Lock()/Unlock()
          • -
        -
      • HAL - - - - MMC update
        • -
          -
        • HAL_MMC_Erase() - API: add missing () to - fix compilation warning - detected with SW4STM32 when - extra feature is enabled.
          • -
        -
      • HAL - - - - RTC update
        • -
          -
        • HAL_RTC_Init() API: update - to force the wait for synchro - before setting TAFCR register - when BYPSHAD bit in CR - register is 0.
          • -
        -
      • HAL - - - - SAI update
        • -
          -
        • Update HAL_SAI_DMAStop() - API to flush fifo - after disabling SAI
          • -
        -
      • HAL - - - - I2S update
        • -
          -
        • Update I2S - DMA fullduplex process to - handle I2S Rx and Tx DMA Half - transfer complete callback
          • -
        -
      • HAL - - - - TIM update
        • -
          -
        • Update HAL_TIMEx_OCN_xxxx() - and HAL_TIMEx_PWMN_xxx() - - - - - API description to remove - support of TIM_CHANNEL_4
          • -
        -
      • LL - - - - DMA update
        • -
          -
        • Update to - clear DMA flags using WRITE_REG() - instead SET_REG() API to avoid - read access to the IFCR - register that is write only.
          • -
        -
      • LL - - - - RTC update
        • -
          -
        • Fix warning - with static analyzer
          • -
        -
      • LL - - - - USART update
        • -
          -
        • Add assert - macros to check USART BaudRate - register
          • -
        -
      • LL - - - - I2C update
        • -
          -
        • Rename - IS_I2C_CLOCK_SPEED() - and IS_I2C_DUTY_CYCLE() - respectively to - IS_LL_I2C_CLOCK_SPEED() and - IS_LL_I2C_DUTY_CYCLE() to - avoid incompatible macros - redefinition.
          • -
        -
      • LL - - - - TIM update
        • -
          -
        • Update LL_TIM_EnableUpdateEvent() - API to clear UDIS bit in TIM - CR1 register instead of - setting it.
          • -
        • Update LL_TIM_DisableUpdateEvent() - API to set UDIS bit in TIM CR1 - register instead of clearing - it.
          • -
        -
      • LL - - - - USART update
        • -
          -
        • Fix MISRA - error w/ IS_LL_USART_BRR() - macro
          • -
        • Fix wrong - check when UART10 instance is - used
          • -
        -
      -

      V1.7.1 - - - - / 14-April-2017

      -

      Main Changes

      -
        -
      • Update - - - - CHM UserManuals - to support LL drivers
        • -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • HAL - - - - CAN update
        • -
          -
        • Add - management of overrun - error. 
          • -
        • Allow - possibility to receive - messages from the 2 RX FIFOs - in parallel via interrupt.
          • -
        • Fix message - - - - lost issue with specific - sequence of transmit requests.
          • -
        • Handle - transmission failure with - error callback, when NART is - enabled.
          • -
        • Add - __HAL_CAN_CANCEL_TRANSMIT() - call to abort transmission - when timeout is reached
          • -
        -
      -
        -
      • HAL - - - - PWR update
        • -
          -
        • HAL_PWREx_EnterUnderDriveSTOPMode() API: remove - check on UDRDY flag
          • -
        -
      -
        -
      • LL - - - - ADC update
        • -
          -
        • Fix wrong ADC - group injected sequence configuration
          • -
            -
          • LL_ADC_INJ_SetSequencerRanks() and LL_ADC_INJ_GetSequencerRanks() - - - - - API's update to take in - consideration the ADC number - of conversions
            • -
          • Update - the defined values for - ADC group injected seqencer - ranks 
            • -
          -
        -
      -

      V1.7.0 - - - - / 17-February-2017

      -

      Main Changes

      -
        -
      • Add - - - - Low Layer drivers allowing - performance and footprint optimization
        • -
          -
        • Low Layer drivers - APIs provide register level - programming: require deep - knowledge of peripherals - described in STM32F4xx - Reference Manuals
          • -
        • Low Layer - drivers are available for: - ADC, Cortex, CRC, DAC, - DMA, DMA2D, EXTI, GPIO, I2C, - IWDG, LPTIM, PWR, RCC, RNG, - RTC, SPI, TIM, USART, WWDG - peripherals and additionnal - Low Level Bus, System and - Utilities APIs.
          • -
        • Low Layer drivers - APIs are implemented as static - inline function in new Inc/stm32f4xx_ll_ppp.h files - - - - - for PPP peripherals, there is - no configuration file and each stm32f4xx_ll_ppp.h file - - - - - must be included in user code.
          • -
        -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • Fix extra - - - - warnings with GCC compiler
        • -
      • HAL - drivers clean up: remove - double casting 'uint32_t' and 'U'
        • -
      • Add - new HAL - - - - MMC driver
        • -
      • The - - - - following changes done on the - HAL drivers require an update - on the application code based - on older HAL versions
        • -
          -
        • HAL SD update
          • -
            -
          • Overall - rework of the driver for a - more - efficient implementation
            • -
              -
            • Modify - initialization API and structures
              • -
            • Modify - Read / Write sequences: - separate transfer process - and SD Cards state management 
              • -
            • Adding - interrupt mode for Read / - Write operations
              • -
            • Update - the HAL_SD_IRQHandler - function by optimizing the - management of interrupt errors
              • -
            -
          • Refer to - the following example to - identify the changes: BSP - example and USB_Device/MSC_Standalone - application
            • -
          -
        • HAL NAND update
          • -
            -
          • Modify NAND_AddressTypeDef, - NAND_DeviceConfigTypeDef - and NAND_HandleTypeDef - structures fields
            • -
          • Add new HAL_NAND_ConfigDevice - API
            • -
          -
        • HAL DFSDM update
          • -
            -
          • Add - support of Multichannel - Delay feature
            • -
              -
            • Add HAL_DFSDM_ConfigMultiChannelDelay - API
              • -
            • The - following APIs are moved - to internal static - functions: HAL_DFSDM_ClockIn_SourceSelection, - HAL_DFSDM_ClockOut_SourceSelection, - HAL_DFSDM_DataInX_SourceSelection - (X=0,2,4,6), HAL_DFSDM_BitStreamClkDistribution_Config
              • -
            -
          -
        • HAL I2S update
          • -
            -
          • Add specific - - - - - callback API to manage I2S - full duplex end of transfer - process:
            • -
              -
            • HAL_I2S_TxCpltCallback() - and - HAL_I2S_RxCpltCallback() - API's will be replaced - with only - HAL_I2SEx_TxRxCpltCallback() - API. 
              • -
            -
          -
        -
      • HAL - - - - update
        • -
          -
        • Modifiy default HAL_Delay - implementation to guarantee - minimum delay 
          • -
        -
      • HAL - - - - Cortex update
        • -
          -
        • Move HAL_MPU_Disable() - and HAL_MPU_Enable() - - - - - from stm32f4xx_hal_cortex.h to - stm32f4xx_hal_cortex.c
          • -
        • Clear the - whole MPU control register - in HAL_MPU_Disable() - API
          • -
        -
      • HAL - - - - FLASH update
        • -
          -
        • IS_FLASH_ADDRESS() - macro update to support OTP - range
          • -
        • FLASH_Program_DoubleWord(): Replace - 64-bit accesses with 2 - double-words operations
          • -
        -
      • LL - - - - GPIO update
        • -
          -
        • Update - IS_GPIO_PIN() - macro implementation to be - more safe
          • -
        -
      • LL - - - - RCC update
        • -
          -
        • Update - IS_RCC_PLLQ_VALUE() - macro implementation: the - minimum accepted value is - 2 instead of 4
          • -
        • Rename - RCC_LPTIM1CLKSOURCE_PCLK - define to - RCC_LPTIM1CLKSOURCE_PCLK1
          • -
        • Fix - compilation issue w/ - __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() - and - __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() - macros for STM32F401xx devices
          • -
        • Add the - following is clock - enabled macros for STM32F401xx - devices
          • -
            -
          •  __HAL_RCC_SDIO_IS_CLK_ENABLED()
            • -
          • __HAL_RCC_SPI4_IS_CLK_ENABLED()
            • -
          • __HAL_RCC_TIM10_IS_CLK_ENABLED()
            • -
          -
        • Add the - following is clock - enabled macros for STM32F410xx - devices
          • -
            -
          •  __HAL_RCC_CRC_IS_CLK_ENABLED()
            • -
          • __HAL_RCC_RNG_IS_CLK_ENABLED()
            • -
          -
        • Update HAL_RCC_DeInit() - to reset the RCC clock - configuration to the default - reset state.
          • -
        • Remove macros - to configure BKPSRAM from - STM32F401xx devices 
          • -
        • Update to - refer to AHBPrescTable[] - and APBPrescTable[] - - - - - tables defined in - system_stm32f4xx.c file - instead of APBAHBPrescTable[] - - - - - table.
          • -
        -
      • HAL - - - - FMPI2C update
        • -
          -
        • Add - FMPI2C_FIRST_AND_NEXT_FRAME - define in Sequential - Transfer Options
          • -
        -
      • HAL - - - - ADC update
        • -
          -
        • HAL_ADCEx_InjectedConfigChannel(): update the - external trigger injected - condition
          • -
        -
      • HAL - - - - DMA update
        • -
          -
        • HAL_DMA_Init(): update to - check compatibility between - FIFO threshold level and size - of the memory burst 
          • -
        -
      • HAL - - - - QSPI update
        • -
          -
        • QSPI_HandleTypeDef structure: - Update transfer parameters on - uint32_t instead of uint16_t
          • -
        -
      • HAL - - - - UART/USART/IrDA/SMARTCARD update
        • -
          -
        • DMA Receive - process; the code has been - updated to clear the USART - OVR flag before - enabling DMA receive - request.
          • -
        • UART_SetConfig() update to - manage correctly USART6 - instance that is not available - on STM32F410Tx devices
          • -
        -
      • HAL - - - - CAN update
        • -
          -
        • Remove Lock - mechanism from HAL_CAN_Transmit_IT() - and HAL_CAN_Receive_IT() - - - - - processes
          • -
        -
      • HAL - - - - TIM update
        • -
          -
        • Add - __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() - macro to disable Master output - without check on TIM channel - state. 
          • -
        • Update HAL_TIMEx_ConfigBreakDeadTime() - to fix TIM BDTR register - corruption.
          • -
        -
      • HAL - - - - I2C update
        • -
          -
        • Update - HAL_I2C_Master_Transmit() - and HAL_I2C_Slave_Transmit() - to avoid sending extra - bytes at the end of the - transmit processes
          • -
        • Update - HAL_I2C_Mem_Read() - API to fix wrong check on - misused parameter �Size�
          • -
        • Update - I2C_MasterReceive_RXNE() - and I2C_MasterReceive_BTF() - static APIs to enhance Master - sequential reception process.
          • -
        -
      • HAL - - - - SPI update
        • -
          -
        • Add transfer - abort APIs and associated - callbacks in interrupt mode
          • -
            -
          • HAL_SPI_Abort()
            • -
          • HAL_SPI_Abort_IT()
            • -
          • HAL_SPI_AbortCpltCallback()
            • -
          -
        -
      • HAL - - - - I2S update
        • -
          -
        • Add specific - - - - - callback API to manage I2S - full duplex end of transfer - process:
          • -
            -
          • HAL_I2S_TxCpltCallback() - and HAL_I2S_RxCpltCallback() - API's will be replaced with - only - HAL_I2SEx_TxRxCpltCallback() - API. 
            • -
          -
        • Update I2S - Transmit/Receive polling - process to manage Overrun - and Underrun errors
          • -
        • Move - the I2S clock input - frequency calculation to - HAL RCC driver.
          • -
        • Update the - HAL I2SEx driver to keep only - full duplex feature.
          • -
        • HAL_I2S_Init() - API updated to
          • -
            -
          • Fix wrong - I2S clock calculation when - PCM mode is used.
            • -
          • Return - state HAL_I2S_ERROR_PRESCALER when - the I2S clock is wrongly configured
            • -
          -
        -
      -
        -
      • HAL - - - - LTDC update
        • -
          -
        • Optimize HAL_LTDC_IRQHandler() - function by using direct - register read
          • -
        • Rename the - following API's
          • -
            -
          • HAL_LTDC_Relaod() by HAL_LTDC_Reload() 
            • -
          • HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()
            • -
          • HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()
            • -
          -
        • Add new - defines for LTDC layers - (LTDC_LAYER_1 / LTDC_LAYER_2)
          • -
        • Remove unused - asserts
          • -
        -
      • HAL - - - - USB PCD - update
        • -
          -
        • Flush all TX - FIFOs on USB Reset
          • -
        • Remove Lock - mechanism from HAL_PCD_EP_Transmit() - and HAL_PCD_EP_Receive() - - - - - API's
          • -
        -
      -
        -
      • LL - - - - USB update
        • -
          -
        • Enable DMA - Burst mode for USB OTG HS
          • -
        • Fix SD card - detection issue
          • -
        -
      • LL - - - - SDMMC update
        • -
          -
        • Add new SDMMC_CmdSDEraseStartAdd, - SDMMC_CmdSDEraseEndAdd, - SDMMC_CmdOpCondition - and SDMMC_CmdSwitch - functions
          • -
        -
      -

      V1.6.0 - - - - / 04-November-2016

      -

      Main Changes

      -
        -
      • Add support of STM32F413xx - and STM32F423xx - devices
        • -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • HAL - - - - CAN update
        • -
          -
        • Update to add - the support of 3 CAN management
          • -
        -
      • HAL - - - - CRYP update
        • -
          -
        • Update to add - the support of AES features
          • -
        -
      • HAL - - - - DFSDM update
        • -
          -
        • Add - definitions for new external - trigger filters
          • -
        • Add - definition for new Channels - 4, 5, 6 and 7
          • -
        • Add - functions and API for Filter - state configuration and management
          • -
        • Add new - functions: 
          • -
            -
          • HAL_DFSDM_BitstreamClock_Start()
            • -
          • HAL_DFSDM_BitstreamClock_Stop()
            • -
          • HAL_DFSDM_BitStreamClkDistribution_Config() 
            • -
          -
        -
      • HAL - - - - DMA
        • -
          -
        • Add the - support of DMA Channels from - 8 to 15
          • -
        • Update HAL_DMA_DeInit() - function with the check on - DMA stream instance
          • -
        -
      • HAL - - - - DSI update
        • -
      -
        -
          -
        • Update HAL_DSI_ConfigHostTimeouts() - and HAL_DSI_Init() - - - - - functions to avoid scratch in - DSI_CCR register
          • -
        -
      • HAL - - - - FLASH update
        • -
          -
        • Enhance FLASH_WaitForLastOperation() - function implementation
          • -
        • Update - __HAL_FLASH_GET_FLAG() - macro implementation
          • -
        -
      • HAL - - - - GPIO update
        • -
          -
        • Add - specific alternate functions - definitions
          • -
        -
      • HAL - - - - I2C update
        • -
          -
        • Update I2C_DMAError() - function implementation to - ignore DMA FIFO error
          • -
        -
      • HAL - - - - I2S update
        • -
          -
        • Enhance - HAL_I2S_Init() - implementation to test on - PCM_SHORT and PCM_LONG - standards
          • -
        -
      • HAL - - - - IRDA update
        • -
          -
        • Add new - functions and call backs for - Transfer Abort
          • -
            -
          • HAL_IRDA_Abort()
            • -
          • HAL_IRDA_AbortTransmit()
            • -
          • HAL_IRDA_AbortReceive()
            • -
          • HAL_IRDA_Abort_IT()
            • -
          • HAL_IRDA_AbortTransmit_IT()
            • -
          • HAL_IRDA_AbortReceive_IT()
            • -
          • HAL_IRDA_AbortCpltCallback()
            • -
          • HAL_IRDA_AbortTransmitCpltCallback()
            • -
          -
        -
      -
        -
          -
            -
          • HAL_IRDA_AbortReceiveCpltCallback()
            • -
          -
        -
      • HAL - - - - PCD update
        • -
      -
        -
          -
        • Update HAL_PCD_GetRxCount() -  function implementation
          • -
        -
      • HAL - - - - RCC update
        • -
          -
        • Update - __HAL_RCC_HSE_CONFIG() - macro implementation
          • -
        • Update __HAL_RCC_LSE_CONFIG() - macro implementation
          • -
        -
      • HAL - - - - SMARTCARD update
        • -
      -
        -
          -
        • Add new - functions and call backs for - Transfer Abort
          • -
            -
          • HAL_ SMARTCARD_Abort()
            • -
          • HAL_ SMARTCARD_AbortTransmit()
            • -
          • HAL_ SMARTCARD_AbortReceive()
            • -
          • HAL_ SMARTCARD_Abort_IT()
            • -
          • HAL_ SMARTCARD_AbortTransmit_IT()
            • -
          • HAL_ SMARTCARD_AbortReceive_IT()
            • -
          • HAL_ SMARTCARD_AbortCpltCallback()
            • -
          • HAL_ SMARTCARD_AbortTransmitCpltCallback()
            • -
          • HAL_ SMARTCARD_AbortReceiveCpltCallback()
            • -
          -
        -
      • HAL - - - - TIM update
        • -
          -
        • Update HAL_TIMEx_RemapConfig() - function to manage TIM - internal trigger remap: - LPTIM or TIM3_TRGO
          • -
        -
      • HAL - - - - UART update
        • -
          -
        • Add - Transfer abort functions and - callbacks
          • -
        -
      • HAL - - - - USART update
        • -
          -
        • Add - Transfer abort functions and - callbacks
          • -
        -
      -

      V1.5.2 - - - - / 22-September-2016

      -

      Main Changes

      -
        -
      • HAL - - - - I2C update
        • -
          -
        • Fix wrong - behavior in consecutive - transfers in case of single - byte transmission - (Master/Memory Receive
          - interfaces)
          • -
        • Update - HAL_I2C_Master_Transmit_DMA() - / - HAL_I2C_Master_Receive_DMA()/ - HAL_I2C_Slave_Transmit_DMA()
          - and - HAL_I2C_Slave_Receive_DMA() to - manage addressing phase - through interruption instead - of polling
          • -
        • Add - a check on I2C handle - state at start of all I2C - API's to ensure that I2C is ready
          • -
        • Update I2C - API's (Polling, IT and DMA - interfaces) to manage I2C XferSize - and XferCount - handle parameters instead of - API size parameter to help - user to get information of - counter in case of - error. 
          • -
        • Update Abort - functionality to manage DMA - use case
          • -
        -
      • HAL - - - - FMPI2C update
        • -
          -
        • Update to - disable Own Address - before setting the new Own - Address - configuration:
          • -
            -
          • Update - HAL_FMPI2C_Init() - to disable FMPI2C_OARx_EN - bit before any - configuration in OARx - registers
            • -
          -
        -
      • HAL - - - - CAN update
        • -
          -
        • Update CAN - receive processes to set CAN - RxMsg - FIFONumber - parameter
          • -
        -
      • HAL - - - - UART update
        • -
          -
        • Update UART - - - - handle TxXferCount - and RxXferCount parameters - - - - - as volatile to avoid - eventual issue with High Speed - optimization  
          • -
        -
      -

      V1.5.1 - - - - / 01-July-2016

      -

      Main Changes

      -
        -
      • HAL - - - - GPIO update
        • -
          -
        • HAL_GPIO_Init()/HAL_GPIO_DeInit() - API's: - update GPIO_GET_INDEX() - macro implementation to - support all GPIO's
          • -
        -
      • HAL - - - - SPI update
        • -
          -
        • Fix - regression issue: - retore HAL_SPI_DMAPause() - and HAL_SPI_DMAResume() API's -
          • -
        -
      • HAL - - - - RCC update
        • -
          -
        • Fix FSMC - macros compilation warnings - with STM32F412Rx devices
          • -
        -
      • HAL - - - - DMA update
        • -
          -
        • HAL_DMA_PollFortransfer() API clean - up
          -
          -
          • -
        -
      • HAL - - - - PPP update(PPP refers to - IRDA, UART, USART and SMARTCARD)
        • -
          -
        • Update - - - - HAL_PPP_IRQHandler() - to add a check on interrupt - source before managing the - error 
          • -
        -
      -
        -
      • HAL - - - - QSPI update
        • -
          -
        • Implement - workaround to fix the - limitation pronounced - - - - in - the Errata - sheet 2.1.8 section: - In some specific cases, - DMA2 data corruption - occurs when managing AHB - and APB2 peripherals in a - concurrent way
          • -
        -
      -

      V1.5.0 - - - - / 06-May-2016

      -

      Main Changes

      -
        -
      • Add support of STM32F412cx, - - - - - STM32F412rx, STM32F412vx and - STM32F412zx devices
        • -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • Add - new HAL driver for DFSDM peripheral
        • -
      • Enhance - - - - HAL delay and time base - implementation:
        • -
          -
        • Add new - drivers - stm32f4xx_hal_timebase_rtc_alarm_template.c - and - stm32f4xx_hal_timebase_rtc_wakeup_template.c - which override the native HAL - time base functions (defined - as weak) to either use the RTC - as time base tick source. For - more details about the usage - of these drivers, please refer - to HAL\HAL_TimeBase_RTC - examples and - - - - - FreeRTOS-based - - - - - applications
          • -
        -
      • The - - - - following changes done on the - HAL drivers require an update - on the application code based - on HAL V1.4.4
        • -
          -
        • HAL UART, - USART, IRDA, SMARTCARD, SPI, - I2C,FMPI2C, - - - - - QSPI (referenced - as PPP here - - - - - below) drivers
          • -
            -
          • Add PPP - error management during DMA - process. This requires the - following updates - on user application:
            • -
              -
            • Configure - and enable the PPP IRQ in - HAL_PPP_MspInit() - function
              • -
            • In stm32f4xx_it.c - - - - - file, PPP_IRQHandler() - function: add - - - - - a call to HAL_PPP_IRQHandler() - - - - - function
              • -
            • Add and - customize the Error - Callback API: HAL_PPP_ErrorCallback()
              • -
            -
          -
        • HAL I2C, FMPI2C (referenced - as PPP here - - - - - below) drivers:
          • -
            -
          • Update to - avoid waiting on STOPF/BTF/AF - - - - - flag under DMA ISR by using - the PPP - - - - end of transfer interrupt in - the DMA transfer process. This - - - - - requires the following - updates on user - application:
            • -
              -
            • Configure - and enable the PPP IRQ in - HAL_PPP_MspInit() - function
              • -
            • In stm32f4xx_it.c - - - - - file, PPP_IRQHandler() - function: add - - - - - a call to HAL_PPP_IRQHandler() - - - - - function
              • -
            -
          -
        • HAL I2C driver:
          • -
            -
          • I2C - transfer processes IT - update: NACK during - addressing phase is managed - through I2C Error - interrupt instead of - HAL state
            • -
          -
        -
      -
        -
          -
        • HAL IWDG driver: - rework overall driver for - better implementation
          • -
            -
          • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() - - - - - and HAL_IWDG_GetState() APIs
            • -
          -
        • HAL WWDG driver: - rework overall driver for - better implementation
          • -
            -
          • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() - - - - - and HAL_WWDG_GetState() - - - - - APIs 
            • -
          • Update - the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, - uint32_t counter) -  function and API -  by removing the -  "counter" parameter
            • -
          -
        • HAL QSPI - driver:  Enhance - the DMA transmit process - by using PPP TC - interrupt instead of waiting - on TC flag under DMA - ISR. This requires the - following updates on user - application:
          • -
            -
          • Configure - and enable the QSPI IRQ - in HAL_QSPI_MspInit() - function
            • -
          • In stm32f4xx_it.c - - - - - file, QSPI_IRQHandler() - function: add - - - - a call to HAL_QSPI_IRQHandler() - - - - - function
            • -
          -
        • HAL CEC - driver:  Overall - driver rework with - compatibility break versus - previous HAL version
          • -
            -
          • Remove HAL - CEC polling Process - functions: HAL_CEC_Transmit() - and HAL_CEC_Receive()
            • -
          • Remove HAL - CEC receive interrupt - process function HAL_CEC_Receive_IT() - and enable the "receive" -  mode during the Init - phase
            • -
          • Rename HAL_CEC_GetReceivedFrameSize() - funtion - to HAL_CEC_GetLastReceivedFrameSize()
            • -
          • Add new HAL - APIs: HAL_CEC_SetDeviceAddress() - and HAL_CEC_ChangeRxBuffer()
            • -
          • Remove - the 'InitiatorAddress' - field from the CEC_InitTypeDef - structure and manage - it as a parameter in - the HAL_CEC_Transmit_IT() - function
            • -
          • Add new - parameter 'RxFrameSize' - in HAL_CEC_RxCpltCallback() - function
            • -
          • Move CEC Rx - buffer pointer from CEC_HandleTypeDef - structure to CEC_InitTypeDef - structure
            • -
          -
        -
      -
        -
      • HAL - - - - RCC update
        • -
          -
        • Update HAL_RCC_ClockConfig() - function to adjust the SystemCoreClock
          • -
        • Rename macros - and Literals:
          • -
            -
          • RCC_PERIPHCLK_CK48 by RCC_PERIPHCLK_CLK48
            • -
          • IS_RCC_CK48CLKSOURCE by - - - - - IS_RCC_CLK48CLKSOURCE
            • -
          • RCC_CK48CLKSOURCE_PLLSAIP - - - - - by RCC_CLK48CLKSOURCE_PLLSAIP
            • -
          • RCC_SDIOCLKSOURCE_CK48 - - - - by RCC_SDIOCLKSOURCE_CLK48
            • -
          • RCC_CK48CLKSOURCE_PLLQ - - - - - by RCC_CLK48CLKSOURCE_PLLQ
            • -
          -
        • Update HAL_RCCEx_GetPeriphCLKConfig() - and HAL_RCCEx_PeriphCLKConfig() - - - - - functions to support TIM Prescaler - for STM32F411xx devices
          • -
        • HAL_RCCEx_PeriphCLKConfig() API: update - to fix the RTC clock - configuration issue
          • -
        -
      • HAL - - - - CEC update
        • -
          -
        • Overall - driver rework with break - of compatibility with HAL - V1.4.4
          • -
            -
          • Remove the - HAL CEC polling Process: HAL_CEC_Transmit() - and HAL_CEC_Receive()
            • -
          -
        -
      -
        -
          -
            -
          • Remove the - HAL CEC receive interrupt - process (HAL_CEC_Receive_IT()) - - - - - and manage the "Receive" - mode enable within the Init - phase
            • -
          • Rename HAL_CEC_GetReceivedFrameSize() - function to HAL_CEC_GetLastReceivedFrameSize() - - - - - function
            • -
          • Add new HAL - APIs: HAL_CEC_SetDeviceAddress() - and HAL_CEC_ChangeRxBuffer()
            • -
          • Remove - the 'InitiatorAddress' - field from the CEC_InitTypeDef - structure and manage - it as a parameter in - the HAL_CEC_Transmit_IT() - function
            • -
          • Add new - parameter 'RxFrameSize' - in HAL_CEC_RxCpltCallback() - function
            • -
          • Move CEC Rx - buffer pointer from CEC_HandleTypeDef - structure to CEC_InitTypeDef - structure
            • -
          -
        • Update driver - to implement the new CEC state - machine:
          • -
            -
          • Add - new "rxState" field - - - - - in CEC_HandleTypeDef - structure to provide the CEC state - - - - - information related to Rx Operations
            • -
          • Rename - "state" field in CEC_HandleTypeDef - structure to "gstate": - - - - CEC state - - - - - information related to - global Handle management and - Tx Operations
            • -
          • Update CEC - process to manage the new - CEC states.
            • -
          • Update - __HAL_CEC_RESET_HANDLE_STATE() - macro to handle the new CEC - state parameters (gState, - rxState)
            • -
          -
        -
      -
        -
      • HAL - - - - UART, USART, SMARTCARD and - IRDA (referenced - - - - as PPP here below) update
        • -
          -
        • Update - Polling management:
          • -
            -
          • The user - Timeout value must be - estimated for the overall - process duration: the - Timeout measurement is - cumulative
            • -
          -
        • Update DMA - process:
          • -
            -
          • Update the - management of PPP peripheral - errors during DMA process. - This requires the following - updates in user application:
            • -
              -
            • Configure - and enable the PPP IRQ in - HAL_PPP_MspInit() - function
              • -
            • In - stm32f4xx_it.c file, PPP_IRQHandler() - function: add a call to HAL_PPP_IRQHandler() - - - - - function
              • -
            • Add and - customize the Error - Callback API: HAL_PPP_ErrorCallback()
              • -
            -
          -
        -
      • HAL - - - - FMC update
        • -
          -
        • Update FMC_NORSRAM_Init() - to remove the Burst access - mode configuration
          • -
        • Update FMC_SDRAM_Timing_Init() - to fix initialization issue - when configuring 2 SDRAM banks
          • -
        -
      • HAL - - - - HCD update
        • -
          -
        • Update HCD_Port_IRQHandler() - to unmask disconnect IT only - when the port is disabled
          • -
        -
      • HAL - - - - I2C/FMPI2C - update
        • -
          -
        • Update Polling - - - - - management:
          • -
            -
          • The Timeout - value must be estimated for - the overall process - duration: the - Timeout measurement is - cumulative
            • -
          -
        • Add the - management of Abort - service: Abort DMA - transfer through interrupt
          • -
            -
          • In the case - of Master Abort IT transfer - usage:
            • -
              -
            • Add new - - - - user HAL_I2C_AbortCpltCallback() - to inform user of the end - of abort process
              • -
            • A new - abort state is defined in - the HAL_I2C_StateTypeDef structure
              • -
            -
          -
        • Add the - management of I2C peripheral - errors, ACK failure and STOP - condition detection during DMA - process. This requires the - following updates on user - application:
          • -
            -
          • Configure - and enable the I2C IRQ in - HAL_I2C_MspInit() - function
            • -
          • In - stm32f4xx_it.c file, I2C_IRQHandler() - function: add a call to - HAL_I2C_IRQHandler() - function
            • -
          • Add and - customize the Error Callback - API: HAL_I2C_ErrorCallback()
            • -
          • Refer to - the I2C_EEPROM or - I2C_TwoBoards_ComDMA project - examples usage of the API
            • -
          -
        • NACK error - during addressing phase is - returned through interrupt - instead of previously through - I2C transfer API's
          • -
        • I2C - addressing phase is updated to - be managed using interrupt - instead of polling (Only - for HAL I2C driver)
          • -
            -
          • Add new - static functions to manage - I2C SB, ADDR and ADD10 flags
            • -
          -
        -
      • HAL - - - - SPI update
        • -
      -
        -
          -
        • Overall - driver optimization to improve - performance in - polling/interrupt mode to - reach maximum peripheral frequency
          • -
            -
          • Polling - mode:
            • -
              -
            • Replace - the use of SPI_WaitOnFlagUnitTimeout() - function by "if" statement - to check on RXNE/TXE flage - while transferring data
              • -
            -
          -
        -
      -
        -
          -
            -
          •  Interrupt - - - - mode:
            • -
              -
            • Minimize - access on SPI registers
              • -
            -
          • All modes:
            • -
              -
            • Add the - USE_SPI_CRC switch to - minimize the number of - statements when CRC - calculation is disabled
              • -
            • Update timeout - - - - - management to check on - global processes
              • -
            • Update - error code management in - all processes
              • -
            -
          -
        • Update DMA - process:
          • -
            -
          • Add the - management of SPI peripheral - errors during DMA process. - This requires the following - updates in the user - application:
            • -
              -
            • Configure - and enable the SPI IRQ in - HAL_SPI_MspInit() - function
              • -
            • In - stm32f4xx_it.c file, SPI_IRQHandler() - function: add a call to HAL_SPI_IRQHandler() - - - - - function
              • -
            • Add and - customize the Error - Callback API: HAL_SPI_ErrorCallback()
              • -
            • Refer to - the following example - which describe the - changes: SPI_FullDuplex_ComDMA
              • -
            -
          -
        • Fix - regression in polling mode:
          • -
            -
          • Add - preparing data to transmit - in case of slave mode in HAL_SPI_TransmitReceive() - and HAL_SPI_Transmit()
            • -
          • Add to - manage properly the overrun - flag at the end of a HAL_SPI_TransmitReceive()
            • -
          -
        • Fix - regression in interrupt mode:
          • -
            -
          • Add a wait - on TXE flag in SPI_CloseTx_ISR() - and in SPI_CloseTxRx_ISR()
            • -
          • Add to - manage properly - the overrun flag in SPI_CloseRxTx_ISR() - and SPI_CloseRx_ISR()
            • -
          -
        -
      -
        -
      • HAL - - - - DMA2D update
        • -
          -
        • Update the - HAL_DMA2D_DeInit() - function to:
          • -
            -
          • Abort - transfer in case of ongoing - DMA2D transfer
            • -
          • Reset DMA2D - control registers
            • -
          -
        • Update - HAL_DMA2D_Abort() - to disable DMA2D interrupts - after stopping transfer
          • -
        • Optimize - HAL_DMA2D_IRQHandler() - by reading status registers - only once
          • -
        • Update - HAL_DMA2D_ProgramLineEvent() - function to:
          • -
            -
          • Return HAL - error state in case of wrong - line value
            • -
          • Enable line - interrupt after setting the - line watermark configuration
            • -
          -
        • Add new - HAL_DMA2D_CLUTLoad() - and HAL_DMA2D_CLUTLoad_IT() functions - - - - - to start DMA2D CLUT loading
          • -
            -
          • HAL_DMA2D_CLUTLoading_Abort() - function to abort the DMA2D - CLUT loading
            • -
          • HAL_DMA2D_CLUTLoading_Suspend() - function to suspend the - DMA2D CLUT loading
            • -
          • HAL_DMA2D_CLUTLoading_Resume() - function to resume the DMA2D - CLUT loading
            • -
          -
        • Add new DMA2D - dead time management:
          • -
            -
          • HAL_DMA2D_EnableDeadTime() - function to enable DMA2D - dead time feature
            • -
          • HAL_DMA2D_DisableDeadTime() - function to disable DMA2D - dead time feature
            • -
          • HAL_DMA2D_ConfigDeadTime() - function to configure dead - time
            • -
          -
        • Update the - name of DMA2D Input/Output - color mode defines to be more - - - - clear for - user (DMA2D_INPUT_XXX for - input layers Colors, - DMA2D_OUTPUT_XXX for output - framebuffer Colors)
          • -
        -
      -
        -
      • HAL - - - - LTDC update
        • -
      -
        -
          -
        • Update HAL_LTDC_IRQHandler() - to manage the case of reload - interrupt
          • -
        • Add new - callback API HAL_LTDC_ReloadEventCallback()
          • -
        • Add HAL_LTDC_Reload() - to configure LTDC reload - feature
          • -
        • Add new No - Reload LTDC variant APIs
          • -
            -
          • HAL_LTDC_ConfigLayer_NoReload() to - configure the LTDC Layer - according to the specified - without reloading
            • -
          • HAL_LTDC_SetWindowSize_NoReload() to set - the LTDC window size without - reloading
            • -
          • HAL_LTDC_SetWindowPosition_NoReload() to set - the LTDC window position - without reloading
            • -
          • HAL_LTDC_SetPixelFormat_NoReload() to - reconfigure the pixel format - without reloading
            • -
          • HAL_LTDC_SetAlpha_NoReload() to - reconfigure the layer alpha - value without reloading
            • -
          • HAL_LTDC_SetAddress_NoReload() to - reconfigure the frame buffer - Address without reloading
            • -
          • HAL_LTDC_SetPitch_NoReload() to - reconfigure the pitch for - specific cases
            • -
          • HAL_LTDC_ConfigColorKeying_NoReload() to - configure the color keying - without reloading
            • -
          • HAL_LTDC_EnableColorKeying_NoReload() to enable - the color keying without - reloading
            • -
          • HAL_LTDC_DisableColorKeying_NoReload() to - disable the color keying - without reloading
            • -
          • HAL_LTDC_EnableCLUT_NoReload() to enable - the color lookup table - without reloading
            • -
          • HAL_LTDC_DisableCLUT_NoReload() to - disable the color lookup - table without reloading
            • -
          • Note: Variant - functions with �_NoReload� - post fix allows to set the - LTDC configuration/settings - without immediate reload. - This is useful in case when - the program requires to - modify several LTDC settings - (on one or both layers) then - applying (reload) these - settings in one shot by - calling the function �HAL_LTDC_Reload�
            • -
          -
        -
      • HAL - - - - RTC update 
        • -
          -
        • Add new - timeout implementation based - on cpu - cycles - for ALRAWF, ALRBWF - and WUTWF flags
          • -
        -
      -
        -
      • HAL - - - - SAI update
        • -
          -
        • Update SAI - state in case of TIMEOUT error - within the HAL_SAI_Transmit() - / HAL_SAI_Receive()
          • -
        • Update HAL_SAI_IRQHandler:
          • -
            -
          • Add error - management in case DMA - errors through XferAbortCallback() - and HAL_DMA_Abort_IT()
            • -
          • Add error - management in case of IT
            • -
          -
        • Move SAI_BlockSynchroConfig() - and SAI_GetInputClock() - - - - - functions to - stm32f4xx_hal_sai.c/.h files - (extension files are kept - empty for projects - compatibility reason)
          • -
        -
      -
        -
      • HAL - - - - DCMI update
        • -
          -
        • Rename DCMI_DMAConvCplt - to DCMI_DMAXferCplt
          • -
        • Update HAL_DCMI_Start_DMA() - function to Enable the - DCMI peripheral
          • -
        • Add new - timeout implementation based - on cpu - cycles for DCMI stop
          • -
        • Add HAL_DCMI_Suspend() - function to suspend DCMI - capture
          • -
        • Add HAL_DCMI_Resume() - function to resume capture - after DCMI suspend
          • -
        • Update lock - mechanism for DCMI process
          • -
        • Update HAL_DCMI_IRQHandler() - function to:
          • -
            -
          • Add error - management in case DMA - errors through XferAbortCallback() - and HAL_DMA_Abort_IT()
            • -
          • Optimize - code by using direct - register read
            • -
          -
        -
      -
        -
      • HAL - - - - DMA - update
        • -
          -
        • Add new APIs - HAL_DMA_RegisterCallback() - and HAL_DMA_UnRegisterCallback - to register/unregister the - different callbacks identified - by the enum - typedef HAL_DMA_CallbackIDTypeDef
          • -
        • Add new API HAL_DMA_Abort_IT() - to abort DMA transfer under - interrupt context
          • -
            -
          • The new - registered Abort callback is - called when DMA transfer - abortion is completed
            • -
          -
        • Add the check - of compatibility between FIFO - threshold level and size of - the memory burst in the HAL_DMA_Init() - API
          • -
        • Add new Error - Codes: HAL_DMA_ERROR_PARAM, - HAL_DMA_ERROR_NO_XFER and - HAL_DMA_ERROR_NOT_SUPPORTED
          • -
        • Remove all - DMA states related to - MEM0/MEM1 in HAL_DMA_StateTypeDef
          • -
        -
      • HAL - - - - IWDG - update
        • -
          -
        • Overall - rework of the driver for a - more - efficient implementation
          • -
            -
          • Remove the - following APIs:
            • -
              -
            • HAL_IWDG_Start()
              • -
            • HAL_IWDG_MspInit()
              • -
            • HAL_IWDG_GetState()
              • -
            -
          • Update - implementation:
            • -
              -
            • HAL_IWDG_Init(): this - function insures the - configuration and the - start of the IWDG counter
              • -
            • HAL_IWDG_Refresh(): this - function insures the - reload of the IWDG counter
              • -
            -
          • Refer to - the following example to - identify the changes: IWDG_Example
            • -
          -
        -
      • HAL - - - - LPTIM - update
        • -
          -
        • Update HAL_LPTIM_TimeOut_Start_IT() - and HAL_LPTIM_Counter_Start_IT( - ) APIs to configure WakeUp - Timer EXTI interrupt to be - able to wakeup - MCU from low power mode by - pressing the EXTI line.
          • -
        • Update HAL_LPTIM_TimeOut_Stop_IT() - and HAL_LPTIM_Counter_Stop_IT( - ) APIs to disable WakeUp - Timer EXTI interrupt. 
          • -
        -
      • HAL - - - - NOR update
        • -
          -
        • Update - NOR_ADDR_SHIFT macro implementation
          • -
        -
      • HAL - - - - PCD update
        • -
          -
        • Update HAL_PCD_IRQHandler() - to get HCLK frequency before - setting TRDT value
          • -
        -
      • HAL - - - - QSPI - update
        • -
      -
        -
          -
        • Update to - manage QSPI error management - during DMA process
          • -
        • Improve the - DMA transmit process by using - QSPI TC interrupt instead of - waiting loop on TC flag under - DMA ISR
          • -
        • These two - improvements require the - following updates on user - application:
          • -
            -
          • Configure - and enable the QSPI IRQ in HAL_QSPI_MspInit() - function
            • -
          • In - stm32f4xx_it.c file, QSPI_IRQHandler() - function: add a call to HAL_QSPI_IRQHandler() - - - - function
            • -
          • Add and - customize the Error Callback - API: HAL_QSPI_ErrorCallback()
            • -
          -
        • Add the - management of non-blocking - transfer abort service: HAL_QSPI_Abort_IT(). - - - - - In this case the user must:
          • -
            -
          • Add new - callback HAL_QSPI_AbortCpltCallback() - to inform user at the end of - abort process
            • -
          • A new value - of State in the HAL_QSPI_StateTypeDef - provides the current state - during the abort phase
            • -
          -
        • Polling - management update:
          • -
            -
          • The Timeout - value user must be estimated - for the overall process - duration: the - Timeout measurement is - cumulative. 
            • -
          -
        • Refer to the - following examples, which - describe the changes:
          • -
            -
          • QSPI_ReadWrite_DMA
            • -
          • QSPI_MemoryMapped
            • -
          • QSPI_ExecuteInPlace
            • -
          -
        -
      -
        -
          -
        • Add two new - APIs for the QSPI fifo - threshold:
          • -
            -
          • HAL_QSPI_SetFifoThreshold(): - configure the FIFO threshold - of the QSPI
            • -
          • HAL_QSPI_GetFifoThreshold(): give the - current FIFO threshold
            • -
          -
        • Fix wrong - data size management in HAL_QSPI_Receive_DMA()
          • -
        -
      -
        -
      • HAL - - - - ADC update
        • -
          -
        • Add new - __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() - macro for STM32F42x and - STM32F43x devices to - provide the possibility - to convert VrefInt - channel when both VrefInt - and Vbat - channels are selected.
          • -
        -
      • HAL - - - - SPDIFRX update
        • -
          -
        • Overall driver - update for wait on flag - management optimization 
          • -
        -
      • HAL - - - - WWDG update 
        • -
          -
        • Overall - rework of the driver for more - efficient implementation
          • -
            -
          • Remove the - following APIs:
            • -
              -
            • HAL_WWDG_Start()
              • -
            • HAL_WWDG_Start_IT()
              • -
            • HAL_WWDG_MspDeInit()
              • -
            • HAL_WWDG_GetState()
              • -
            -
          • Update - implementation:
            • -
              -
            • HAL_WWDG_Init()
              • -
                -
              • A new - - - - parameter in the Init - Structure: EWIMode
                • -
              -
            • HAL_WWDG_MspInit()
              • -
            • HAL_WWDG_Refresh() 
              • -
                -
              • This - function insures the - reload of the counter
                • -
              • The - "counter" parameter has - been removed
                • -
              -
            • HAL_WWDG_IRQHandler()
              • -
            • HAL_WWDG_EarlyWakeupCallback() is the - new prototype of HAL_WWDG_WakeUpCallback()
              • -
            -
          -
        • Refer to the - following example to identify - the changes: WWDG_Example
          • -
        -
      -

      V1.4.4 - - - - / 22-January-2016

      -

      Main Changes

      -
        -
      • HAL - - - - Generic update
        • -
          -
        • stm32f4xx_hal_conf_template.h
          • -
            -
          • Optimize - HSE Startup Timeout value - from 5000ms to 100 ms
            • -
          • Add new - define LSE_STARTUP_TIMEOUT
            • -
          • Add new - define USE_SPI_CRC for code - cleanup when the CRC - calculation is disabled.
            • -
          -
        • Update HAL - drivers to support MISRA C - 2004 rule 10.6
          • -
        • Add new - template driver to - configure timebase - using TIMER :
          • -
            -
          • stm32f4xx_hal_timebase_tim_template.c
            • -
          -
        -
      -
        -
      • HAL - - - - CAN update
        • -
          -
        • Update HAL_CAN_Transmit() - and HAL_CAN_Transmit_IT() - - - - - functions to unlock - process when all Mailboxes are - busy
          • -
        -
      -
        -
      • HAL - - - - DSI update
        • -
          -
        • Update HAL_DSI_SetPHYTimings() - functions to use the correct - mask
          • -
        -
      • HAL - - - - UART update
        • -
          -
        • Several - update on HAL UART driver to - implement the new UART state - machine: 
          • -
            -
          • Add new - field in UART_HandleTypeDef - structure: "rxState", - - - - - UART state information - related to Rx Operations
            • -
          • Rename - "state" field in UART_HandleTypeDef - structure by "gstate": - - - - UART state information - related to global Handle - management and Tx Operations
            • -
          • Update UART - process to manage the new - UART states.
            • -
          • Update - __HAL_UART_RESET_HANDLE_STATE() - macro to handle the new UART - state parameters (gState, - rxState)
            • -
          -
        • Update - UART_BRR_SAMPLING16() and - UART_BRR_SAMPLING8() Macros to - fix wrong baudrate - calculation.
          • -
        -
      -
        -
      • HAL - - - - IRDA update
        • -
          -
        • Several - update on HAL IRDA driver to - implement the new UART state - machine: 
          • -
            -
          • Add new - field in IRDA_HandleTypeDef - structure: "rxState", - - - - - IRDA state information - related to Rx Operations
            • -
          • Rename - "state" field in UART_HandleTypeDef - structure by "gstate": - - - - IRDA state information - related to global Handle - management and Tx Operations
            • -
          • Update IRDA - process to manage the new - UART states.
            • -
          • Update - __HAL_IRDA_RESET_HANDLE_STATE() - macro to handle the new IRDA - state parameters (gState, - rxState)
            • -
          -
        • Removal of - IRDA_TIMEOUT_VALUE define
          • -
        • Update IRDA_BRR() - Macro to fix wrong baudrate - calculation
          • -
        -
      • HAL - - - - SMARTCARD update
        • -
          -
        • Several - update on HAL SMARTCARD driver - to implement the new UART - state machine: 
          • -
            -
          • Add new - field in SMARTCARD_HandleTypeDef - structure: "rxState", - - - - - SMARTCARDstate - information related to Rx Operations
            • -
          • Rename - "state" field in UART_HandleTypeDef - structure by "gstate": - - - - SMARTCARDstate - information related to - global Handle management and - Tx Operations
            • -
          • Update SMARTCARD - - - - - process to manage the new - UART states.
            • -
          • Update - __HAL_SMARTCARD_RESET_HANDLE_STATE() - macro to handle the - new SMARTCARD state - parameters (gState, - rxState)
            • -
          -
        • Update - SMARTCARD_BRR() - macro to fix wrong baudrate - calculation
          • -
        -
      -
        -
      • HAL  - RCC - update
        • -
          -
        • Add new - default define value for HSI - calibration - "RCC_HSICALIBRATION_DEFAULT"
          • -
        • Optimize - Internal oscillators and PLL - startup timeout 
          • -
        • Update to - avoid the disable for HSE/LSE - oscillators before setting the - new RCC HSE/LSE configuration - and add the following notes in - HAL_RCC_OscConfig() - API description:
          • -
        -
      -

           - - - -       -     -     -     -       * - @note   Transitions LSE - Bypass to LSE On and LSE On to LSE - Bypass are not
      -           - - - - -     -     -     -     -     -      - *         -     supported by this - API. User should request a - transition to LSE Off
      -           - - - - -     -     -     -     -     -      - *         -     first and then LSE - On or LSE Bypass.
      -           - - - - -     -     -     -     -     -      * - @note   Transition HSE - Bypass to HSE On and HSE On to HSE - Bypass are not
      -           - - - - -     -     -     -     -     -      - *         -     supported by this - API. User should request a - transition to HSE Off
      -           - - - - -     -     -     -         -      - *         -     first and then HSE - On or HSE Bypass.

      -
        -
          -
        • Optimize - the HAL_RCC_ClockConfig() - API implementation.
          • -
        -
      -
        -
      • HAL - - - - DMA2D update
        • -
          -
        • Update - HAL_DMA2D_Abort() - Function to end current DMA2D - transfer properly
          • -
        • Update - HAL_DMA2D_PollForTransfer() - function to add poll for - background CLUT loading (layer - 0 and layer 1).
          • -
        • Update - HAL_DMA2D_PollForTransfer() - to set the corresponding ErrorCode - in case of error occurrence
          • -
        • Update - HAL_DMA2D_ConfigCLUT() - function to fix wrong CLUT - size and color mode settings
          • -
        • Removal of - useless macro __HAL_DMA2D_DISABLE()
          • -
        • Update - HAL_DMA2D_Suspend() - to manage correctly the case - where no transfer is on going
          • -
        • Update - HAL_DMA2D_Resume() to - - - - - manage correctly the case - where no transfer is on going
          • -
        • Update - HAL_DMA2D_Start_IT() - to enable all required - interrupts before enabling the - transfer.
          • -
        • Add - HAL_DMA2D_CLUTLoad_IT() - Function to allow loading a - CLUT with interruption model.
          • -
        •  Update - HAL_DMA2D_IRQHandler() - to manage the following - cases :
          -
          -
          • -
            -
          • CLUT - transfer complete
            • -
          • CLUT access - error
            • -
          • Transfer - watermark reached
            • -
          -
        • Add new - Callback APIs:
          • -
            -
          •  HAL_DMA2D_LineEventCallback() - to signal a transfer - watermark reached event
            • -
          •  HAL_DMA2D_CLUTLoadingCpltCallback() - to signal a CLUT loading - complete event
            • -
          -
        -
      -
        -
          -
        • Miscellaneous - Improvement:
          • -
            -
          • Add - "HAL_DMA2D_ERROR_CAE" new - define for CLUT Access error - management.
            • -
          • Add     �assert_param� - used for parameters check is - now done on the top of the - exported functions : before - locking the process using - __HAL_LOCK
            • -
          -
        -
      -

       

      -
        -
      • HAL - - - - I2C update
        • -
          -
        • Add support - of I2C repeated start feature:
          • -
            -
          • With the - following new API's
            • -
              -
            • HAL_I2C_Master_Sequential_Transmit_IT()
              • -
            • HAL_I2C_Master_Sequential_Receive_IT()
              • -
            • HAL_I2C_Master_Abort_IT()
              • -
            • HAL_I2C_Slave_Sequential_Transmit_IT()
              • -
            • HAL_I2C_Slave_Sequential_Receive_IT()
              • -
            • HAL_I2C_EnableListen_IT()
              • -
            • HAL_I2C_DisableListen_IT()
              • -
            -
          • Add new - user callbacks:
            • -
              -
            • HAL_I2C_ListenCpltCallback()
              • -
            • HAL_I2C_AddrCallback()
              • -
            -
          -
        • Update to - generate STOP condition when a - acknowledge failure error is detected
          • -
        • Several - update on HAL I2C driver to - implement the new I2C state - machine: 
          • -
            -
          • Add new API - to get the I2C mode: - HAL_I2C_GetMode()
            • -
          • Update I2C - process to manage the new - I2C states.
            • -
          -
        • Fix wrong behaviour - in single byte transmission 
          • -
        • Update I2C_WaitOnFlagUntilTimeout() to - - - - - manage the NACK feature.
          • -
        • Update  I2C - transmission process to - support the case data size - equal 0
          • -
        -
      -
        -
      • HAL - - - - FMPI2C update
        • -
          -
        • Add support - of FMPI2C repeated start - feature:
          • -
            -
          • With the - following new API's
            • -
              -
            • HAL_FMPI2C_Master_Sequential_Transmit_IT()
              • -
            • HAL_FMPI2C_Master_Sequential_Receive_IT()
              • -
            • HAL_FMPI2C_Master_Abort_IT()
              • -
            • HAL_FMPI2C_Slave_Sequential_Transmit_IT()
              • -
            • HAL_FMPI2C_Slave_Sequential_Receive_IT()
              • -
            • HAL_FMPI2C_EnableListen_IT()
              • -
            • HAL_FMPI2C_DisableListen_IT()
              • -
            -
          • Add new - user callbacks:
            • -
              -
            • HAL_FMPI2C_ListenCpltCallback()
              • -
            • HAL_FMPI2C_AddrCallback()
              • -
            -
          -
        • Several - update on HAL I2C driver to - implement the new I2C state - machine: 
          • -
            -
          • Add new API - to get the FMPI2C mode: - HAL_FMPI2C_GetMode()
            • -
          • Update - FMPI2C process to manage the - new FMPI2C states.
            • -
          -
        -
      -
        -
      • HAL - - - - SPI update
        • -
          -
        • Major Update - to improve performance in - polling/interrupt mode to - reach max frequency:
          • -
            -
          • Polling mode - - - - :
            • -
              -
            • Replace - use of SPI_WaitOnFlagUnitTimeout() - funnction - by "if" statement to check - on RXNE/TXE flage - while transferring data.
              • -
            • Use API - data pointer instead of - SPI handle data pointer.
              • -
            • Use a Goto - implementation instead of - "if..else" - statements.
              • -
            -
          -
        -
      -
        -
          -
            -
          • Interrupt - mode
            • -
              -
            • Minimize - access on SPI registers.
              • -
            • Split the - SPI modes into dedicated - static functions to - minimize checking - statements under HAL_IRQHandler():
              • -
                -
              • 1lines/2lines - - - - modes
                • -
              • 8 bit/ - 16 bits data formats
                • -
              • CRC - calculation - enabled/disabled.
                • -
              -
            • Remove - waiting loop under ISR - when closing - - - -  the - communication.
              • -
            -
          • All - modes:  
            • -
              -
            • Adding - switch USE_SPI_CRC to - minimize number of - statements when CRC - calculation is disabled.
              • -
            • Update - Timeout management to - check on global process.
              • -
            • Update - Error code management in - all processes.
              • -
            -
          -
        • Add note to - the max frequencies reached in - all modes.
          • -
        • Add note - about Master Receive mode restrictions :
          • -
            -
          • Master - - - - Receive mode restriction:
            -       - (#) In Master - unidirectional receive-only - mode (MSTR =1, BIDIMODE=0, - RXONLY=0) or
            -           - - - - - bidirectional receive mode - (MSTR=1, BIDIMODE=1, - BIDIOE=0), to ensure that - the SPI
            -           - - - - does not initiate a new - transfer the following - procedure has to be - respected:
            -           - - - - (##) HAL_SPI_DeInit()
            -           - - - - (##) HAL_SPI_Init() - - - -
            • -
          -
        -
      -
        -
      • HAL - - - - SAI update
        • -
          -
        • Update for - proper management of the - external synchronization input - selection
          • -
            -
          • update - of HAL_SAI_Init - () funciton
            • -
          • update - definition of SAI_Block_SyncExt - and SAI_Block_Synchronization - groups
            • -
          -
        • Update - SAI_SLOTACTIVE_X -  defines - values
          • -
        • Update HAL_SAI_Init() - function for proper companding - mode management
          • -
        • Update SAI_Transmit_ITxxBit() - functions to add the check on - transfer counter before - writing new data to SAIx_DR - registers
          • -
        • Update SAI_FillFifo() - function to avoid issue when - the number of data to transmit - is smaller than the FIFO size
          • -
        • Update HAL_SAI_EnableRxMuteMode() - function for proper mute - management
          • -
        • Update SAI_InitPCM() - function to support 24bits - configuration
          • -
        -
      • HAL - - - - ETH update
        • -
          -
        • Removal of - ETH MAC debug register defines
          • -
        -
      • HAL - - - - FLASH update
        • -
          -
        • Update FLASH_MassErase() - function to apply correctly - voltage range parameter
          • -
        -
      • HAL - - - - I2S update
        • -
          -
        • Update I2S_DMATxCplt() - and I2S_DMARxCplt() to manage - properly FullDuplex - mode without any risk of - missing data.
          • -
        -
      • LL - - - - FMC update
        • -
          -
        • Update the FMC_NORSRAM_Init() - function to use BurstAccessMode - field properly
          • -
        -
      • LL - - - - FSMC  - - - - update
        • -
          -
        • Update the FSMC_NORSRAM_Init() - function to use BurstAccessMode - field properly
          • -
        -
      -


      -
      -

      -

      V1.4.4 - / 11-December-2015

      -

      Main Changes

      -
        -
      • HAL - - - - Generic update
        • -
          -
        • Update HAL - weak empty callbacks to - prevent unused argument - compilation warnings with some - compilers by calling the - following line:
          • -
            -
          • UNUSED(hppp);
            • -
          -
        • STM32Fxxx_User_Manual.chm - - - - - files regenerated for HAL - V1.4.3
          • -
        -
      • HAL - - - - ETH update 
        • -
          -
        • Update HAL_ETH_Init() - function to add timeout on the - Software reset management
          • -
        -
      -

      V1.4.2 - - - - / 10-November-2015

      -

      Main Changes

      -
        -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • One - - - - change done on the HAL CRYP - requires an update on the - application code based on HAL - V1.4.1
        • -
          -
        • Update HAL_CRYP_DESECB_Decrypt() - API to invert pPlainData - and pCypherData - parameters
          • -
        -
      • HAL - - - - generic - update
        • -
          -
        • Update HAL - weak empty callbacks to - prevent unused argument - compilation warnings with some - compilers by calling the - following line:
          • -
            -
          • UNUSED(hppp);
            • -
          -
        -
      -
        -
      • HAL - - - - CORTEX update
        • -
          -
        • Remove - duplication for - __HAL_CORTEX_SYSTICKCLK_CONFIG() - macro
          • -
        -
      -
        -
      • HAL - - - - HASH update
        • -
          -
        • Rename HAL_HASH_STATETypeDef - to HAL_HASH_StateTypeDef
          • -
        • Rename HAL_HASH_PhaseTypeDef - to HAL_HASH_PhaseTypeDef
          • -
        -
      • HAL - - - - RCC update
        • -
          -
        • Add new - macros __HAL_RCC_PPP_IS_CLK_ENABLED() - to check on Clock - enable/disable status
          • -
        • Update - __HAL_RCC_USB_OTG_FS_CLK_DISABLE() - macro to remove the disable - for the SYSCFG
          • -
        • Update HAL_RCC_MCOConfig() - API to use new defines for the - GPIO Speed
          • -
        • Generic - update to improve the - PLL VCO min - value(100MHz): PLLN, PLLI2S - and PLLSAI min value is 50 - instead of 192
          • -
        -
      • HAL - - - - FLASH update
        • -
          -
        • __HAL_FLASH_INSTRUCTION_CACHE_RESET() - macro: update to reset -  ICRST bit in - the ACR register after - setting it.
          • -
        • Update to - support until 15 FLASH wait - state (FLASH_LATENCY_15) for - STM32F446xx devices -
          • -
        -
      -

      �  - - - - - HAL CRYP update

      -
        -
          -
        • Update HAL_CRYP_DESECB_Decrypt() - API to fix the inverted pPlainData - and pCypherData - parameters issue
          • -
        -
      • HAL - - - - I2S update
        • -
          -
        • Update - HAL_I2S_Init() - API to call - __HAL_RCC_I2S_CONFIG() macro - when external I2S clock is - selected
          • -
        -
      • HAL - - - - LTDC update
        • -
          -
        • Update HAL_LTDC_SetWindowPosition() - API to configure - Immediate reload register - instead of vertical blanking - reload register.
          • -
        -
      • HAL - - - - TIM update
        • -
          -
        • Update HAL_TIM_ConfigClockSource() - API to check only the - required parameters
          • -
        -
      • HAL - - - - NAND update
        • -
          -
        • Update - HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() - APIs to manage correctly the - NAND Page access
          • -
        -
      • HAL - - - - CAN update
        • -
          -
        • Update to use - "=" instead of "|=" to clear - flags in the MSR, TSR, RF0R - and RF1R registers
          • -
        -
      • HAL - - - - HCD update
        • -
          -
        • Fix typo in - __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() - macro implementation
          • -
        -
      • HAL - - - - PCD update
        • -
          -
        • Update HAL_PCD_IRQHandler() - API to avoid issue - when DMA mode enabled for - Status Phase IN stage
          • -
        -
      • LL - - - - FMC update
        • -
          -
        • Update the FMC_NORSRAM_Extended_Timing_Init() - API to remove the check - on CLKDIvison - and DataLatency - parameters
          • -
        • Update the FMC_NORSRAM_Init() - API to add a check on the PageSize - parameter for STM32F42/43xx - devices
          • -
        -
      • LL - - - - FSMC update
        • -
          -
        • Update the FSMC_NORSRAM_Extended_Timing_Init() - API to remove the check - on CLKDIvison - and DataLatency - parameters
          • -
        -
      -

      V1.4.1 - - - - / 09-October-2015

      -

      Main Changes

      -
        -
      • HAL - - - - DSI update
        • -
          -
        • Update TCCR - register assigned value - in HAL_DSI_ConfigHostTimeouts() - function
          • -
        • Update WPCR - register assigned value - in HAL_DSI_Init(), - - - - - HAL_DSI_SetSlewRateAndDelayTuning(), - - - - - HAL_DSI_SetSlewRateAndDelayTuning(), - - - - - HAL_DSI_SetLowPowerRXFilter() - - - - - / HAL_DSI_SetSDD(), - - - - - HAL_DSI_SetLanePinsConfiguration(), - - - - - HAL_DSI_SetPHYTimings(), - - - - - HAL_DSI_ForceTXStopMode(), - - - - - HAL_DSI_ForceRXLowPower(), - - - - - HAL_DSI_ForceDataLanesInRX(), - - - - - HAL_DSI_SetPullDown() - - - - - and HAL_DSI_SetContentionDetectionOff() - - - - - functions
          • -
        • Update - DSI_HS_PM_ENABLE define value
          • -
        • Implement - workaround for the hardware - limitation: �The time to - activate the clock between HS - transmissions is not - calculated correctly�
          • -
        -
      -

      V1.4.0 - - - - / 14-August-2015

      -

      Main Changes

      -
        -
      • Add - support of STM32F469xx, STM32F479xx, - STM32F410Cx, STM32F410Rx - and STM32F410Tx  - devices
        • -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • Add - new HAL drivers for DSI and LPTIM - - - - - peripherals
        • -
      -
        -
      • HAL - - - - ADC update
        • -
          -
        • Rename - ADC_CLOCKPRESCALER_PCLK_DIV2 - define to - ADC_CLOCK_SYNC_PCLK_DIV2
          • -
        • Rename - ADC_CLOCKPRESCALER_PCLK_DIV4 - define to - ADC_CLOCK_SYNC_PCLK_DIV4
          • -
        • Rename - ADC_CLOCKPRESCALER_PCLK_DIV6 - define to - ADC_CLOCK_SYNC_PCLK_DIV6
          • -
        • Rename - ADC_CLOCKPRESCALER_PCLK_DIV8 - define to - ADC_CLOCK_SYNC_PCLK_DIV8
          • -
        -
      • HAL - - - - CORTEX update
        • -
          -
        • Add specific - API for MPU management
          • -
            -
          • add MPU_Region_InitTypeDef - structure
            • -
          • add new - function HAL_MPU_ConfigRegion()
            • -
          -
        -
      • HAL - - - - DMA update
        • -
          -
        • Overall driver - update for code optimization
          • -
            -
          • add StreamBaseAddress - and StreamIndex - new fields in the DMA_HandleTypeDef - structure
            • -
          • add DMA_Base_Registers - private structure
            • -
          • add static - function DMA_CalcBaseAndBitshift()
            • -
          • update HAL_DMA_Init() - function to use the new - added static function
            • -
          • update HAL_DMA_DeInit() - function to optimize clear - flag operations
            • -
          • update HAL_DMA_Start_IT() - function to optimize - interrupts enable
            • -
          • update HAL_DMA_PollForTransfer() - function to optimize check - on flags
            • -
          • update HAL_DMA_IRQHandler() - function to optimize - interrupt flag management
            • -
          -
        -
      • HAL - - - - FLASH update
        • -
          -
        • update HAL_FLASH_Program_IT() - function by removing the - pending flag clear
          • -
        • update HAL_FLASH_IRQHandler() - function to improve erase - operation procedure
          • -
        • update FLASH_WaitForLastOperation() - function by checking on end of - operation flag
          • -
        -
      • HAL - - - - GPIO update
        • -
          -
        • Rename - GPIO_SPEED_LOW define to - GPIO_SPEED_FREQ_LOW
          • -
        • Rename - GPIO_SPEED_MEDIUM define to - GPIO_SPEED_FREQ_MEDIUM
          • -
        • Rename - GPIO_SPEED_FAST define to - GPIO_SPEED_FREQ_HIGH
          • -
        • Rename - GPIO_SPEED_HIGH define to - GPIO_SPEED_FREQ_VERY_HIGH
          • -
        -
      • HAL - - - - I2S update
        • -
          -
        • Move - I2S_Clock_Source defines to - extension file to properly add - the support of STM32F410xx devices
          • -
        -
      • HAL - - - - LTDC update
        • -
          -
        • rename HAL_LTDC_LineEvenCallback() - function to HAL_LTDC_LineEventCallback()
          • -
        • add new - function HAL_LTDC_SetPitch()
          • -
        • add new - functions HAL_LTDC_StructInitFromVideoConfig() - and HAL_LTDC_StructInitFromAdaptedCommandConfig() - - - - - applicable only to STM32F469xx - and STM32F479xx devices
          • -
        -
      • HAL - - - - PWR update
        • -
          -
        • move - __HAL_PWR_VOLTAGESCALING_CONFIG() - macro to extension file
          • -
        • move - PWR_WAKEUP_PIN2 define to - extension file
          • -
        • add - PWR_WAKEUP_PIN3 define, - applicable only to STM32F10xx - devices
          • -
        • add new - functions HAL_PWREx_EnableWakeUpPinPolarityRisingEdge() - and HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(), - - - - - applicable only to STM32F469xx - and STM32F479xx devices
          • -
        -
      -
        -
      • HAL - - - - RTC update
        • -
          -
        • Update HAL_RTCEx_SetWakeUpTimer() - and HAL_RTCEx_SetWakeUpTimer_IT() - - - - - functions to properly check on - the WUTWF flag
          • -
        -
      • HAL - - - - TIM update
        • -
          -
        • add new - defines TIM_SYSTEMBREAKINPUT_HARDFAULT,  - - - - TIM_SYSTEMBREAKINPUT_PVD - - - - - and - TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD, - applicable only to STM32F410xx - devices
          • -
        -
      -

      V1.3.2 - - - - / 26-June-2015

      -

      Main Changes

      -
        -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • One - - - - changes - done on the HAL may require an - update on the application code - based on HAL V1.3.1
        • -
          -
        • HASH IT - process: update to call the HAL_HASH_InCpltCallback() - at the end of the complete - buffer instead of every each - 512 bits
          • -
        -
      -
        -
      • HAL - - - - RCC update
        • -
          -
        • HAL_RCCEx_PeriphCLKConfig() updates:
          • -
            -
          • Update the - LSE check condition after - backup domain reset: - update to check LSE - ready flag when LSE - oscillator is already - enabled instead of check on - LSE oscillator only when LSE - is used as RTC clock source
            • -
          • Use the - right macro to check the - PLLI2SQ parameters -
            • -
          -
        -
      -
        -
      • HAL - - - - RTC update
        • -
          -
        • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() - macro: fix implementation - issue
          • -
        • __HAL_RTC_ALARM_GET_IT(), - - - - - __HAL_RTC_ALARM_CLEAR_FLAG(), - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(), - - - - - __HAL_RTC_TIMESTAMP_CLEAR_FLAG() - - - - and - __HAL_RTC_TAMPER_CLEAR_FLAG() - macros implementation changed: - remove unused cast
          • -
        • IS_RTC_TAMPER() - macro: update to use literal - instead of hardcoded - value 
          • -
        • Add new - parameter SecondFraction - in RTC_TimeTypeDef - structure
          • -
        • HAL_RTC_GetTime() API update - to support the new - parameter SecondFraction -
          • -
        -
      • HAL - - - - ADC update
        • -
          -
        • Add new - literal: - ADC_INJECTED_SOFTWARE_START to - be used as possible value for - the ExternalTrigInjecConvEdge - parameter in the ADC_InitTypeDef - structure to select the ADC - software trigger mode.
          • -
        -
      • HAL - - - - FLASH update
        • -
          -
        • FLASH_OB_GetRDP() API update - to return uint8_t instead of FlagStatus
          • -
        •  __HAL_FLASH_GET_LATENCY() - new macro add to get the flash - latency
          • -
        -
      • HAL - - - - SPI update
        • -
          -
        • Fix the wrong - definition of - HAL_SPI_ERROR_FLAG literal
          • -
        -
      • HAL - - - - I2S update
        • -
          -
        • HAL_I2S_Transmit() - API update to check on busy - flag only for I2S slave mode
          • -
        -
      • HAL - - - - CRC update
        • -
          -
        • __HAL_CRC_SET_IDR() - macro implementation change to - use WRITE_REG() instead of - MODIFY_REG()
          • -
        -
      • HAL - - - - DMA2D update
        • -
          -
        • HAL_DMA2D_ConfigLayer() - API update to use "=" instead - of "|=" to erase BGCOLR and - FGCOLR registers before - setting the new configuration
          • -
        -
      • HAL - - - - HASH update
        • -
          -
        • HAL_HASH_MODE_Start_IT() (MODE - - - - stands for MD5, SHA1, - SHA224 and SHA36) updates:
          • -
            -
          • Fix processing - - - - - fail for small input buffers
            • -
          • Update to - unlock the process and - call return - HAL_OK at the end of - HASH processing to avoid - incorrectly repeating software
            • -
          • Update to - properly manage the HashITCounter
            • -
          • Update to - call the HAL_HASH_InCpltCallback() - at the end of the complete - buffer instead of every each - 512 bits
            • -
          -
        • __HAL_HASH_GET_FLAG() - update to  check the - right register when the DINNE - flag  is selected
          • -
        • HAL_HASH_SHA1_Accumulate() - updates:
          • -
            -
          • Add - a call to the new - IS_HASH_SHA1_BUFFER_SIZE() - macro to check the size - parameter. 
            • -
          • Add the - following note in API description
            • -
          -
        -
      -
      -

       * - - - - - @note  - - - - - Input buffer - size in bytes must be a multiple - of 4 otherwise the digest - computation is corrupted.

      -
      -
        -
      • HAL - - - - RTC update
        • -
          -
        • Update to - define hardware - independent literals names:
          • -
            -
          • Rename - RTC_TAMPERPIN_PC13 by - - - -  RTC_TAMPERPIN_DEFAULT
            • -
          • Rename - RTC_TAMPERPIN_PA0 by - RTC_TAMPERPIN_POS1
            • -
          • Rename - RTC_TAMPERPIN_PI8 by - RTC_TAMPERPIN_POS1
            • -
          • Rename - RTC_TIMESTAMPPIN_PC13 by - RTC_TIMESTAMPPIN_DEFAULT
            • -
          • Rename - RTC_TIMESTAMPPIN_PA0 by - RTC_TIMESTAMPPIN_POS1
            • -
          • Rename - RTC_TIMESTAMPPIN_PI8 by - RTC_TIMESTAMPPIN_POS1
            • -
          -
        -
      • HAL - - - - ETH update
        • -
          -
        • Remove - duplicated IS_ETH_DUPLEX_MODE() - and IS_ETH_RX_MODE() macros
          • -
        • Remove - illegal space - ETH_MAC_READCONTROLLER_FLUSHING - macro
          • -
        • Update - ETH_MAC_READCONTROLLER_XXX - defined values (XXX can be - IDLE, READING_DATA and - READING_STATUS)
          • -
        -
      • HAL - - - - PCD update
        • -
          -
        • HAL_PCD_IRQHandler API: fix the - bad Configuration of - Turnaround Time
          • -
        -
      • HAL - - - - HCD update
        • -
          -
        • Update to use - local variable in USB - Host channel re-activation
          • -
        -
      • LL - - - - FMC update
        • -
          -
        • FMC_SDRAM_SendCommand() API: remove - the following line: return - HAL_ERROR;
          • -
        -
      • LL - - - - USB update
        • -
          -
        • USB_FlushTxFifo API: - update to flush all Tx FIFO
          • -
        • Update to use - local variable in USB - Host channel re-activation
          • -
        -
      -

      V1.3.1 - - - - / 25-Mars-2015

      -

      Main Changes

      -
        -
      • HAL - - - - PWR update
        • -
          -
        • Fix - compilation issue with - STM32F417xx product: - update STM32F17xx - by STM32F417xx
          • -
        -
      • HAL - - - - SPI update
        • -
          -
        • Remove unused - variable to avoid warning with - TrueSTUDIO 
          • -
        -
      • HAL - - - - I2C update
        • -
          -
        • I2C - Polling/IT/DMA processes: move - the wait loop on busy - flag at the top of the - processes, to ensure that - software not perform any write - access to I2C_CR1 register - before hardware - clearing STOP bit and to - avoid - - - - - also the - waiting loop on BUSY flag - under I2C/DMA ISR.
          • -
        • Update busy - flag Timeout value
          • -
        • I2C Master - Receive Processes update to - disable ACK before generate - the STOP 
          • -
        -
      • HAL - - - - DAC update
        • -
          -
        • Fix V1.3.0 - regression issue with DAC - software trigger configuration
          • -
        -
      -

      V1.3.0 - - - - / 09-Mars-2015

      -

      Main Changes

      -
        -
      • Add - support of STM32F446xx devices
        • -
      • General - - - - updates to fix known defects and - enhancements implementation
        • -
      • Add - new HAL drivers for CEC, - QSPI, FMPI2C and SPDIFRX - - - - peripherals
        • -
      • Two - - - - changes done on the HAL - requires an update on the - application code based on HAL - V1.2.0
        • -
          -
        • Overall SAI - driver rework to have - exhaustive support of the - peripheral features: details - are provided in HAL SAI update - - - - section below --> Compatibility - - - - - with previous version is impacted
          • -
        • CRYP driver - updated to support multi instance,so - user must ensure that the - new parameter Instance is - initalized - in his application(CRYPHandle.Instance - = CRYP) 
          • -
        -
      -
        -
      • HAL - - - - Generic update
        • -
          -
        • stm32f4xx_hal_def.h
          • -
            -
          • Remove NULL - definition and add - include for stdio.h
            • -
          -
        • stm32_hal_legacy.h
          • -
            -
          • Update method - - - - to manage deference in - alias implementation between - all STM32 families
            • -
          -
        • stm32f4xx_hal_ppp.c
          • -
            -
          • HAL_PPP_Init(): update - to force the - HAL_PPP_STATE_RESET before - calling the HAL_PPP_MspInit()
            • -
          -
        -
      -
        -
      • HAL - - - - RCC update
        • -
          -
        • Add new - function HAL_RCCEx_GetPeriphCLKFreq()
          • -
        • Move RCC_PLLInitTypeDef - structure to extension file - and add the new PLLR field - specific to STM32F446xx devices
          • -
        • Move the - following functions to - extension file and add a - __weak attribute in generic driver - - - - : this - update is related to new - system clock source (PLL/PLLR) - added and only available for - STM32F44xx devices
          • -
            -
          • HAL_RCC_OscConfig()
            • -
          • HAL_RCC_GetSysClockFreq()
            • -
          • HAL_RCC_GetOscConfig()
            • -
          -
        • Move the - following macro to extension - file as they have device - dependent implementation
          • -
            -
          • __HAL_RCC_PLL_CONFIG()
            • -
          • __HAL_RCC_PLLI2S_CONFIG()
            • -
          • __HAL_RCC_I2S_CONFIG()
            • -
          -
        • Add new - structure RCC_PLLI2SInitTypeDef - containing new PLLI2S - division factors used only w/ - STM32F446xx devices
          • -
        • Add new - structure RCC_PLLSAIInitTypeDef - containing new PLLSAI - division factors used only w/ - STM32F446xx devices
          • -
        • Add new RCC_PeriphCLKInitTypeDef - to support the peripheral - source clock selection for (I2S, - - - - SAI, SDIO, FMPI2C, CEC, - SPDIFRX and CLK48)
          • -
        • Update the HAL_RCCEx_PeriphCLKConfig() - and HAL_RCCEx_GetPeriphCLKConfig() - - - - - functions to support the - new peripherals Clock source - selection
          • -
        • Add __HAL_RCC_PLL_CONFIG() - macro (the number of parameter - and the implementation depend - on the device part number)
          • -
        • Add __HAL_RCC_PLLI2S_CONFIG() - macro(the number of parameter - and the implementation depend - on device part number)
          • -
        • Update __HAL_RCC_PLLSAI_CONFIG() - macro to support new PLLSAI - factors (PLLSAIM and - PLLSAIP)
          • -
        • Add new - macros for clock - enable/Disable for the - following peripherals (CEC, - - - - SPDIFRX, SAI2, QUADSPI)
          • -
        • Add the - following new macros for clock - source selection - - - - :
          • -
            -
          • __HAL_RCC_SAI1_CONFIG() - / - __HAL_RCC_GET_SAI1_SOURCE()
            • -
          • __HAL_RCC_SAI2_CONFIG() - / - __HAL_RCC_GET_SAI2_SOURCE()
            • -
          • __HAL_RCC_I2S1_CONFIG() - / - __HAL_RCC_GET_I2S1_SOURCE()
            • -
          • __HAL_RCC_I2S2_CONFIG() - / - __HAL_RCC_GET_I2S2_SOURCE()
            • -
          • __HAL_RCC_CEC_CONFIG() - / - __HAL_RCC__GET_CEC_SOURCE() -
            • -
          • __HAL_RCC_FMPI2C1_CONFIG() - / - __HAL_RCC_GET_FMPI2C1_SOURCE() -
            • -
          • __HAL_RCC_SDIO_CONFIG() - / - __HAL_RCC_GET_SDIO_SOURCE() -
            • -
          • __HAL_RCC_CLK48_CONFIG() - / - __HAL_RCC_GET_CLK48_SOURCE() -
            • -
          • __HAL_RCC_SPDIFRXCLK_CONFIG() - / - __HAL_RCC_GET_SPDIFRX_SOURCE()
            • -
          -
        • __HAL_RCC_PPP_CLK_ENABLE(): - - - - - Implement workaround to cover - RCC limitation regarding - peripheral enable delay
          • -
        • HAL_RCC_OscConfig() fix - issues: 
          • -
            -
          • Add a check - on LSERDY flag when - LSE_BYPASS is selected as - new state for LSE - oscillator.
            • -
          -
        • Add - new possible value RCC_PERIPHCLK_PLLI2S - - - - to be selected as PeriphClockSelection - parameter in the - - - - -  RCC_PeriphCLKInitTypeDef - structure to allow the - possibility to output the - PLLI2S on MCO without - activating the I2S or the SAI.
          • -
        • __HAL_RCC_HSE_CONFIG() -  macro: add - the comment below:
          • -
        -
      -
      -

       * - - - - - @note   Transition - HSE Bypass to HSE On and HSE - On to HSE Bypass are not - supported by this macro.
      -  *         - - - - User should request a - transition to HSE Off first - and then HSE On or HSE Bypass.

      -
      -
        -
          -
        • __HAL_RCC_LSE_CONFIG()  macro: add - the comment below:
          • -
        -
      -
      -

        * - - - - - @note   Transition - LSE Bypass to LSE On and LSE - On to LSE Bypass are not - supported by this macro.
      -   - *         - User should request a - transition to LSE Off first - and then LSE On or LSE Bypass.

      -
      -
        -
          -
        • Add the - following new macros for - PLL source and PLLM selection - - - - :
          • -
            -
          • __HAL_RCC_PLL_PLLSOURCE_CONFIG()
            • -
          • __HAL_RCC_PLL_PLLM_CONFIG()
            • -
          -
        • Macros - rename:
          • -
            -
          • HAL_RCC_OTGHS_FORCE_RESET() -by HAL_RCC_USB_OTG_HS_FORCE_RESET()
            • -
          • HAL_RCC_OTGHS_RELEASE_RESET() -by HAL_RCC_USB_OTG_HS_RELEASE_RESET()
            • -
          • HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() -by HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()
            • -
          • HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() -by HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()
            • -
          • HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() -by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
            • -
          • HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() -by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
            • -
          -
        • Add __HAL_RCC_SYSCLK_CONFIG() - new macro to configure the - system clock source (SYSCLK)
          • -
        • __HAL_RCC_GET_SYSCLK_SOURCE() - updates:
          • -
            -
          • Add new RCC - Literals:
            • -
              -
            • RCC_SYSCLKSOURCE_STATUS_HSI
              • -
            • RCC_SYSCLKSOURCE_STATUS_HSE
              • -
            • RCC_SYSCLKSOURCE_STATUS_PLLCLK
              • -
            • RCC_SYSCLKSOURCE_STATUS_PLLRCLK
              • -
            -
          •  Update - - - - macro description to refer - to the literals above -
            • -
          -
        -
      • HAL - - - - PWR update
        • -
          -
        • Add new - define PWR_WAKEUP_PIN2
          • -
        • Add new API - to Control/Get VOS bits - of CR register
          • -
            -
          • HAL_PWR_HAL_PWREx_ControlVoltageScaling()
            • -
          • HAL_PWREx_GetVoltageRange()
            • -
          -
        • __HAL_PWR_ - VOLTAGESCALING_CONFIG(): Implement - workaround to cover VOS - limitation delay when PLL is - enabled after setting the VOS - configuration
          • -
        -
      • HAL - - - - GPIO update
        • -
          -
        • Add the new - Alternate functions literals - related to remap for SPI, - - - - USART, I2C, SPDIFRX, CEC - and QSPI
          • -
        • HAL_GPIO_DeInit(): - - - - Update to check if GPIO - Pin x is already used in EXTI - mode on another GPIO Port - before De-Initialize the EXTI - registers
          • -
        -
      • HAL - - - - FLASH update
        • -
          -
        • __HAL_FLASH_INSTRUCTION_CACHE_RESET() - macro: update to reset -  ICRST bit in - the ACR register after - setting it.
          • -
        • __HAL_FLASH_DATA_CACHE_RESET() macro: - - - - - update to reset -  DCRST bit in the ACR - register after setting it.
          • -
        -
      • HAL - - - - ADC update
        • -
          -
        • Add new - literal: ADC_SOFTWARE_START to - be used as possible value for - the ExternalTrigConv - parameter in the ADC_InitTypeDef - structure to select the ADC - software trigger mode.
          • -
        • IS_ADC_CHANNEL() - macro update to don't assert - stop the ADC_CHANNEL_TEMPSENSOR - value
          • -
        • HAL_ADC_PollForConversion(): update to - manage particular case when - ADC configured in DMA mode and - ADC sequencer with several - ranks and polling for end of - each conversion
          • -
        • HAL_ADC_Start()/HAL_ADC_Start_IT() - /HAL_ADC_Start_DMA() - - - - - update:
          • -
            -
          • unlock the - process before starting the - ADC software conversion.
            • -
          • Optimize - the ADC stabilization delays
            • -
          -
        • __HAL_ADC_GET_IT_SOURCE() - update macro implementation
          • -
        • Add more - details in 'How to use this - driver' section
          • -
        -
      • HAL - - - - DAC update
        • -
          -
        • Add new macro - to check if the specified DAC - interrupt source is enabled or - disabled
          • -
            -
          • __HAL_DAC_GET_IT_SOURCE()
            • -
          -
        • HAL_DACEx_TriangleWaveGeneration() update to - use DAC CR bit mask definition
          • -
        • HAL_DACEx_NoiseWaveGeneration() update to - use DAC CR bit mask definition
          • -
        -
      • HAL - - - - CAN update
        • -
          -
        • CanTxMsgTypeDef structure: - update to use uint8_t Data[8] - - - - - instead of - uint32_t Data[8]
          • -
        • CanRxMsgTypeDef structure: - update to use uint8_t Data[8] - instead of - uint32_t Data[8]
          • -
        -
      -
        -
      • HAL - - - - RTC update
        • -
          -
        • Update to - use CMSIS mask definition - instead of hardcoded values (EXTI_IMR_IM17, - EXTI_IMR_IM19..)
          • -
        -
      • HAL - - - - LTDC update
        • -
          -
        • LTDC_SetConfig() update to - allow the drawing - of partial bitmap in - active layer.
          • -
        -
      • HAL - - - - USART update
        • -
          -
        • HAL_USART_Init() fix USART - baud rate configuration - issue: USART baud rate is - twice Higher than expected
          • -
        -
      • HAL - - - - SMARTCARD update
        • -
          -
        • HAL_SMARTCARD_Transmit_IT() update to - force the disable for the ERR - interrupt to avoid the OVR - interrupt
          • -
        • HAL_SMARTCARD_IRQHandler() - update check condition - for transmission end
          • -
        • Clean up: - remove the following - literals that aren't used in - smartcard mode
          • -
            -
          • SMARTCARD_PARITY_NONE
            • -
          • SMARTCARD_WORDLENGTH_8B
            • -
          • SMARTCARD_STOPBITS_1
            • -
          • SMARTCADR_STOPBITS_2
            • -
          -
        -
      • HAL - - - - SPI update
        • -
          -
        • HAL_SPI_Transmit_DMA()/HAL_SPI_Receive_DMA()/HAL_SPI_TarnsmitReceive_DMA() - update to unlock - the process before - enabling the SPI peripheral
          • -
        • HAL_SPI_Transmit_DMA() update to - manage correctly the DMA RX - stream in SPI Full duplex mode
          • -
        • Section - SPI_Exported_Functions_Group2 update - to remove duplication in *.chm - UM
          • -
        -
      • HAL - - - - CRYP update
        • -
          -
        • Update to - manage multi instance:
          • -
            -
          • Add new - parameter Instance in the CRYP_HandleTypeDef - Handle structure.
            • -
          • Add new - parameter in all HAL CRYP - macros
            • -
              -
            • example: __HAL_CRYP_ENABLE() -  updated by - __HAL_CRYP_ENABLE(__HANDLE__)
              • -
            -
          -
        -
      • HAL - - - - DCMI update
        • -
          -
        • Add an - extension - driver stm32f4xx_hal_dcmi_ex.c/h - to manage the support of new - Black and White feature -
          • -
        • Add  __weak attribute - for HAL_DCMI_Init() - function and add a new - implementation in the - extension driver to manage the - black and white configuration - only available in the  - STM32F446xx devices. -
          • -
        • Move DCMI_InitTypeDef - structure to extension driver - and add the - following new fields - related to black and white - feature: ByteSelectMode, ByteSelectStart, LineSelectMode - and LineSelectStart
          • -
        -
      • HAL - - - - PCD update
        • -
          -
        • Add the - support of LPM feature
          • -
            -
          • add PCD_LPM_StateTypeDef - enum
            • -
          • update PCD_HandleTypeDef - structure to support the LPM - feature
            • -
          • add new - functions HAL_PCDEx_ActivateLPM(), - - - - - HAL_PCDEx_DeActivateLPM() - - - - - and HAL_PCDEx_LPM_Callback() - - - - - in the - stm32f4xx_hal_pcd_ex.h/.c - files
            • -
          -
        -
      • HAL - - - - TIM update
        • -
          -
        • Add  - TIM_TIM11_SPDIFRX - - - - define
          • -
        -
      • HAL - - - - SAI update
        • -
          -
        • Add - stm32f4xx_hal_sai_ex.h/.c - files for the SAI_BlockSynchroConfig() - and the SAI_GetInputClock() - - - - - management
          • -
        • Add new - defines HAL_SAI_ERROR_AFSDET, - HAL_SAI_ERROR_LFSDET, - HAL_SAI_ERROR_CNREADY, - HAL_SAI_ERROR_WCKCFG, - HAL_SAI_ERROR_TIMEOUT in the SAI_Error_Code - group
          • -
        • Add new - defines SAI_SYNCEXT_DISABLE, - SAI_SYNCEXT_IN_ENABLE, - SAI_SYNCEXT_OUTBLOCKA_ENABLE, - SAI_SYNCEXT_OUTBLOCKB_ENABLE - for the SAI External - synchronization
          • -
        • Add new - defines SAI_I2S_STANDARD, - SAI_I2S_MSBJUSTIFIED, - SAI_I2S_LSBJUSTIFIED, - SAI_PCM_LONG and SAI_PCM_SHORT - for the SAI Supported protocol
          • -
        • Add new - defines - SAI_PROTOCOL_DATASIZE_16BIT, - SAI_PROTOCOL_DATASIZE_16BITEXTENDED, - SAI_PROTOCOL_DATASIZE_24BIT - and - SAI_PROTOCOL_DATASIZE_32BIT - for SAI protocol data size
          • -
        • Add SAI - Callback prototype definition
          • -
        • Update SAI_InitTypeDef - structure by adding new - fields: SynchroExt, - Mckdiv, - MonoStereoMode, - CompandingMode, - TriState
          • -
        • Update SAI_HandleTypeDef - structure:
          • -
            -
          • remove - uint16_t *pTxBuffPtr, - *pRxBuffPtr, - TxXferSize, - RxXferSize, - TxXferCount - and RxXferCount - and replace them - respectively by uint8_t *pBuffPtr, - uint16_t XferSize and - - - - - uint16_t XferCount
            • -
          • add mutecallback - field
            • -
          • add struct - __SAI_HandleTypeDef - *hsai field
            • -
          -
        • Remove - SAI_CLKSOURCE_PLLR and - SAI_CLOCK_PLLSRC defines
          • -
        • Add - SAI_CLKSOURCE_NA define
          • -
        • Add - SAI_AUDIO_FREQUENCY_MCKDIV - define
          • -
        • Add - SAI_SPDIF_PROTOCOL define
          • -
        • Add - SAI_SYNCHRONOUS_EXT define
          • -
        • Add new - functions HAL_SAI_InitProtocol(), - - - - - HAL_SAI_Abort(), - - - - - HAL_SAI_EnableTxMuteMode(), - - - - - HAL_SAI_DisableTxMuteMode(), - - - - - HAL_SAI_EnableRxMuteMode(), - - - - - HAL_SAI_DisableRxMuteMode()
          • -
        • Update HAL_SAI_Transmit(), - - - - - HAL_SAI_Receive(), - - - - - HAL_SAI_Transmit_IT(), - - - - - HAL_SAI_Receive_IT(), - - - - - HAL_SAI_Transmit_DMA(), - - - - - HAL_SAI_Receive_DMA() - - - - - functions to use uint8_t *pData - instead of uint16_t *pData - --> This update is mainly - impacting the compatibility - with previous driver - version.
          • -
        -
      • HAL - - - - I2S update
        • -
          -
        • Split the - following - functions between Generic - and Extended API based on full - duplex management and add the - attribute __weak in the - Generic API
          • -
            -
          • HAL_I2S_Init(), - - - - - HAL_I2S_DMAPause(), HAL_I2S_DMAStop(), HAL_I2S_DMAResume(), HAL_I2S_IRQHandle() - - - - -
            • -
          -
        • Move the - following static functions - from generic to extension driver
          • -
            -
          •  I2S_DMARxCplt() - and I2S_DMATxCplt()
            • -
          -
        • Remove static - attribute from I2S_Transmit_IT() - and I2S_Receive_IT() functions
          • -
        • Move I2SxEXT() - macro to extension file
          • -
        • Add - I2S_CLOCK_PLLR and - I2S_CLOCK_PLLSRC defines for - I2S clock source
          • -
        • Add new - function I2S_GetInputClock()
          • -
        -
      • HAL - - - - LL FMC update
        • -
          -
        • Add WriteFifo - and PageSize - fields in the FMC_NORSRAM_InitTypeDef - structure
          • -
        • Add - FMC_PAGE_SIZE_NONE, - FMC_PAGE_SIZE_128, - FMC_PAGE_SIZE_256, - FMC_PAGE_SIZE_1024, - FMC_WRITE_FIFO_DISABLE, - FMC_WRITE_FIFO_ENABLE defines
          • -
        • Update FMC_NORSRAM_Init(), - - - - - FMC_NORSRAM_DeInit() - - - - - and FMC_NORSRAM_Extended_Timing_Init() functions
          • -
        -
      • HAL - - - - LL USB update
        • -
          -
        • Update USB_OTG_CfgTypeDef - structure to support LPM, lpm_enable - field added
          • -
        • Update USB_HostInit() - and USB_DevInit() - - - - - functions to support the VBUS - Sensing B activation
          • -
        -
      -

      V1.2.0 - - - - / 26-December-2014

      -

      Main Changes

      -
        -
      • Maintenance - - - - release to fix known defects - and enhancements implementation
        • -
      -
        -
      • Macros - - - - and literals renaming to - ensure compatibles across - STM32 series, - backward compatibility - maintained thanks to new added - file stm32_hal_legacy.h under - - - - /Inc/Legacy
        • -
      • Add - *.chm UM for all drivers, a UM - is provided for each superset RPN
        • -
      • Update - - - - drivers to be C++ compliant
        • -
      • Several - - - - update on source code - formatting, for better UM - generation (i.e. - Doxygen - tags updated)
        • -
      • Two - - - - changes done on the HAL - requires an update on the - application code based on HAL - V1.1.0
        • -
          -
        • LSI_VALUE constant has - been corrected in - stm32f4xx_hal_conf.h file, its - value changed from 40 KHz - to 32 KHz
          • -
        • UART, USART, - IRDA and SMARTCARD - (referenced as PPP - here below) drivers: - in DMA transmit process, the - code has been updated to avoid - waiting on TC flag under DMA - ISR, PPP TC interrupt - is used instead. Below the - update to be done on user - application:
          • -
            -
          • Configure - and enable the USART IRQ in - HAL_PPP_MspInit() - function
            • -
          • In - stm32f4xx_it.c file, PPP_IRQHandler() - function: add a call to HAL_PPP_IRQHandler() - - - - function
            • -
          -
        -
      -
        -
      • HAL - - - - generic - update
        • -
      -
        -
          -
        • stm32f4xx_hal_def.h
          • -
            -
          • Update NULL - definition to fix C++ - compilation issue
            • -
          • Add UNUSED() - macro
            • -
          • Add a new - define __NOINLINE to be used - for the no inline code - independent from tool chain
            • -
          -
        • stm32f4xx_hal_conf_template.h
          • -
            -
          • LSI_VALUE constant - has been corrected, - its value changed from 40 KHz - to 32 KHz
            • -
          -
        -
      -
        -
          -
        • Update all - macros and literals naming to - be uper - case
          • -
        • ErrorCode parameter in - PPP_HandleTypeDef - structure updated - to uint32_t instead - of enum HAL_PPP_ErrorTypeDef
          • -
        • Remove the - - - - unused FLAG and IT assert macros
          • -
        -
      • HAL - - - - ADC update
        • -
          -
        • Fix temperature - - - - - sensor channel configuration - issue for STM32F427/437xx - - - - -  and STM32F429/439xx - - - - devices
          • -
        -
      • HAL - - - - DAC update
        • -
          -
        • HAL_DAC_ConfigChannel(): update the - access to the DAC peripheral - registers via the hdac - handle instance
          • -
        • HAL_DAC_IRQHandler(): update to - check on both DAC_FLAG_DMAUDR1 - and DAC_FLAG_DMAUDR2
          • -
        • HAL_DACEx_NoiseWaveGenerate(): update to - reset DAC CR register before - setting the new DAC - configuration
          • -
        • HAL_DACEx_TriangleWaveGenerate(): update to - reset DAC CR register before - setting the new DAC - configuration
          • -
        -
      • HAL - - - - CAN update
        • -
          -
        • Unlock the - CAN process when communication - error occurred
          • -
        -
      • HAL - - - - CORTEX update
        • -
          -
        • Add new macro - IS_NVIC_DEVICE_IRQ() - to check on negative values of - IRQn - parameter
          • -
        -
      -

      �  - - - - - HAL CRYP update

      -
        -
          -
        • HAL_CRYP_DESECB_Decrypt_DMA(): fix the - inverted pPlainData - and pCypherData - parameters issue
          • -
        • CRYPEx_GCMCCM_SetInitVector(): remove - the IVSize - parameter as the key length - 192bits and 256bits are not - supported by this version
          • -
        • Add restriction for - - - - - the CCM Encrypt/Decrypt API's - that only DataType - equal to 8bits is supported
          • -
        • HAL_CRYPEx_AESGCM_Finish():
          • -
            -
          • Add restriction - - - - - that the implementation is - limited to 32bits inputs - data length  (Plain/Cyphertext, - - - - Header) compared with GCM stadards - specifications (800-38D)
            • -
          • Update Size - parameter on 32bits instead - of 16bits
            • -
          • Fix issue - with 16-bit Data Type: - update to use intrinsic __ROR() - instead of __REV16()
            • -
          -
        -
      -

      �  - - - - - HAL DCMI update

      -
        -
          -
        • HAL_DCMI_ConfigCROP(): Invert - assert macros to check Y0 and - Ysize - parameters
          • -
        -
      -

      �  - - - - - HAL DMA update

      -
        -
          -
        • HAL_DMA_Init(): Update to - - - - - clear the DBM bit in the - SxCR - register before setting the - new configuration
          • -
        • DMA_SetConfig(): - add to clear the DBM - bit in the SxCR - register
          • -
        -
      -

      �  - - - - - HAL FLASH update

      -
        -
          -
        • Add "HAL_" - prefix in the defined values - for the FLASH error code
          • -
            -
          • Example: FLASH_ERROR_PGP - renamed by HAL_FLASH_ERROR_PGP
            • -
          -
        • Clear the - - - - Flash ErrorCode - in the FLASH_WaitForLastOperation() - function
          • -
        • Update FLASH_SetErrorCode() - function to use "|=" - operant to update the Flash ErrorCode - parameter in the FLASH handle
          • -
        • IS_FLASH_ADDRESS(): Update the - macro check using '<=' - condition instead of '<'
          • -
        • IS_OPTIONBYTE(): Update the - macro check using '<=' - condition instead of '<'
          • -
        • Add "FLASH_" - - - - - prefix in the defined values - of FLASH Type Program - parameter
          • -
            -
          • Example: TYPEPROGRAM_BYTE - renamed by FLASH_TYPEPROGRAM_BYTE
            • -
          -
        • Add "FLASH_" - - - - - prefix in the defined values - of FLASH Type Erase parameter
          • -
            -
          • Example: TYPEERASE_SECTORS - renamed by FLASH_TYPEERASE_SECTORS
            • -
          -
        • Add "FLASH_" - - - - - prefix in the defined values - of FLASH Voltage Range - parameter
          • -
            -
          • Example: VOLTAGE_RANGE_1 - renamed by FLASH_VOLTAGE_RANGE_1
            • -
          -
        • Add "OB_" - - - - - prefix in the defined values - of FLASH WRP State parameter
          • -
            -
          • Example: WRPSTATE_ENABLE - renamed by OB_WRPSTATE_ENABLE
            • -
          -
        • Add "OB_" - - - - - prefix in the defined values - of the FLASH PCROP State - parameter
          • -
            -
          • PCROPSTATE_DISABLE  - updated by OB_PCROP_STATE_DISABLE
            • -
          • PCROPSTATE_ENABLE -  updated by OB_PCROP_STATE_ENABLE
            • -
          -
        • Change - "OBEX" prefix by - "OPTIONBYTE" prefix in these - defines:
          • -
            -
          • OBEX_PCROP - - - - by OPTIONBYTE_PCROP 
            • -
          • OBEX_BOOTCONFIG - - - - by OPTIONBYTE_BOOTCONFIG
            • -
          -
        -
      -

      �  - - - - - HAL ETH update

      -
        -
          -
        • Fix macros - naming typo
          • -
        -
      -
        -
          -
            -
          • Update - __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() - by - __HAL_ETH_EXTI_SET_RISING_EDGE_TRIGGER()
            • -
          • Update - __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() -by __HAL_ETH_EXTI_SET_FALLING_EDGE_TRIGGER()
            • -
          -
        -
      -

      �  - - - - - HAL PWR update

      -
        -
          -
        • Add new API - to manage SLEEPONEXIT and - SEVONPEND bits of SCR register
          • -
            -
          • HAL_PWR_DisableSleepOnExit()
            • -
          • HAL_PWR_EnableSleepOnExit()
            • -
          • HAL_PWR_EnableSEVOnPend()
            • -
          • HAL_PWR_DisableSEVOnPend()
            • -
          -
        • HAL_PWR_EnterSTOPMode()
          • -
            -
          • Update to - - - - clear the CORTEX SLEEPDEEP - bit of SCR register - before entering in sleep mode
            • -
          • Update - usage of __WFE() - in low power entry function: - if there is a pending event, - calling __WFE() will not - enter the CortexM4 core to - sleep mode. The solution is - to made the call below; the - first __WFE() - is always ignored and clears - the event if one was already - pending, the second is - always applied
            • -
          -
        -
      -
      -

      __SEV()
      -       __WFE()
      -       __WFE()

      -
      -
        -
          -
        • Add - new PVD configuration modes
          • -
            -
          • PWR_PVD_MODE_NORMAL
            • -
          • PWR_PVD_MODE_EVENT_RISING 
            • -
          • PWR_PVD_MODE_EVENT_FALLING
            • -
          • PWR_PVD_MODE_EVENT_RISING_FALLING
            • -
          -
        • Add new - macros to manage PVD Trigger
          • -
            -
          • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()
            • -
          • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(
            • -
          • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()
            • -
          • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
            • -
          • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
            • -
          • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
            • -
          -
        • PVD macros:
          • -
            -
          • Remove the - __EXTILINE__ parameter
            • -
          • Update to - use prefix "__HAL_PWR_PVD_" - instead of  prefix - "__HAL_PVD"
            • -
          -
        -
      -
        -
          -
        • Rename HAL_PWR_PVDConfig() - by HAL_PWR_ConfigPVD()
          • -
        • Rename HAL_PWREx_ActivateOverDrive() - by HAL_PWREx_EnableOverDrive() - - - - -
          • -
        • Rename HAL_PWREx_DeactivateOverDrive() - by HAL_PWREx_DisableOverDrive() - - - - -
          • -
        -
      • HAL - - - - GPIO update
        • -
          -
        • HAL_GPIO_Init()/HAL_GPIO_DeInit(): add a call - to the CMSIS assert macro - to check GPIO instance: - IS_GPIO_ALL_INSTANCE() 
          • -
        • HAL_GPIO_WritePin(): update to - write in BSRR register
          • -
        • Rename GPIO_GET_SOURCE() - by GET_GPIO_INDEX() and - - - - move this later to file  - stm32f4xx_hal_gpio_ex.h
          • -
        • Add new - define for alternate function - GPIO_AF5_SPI3 for - STM32F429xx/439xx and - STM32F427xx/437xx devices
          • -
        -
      • HAL - - - - HASH update
        • -
          -
        • HAL_HASH_MD5_Start_IT(): - - - - - fix input - address management issue
          • -
        -
      • HAL - - - - RCC update
        • -
          -
        • Rename the - following Macros
          • -
            -
          • __PPP_CLK_ENABLE()  - - - - - by - __HAL_RCC_PPP_CLK_ENABLE()
            • -
          • __PPP_CLK_DISABLE()  - - - - - by - __HAL_RCC_PPP_CLK_DISABLE()
            • -
          • __PPP_FORCE_RESET()  - - - - - by - __HAL_RCC_PPP_FORCE_RESET()
            • -
          • __PPP_RELEASE_RESET()  - - - - - by - __HAL_RCC_PPP_RELEASE_RESET()
            • -
          • __PPP_CLK_SLEEP_ENABLE() - by - __HAL_RCC_PPP_CLK_SLEEP_ENABLE()
            • -
          • __PPP_CLK_SLEEP_DISABLE() - by - __HAL_RCC_PPP_CLK_SLEEP_DISABLE()
            • -
          -
        • IS_RCC_PLLSAIN_VALUE() - macro: update the check - condition
          • -
        • Add - description of RCC known Limitations
          • -
        • Rename HAL_RCC_CCSCallback() - by HAL_RCC_CSSCallback()
          • -
        • HAL_RCC_OscConfig() fix - issues: 
          • -
            -
          • Remove the - disable of HSE - oscillator when - HSE_BYPASS is used as - system clock source or as - PPL clock source
            • -
          • Add a check - on HSERDY flag - when HSE_BYPASS is - selected as new state - for HSE oscillator.
            • -
          -
        • Rename - __HAL_RCC_I2SCLK() - by __HAL_RCC_I2S_Config()
          • -
        -
      -

      �  - - - - - HAL I2S update

      -
        -
          -
        • HAL_I2S_Init(): add check - on I2S instance - using CMSIS macro IS_I2S_ALL_INSTANCE() 
          • -
        • HAL_I2S_IRQHandler() - update for compliancy w/ C++
          • -
        • Add use - of tmpreg - variable in __HAL_I2S_CLEAR_OVRFLAG() - and __HAL_I2S_CLEAR_UDRFLAG() - macro for compliancy with C++
          • -
        • HAL_I2S_GetError(): update to - return uint32_t instead of - HAL_I2S_ErrorTypeDef - enumeration
          • -
        -
      -

      �  - - - - - HAL I2C update

      -
        -
          -
        • Update to - - - - - clear the POS bit in the - CR1 register at the end - of HAL_I2C_Master_Read_IT() - and HAL_I2C_Mem_Read_IT() - process
          • -
        • Rename - HAL_I2CEx_DigitalFilter_Config()  - - - - by - HAL_I2CEx_ConfigDigitalFilter() -
          • -
        • Rename - HAL_I2CEx_AnalogFilter_Config()  - - - - by - HAL_I2CEx_ConfigAnalogFilter() -
          • -
        • Add use - of tmpreg - variable in __HAL_I2C_CLEAR_ADDRFLAG() - and __HAL_I2C_CLEAR_STOPFLAG() - macro for compliancy with - C++
          • -
        -
      • HAL - - - - IrDA update
        • -
          -
        • DMA transmit - process; the code has been - updated to avoid waiting on TC - flag under DMA ISR, IrDA TC - interrupt is used instead. - Below the update to be done on - user application:
          • -
            -
          • Configure - and enable the USART IRQ in - HAL_IRDA_MspInit() - function
            • -
          • In - stm32f4xx_it.c file, UASRTx_IRQHandler() - function: add a call to HAL_IRDA_IRQHandler() - - - - function
            • -
          -
        • IT transmit - process; the code has been - updated to avoid waiting on TC - flag under IRDA ISR, IrDA TC - interrupt is used instead. No - impact on user application
          • -
        • Rename - Macros: add prefix "__HAL"
          • -
            -
          • __IRDA_ENABLE() - by __HAL_IRDA_ENABLE()
            • -
          • __IRDA_DISABLE() - by __HAL_IRDA_DISABLE()
            • -
          -
        • Add new user - macros to manage the sample - method feature
          • -
            -
          • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE()
            • -
          • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE()
            • -
          -
        • HAL_IRDA_Transmit_IT(): update to - remove the enable of the - parity error interrupt
          • -
        • Add use - of tmpreg - variable in __HAL_IRDA_CLEAR_PEFLAG() - macro for compliancy with - C++
          • -
        • HAL_IRDA_Transmit_DMA() update to - follow the - right procedure - "Transmission using DMA"  - in the reference manual
          • -
            -
          • Add clear - the TC flag in the SR - register before enabling the - DMA transmit - request
            • -
          -
        -
      • HAL - - - - IWDG update
        • -
          -
        • Rename the - defined IWDG keys: 
          • -
            -
          • KR_KEY_RELOAD - - - - by IWDG_KEY_RELOAD
            • -
          • KR_KEY_ENABLE - - - - by IWDG_KEY_ENABLE
            • -
          • KR_KEY_EWA - by - IWDG_KEY_WRITE_ACCESS_ENABLE
            • -
          • KR_KEY_DWA - by - IWDG_KEY_WRITE_ACCESS_DISABLE
            • -
          -
        •  Add new - macros - __HAL_IWDG_RESET_HANDLE_STATE() - and - __HAL_IWDG_CLEAR_FLAG() 
          • -
        • Update - __HAL_IWDG_ENABLE_WRITE_ACCESS() - and - __HAL_IWDG_DISABLE_WRITE_ACCESS() - as private macro
          • -
        -
      -

      �  - - - - - HAL SPI update

      -
        -
          -
        • HAL_SPI_TransmitReceive_DMA() update to - remove the  DMA Tx Error - Callback initialization when - SPI RxOnly - mode is selected
          • -
        • Add use of UNUSED(tmpreg) - in __HAL_SPI_CLEAR_MODFFLAG(), - __HAL_SPI_CLEAR_OVRFLAG(), - __HAL_SPI_CLEAR_FREFLAG() to - fix "Unused variable" warning - with TrueSTUDIO.
          • -
        • Rename - Literals: remove "D" from - "DISABLED" and "ENABLED"
          • -
            -
          • SPI_TIMODE_DISABLED by - - - - - SPI_TIMODE_DISABLE
            • -
          • SPI_TIMODE_ENABLED by SPI_TIMODE_ENABLE
            • -
          • SPI_CRCCALCULATION_DISABLED - by - - - - -  SPI_CRCCALCULATION_DISABLE
            • -
          • SPI_CRCCALCULATION_ENABLED - by - - - - -  SPI_CRCCALCULATION_ENABLE
            • -
          -
        • Add use - of tmpreg - variable in __HAL_SPI_CLEAR_MODFFLAG(), - - - - - __HAL_SPI_CLEAR_FREFLAG() and - __HAL_SPI_CLEAR_OVRFLAG() - macros for compliancy - with C++
          • -
        -
      -

      �  - - - - - HAL SDMMC update

      -
        -
          -
        • IS_SDIO_ALL_INSTANCE() -  macro moved to CMSIS - files
          • -
        -
      • HAL - - - - LTDC update
        • -
          -
        • HAL_LTDC_ConfigCLUT: optimize - the function when pixel format -is LTDC_PIXEL_FORMAT_AL44 
          • -
            -
          • Update the - size of color look up table - to 16 instead of 256 when - the pixel format - is LTDC_PIXEL_FORMAT_AL44 -
            • -
          -
        -
      • HAL - - - - NAND update
        • -
          -
        • Rename NAND - Address structure to NAND_AddressTypeDef - instead of NAND_AddressTypedef
          • -
        • Update the - used algorithm of these functions
          • -
            -
          • HAL_NAND_Read_Page()
            • -
          • HAL_NAND_Write_Page()
            • -
          • HAL_NAND_Read_SpareArea()
            • -
          • HAL_NAND_Write_SpareArea()
            • -
          -
        • HAL_NAND_Write_Page(): move - initialization of tickstart - before while loop
          • -
        • HAL_NAND_Erase_Block(): add whait - until NAND status is ready - before exiting this function
          • -
        -
      • HAL - - - - NOR update
        • -
          -
        • Rename NOR - Address structure to NOR_AddressTypeDef - instead of NOR_AddressTypedef
          • -
        • NOR Status - literals renamed
          • -
            -
          • NOR_SUCCESS - by HAL_NOR_STATUS_SUCCESS
            • -
          • NOR_ONGOING - by HAL_NOR_STATUS_ONGOING
            • -
          • NOR_ERROR - by HAL_NOR_STATUS_ERROR
            • -
          • NOR_TIMEOUT - by HAL_NOR_STATUS_TIMEOUT
            • -
          -
        • HAL_NOR_GetStatus() update to - fix Timeout issue - and exit from waiting - loop when timeout occurred
          • -
        -
      • HAL - - - - PCCARD update
        • -
          -
        • Rename PCCARD - Address structure to HAL_PCCARD_StatusTypeDef - instead of CF_StatusTypedef
          • -
        • PCCARD Status - literals renamed
          • -
            -
          • CF_SUCCESS - by HAL_PCCARD_STATUS_SUCCESS
            • -
          • CF_ONGOING - by HAL_PCCARD_STATUS_ONGOING
            • -
          • CF_ERROR - by HAL_PCCARD_STATUS_ERROR
            • -
          • CF_TIMEOUT - by HAL_PCCARD_STATUS_TIMEOUT
            • -
          -
        • Update "CF" - by "PCCARD" in functions, - literals - and macros
          • -
        -
      • HAL - - - - PCD update
        • -
          -
        • Rename functions
          • -
            -
          • HAL_PCD_ActiveRemoteWakeup() by HAL_PCD_ActivateRemoteWakeup()
            • -
          • HAL_PCD_DeActiveRemoteWakeup() by HAL_PCD_DeActivateRemoteWakeup()
            • -
          -
        • Rename literals
          • -
            -
          • USB_FS_EXTI_TRIGGER_RISING_EDGE - - - - - by - USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
            • -
          • USB_FS_EXTI_TRIGGER_FALLING_EDGE - - - - - by - USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
            • -
          • USB_FS_EXTI_TRIGGER_BOTH_EDGE() - by - USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
            • -
          • USB_HS_EXTI_TRIGGER_RISING_EDGE - - - - - by - USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 
            • -
          • USB_HS_EXTI_TRIGGER_FALLING_EDGE - - - - - by - USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
            • -
          • USB_HS_EXTI_TRIGGER_BOTH_EDGE - - - - - by - USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
            • -
          • USB_HS_EXTI_LINE_WAKEUP - - - - - by - USB_OTG_HS_EXTI_LINE_WAKEUP
            • -
          • USB_FS_EXTI_LINE_WAKEUP - - - - - by - USB_OTG_FS_EXTI_LINE_WAKEUP
            • -
          -
        • Rename USB - EXTI macros (FS, HS - - - - referenced as SUBBLOCK - here below)
          • -
            -
          • __HAL_USB_SUBBLOCK_EXTI_ENABLE_IT() -  by  - __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_IT()  
            • -
          • __HAL_USB_SUBBLOCK_EXTI_DISABLE_IT() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_DISABLE_IT()
            • -
          • __HAL_USB_SUBBLOCK_EXTI_GET_FLAG() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GET_FLAG() 
            • -
          • __HAL_USB_SUBBLOCK_EXTI_CLEAR_FLAG() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_CLEAR_FLAG()
            • -
          • __HAL_USB_SUBBLOCK_EXTI_SET_RISING_EGDE_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_EDGE()
            • -
          • __HAL_USB_SUBBLOCK_EXTI_SET_FALLING_EGDE_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
            • -
          • __HAL_USB_SUBBLOCK_EXTI_SET_FALLINGRISING_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
            • -
          • __HAL_USB_SUBBLOCK_EXTI_GENERATE_SWIT()  - - - - - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GENERATE_SWIT()                                       - - - - -
            • -
          -
        -
      -
        -
      • HAL - - - - RNG update
        • -
          -
        • Add new functions
          • -
            -
          • HAL_RNG_GenerateRandomNumber(): to - generate a 32-bits random - number, - return - random value in argument and - return HAL status.
            • -
          • HAL_RNG_GenerateRandomNumber_IT(): to -  start generation of - the 32-bits random - number, user should call - the HAL_RNG_ReadLastRandomNumber() - - - - - function under the HAL_RNG_ReadyCallback() - - - - to get the generated random - value.
            • -
          • HAL_RNG_ReadLastRandomNumber(): to - return the last random value - stored in the RNG handle
            • -
          -
        • HAL_RNG_GetRandomNumber(): return - value update (obsolete), - replaced by HAL_RNG_GenerateRandomNumber()
          • -
        • HAL_RNG_GetRandomNumber_IT(): wrong - implementation (obsolete), - replaced by HAL_RNG_GenerateRandomNumber_IT()
          • -
        • __HAL_RNG_CLEAR_FLAG() - macro (obsolete), replaced by - new __HAL_RNG_CLEAR_IT() macro
          • -
        • Add new - define for RNG ready - interrupt:  RNG_IT_DRDY
          • -
        -
      • HAL - - - - RTC update
        • -
          -
        • HAL_RTC_GetTime() and HAL_RTC_GetDate(): - - - - - add the comment below
          • -
        -
      -
      -
      -

        - - - - - * @note You must call HAL_RTC_GetDate() - after HAL_RTC_GetTime() - - - - - to unlock the values
      -         - - - - - * in the higher-order - calendar shadow registers to - ensure consistency between - the time and date values.
      -         - - - - - * Reading RTC current time - locks the values in calendar - shadow registers until - Current date is read. 

      -
      -
      -
        -
          -
        • Rename - literals: add prefix "__HAL"
          • -
            -
          • FORMAT_BIN by HAL_FORMAT_BIN
            • -
          • FORMAT_BCD - by HAL_FORMAT_BCD
            • -
          -
        • Rename macros - (ALARM, WAKEUPTIMER and - TIMESTAMP referenced - as SUBBLOCK here - below)
          • -
            -
          • __HAL_RTC_EXTI_ENABLE_IT() - by  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_IT()
            • -
          • __HAL_RTC_EXTI_DISABLE_IT() - by  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_IT()
            • -
          • __HAL_RTC_EXTI_CLEAR_FLAG() - by  __HAL_RTC_SUBBLOCK_EXTI_CLEAR_FLAG()
            • -
          • __HAL_RTC_EXTI_GENERATE_SWIT() - by __HAL_RTC_SUBBLOCK_EXTI_GENERATE_SWIT()
            • -
          -
        • Add new - macros (ALARM, - WAKEUPTIMER and TAMPER_TIMESTAMP - - - - referenced as SUBBLOCK - here below)
          • -
            -
          • __HAL_RTC_SUBBLOCK_GET_IT_SOURCE() 
            • -
          • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_EVENT()
            • -
          • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_EVENT()
            • -
          • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_FALLING_EDGE()
            • -
          • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_FALLING_EDGE()
            • -
          • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_EDGE()
            • -
          • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_EDGE()
            • -
          •  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_FALLING_EDGE()
            • -
          •  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_FALLING_EDGE()
            • -
          •  __HAL_RTC_SUBBLOCK_EXTI_GET_FLAG()
            • -
          -
        -
      • HAL - - - - SAI update
        • -
          -
        • Update - SAI_STREOMODE by SAI_STEREOMODE
          • -
        • Update FIFO - status Level defines in upper - case
          • -
        • Rename - literals: remove "D" from - "DISABLED" and "ENABLED"
          • -
            -
          • SAI_OUTPUTDRIVE_DISABLED - - - - -  by - SAI_OUTPUTDRIVE_DISABLE
            • -
          • SAI_OUTPUTDRIVE_ENABLED - - - - -  by - SAI_OUTPUTDRIVE_ENABLE
            • -
          • SAI_MASTERDIVIDER_ENABLED  by - SAI_MASTERDIVIDER_ENABLE
            • -
          • SAI_MASTERDIVIDER_DISABLED  by - SAI_MASTERDIVIDER_DISABLE
            • -
          -
        -
      -
        -
      • HAL - - - - SD update
        • -
          -
        • Rename - SD_CMD_SD_APP_STAUS by SD_CMD_SD_APP_STATUS
          • -
        • SD_PowerON() updated to - add 1ms required power up - waiting time before starting - the SD initialization sequence
          • -
        • SD_DMA_RxCplt()/SD_DMA_TxCplt(): - - - - - add a call to - HAL_DMA_Abort()
          • -
        • HAL_SD_ReadBlocks() update to - set the defined - DATA_BLOCK_SIZE as SDIO DataBlockSize - parameter
          • -
        • HAL_SD_ReadBlocks_DMA()/HAL_SD_WriteBlocks_DMA() - update to call the HAL_DMA_Start_IT() - - - - function with DMA Datalength - set to BlockSize/4  - - - - - as the DMA is - configured in word 
          • -
        -
      • HAL - - - - SMARTCARD update 
        • -
          -
        • DMA transmit - process; the code has been - updated to avoid waiting on TC - flag under DMA ISR, SMARTCARD - TC interrupt is used instead. - Below the update to be done on - user application:
          • -
            -
          • Configure - and enable the USART IRQ in - HAL_SAMRTCARD_MspInit() - function
            • -
          • In - stm32f4xx_it.c file, UASRTx_IRQHandler() - function: add a call to HAL_SMARTCARD_IRQHandler() - - - - - function
            • -
          -
        • IT transmit - process; the code has been - updated to avoid waiting on TC - flag under SMARTCARD - ISR, SMARTCARD TC - interrupt is used instead. No - impact on user application
          • -
        • Rename - macros: add prefix "__HAL"
          • -
            -
          • __SMARTCARD_ENABLE() - by __HAL_SMARTCARD_ENABLE()
            • -
          • __SMARTCARD_DISABLE() - by __HAL_SMARTCARD_DISABLE()
            • -
          • __SMARTCARD_ENABLE_IT() - by - __HAL_SMARTCARD_ENABLE_IT()
            • -
          • __SMARTCARD_DISABLE_IT() - by - __HAL_SMARTCARD_DISABLE_IT()
            • -
          • __SMARTCARD_DMA_REQUEST_ENABLE() - by - __HAL_SMARTCARD_DMA_REQUEST_ENABLE()
            • -
          • __SMARTCARD_DMA_REQUEST_DISABLE() - by - __HAL_SMARTCARD_DMA_REQUEST_DISABLE()
            • -
          -
        • Rename - literals: remove "D" from - "DISABLED" and "ENABLED"
          • -
            -
          • SMARTCARD_NACK_ENABLED by - - - - - SMARTCARD_NACK_ENABLE
            • -
          • SMARTCARD_NACK_DISABLED by SMARTCARD_NACK_DISABLE
            • -
          -
        • Add new user - macros to manage the sample - method feature
          • -
            -
          • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE()
            • -
          • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE()
            • -
          -
        • Add use - of tmpreg - variable in - __HAL_SMARTCARD_CLEAR_PEFLAG() - macro for compliancy with - C++
          • -
        • HAL_SMARTCARD_Transmit_DMA() update to - follow the - right procedure - "Transmission using DMA"  - in the reference manual
          • -
            -
          • Add clear - the TC flag in the SR - register before enabling the - DMA transmit - request
            • -
          -
        -
      • HAL - - - - TIM update
        • -
          -
        • Add - TIM_CHANNEL_ALL as possible - value for all Encoder - Start/Stop APIs Description
          • -
        • HAL_TIM_OC_ConfigChannel() remove call - to IS_TIM_FAST_STATE() assert - macro
          • -
        • HAL_TIM_PWM_ConfigChannel() add a call - to IS_TIM_FAST_STATE() assert - macro to check the OCFastMode - parameter
          • -
        • HAL_TIM_DMADelayPulseCplt() Update to - set the TIM Channel before to - call  HAL_TIM_PWM_PulseFinishedCallback()
          • -
        • HAL_TIM_DMACaptureCplt() update to - set the TIM Channel before to - call  HAL_TIM_IC_CaptureCallback()
          • -
        • TIM_ICx_ConfigChannel() update - to fix Timer CCMR1 register - corruption when setting ICFilter - parameter
          • -
        • HAL_TIM_DMABurst_WriteStop()/HAL_TIM_DMABurst_ReadStop() - update to abort the DMA - transfer for the specifc - TIM channel
          • -
        • Add new - function for TIM Slave - configuration in IT mode: - HAL_TIM_SlaveConfigSynchronization_IT() 
          • -
        • HAL_TIMEx_ConfigBreakDeadTime() add an - assert check on Break & DeadTime - parameters values
          • -
        • HAL_TIMEx_OCN_Start_IT() add the - enable of Break Interrupt for - all output modes
          • -
        • Add new - macros to ENABLE/DISABLE URS - bit in TIM CR1 register:
          • -
            -
          • __HAL_TIM_URS_ENABLE()
            • -
          • __HAL_TIM_URS_DISABLE()
            • -
          -
        • Add new macro - for TIM Edge modification: - __HAL_TIM_SET_CAPTUREPOLARITY()
          • -
        -
      • HAL - - - - UART update
        • -
          -
        • Add IS_LIN_WORD_LENGTH() - and - IS_LIN_OVERSAMPLING()  - macros: to check respectively - WordLength - and OverSampling - parameters in LIN mode
          • -
        • DMA transmit - process; the code has been - updated to avoid waiting on TC - flag under DMA ISR, UART TC - interrupt is used instead. - Below the update to be done on - user application:
          • -
            -
          • Configure - and enable the USART IRQ in - HAL_UART_MspInit() - function
            • -
          • In - stm32f4xx_it.c file, USARTx_IRQHandler() - function: add a call to HAL_UART_IRQHandler() - - - - function
            • -
          -
        • IT transmit - process; the code has been - updated to avoid waiting on TC - flag under UART ISR, UART - TC interrupt is used instead. - No impact on user application
          • -
        • Rename - macros:
          • -
            -
          • __HAL_UART_ONEBIT_ENABLE() - by - __HAL_UART_ONE_BIT_SAMPLE_ENABLE()
            • -
          • __HAL_UART_ONEBIT_DISABLE() - by - __HAL_UART_ONE_BIT_SAMPLE_DISABLE()
            • -
          -
        • Rename - literals:
          • -
            -
          • UART_WAKEUPMETHODE_IDLELINE by - - - - - UART_WAKEUPMETHOD_IDLELINE
            • -
          • UART_WAKEUPMETHODE_ADDRESSMARK by -UART_WAKEUPMETHOD_ADDRESSMARK
            • -
          -
        • Add use - of tmpreg - variable in __HAL_UART_CLEAR_PEFLAG() - macro for compliancy with - C++
          • -
        • HAL_UART_Transmit_DMA() update to - follow the right procedure - "Transmission using DMA" in - the reference manual
          • -
            -
          • Add clear - the TC flag in the SR - register before enabling the - DMA transmit - request
            • -
          -
        -
      • HAL - - - - USART update
        • -
          -
        • DMA transmit - process; the code has been - updated to avoid waiting on TC - flag under DMA ISR, USART TC - interrupt is used instead. - Below the update to be done on - user application:
          • -
            -
          • Configure - and enable the USART IRQ in - HAL_USART_MspInit() - function
            • -
          • In - stm32f4xx_it.c file, USARTx_IRQHandler() - function: add a call to HAL_USART_IRQHandler() - - - - - function
            • -
          -
        • IT transmit - process; the code has been - updated to avoid waiting on TC - flag under USART ISR, - USART TC interrupt is used - instead. No impact on user - application
          • -
        • HAL_USART_Init() update - to enable the USART - oversampling by 8 by default - in order to reach max USART - frequencies
          • -
        • USART_DMAReceiveCplt() update - to set the new USART state - after checking on the - old state
          • -
        • HAL_USART_Transmit_DMA()/HAL_USART_TransmitReceive_DMA() - update to - follow the - right procedure - "Transmission using DMA"  - in the reference manual
          • -
            -
          • Add clear - the TC flag in the SR - register before enabling the - DMA transmit - request
            • -
          -
        • Rename - macros:
          • -
            -
          • __USART_ENABLE() - by __HAL_USART_ENABLE()
            • -
          • __USART_DISABLE() - by __HAL_USART_DISABLE()
            • -
          • __USART_ENABLE_IT() - by __HAL_USART_ENABLE_IT()
            • -
          • __USART_DISABLE_IT() - by __HAL_USART_DISABLE_IT()
            • -
          -
        • Rename - literals: remove "D" from - "DISABLED" and "ENABLED"
          • -
            -
          • USART_CLOCK_DISABLED by - - - - - USART_CLOCK_DISABLE
            • -
          • USART_CLOCK_ENABLED by - - - - - USART_CLOCK_ENABLEAdded two + new APIs:
            • +
              +
            • HAL_DACEx_DualStart()
              • +
            • HAL_DACEx_DualStop()
              • +
            +
          +
        • Added + position bit definition to + be used instead of + __DAC_MASK_SHIFT macro
          • +
            +
          • __DAC_MASK_SHIFT - "Times New Roman"">
            • -
          • Updated HAL_DAC_Start_DMA() + API to return HAL_ERROR when + error occurs.
            • +
          • Updated HAL_DAC_Stop_DMA() + API to not return HAL_ERROR + when DAC is already + disabled.
            • +
          +
        • HAL CEC update
          • +
            +
          • Updated HAL_CEC_IRQHandler() + API to avoid appending an + extra byte to the end of a + message.
            • +
          +
        • HAL/LL GPIO update
          • +
            +
          • Updated + IS_GPIO_AF() to + add missing values for + STM32F401xC and STM32F401xE + devices:
            • +
              +
            • GPIO_AF3_TIM9
              • +
            • GPIO_AF3_TIM10
              • +
            • GPIO_AF3_TIM11
              • +
            +
          • Updated + LL/HAL GPIO_TogglePin() + APIs to allow multi Pin�s + toggling.
            • +
          • Updated HAL_GPIO_Init() + API to avoid the + configuration of PUPDR + register when Analog mode is + selected.
            • +
          +
        • HAL/LL RCC update
          • +
            +
          • Updated HAL_RCC_OscConfig() + API to add missing checks + and to don�t return + HAL_ERROR if request repeats + the current PLL + configuration.
            • +
          • Updated + IS_RCC_PLLN_VALUE(VALUE) + macro in case of STM32F411xE + device in order to + be aligned with reference + manual.
            • +
          +
        • HAL SD update
          • +
            +
          • Update + function SD_FindSCR() + to resolve issue of FIFO + blocking when reading.
            • +
          • Update + read/write functions in DMA + mode in - mso-fareast-font-family:"Times + order to + force the DMA direction, + updated functions:
            • +
              +
            • HAL_SD_ReadBlocks_DMA()
              • +
            • HAL_SD_WriteBlocks_DMA()
              • +
            +
          • Add the + block size settings in the + initialization functions and + remove it from read/write + transactions to avoid + repeated and inefficient + reconfiguration, updated + functions:
            • +
              +
            • HAL_SD_InitCard()
              • +
            • HAL_SD_GetCardStatus()
              • +
            • HAL_SD_ConfigWideBusOperation() 
              • +
            • HAL_SD_ReadBlocks()
              • +
            • HAL_SD_WriteBlocks()
              • +
            • HAL_SD_ReadBlocks_IT()
              • +
            • HAL_SD_WriteBlocks_IT()
              • +
            • HAL_SD_ReadBlocks_DMA()
              • +
            • HAL_SD_WriteBlocks_DMA()
              • +
            +
          +
        • HAL MMC update
          • +
            +
          • Add the + block size settings in the + initialization function and + remove it from read/write + transactions to avoid + repeated and inefficient + reconfiguration, updated + functions:
            • +
              +
            • HAL_MMC_InitCard()
              • +
            • HAL_MMC_ReadBlocks()
              • +
            • HAL_MMC_WriteBlocks()
              • +
            • HAL_MMC_ReadBlocks_IT()
              • +
            • HAL_MMC_WriteBlocks_IT()
              • +
            • HAL_MMC_ReadBlocks_DMA()
              • +
            • HAL_MMC_WriteBlocks_DMA()
              • +
            +
          • Update + read/write functions in DMA + mode in - New Roman"">USARTNACK_ENABLED + order to + force the DMA direction, + updated functions:
            • +
              +
            • HAL_MMC_ReadBlocks_DMA()
              • +
            • HAL_MMC_WriteBlocks_DMA()
              • +
            +
          • Deploy new + functions MMC_ReadExtCSD() + and SDMMC_CmdSendEXTCSD + () that read and check the + sectors number of the + device in order to resolve + the issue of wrongly reading + big memory size.
            • +
          +
        • HAL NAND + update
          • +
            +
          • Update + functions + HAL_NAND_Read_SpareArea_16b() + and + HAL_NAND_Write_SpareArea_16b() + to fix column address + calculation issue.
            • +
          +
        • LL SDMMC + update
          • +
            +
          • Update the + definition of + SDMMC_DATATIMEOUT constant in - by USART_NACK_ENABLERemove + 'register' storage class + specifier from LL SDMMC + driver.
            • +
          • Deploy new + functions MMC_ReadExtCSD() + and SDMMC_CmdSendEXTCSD + () that read and check the + sectors number of the device + in order to resolve the + issue of wrongly reading big + memory size.
            • +
          +
        • HAL SMBUS update
          • +
            +
          • Support for + Fast Mode Plus to be SMBUS + rev 3 compliant.
            • +
          • Added HAL_FMPSMBUSEx_EnableFastModePlus() + and HAL_FMPSMBUSEx_DisableFastModePlus() - New Roman"">
            • -
          • Updated SMBUS_MasterTransmit_BTF() + , SMBUS_MasterTransmit_TXE() - mso-fareast-font-family:"Times + and SMBUS_MasterReceive_BTF() - New Roman"">USARTNACK_DISABLED - by USART_NACK_DISABLECurrentXferOptions + is different from + SMBUS_FIRST_FRAME and + SMBUS_NEXT_FRAME.
            • +
          • Updated SMBUS_ITError() + API to correct the twice + call of HAL_SMBUS_ErrorCallback.
            • +
          +
        • HAL SPI update
          • +
            +
          • Updated HAL_SPI_Init() + API
            • +
              +
            • To avoid + setting the BaudRatePrescaler + in case of Slave Motorola + Mode.
              • +
            • Use the bit-mask + for SPI configuration.
              • +
            +
          • Updated + Transmit/Receive processes + in half-duplex mode
            • +
              +
            • Disable + the SPI instance before + setting BDIOE bit.
              • +
            +
          • Fixed wrong + timeout management
            • +
          • Calculate + Timeout based on a software + loop to avoid blocking issue + if Systick + is disabled.
            • +
          +
        • HAL + SPDIFRX update
          • +
            +
          • Remove + 'register' storage class + specifier from HAL SPDIFRX + driver.
            • +
          +
        • HAL I2S update
          • +
            +
          • Updated + I2SEx APIs to correctly + support circular transfers
            • +
              +
            • Updated + I2SEx_TxRxDMACplt() + API to manage DMA circular + mode.
              • +
            +
          • Updated + HAL_I2SEx_TransmitReceive_DMA() + API to set hdmatx + (transfert + callback and half) to NULL.
            • +
          +
        • HAL SAI update
          • +
            +
          • Updated to + avoid the incorrect + left/right synchronization.
            • +
              +
            • Updated HAL_SAI_Transmit_DMA() + API to follow the sequence + described in the reference + manual for slave + transmitter mode.
              • +
            +
          • Updated HAL_SAI_Init() + API to correct the formula + in case of SPDIF is wrong.
            • +
          +
        • HAL CRYP update
          • +
            +
          • Updated HAL_CRYP_SetConfig() + and HAL_CRYP_GetConfig() - "Times New Roman"">
            • + APIs to set/get the + continent of KeyIVConfigSkip + correctly.
          -
        • HAL EXTI update
          • +
            +
          • __EXTI_LINE__ - mso-fareast-font-family:"Times + is now used instead of + __LINE__ which is a standard + C macro.
            • +
          +
        • HAL DCMI
          • +
            +
          • Support of + HAL callback registration + feature for DCMI extended + driver.
            • +
          +
        • HAL/LL TIM update
          • +
            +
          • Updated HAL_TIMEx_OnePulseN_Start() + and HAL_TIMEx_OnePulseN_Stop() - New Roman"">Add new user - macros to manage the sample - method featureOutputChannel + parameters.
            • +
          • Corrected + reversed description of + TIM_LL_EC_ONEPULSEMODE One + Pulse Mode.
            • +
          • Updated LL_TIM_GetCounterMode() + API to return the correct + counter mode.
            • +
          +
        • HAL/LL + SMARTCARD update
          • +
            +
          • Fixed + invalid initialization of + SMARTCARD configuration by + removing FIFO mode + configuration as it is not + member of SMARTCARD_InitTypeDef + Structure.
            • +
          • Fixed typos + in SMARTCARD State + definition description
            • +
          +
        • HAL/LL IRDA update
          • +
            +
          • Fixed typos + in IRDA State definition + description
            • +
          +
        • LL USART update
          • +
            +
          • Remove + useless check on maximum BRR + value by removing + IS_LL_USART_BRR_MAX() + macro.
            • +
          • Update + USART polling and + interruption processes to + fix issues related to + accesses out of user + specified buffer.
            • +
          +
        • HAL USB update
          • +
            +
          • Enhanced + USB OTG host HAL with USB + DMA is enabled:
            • +
              +
            • fixed + ping and data toggle + issue,
              • +
            • reworked + Channel error report + management
              • +
            +
          +
        +
      +

      V1.7.10 - New Roman""> -
        -

      +

      Main Changes

      +
        +
      • General - mso-fareast-font-family:"Times + updates to fix known defects.
        • +
      • HAL/LL - New Roman"">__HAL_USART_ONE_BIT_SAMPLE_ENABLE()update
        • +
      +
        +
          +
        •   Update + to fix hardfault + issue with HAL_I2C_Mem_Write_DMA() + API:
          • +
            +
          •   + Abort the right ongoing DMA + transfer when memory write + access request operation + failed: fix typo �hdmarx� + replaced by �hdmatx�
            • +
          +
        +
      +

      V1.7.9 - New Roman""> -

      • +

      Main Changes

      +
        +
      • General + updates to fix known defects and + enhancements implementation
        • +
      • HAL/LL - mso-fareast-font-family:"Times + I2C update
        • +
      +
        +
          +
        •   Update + HAL_I2C_ER_IRQHandler() + API to fix acknowledge failure + issue with I2C memory IT + processes
          • +
            +
          •   Add + stop condition generation + when NACK occurs.
            • +
          +
        •   Update + I2C_DMAXferCplt(), - New Roman"">__HAL_USART_ONE_BIT_SAMPLE_DISABLE()
          • + I2C_DMAError() and + I2C_DMAAbort() APIs to fix hardfault + issue when hdmatx + and hdmarx + parameters in i2c handle + aren't initialized (NULL + pointer). +
            +
          •   Add + additional check on + hi2c->hdmtx + and hi2c->hdmarx + before resetting DMA Tx/Rx + complete callbacks
          -
        •   Update + Sequential transfer APIs to + adjust xfermode + condition.
          • +
            +
          •   - mso-fareast-font-family:"Times - New Roman"">Add use - of tmpreg - variable in __HAL_USART_CLEAR_PEFLAG() - macro for compliancy with - C++
            • + Replace hi2c->XferCount + < MAX_NBYTE_SIZE by + hi2c->XferCount + <= MAX_NBYTE_SIZE which + corresponds to a case + without reload +
        -
      • +
      •  HAL/LL - "Times New Roman"">HAL + USB update
        • +
          +
        •   Bug - WWDG USB_ReadPMA() + and USB_WritePMA() - New Roman"">update
          • -
            -
          •   Bug + fix: correct USB RX count + calculation
            • +
          •   Fix + USB Bulk transfer double + buffer mode
            • +
          •   Remove + register keyword from USB + defined macros as no more + supported by C++ compiler
            • +
          •   Minor + rework on USBD_Start() + and USBD_Stop() - mso-fareast-font-family:"Times - New Roman"">Add new - parameter in - __HAL_WWDG_ENABLE_IT() - macro
            • -
          • HAL_PCD_DeInit() - mso-fareast-font-family:"Times + API.
            • +
          •   Remove + non used API for USB device + mode.
            • +
          +
        +

        V1.7.8 - New Roman"">Add new - macros to manage WWDG IT & - correction: -
          -

        +

        Main Changes

        +
          +
        • Add + new HAL FMPSMBUS and LL + FMPI2C drivers
          • +
        • General - mso-fareast-font-family:"Times + updates to fix known defects and + enhancements implementation
          • +
        +
          +
        • Update - New Roman"">__HAL_WWDG_DISABLE()
          • +
        • Improve - New Roman"">
          • -
        • violations
          • +
        • HAL/LL - mso-fareast-font-family:"Times + USB update
          • +
            +
          •  Add + handling USB host babble error + interrupt
            • +
          •  Fix + Enabling ULPI interface for + platforms that integrates USB + HS PHY
            • +
          •  Fix + Host data toggling for IN Iso + transfers
            • +
          •  Ensure + to disable USB EP during + endpoint deactivation
            • +
          +
        • HAL - New Roman"">__HAL_WWDG_DISABLE_IT()update
          • +
            +
          •  Update + HAL CRYP driver to support + block by block decryption + without initializing the IV + and KEY at each call.
            • +
              +
            • Add new + CRYP Handler parameters: "KeyIVConfig" + and "SizesSum"
              • +
            • Add new + CRYP init + parameter: "KeyIVConfigSkip"
              • +
            +
          +
        • HAL - New Roman"">
          • -
        • update
          • +
            +
          • Update + HAL_I2S_DMAStop() + API to be more safe
            • +
              +
            • Add a check + on BSY, TXE and RXNE flags + before disabling the I2S
              • +
            +
          • Update + HAL_I2S_DMAStop() + API to fix multi-call transfer + issue(to avoid re-initializing + the I2S for the next + transfer).
            • +
              +
            • Add + __HAL_I2SEXT_FLUSH_RX_DR() + and __HAL_I2S_FLUSH_RX_DR() + macros to flush the + remaining data inside DR + registers.
              • +
            • Add new ErrorCode + define: + HAL_I2S_ERROR_BUSY_LINE_RX
              • +
            +
          +
        +

        V1.7.7 - mso-fareast-font-family:"Times + / 06-December-2019

        +

        Main Changes

        +
          +
        • General - New Roman"">__HAL_WWDG_GET_IT()implementation
          • +
        • HAL - New Roman"">
          • -
        • update
          • +
            +
          • HAL_SetTickFreq(): update to + restore the previous tick + frequency when HAL_InitTick() - mso-fareast-font-family:"Times + configuration failed.
            • +
          +
        • HAL/LL - New Roman"">__HAL_WWDG_GET_IT_SOURCE()update
          • +
            +
          • Update GPIO + initialization sequence to - New Roman"">
            • -
          + avoid unwanted pulse on GPIO Pin's
        -
      -

      HAL - New Roman";color:white">V1.1.0 - - - - / 19-June-2014

      -

      Main Changes

      -
        -
      • update
        • +
      +
        +
          +
        • General + update to enhance HAL EXTI + driver robustness 
          • +
            +
          • Add + additional assert check on + EXTI config lines
            • +
          • Update to + compute EXTI line mask + before read/write access + to EXTI registers
            +
            +
            • +
          +
        • Update EXTI + callbacks management to be + compliant with reference + manual: only one PR + register for rising and + falling interrupts.
          • +
            +
          • Update + parameters in EXTI_HandleTypeDef + structure: merge HAL + EXTI RisingCallback + and FallingCallback + in only one PendingCallback
            • +
          • Remove + HAL_EXTI_RISING_CB_ID and + HAL_EXTI_FALLING_CB_ID + values from EXTI_CallbackIDTypeDef + enumeration.
            +
            +
            • +
          +
        • Update + HAL_EXTI_IRQHandler() + API to serve interrupts + correctly.
          • +
            +
          • Update to + compute EXTI line mask + before handle + EXTI interrupt.
            • +
          +
        • Update to + support GPIO port + interrupts:
          • +
            +
          • Add new "GPIOSel" + parameter in EXTI_ConfigTypeDef + structure
            • +
          +
        +
      • HAL/LL - "Times New Roman"">Add - support of STM32F411xE devicesupdate
        • +
          +
        • Update HAL_RCCEx_PeriphCLKConfig() + API to support PLLI2S + configuration for STM32F42xxx + and STM32F43xxx devices
          • +
        • Update the HAL_RCC_ClockConfig() + and HAL_RCC_DeInit() - New Roman"">
          • -
        -
          -
          • +
        • Fix LL_RCC_DeInit() + failure detected with gcc + compiler and high optimization + level is selected(-03)
          • +
        • Update HAL_RCC_OscConfig() + API to don't return + HAL_ERROR if request repeats + the current PLL configuration
          • +
        +
      • HAL - "Times New Roman"">HAL + ADC update
        • +
          +
        • Update LL_ADC_REG_Init() + to fix wrong ADC CR1 register + configuration
          • +
            +
          • The ADC + sequencer length is part + of ADC SQR1 + register not of ADC CR1 + register
            • +
          +
        +
      • HAL - genericupdate
        • +
          +
        • Update HAL_CRYP_Encrypt() + and HAL_CRYP_Decrypt() - "Times New Roman""> - update
          • -
            -
            • +
          +
        • HAL + RNG update
          • +
            +
          • Update HAL_RNG_IRQHandler() + API to fix error code + management issue: error code + is assigned + "HAL_RNG_ERROR_CLOCK" in case + of clock error and + "HAL_RNG_ERROR_SEED" in case + of seed error, not the + opposite.
            • +
          +
        • HAL - mso-fareast-font-family:"Times + DFSDM update
          • +
            +
          • Update DFSDM_GetChannelFromInstance() + API to remove unreachable + check condition
            • +
          +
        • HAL - New Roman"">Enhance HAL - delay and time base implementationupdate
          • +
            +
          • Update HAL_DMA_Start_IT() + API to omit the FIFO error
            • +
          +
        • HAL - New Roman"">
          • -
            -
          • update
            • +
              +
            • Update FLASH_Program_DoubleWord() + API to fix with EWARM high + level optimization issue
              • +
            +
          • HAL - New Roman"">Systickupdate
            • +
              +
            • Remove Lock + mechanism from HAL_QSPI_Init() + and HAL_QSPI_DeInit() - mso-fareast-font-family:"Times + APIs
              • +
            +
          • HAL - New Roman""> timer is - used by default as source of - time base, but user can - eventually implement his - proper time base source (a general + HASH update
            • +
              +
            • Null pointer + on handler "hhash" + is now checked before + accessing structure member "hhash->Init.DataType" + in the following API:
              • +
                +
              • HAL_HASH_Init()
                • +
              +
            • Following interrupt-based + APIs have been added. + Interrupt mode could allow the + MCU to enter "Sleep" mode + while a data block is being + processed. Please refer to the + "##### How to use this driver + #####" section for details + about their use.
              • +
                +
              • HAL_HASH_SHA1_Accmlt_IT()
                • +
              • HAL_HASH_MD5_Accmlt_IT()
                • +
              • HAL_HASHEx_SHA224_Accmlt_IT()
                • +
              • HAL_HASHEx_SHA256_Accmlt_IT()
                • +
              +
            • Following aliases + have been added (just for + clarity sake) as they + shall be used at the end + of the computation of a + multi-buffers message and not + at the start:
              • +
                +
              • HAL_HASH_SHA1_Accmlt_End() + to be used instead of + HAL_HASH_SHA1_Start()
                • +
              • HAL_HASH_MD5_Accmlt_End() + to be used instead of + HAL_HASH_MD5_Start()
                • +
              • HAL_HASH_SHA1_Accmlt_End_IT() + to be used instead of + HAL_HASH_SHA1_Start_IT()
                • +
              • HAL_HASH_MD5_Accmlt_End_IT() + to be used instead of + HAL_HASH_MD5_Start_IT()
                • +
              • HAL_HASHEx_SHA224_Accmlt_End() + to be used instead of + HAL_HASHEx_SHA224_Start()
                • +
              • HAL_HASHEx_SHA256_Accmlt_End() + to be used instead of + HAL_HASHEx_SHA256_Start()
                • +
              +
            +
          +
            +
              +
                +
              • HAL_HASHEx_SHA224_Accmlt_End_IT() + to be used instead of + HAL_HASHEx_SHA224_Start_IT()
                • +
              • HAL_HASHEx_SHA256_Accmlt_End_IT() + to be used instead of + HAL_HASHEx_SHA256_Start_IT()
                • +
              +
            +
          +
            +
              +
            • MISRAC-2012 + rule R.5.1 (identifiers + shall be distinct in the first + 31 characters) constrained the + naming of the above listed + aliases (e.g. + HAL_HASHEx_SHA256_Accmlt_End() + could not be named + HAL_HASHEx_SHA256_Accumulate_End(). - purpose - timer for example or other - time source)
              • -
            • IT()). + In - mso-fareast-font-family:"Times - New Roman"">Functions - affecting time base - configurations are declared - as __Weak to make override - possible in case of other - implementations in user - file, for more details - please refer to HAL_TimeBase - example
              • + order to + have aligned names following + APIs have been renamed: +
            +
          +
            +
              +
                +
                  +
                • HAL_HASH_MD5_Accumulate() + renamed + HAL_HASH_MD5_Accmlt()
                  • +
                • HAL_HASH_SHA1_Accumulate() + renamed + HAL_HASH_SHA1_Accmlt()
                  • +
                • HAL_HASHEx_SHA224_Accumulate() + renamed + HAL_HASHEx_SHA224_Accmlt()
                  • +
              -
            • +
                +
                  +
                    +
                  • HAL_HASHEx_SHA256_Accumulate() + renamed + HAL_HASHEx_SHA256_Accmlt()
                    • +
                  +
                +
              +
            +
              +
                +
              • HASH handler + state is no more + reset to HAL_HASH_STATE_READY + once DMA has been started + in the following APIs:
                • +
                  +
                • HAL_HASH_MD5_Start_DMA()
                  • +
                • HAL_HMAC_MD5_Start_DMA()
                  • +
                • HAL_HASH_SHA1_Start_DMA()
                  • +
                • HAL_HMAC_SHA1_Start_DMA()
                  • +
                +
              • HASH phase + state is now set to + HAL_HASH_PHASE_READY once + the digest has been read + in the following APIs:
                • +
                  +
                • HASH_IT()
                  • +
                • HMAC_Processing()
                  • +
                • HASH_Start()
                  • +
                • HASH_Finish()
                  • +
                +
              • Case of a + large buffer scattered around + in memory each piece of which + is not necessarily a multiple - mso-fareast-font-family:"Times + of 4 bytes in length.
                • +
                  +
                • In section + "##### How to use this + driver #####", sub-section + "*** Remarks on message + length ***" added to provide + recommendations to follow in + such case.
                  • +
                • No + modification of the driver + as the root-cause is at + design-level.
                  • +
                +
              +
            +
              +
            • HAL CAN - New Roman"">Fix flag - clear procedure: use atomic - write operation "=" instead of - ready-modify-write operation - "|=" or "&="
              • -
            • update
              • +
                +
              • HAL_CAN_GetRxMessage() update to + get the correct value for the + RTR (type of frame for + the message that will be + transmitted) field in the CAN_RxHeaderTypeDef + structure.
                • +
              +
            • HAL + DCMI update
              • +
                +
              • Add new HAL_DCMI_ConfigSyncUnmask() + API to set embedded + synchronization delimiters + unmasks.
                • +
              +
            • HAL - mso-fareast-font-family:"Times + RTC update
              • +
                +
              • Following IRQ + handlers' implementation has + been aligned with the + STM32Cube firmware + specification (in case of + interrupt lines shared by + multiple events, first check + the IT enable bit is set then + check the IT flag is set too):
                • +
                  +
                • HAL_RTC_AlarmIRQHandler()
                  • +
                • HAL_RTCEx_WakeUpTimerIRQHandler()
                  • +
                • HAL_RTCEx_TamperTimeStampIRQHandler()
                  • +
                +
              +
            +
              +
            • HAL - New Roman"">Fix on - Timeout management, Timeout - value set to 0 passed to API - automatically exits the - function after checking the - flag without any wait update
              • +
                +
              • In "##### + WWDG Specific features #####" + descriptive comment section:
                • +
                  +
                • Maximal prescaler + value has been corrected (8 + instead of 128).
                  • +
                • Maximal APB + frequency has been corrected + (42MHz instead of 56MHz) and + possible timeout values + updated.
                  • +
                +
              +
            • HAL - New Roman"">
              • -
            • update
              • +
            +
              +
                +
              • Add the + following API's to Start DMA2D + CLUT Loading.
                • +
                  +
                • HAL_DMA2D_CLUTStartLoad() + Start DMA2D CLUT Loading.
                  • +
                • HAL_DMA2D_CLUTStartLoad_IT() + Start DMA2D CLUT Loading + with interrupt enabled.
                  • +
                +
              • The following + old wrong services will be + kept in the HAL DCMI driver + for legacy purpose and a + specific Note is added:
                • +
                  +
                • HAL_DMA2D_CLUTLoad() + can be replaced with + HAL_DMA2D_CLUTStartLoad()
                  • +
                • HAL_DMA2D_CLUTLoad_IT() can - mso-fareast-font-family:"Times + be replaced with + HAL_DMA2D_CLUTStartLoad_IT()
                  • +
                • HAL_DMA2D_ConfigCLUT() + can be omitted as the config + can be performed using + the HAL_DMA2D_CLUTStartLoad() + API.
                  • +
                +
              +
            +
              +
            • HAL - New Roman"">Common update - for the following - communication peripherals: - SPI, UART, USART and IRDAupdate
              • +
                +
              • Fix  + typo in "FileFormatGroup" + parameter in the HAL_MMC_CardCSDTypeDef + and HAL_SD_CardCSDTypeDef + structures 
                • +
              • Fix an + improve handle state and + error management
                • +
              • Rename the + defined MMC card capacity type + to be more meaningful:
                • +
                  +
                • Update MMC_HIGH_VOLTAGE_CARD to - New Roman"">
                  • -
                    -
                    • +
                  • Update MMC_DUAL_VOLTAGE_CRAD + to MMC_HIGH_CAPACITY_CARD
                    • +
                  +
                • Fix + management of peripheral + flags depending on commands + or data transfers
                  • +
                    +
                  • Add new + defines + "SDIO_STATIC_CMD_FLAGS" + and "SDIO_STATIC_DATA_FLAGS" 
                    • +
                  • Updates HAL - mso-fareast-font-family:"Times + SD and HAL MMC drivers to + manage the new SDIO static + flags.
                    +
                    +
                    • +
                  +
                • Due to + limitation SDIO hardware flow + control indicated in Errata + Sheet:
                  • +
                    +
                  • In 4-bits + bus wide mode, do not use + the HAL_SD_WriteBlocks_IT() + or HAL_SD_WriteBlocks() - New Roman"">Add DMA - circular mode support
                    • -
                    • +
                  • Use DMA + mode when using 4-bits bus + wide mode or decrease the + SDIO_CK frequency.
                    • +
                  +
                +
              • HAL + UART update
                • +
                  +
                • Update UART + polling processes to handle + efficiently the Lock mechanism
                  • +
                    +
                  •  Move + the process unlock at the + top of the HAL_UART_Receive() + and HAL_UART_Transmit() - mso-fareast-font-family:"Times - New Roman"">Remove lock - from recursive process
                    • +
                  +
                • Fix baudrate + calculation error for clock + higher than 172Mhz
                  • +
                    +
                  • Add a + forced cast on + UART_DIV_SAMPLING8() and + UART_DIV_SAMPLING16() + macros.
                    • +
                  • Remove + useless parenthesis from + UART_DIVFRAQ_SAMPLING8(), + UART_DIVFRAQ_SAMPLING16(), + UART_BRR_SAMPLING8() and + UART_BRR_SAMPLING16() macros + to solve some MISRA + warnings.
                    • +
                  +
                • Update UART + interruption handler to manage + correctly the overrun interrupt
                  • +
                    +
                  • Add in + the HAL_UART_IRQHandler() + API a check on + USART_CR1_RXNEIE bit when an + overrun interrupt occurs.
                    • +
                  +
                • Fix baudrate + calculation error UART9 + and UART10
                  • +
                    +
                  • In UART_SetConfig() + API fix UART9 and UART10 + clock source when computing + baudrate + values by adding a check on + these instances and setting + clock sourcePCLK2 instead of + PCLK1.
                    • +
                  +
                • Update UART_SetConfig() + API
                  • +
                    +
                  • Split + HAL_RCC_GetPCLK1Freq() + and HAL_RCC_GetPCLK2Freq() + macros from the + UART_BRR_SAMPLING8() and + UART_BRR_SAMPLING8() + macros 
                    • +
                  +
                +
              • HAL - New Roman"">
                • + USART update +
                  +
                • Fix baudrate + calculation error for clock + higher than 172Mhz
                  • +
                    +
                  • Add a + forced cast on USART_DIV() + macro.
                    • +
                  • Remove + useless parenthesis + from USART_DIVFRAQ() + macro to solve some MISRA + warnings.
                  -
                • Update USART + interruption handler to manage + correctly the overrun interrupt
                  • +
                    +
                  • Add in + the HAL_USART_IRQHandler() + API a check on + USART_CR1_RXNEIE bit when an + overrun interrupt occurs.
                    • +
                  +
                • Fix baudrate + calculation error UART9 + and UART10
                  • +
                    +
                  • In USART_SetConfig() + API fix UART9 and UART10 + clock source when computing + baudrate + values by adding a check on + these instances and setting + clock sourcePCLK2 instead of + PCLK1.
                    • +
                  +
                • Update USART_SetConfig() + API
                  • +
                    +
                  • Split + HAL_RCC_GetPCLK1Freq() + and HAL_RCC_GetPCLK2Freq() + macros from the USART_BRR() + macro
                    • +
                  +
                +
              • HAL - mso-fareast-font-family:"Times + IRDA update
                • +
                  +
                • Fix baudrate + calculation error for clock + higher than 172Mhz
                  • +
                    +
                  • Add a + forced cast on IRDA_DIV() + macro.
                    • +
                  • Remove + useless parenthesis + from IRDA_DIVFRAQ() + macro to solve some + MISRA warnings.
                    • +
                  +
                • Update IRDA + interruption handler to manage + correctly the overrun interrupt
                  • +
                    +
                  • Add in + the HAL_IRDA_IRQHandler() + API a check on + USART_CR1_RXNEIE bit when an + overrun interrupt occurs.
                    • +
                  +
                • Fix baudrate + calculation error UART9 + and UART10
                  • +
                    +
                  • In IRDA_SetConfig() + API fix UART9 and UART10 + clock source when computing + baudrate + values by adding a check on + these instances and setting + clock sourcePCLK2 instead of + PCLK1.
                    • +
                  +
                • Update IRDA_SetConfig() + API
                  • +
                    +
                  • Split + HAL_RCC_GetPCLK1Freq() + and HAL_RCC_GetPCLK2Freq() + macros from the IRDA_BRR() + macro
                    • +
                  +
                +
              • HAL - New Roman"">Add new macro - __HAL_RESET_HANDLE_STATE to - reset a given handle stateupdate
                • +
                  +
                • Fix baudrate + calculation error for clock + higher than 172Mhz
                  • +
                    +
                  • Add a + forced cast on SMARTCARD_DIV() + macro.
                    • +
                  • Remove useless parenthesis - New Roman"">
                    • -
                  • DIVFRAQ() + macro to solve some + MISRA warnings.
                    • +
                  +
                • Update + SMARTCARD interruption handler + to manage correctly the + overrun interrupti
                  • +
                    +
                  • Add in + the HAL_SMARTCARD_IRQHandler() + API a check on + USART_CR1_RXNEIE bit when an + overrun interrupt occurs.
                    • +
                  +
                • Update SMARTCARD_SetConfig() + API
                  • +
                    +
                  • Split + HAL_RCC_GetPCLK1Freq() + and HAL_RCC_GetPCLK2Freq() + macros from the + SMARTCARD_BRR() macro
                    • +
                  +
                +
              • HAL - mso-fareast-font-family:"Times + TIM update
                • +
                  +
                • Add new + macros to enable and disable + the fast mode when using the + one pulse mode to output a + waveform with a minimum delay
                  • +
                    +
                  • __HAL_TIM_ENABLE_OCxFAST() + and __HAL_TIM_DISABLE_OCxFAST().
                    • +
                  +
                • Update + Encoder interface mode to + keep TIM_CCER_CCxNP + bits low
                  • +
                    +
                  • Add TIM_ENCODERINPUTPOLARITY_RISING - New Roman"">Add a new - attribute for functions - executed from internal SRAM - and depending from - Compiler implementation
                    • +
                  • Add + IS_TIM_ENCODERINPUT_POLARITY() + macro to check the + encoder input polarity.
                    • +
                  • Update HAL_TIM_Encoder_Init() + API 
                    • +
                      +
                    • Replace + IS_TIM_IC_POLARITY() + macro by + IS_TIM_ENCODERINPUT_POLARITY() + macro.
                      • +
                    +
                  +
                • Update TIM + remapping input configuration + in HAL_TIMEx_RemapConfig() + API
                  • +
                    +
                  • Remove + redundant check on + LPTIM_OR_TIM5_ITR1_RMP bit + and replace it by check on + LPTIM_OR_TIM9_ITR1_RMP bit.
                    • +
                  +
                • Update HAL_TIMEx_MasterConfigSynchronization() + API to avoid functional errors + and assert fails when using + some TIM instances as input + trigger.
                  • +
                    +
                  • Replace IS_TIM_SYNCHRO_INSTANCE() + macro by + IS_TIM_MASTER_INSTANCE() + macro. 
                    • +
                  • Add IS_TIM_SLAVE_INSTANCE() + macro to check on + TIM_SMCR_MSM bit.
                    • +
                  +
                • Add lacking + TIM input remapping definition 
                  • +
                    +
                  • Add + LL_TIM_TIM11_TI1_RMP_SPDIFRX + and + LL_TIM_TIM2_ITR1_RMP_ETH_PTP.
                    • +
                  • Add lacking + definition for linked + LPTIM_TIM input trigger remapping  
                    • +
                      +
                    • Add + following definitions - "Times New Roman"">
                      • -
                    • When USE_RTOS - == 1 (in - stm32l0xx_hal_conf.h), the - __HAL_LOCK() - is not defined instead of - being defined empty
                      • -
                      • +
                    • Add a new + mechanism in LL_TIM_SetRemap() + API to remap TIM1, TIM9, + and TIM5 input + triggers mapped on LPTIM + register. 
                      • +
                    +
                  +
                +
              • HAL - New Roman"">Miscellaneous - comments and formatting updateupdate
                • +
                  +
                • Add a polling + mechanism to check + on LPTIM_FLAG_XXOK flags + in different API 
                  • +
                    +
                  • Add  + LPTIM_WaitForFlag() API to + wait for flag set.
                    • +
                  • Perform new + checks on + HAL_LPTIM_STATE_TIMEOUT.
                    • +
                  +
                • Add lacking + definitions of LPTIM input + trigger remapping and its + related API
                  • +
                    +
                      +
                    • LL_LPTIM_INPUT1_SRC_PAD_AF, - "Times New Roman"">
                      • -
                    • stm32f4xx_hal_conf_template.h
                      • +
                    • Add a new + API LL_LPTIM_SetInput1Src() + to access to the LPTIM_OR + register and remap the + LPTIM input trigger.
                      • +
                    +
                  +
                • Perform a new + check on indirect EXTI23 line + associated to the LPTIM wake + up timer
                  • +
                    +
                  • Condition + the use of the LPTIM Wake-up + Timer associated EXTI + line configuration's + macros by EXTI_IMR_MR23 + bit in different API - New Roman"">
                    • -
                      -
                      • +
                        +
                      • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE/DDISABLE_FALLING_EDGE()
                        • +
                      • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()
                        • +
                      • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() 
                        • +
                      • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()
                        • +
                      • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
                        • +
                      • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
                        • +
                      • __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()
                        • +
                      • __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()
                        • +
                      • __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() 
                        • +
                      +
                    • Update HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop_IT(), - mso-fareast-font-family:"Times + HAL_LPTIM_Counter_Start_IT() - New Roman"">Add a new - define for LSI default value - LSI_VALUEHAL_LPTIM_Counter_Stop_IT() - New Roman"">
                      • -
                    • Exti + line.
                      • +
                    • Add + __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() + in the end of the HAL_LPTIM_IRQHandler() - mso-fareast-font-family:"Times + API conditioned by + EXTI_IMR_MR23 bit.
                      • +
                    +
                  +
                • HAL - New Roman"">Add a new - define for LSE default value - LSE_VALUEupdate
                  • +
                    +
                  • Update + HAL_I2C_EV_IRQHandler() + API to fix I2C send break + issue 
                    • +
                      +
                    • Add + additional check on + hi2c->hdmatx, + hdmatx->XferCpltCallback, + hi2c->hdmarx, + hdmarx->XferCpltCallback + in I2C_Master_SB() + API to avoid enabling + DMA request when IT + mode is used.
                      • +
                    +
                  • Update + HAL_I2C_ER_IRQHandler() + API to fix acknowledge failure + issue with I2C memory IT + processes
                    • +
                      +
                    •  Add stop - New Roman"">
                      • -
                      • +
                    +
                  • Update + HAL_I2C_Init() + API to force software reset + before setting new I2C + configuration
                    • +
                  • Update HAL + I2C processes to report ErrorCode + when wrong I2C start condition + occurs
                    • +
                      +
                    •  Add + new ErrorCode + define: HAL_I2C_WRONG_START
                      • +
                    •  Set ErrorCode + parameter in I2C handle + to HAL_I2C_WRONG_START
                      • +
                    +
                  • Update I2C_DMAXferCplt(), - mso-fareast-font-family:"Times - New Roman"">Add a new - define for Tick interrupt - priority TICK_INT_PRIORITY - (needed for the enhanced - time base implementation)hardfault + issue when hdmatx + and hdmarx parameters - "Times New Roman"">
                    • + in i2c handle aren't + initialized (NULL pointer). +
                      +
                    • Add + additional check on + hi2c->hdmtx + and hi2c->hdmarx + before resetting DMA + Tx/Rx complete callbacks
                    -
                  • HAL - New - Roman";color:windowtext">Important + FMPI2C update
                    • +
                      +
                    • Fix HAL + FMPI2C slave interrupt + handling issue with I2C + sequential transfers.
                      • +
                        +
                      • Update + FMPI2C_Slave_ISR_IT() + and FMPI2C_Slave_ISR_DMA() + APIs to check on STOP + condition and handle it + before clearing the ADDR + flag
                        • +
                      +
                    +
                  • HAL - Note:update
                    • +
                      +
                    • Update + HAL_NAND_Write_Page_8b(), + HAL_NAND_Write_Page_16b() + and  + HAL_NAND_Write_SpareArea_16b() + to manage correctly the time + out condition.
                      • +
                    +
                  • HAL - mso-fareast-font-family:"Times + SAI update
                    • +
                      +
                    • Optimize SAI_DMATxCplt() + and SAI_DMARxCplt() - New - Roman";color:windowtext"> - aliases has been added for any - API naming change, to keep - compatibility with previous version
                      • + APIs to check on "Mode" + parameter instead of CIRC + bit in the CR register. +
                    • Remove unused + SAI_FIFO_SIZE define
                      • +
                    • Update HAL_SAI_Receive_DMA() + programming sequence to be inline + with reference manual
                    -
                  • V1.7.6 - "Times New Roman"">HAL + / 12-April-2019

    +

    Main Changes

    +
      +
    • General - GPIO implementation
      • +
    • HAL - New Roman"">updateupdate
      • +
        +
      • Fix I2C send + break issue in IT processes
        • +
          +
        • Add + additional check on + hi2c->hdmatx + and hi2c->hdmarx to - New Roman"">
          • -
        -
          -
            -
            • +
          +
        +
      • HAL - mso-fareast-font-family:"Times + SPI update
        • +
          +
        • Update to + implement Erratasheet: + BSY bit may stay high at the + end of a data transfer in + Slave mode
          • +
        +
      • LL - New Roman"">Add a new - macro __HAL_GPIO_EXTI_GENERATE_SWIT() - to manage the generation of - software interrupt on selected - EXTI line
        • -
      • update
        • +
          +
        • Fix + compilation errors with LL_LPTIM_WriteReg() + and LL_LPTIM_ReadReg() - New Roman"">HAL_GPIO_
          • +
        +
      • HAL - New Roman"">Init(update
        • +
          +
        • Fix + preprocessing compilation + issue with SDIO + STA STBITERR interrupt
          • +
        +
      • HAL/LL - mso-fareast-font-family:"Times + USB update
        • +
          +
        • Updated USB_WritePacket(), - New Roman"">): use - temporary variable when - modifying the registers, to - avoid unexpected transition in - the GPIO pin configurationUSB_ReadPacket() - New Roman"">
          • -
        • Rework USB_EPStartXfer() + API to enable the USB endpoint + before unmasking the TX FiFo + empty interrupt in case DMA is + not used
          • +
        • USB HAL_HCD_Init() + and HAL_PCD_Init() - mso-fareast-font-family:"Times + APIs updated to avoid enabling + USB DMA feature for OTG FS + instance, USB DMA feature is + available only on OTG HS + Instance
          • +
        • Remove + duplicated line in hal_hcd.c + header file comment section +
          • +
        • Rework USB + HAL driver to use instance PCD_SPEED_xxx, + HCD_SPEED_xx + speeds instead of OTG register + Core speed definition during + the instance initialization
          • +
        • Software + Quality improvement with a fix + of CodeSonar + warning on PCD_Port_IRQHandler() + and  HCD_Port_IRQHandler() - New Roman"">Remove - IS_GET_GPIO_PIN macro
          • -
        • V1.7.5 + / 08-February-2019 +

          Main Changes

          +
            +
          • General - mso-fareast-font-family:"Times + updates to fix known defects and + enhancements implementation
            • +
          • General - New Roman"">Add a new - function HAL_GPIO_LockPin()CodeSonar + compilation warnings
            • +
          • General - New Roman"">
            • -
          • Linux
            • +
          • General - mso-fareast-font-family:"Times + updates to fix the user manual + .chm files
            • +
          • Add + support of HAL callback + registration feature
            • +
          +
            +
          • Add + new HAL - New Roman"">Private Macro - __HAL_GET_GPIO_SOURCE renamed - into GET_GPIO_SOURCE driver
            • +
          • Add + new HAL - New Roman"">
            • -
          • driver
            • +
          • The - mso-fareast-font-family:"Times + following changes done on the + HAL drivers require an update + on the application code based + on older HAL versions
            • +
              +
            • Rework of HAL + CRYP driver (compatibility + break)
              • +
                +
              • HAL CRYP + driver has been redesigned + with new API's, to bypass + limitations on data + Encryption/Decryption + management present with + previous HAL CRYP driver + version.
                • +
              • The new HAL + CRYP driver is the + recommended version. It is + located as usual in + Drivers/STM32F4xx_HAL_Driver/Src + and + Drivers/STM32f4xx_HAL_Driver/Inc + folders. It can be enabled + through switch + HAL_CRYP_MODULE_ENABLED in + stm32f4xx_hal_conf.h
                • +
              • The legacy + HAL CRYP driver is no longer + supported.
                • +
              +
            • Add new AutoReloadPreload + field in TIM_Base_InitTypeDef + structure to allow the + possibilities to enable or + disable the TIM Auto Reload + Preload.
              • +
            +
          +
            +
          • HAL/LL - New Roman"">Add the - support of STM32F411xx devices + Generic update
            • +
              +
            • Add support + of HAL callback + registration feature
              • +
                +
              • The feature + disabled by default is + available for the following + HAL drivers:
                • +
                  +
                • ADC, + CAN, CEC, CRYP, DAC, + DCMI, DFSDM, DMA2D, DSI, + ETH, HASH, HCD, I2C, + FMPI2C, SMBUS,
                  + UART, USART, IRDA, + SMARTCARD, LPTIM, LTDC, + MMC, NAND, NOR, + PCCARD, PCD, QSPI, RNG,
                  +                   RTC, + SAI, SD, SDRAM, SRAM, + SPDIFRX, SPI, I2S, TIM, + and WWDG
                  • +
                +
              • The feature + may be enabled individually + per HAL PPP driver + by setting the corresponding + definition USE_HAL_PPP_REGISTER_CALLBACKS - : add the - new Alternate functions values - related to new remap added for - SPI, USART, I2C
                • -
              • from  + Drivers/STM32F4xx_HAL_Driver/Inc)
                • +
              • Once enabled - mso-fareast-font-family:"Times + , the user + application may resort to HAL_PPP_RegisterCallback() - New Roman"">Update the - following HAL GPIO macros - description: rename EXTI_Linex - by GPIO_PIN_x
                • -
                  -
                • HAL_PPP_UnRegisterCallback().
                  • +
                +
              • General + updates to fix MISRA 2012 + compilation errors
                • +
                  +
                • Replace HAL_GetUID() + API by HAL_GetUIDw0(), + HAL_GetUIDw1() and + HAL_GetUIDw2()
                  • +
                • HAL_IS_BIT_SET()/HAL_IS_BIT_CLR() + macros implementation update
                  • +
                • "stdio.h" + include updated with "stddef.h"
                  • +
                +
              +
            • HAL - mso-fareast-font-family:"Times + GPIO  - New Roman"">__HAL_GPIO_EXTI_CLEAR_IT()
              • -
            • update
              • +
                +
              • Add missing + define for SPI3 alternate + function "GPIO_AF5_SPI3" for + STM32F401VE devices
                • +
              • Remove + "GPIO_AF9_TIM14" from defined + alternate function list for + STM32F401xx devices
                • +
              • HAL_GPIO_TogglePin() reentrancy + robustness improvement
                • +
              • HAL_GPIO_DeInit() API update + to avoid potential pending + interrupt after call
                • +
              • Update + GPIO_GET_INDEX() + API for more compliance with + STM32F412Vx/STM32F412Rx/STM32F412Cx + devices
                • +
              • Update + GPIO_BRR registers with + Reference Manual regarding + registers and bit definition + values
                • +
              +
            • HAL - mso-fareast-font-family:"Times + CRYP update
              • +
                +
              • The CRYP_InitTypeDef + is no more + supported, changed by CRYP_ConfigTypedef + to allow changing parameters + using HAL_CRYP_setConfig() + API without reinitialize the + CRYP IP using the HAL_CRYP_Init() - New Roman"">__HAL_GPIO_EXTI_GET_IT()
                • -
                • +
              • New + parameters added in the CRYP_ConfigTypeDef + structure: B0 and DataWidthUnit
                • +
              • Input data + size parameter is added in the + CRYP_HandleTypeDef + structure
                • +
              • Add new APIs + to manage the CRYP + configuration:
                • +
                  +
                •  HAL_CRYP_SetConfig()
                  • +
                • HAL_CRYP_GetConfig()
                  • +
                +
              • Add new APIs + to manage the Key derivation:
                • +
                  +
                • HAL_CRYPEx_EnableAutoKeyDerivation()
                  • +
                • HAL_CRYPEx_DisableAutoKeyDerivation()
                  • +
                +
              • Add new APIs + to encrypt and decrypt data:
                • +
                  +
                • HAL_CRYP_Encypt()
                  • +
                • HAL_CRYP_Decypt()
                  • +
                • HAL_CRYP_Encypt_IT()
                  • +
                • HAL_CRYP_Decypt_IT()
                  • +
                • HAL_CRYP_Encypt_DMA()
                  • +
                • HAL_CRYP_Decypt_DMA()
                  • +
                +
              • Add new APIs + to generate TAG:
                • +
                  +
                • HAL_CRYPEx_AESGCM_GenerateAuthTAG()
                  • +
                • HAL_CRYPEx_AESCCM_Generago teAuthTAG()
                  • +
                +
              +
            • HAL - mso-fareast-font-family:"Times + LPTIM update
              • +
                +
              • Remove + useless LPTIM Wakeup EXTI + related macros from HAL_LPTIM_TimeOut_Start_IT() + API
                • +
              +
            • HAL - New Roman"">__HAL_GPIO_EXTI_CLEAR_FLAG()
              • -
            • update
              • +
                +
              • I2C API + changes for MISRA-C 2012 + compliancy:
                • +
                  +
                • Rename + HAL_I2C_Master_Sequential_Transmit_IT() + to + HAL_I2C_Master_Seq_Transmit_IT()
                  • +
                • Rename + HAL_I2C_Master_Sequentiel_Receive_IT() + to + HAL_I2C_Master_Seq_Receive_IT()
                  • +
                • Rename + HAL_I2C_Slave_Sequentiel_Transmit_IT() + to + HAL_I2C_Slave_Seq_Transmit_IT() +
                  • +
                • Rename + HAL_I2C_Slave_Sequentiel_Receive_DMA() + to + HAL_I2C_Slave_Seq_Receive_DMA()
                  • +
                +
              • SMBUS defined + flags are removed as not used + by the HAL I2C driver
                • +
                  +
                • I2C_FLAG_SMBALERT
                  • +
                • I2C_FLAG_TIMEOUT
                  • +
                • I2C_FLAG_PECERR
                  • +
                • I2C_FLAG_SMBHOST
                  • +
                • I2C_FLAG_SMBDEFAULT
                  • +
                +
              • Add support + of I2C repeated start feature + in DMA Mode:
                • +
                  +
                • With the + following new API's
                  • +
                    +
                  • HAL_I2C_Master_Seq_Transmit_DMA()
                    • +
                  • HAL_I2C_Master_Seq_Receive_DMA()
                    • +
                  • HAL_I2C_Slave_Seq_Transmit_DMA()
                    • +
                  • HAL_I2C_Slave_Seq_Receive_DMA()
                    • +
                  +
                +
              • Add new I2C + transfer options to easy + manage the sequential transfers
                • +
                  +
                • I2C_FIRST_AND_NEXT_FRAME
                  • +
                • I2C_LAST_FRAME_NO_STOP
                  • +
                • I2C_OTHER_FRAME
                  • +
                • I2C_OTHER_AND_LAST_FRAME
                  • +
                +
              +
            • HAL - mso-fareast-font-family:"Times + FMPI2C update
              • +
                +
              • I2C API + changes for MISRA-C 2012 + compliancy:
                • +
                  +
                • Rename + HAL_FMPI2C_Master_Sequential_Transmit_IT() + to + HAL_FMPI2C_Master_Seq_Transmit_IT()
                  • +
                • Rename + HAL_FMPI2C_Master_Sequentiel_Receive_IT() + to + HAL_FMPI2C_Master_Seq_Receive_IT()
                  • +
                • Rename + HAL_FMPI2C_Master_Sequentiel_Transmit_DMA() + to + HAL_FMPI2C_Master_Seq_Transmit_DMA() +
                  • +
                • Rename + HAL_FMPI2C_Master_Sequentiel_Receive_DMA() + to + HAL_FMPI2C_Master_Seq_Receive_DMA()
                  • +
                +
              • Rename + FMPI2C_CR1_DFN to + FMPI2C_CR1_DNF for more + compliance with Reference + Manual regarding registers and + bit definition naming
                • +
              • Add support + of I2C repeated start feature + in DMA Mode:
                • +
                  +
                • With the + following new API's
                  • +
                    +
                  • HAL_FMPI2C_Master_Seq_Transmit_DMA()
                    • +
                  • HAL_FMPI2C_Master_Seq_Receive_DMA()
                    • +
                  • HAL_FMPI2C_Slave_Seq_Transmit_DMA()
                    • +
                  • HAL_FMPI2C_Slave_Seq_Receive_DMA()
                    • +
                  +
                +
              +
            • HAL - New Roman"">__HAL_GPIO_EXTI_GET_FLAG()update
              • +
                +
              • Update the FLASH_OB_GetRDP() + API to return the correct RDP + level
                • +
              +
            • HAL  + RCC + update
              • +
                +
              • Remove GPIOD + CLK macros for STM32F412Cx + devices (X = D)
                • +
              • Remove GPIOE + CLK macros for + STM32F412Rx\412Cx devices: (X + = E)
                • +
              • Remove + GPIOF/G CLK macros for + STM32F412Vx\412Rx\412Cx + devices (X= F or G)
                • +
                  +
                • __HAL_RCC_GPIOX_CLK_ENABLE()
                  • +
                • __HAL_RCC_GPIOX_CLK_DISABLE()
                  • +
                • __HAL_RCC_GPIOX_IS_CLK_ENABLED()
                  • +
                • __HAL_RCC_GPIOX_IS_CLK_DISABLED()
                  • +
                • __HAL_RCC_GPIOX_FORCE_RESET()
                  • +
                +
              +
            • HAL - New Roman"">
              • + RNG update +
                +
              • Update to + manage RNG error code:
                • +
                  +
                • Add ErrorCode + parameter in HAL RNG Handler + structure
              -
            -

            �  +

          • LL - - HAL DMA update

            -
              -
                -
              • update
                • +
                  +
                • Add + __LL_ADC_CALC_TEMPERATURE() + helper macro to calculate the + temperature (unit: degree + Celsius) from ADC conversion + data of internal temperature + sensor.
                  • +
                • Fix ADC + channels configuration issues + on STM32F413xx/423xx devices
                  • +
                    +
                  • To allow + possibility to switch + between VBAT and TEMPERATURE + channels configurations
                    • +
                  +
                • HAL_ADC_Start(), HAL_ADC_Start_IT() - mso-fareast-font-family:"Times + and HAL_ADC_Start_DMA() - New Roman"">Fix in HAL_DMA_PollForTransfer() - to:
                  • -
                    -
                    • +
                  +
                • HAL - mso-fareast-font-family:"Times + DFSDM  - New Roman"">set DMA - error code in case of - HAL_ERROR status update
                  • +
                    +
                  • General + updates to be compliant with + DFSDM bits naming used in + CMSIS files.
                    • +
                  +
                • HAL + CAN  - "Times New Roman"">
                  • -
                • update
                  • +
                    +
                  • Update + possible values list for FilterActivation + parameter in CAN_FilterTypeDef + structure
                    • +
                      +
                    • CAN_FILTER_ENABLE - mso-fareast-font-family:"Times + instead of ENABLE
                      • +
                    • CAN_FILTER_DISABLE - New Roman"">set HAL - Unlock before DMA state update
                      • + instead of DISABLE
                  -
                -

                �  - +

              • HAL - HAL DMA2D - update

                -
                  -
                    -
                  • CEC  - - mso-fareast-font-family:"Times + update
                    • +
                      +
                    • Update HAL + CEC State management method:
                      • +
                        +
                      • Remove HAL_CEC_StateTypeDef + structure parameters
                        • +
                      • Add new + defines for CEC states
                        • +
                      +
                    +
                  • HAL - New Roman"">Add - configuration of source - address in case of A8 or A4 - M2M_PFC DMA2D modeDMA  - New Roman"">
                    • + update +
                      +
                    • Add clean of + callbacks in HAL_DMA_DeInit() + API
                    -
                  • HAL - "Times New Roman"">HAL + DMA2D  - FLASH update
                    • +
                      +
                    • Remove unused + DMA2D_ColorTypeDef structure + to be compliant with MISRAC + 2012 Rule 2.3
                      • +
                    • General + update to use dedicated + defines for + DMA2D_BACKGROUND_LAYER and + DMA2D_FOREGROUND_LAYER instead + of numerical values: 0/1.
                      • +
                    +
                  • HAL - New Roman"">updateDSI  - New Roman"">
                    • + update +
                      +
                    • Fix read + multibyte issue: remove extra + call to __HAL_UNLOCK__ from DSI_ShortWrite() + API.
                      • +
                  -
                    -
                      -
                    • +
                    • HAL/LL - mso-fareast-font-family:"Times - - + RTC update
                      • +
                    +
                      +
                        +
                      • HAL/ LL drivers + optimization
                        • +
                          +
                        • HAL driver: + remove unused variables
                          • +
                        • LL driver: + getter APIs optimization
                          • +
                        +
                      +
                    • HAL - New Roman"">Functions - reorganization update, - depending on the features - supported by each STM32F4 device
                      • -
                    • update
                      • +
                        +
                      • Remove the + followings API's as feature + not supported by + STM32F469xx/479xx devices
                        • +
                          +
                        • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
                          • +
                        • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
                          • +
                        +
                      +
                    • HAL - mso-fareast-font-family:"Times + SPI update
                      • +
                        +
                      • Update HAL_SPI_StateTypeDef + structure to add new state: + HAL_SPI_STATE_ABORT
                        • +
                      +
                    • HAL/LL - New Roman"">Add new - driver - (stm32f4xx_hal_flash_ramfunc.h/.c) - to manage function executed - from RAM, these functions are - available only for STM32F411xx - Devices
                      • -
                        -
                      • update
                        • +
                          +
                        • Add new AutoReloadPreload + field in TIM_Base_InitTypeDef + structure
                          • +
                            +
                          • Refer to + the TIM examples to identify + the changes +
                            • +
                          +
                        • Move the + following TIM structures from + stm32f4xx_hal_tim_ex.h into + stm32f4xx_hal_tim.h
                          • +
                            +
                          • TIM_MasterConfigTypeDef
                            • +
                          • TIM_BreakDeadTimeConfigTypeDef
                            • +
                          +
                        • Add new TIM + Callbacks API's:
                          • +
                            +
                          • HAL_TIM_PeriodElapsedHalfCpltCallback()
                            • +
                          • HAL_TIM_IC_CaptureHalfCpltCallback()
                            • +
                          • HAL_TIM_PWM_PulseFinishedHalfCpltCallback()
                            • +
                          • HAL_TIM_TriggerHalfCpltCallback()
                            • +
                          +
                        • TIM API + changes for MISRA-C 2012 + compliancy:
                          • +
                            +
                          • Rename HAL_TIM_SlaveConfigSynchronization + to HAL_TIM_SlaveConfigSynchro
                            • +
                          • Rename HAL_TIM_SlaveConfigSynchronization_IT + to HAL_TIM_SlaveConfigSynchro_IT
                            • +
                          • Rename HAL_TIMEx_ConfigCommutationEvent + to HAL_TIMEx_ConfigCommutEvent
                            • +
                          • Rename HAL_TIMEx_ConfigCommutationEvent_IT + to HAL_TIMEx_ConfigCommutEvent_IT
                            • +
                          • Rename HAL_TIMEx_ConfigCommutationEvent_DMA + to HAL_TIMEx_ConfigCommutEvent_DMA
                            • +
                          • Rename HAL_TIMEx_CommutationCallback + to HAL_TIMEx_CommutCallback
                            • +
                          • Rename HAL_TIMEx_DMACommutationCplt + to TIMEx_DMACommutationCplt
                            • +
                          +
                        +
                      +
                        +
                      • HAL/LL - New Roman"">FLASH_ update
                        • +
                          +
                        • Rework USB + interrupt handler and improve + HS DMA support in Device mode
                          • +
                        • Fix BCD + handling fr OTG + instance in device mode
                          • +
                        • cleanup + reference to low speed in + device mode
                          • +
                        • allow writing + TX FIFO in case of transfer + length is equal to available + space in the TX FIFO
                          • +
                        • Fix Toggle + OUT interrupt channel in host + mode
                          • +
                        • Update USB + OTG max number of endpoints (6 + FS and 9 HS instead of 5 and + 8)
                          • +
                        • Update USB + OTG IP to enable internal + transceiver when starting USB + device after committee BCD negotiation
                          • +
                        +
                      • LL - New Roman"">StopFlashInterfaceClk(update
                        • +
                          +
                        • Update LL + inline macros to use IWDGx + parameter instead of IWDG + instance defined in CMSIS device
                          • +
                        +
                      +

                      V1.7.4 - mso-fareast-font-family:"Times + / 02-February-2018

                      +

                      Main Changes

                      +
                        +
                      • General - New Roman"">)implementation
                        • +
                      • HAL update
                        • +
                          +
                        • Update UNUSED() + macro implementation to avoid + GCC warning
                          • +
                            +
                          • The warning + is detected when the UNUSED() + macro is called from C++ + file
                            • +
                          +
                        • Update to + make RAMFUNC define as generic + type instead of HAL_StatusTypdef + type.
                          • +
                        +
                      • HAL + FLASH update
                        • +
                          +
                        • Update + the prototypes of the + following APIs after change on + RAMFUNC defines 
                          • +
                            +
                          • HAL_FLASHEx_StopFlashInterfaceClk()
                            • +
                          • HAL_FLASHEx_StartFlashInterfaceClk()
                            • +
                          • HAL_FLASHEx_EnableFlashSleepMode()
                            • +
                          • HAL_FLASHEx_DisableFlashSleepMode()
                            • +
                          +
                        +
                      • HAL - mso-fareast-font-family:"Times + SAI update
                        • +
                          +
                        • Update HAL_SAI_DMAStop() + and HAL_SAI_Abort() - New Roman"">  : - Stop the flash interface - while System Run
                          • -
                        • FLASH_
                          • +
                        +
                      +

                      V1.7.3 - New Roman"">StartFlashInterfaceClk(

                      +

                      Main Changes

                      +
                        +
                      • General + updates to fix known defects and + enhancements implementation
                        • +
                      • The - mso-fareast-font-family:"Times + following changes done on the + HAL drivers require an update + on the application code based + on older HAL versions
                        • +
                          +
                        • Rework of + HAL CAN driver + (compatibility break) 
                          • +
                            +
                          • A new HAL + CAN driver has been + redesigned with new APIs, to + bypass limitations on CAN + Tx/Rx FIFO management + present with previous HAL + CAN driver version.
                            • +
                          • The new HAL + CAN driver is the + recommended version. It is + located as usual in + Drivers/STM32F4xx_HAL_Driver/Src + and + Drivers/STM32f4xx_HAL_Driver/Inc + folders. It can be enabled + through switch + HAL_CAN_MODULE_ENABLED in + stm32f4xx_hal_conf.h
                            • +
                          • The legacy + HAL CAN driver is also + present in the release in + Drivers/STM32F4xx_HAL_Driver/Src/Legacy - New Roman"">)
                            • +
                          +
                        +
                      • HAL update
                        • +
                          +
                        • Update HAL + driver to allow user to change + systick + period to 1ms, 10 ms + or 100 ms :
                          • +
                            +
                          • Add the + following API's + + + + :  
                            • +
                              +
                            • HAL_GetTickPrio(): + Returns a tick priority.
                              • +
                            • HAL_SetTickFreq(): Sets + new tick frequency.
                              • +
                            • HAL_GetTickFreq(): + Returns tick frequency.
                              • +
                            +
                          • Add HAL_TickFreqTypeDef + enumeration for the + different Tick Frequencies: + 10 Hz, 100 Hz and 1KHz + (default).
                            • +
                          +
                        +
                      • HAL - mso-fareast-font-family:"Times + CAN update
                        • +
                          +
                        • Fields of CAN_InitTypeDef + structure are reworked:
                          • +
                            +
                          • SJW to SyncJumpWidth, + BS1 to TimeSeg1, BS2 to + TimeSeg2, TTCM to TimeTriggeredMode, + ABOM to AutoBusOff, + AWUM to AutoWakeUp, + NART to AutoRetransmission + (inversed), RFLM to ReceiveFifoLocked + and TXFP to TransmitFifoPriority
                            • +
                          +
                        • HAL_CAN_Init() is split + into both HAL_CAN_Init() - New Roman""> : Stop the - flash interface while System - Run
                          • -
                        • HAL_CAN_Start() - New Roman"">FLASH_EnableFlashSleepMode(
                          • +
                        • HAL_CAN_Transmit() is replaced + by HAL_CAN_AddTxMessage() - mso-fareast-font-family:"Times + to place Tx Request, then HAL_CAN_GetTxMailboxesFreeLevel() - New Roman"">)
                          • +
                        • HAL_CAN_Transmit_IT() is replaced + by HAL_CAN_ActivateNotification() - mso-fareast-font-family:"Times + to enable transmit IT, then HAL_CAN_AddTxMessage() - New Roman""> : Enable - the flash sleep while System - Run
                          • -
                          • +
                        • HAL_CAN_Receive() is replaced + by HAL_CAN_GetRxFifoFillLevel() - New Roman"">FLASH_DisableFlashSleepMode(HAL_CAN_GetRxMessage() - mso-fareast-font-family:"Times +
                          + to get Rx message.
                          • +
                        • HAL_CAN_Receive_IT() is replaced + by HAL_CAN_ActivateNotification() to - New Roman"">)HAL_CAN_GetRxMessage()
                          + in the receivecallback + to get Rx message
                          • +
                        • HAL_CAN_Slepp() is renamed + as HAL_CAN_RequestSleep()
                          • +
                        • HAL_CAN_TxCpltCallback() is split + into + HAL_CAN_TxMailbox0CompleteCallback(), +HAL_CAN_TxMailbox1CompleteCallback() +and HAL_CAN_TxMailbox2CompleteCallback().
                          • +
                        • HAL_CAN_RxCpltCallback is split + into HAL_CAN_RxFifo0MsgPendingCallback() + and + HAL_CAN_RxFifo1MsgPendingCallback().
                          • +
                        • More complete + "How to use the new driver" is + detailed in the driver header + section itself.
                          • +
                        +
                      • HAL - mso-fareast-font-family:"Times + FMPI2C update
                        • +
                          +
                        • Add new + option + FMPI2C_LAST_FRAME_NO_STOP for + the sequential transfer management
                          • +
                            +
                          • This option + allows to manage a restart + condition after several call + of the same master + sequential interface. 
                            • +
                          +
                        +
                      • HAL - New Roman""> :  - Disable the flash sleep - while System Runupdate
                        • +
                          +
                        • Add new HAL macros
                          • +
                            +
                          • __HAL_RCC_GET_RTC_SOURCE() + allowing to get the RTC + clock source
                            • +
                          • __HAL_RCC_GET_RTC_HSE_PRESCALER() + allowing to get the HSE + clock divider for RTC + peripheral
                            • +
                          +
                        • Ensure reset + of CIR and CSR registers when + issuing HAL_RCC_DeInit()/LL_RCC_DeInit + functions
                          • +
                        • Update HAL_RCC_OscConfig() to - "Times New Roman"">
                          • + keep backup domain enabled + when configuring + respectively LSE and RTC + clock source +
                        • Add new HAL + interfaces allowing to control + the activation or deactivation + of PLLI2S and PLLSAI:
                          • +
                            +
                          • HAL_RCCEx_EnablePLLI2S()
                            • +
                          • HAL_RCCEx_DisablePLLI2S()
                            • +
                          • HAL_RCCEx_EnablePLLSAI()
                            • +
                          • HAL_RCCEx_DisablePLLSAI()
                      -
                        -
                      • +
                      • LL - "Times New Roman"">HAL - - - PWR update 
                        • +
                          +
                        • Add new LL + RCC macro
                          • +
                            +
                          • LL_RCC_PLL_SetMainSource() allowing + to configure PLL main clock + source
                            • +
                          +
                        +
                      • LL - New Roman"">update
                        • + FMC / LL FSMC update +
                          +
                        • Add clear of + the PTYP bit to select the + PCARD mode in FMC_PCCARD_Init() + / FSMC_PCCARD_Init()
                          • +
                      -
                        -
                          -
                        • V1.7.2 - New Roman"">HAL_PWR_ +

                          Main Changes

                          +
                            +
                          • General - New Roman"">PVDConfig(implementation
                            • +
                          • Fix + compilation warning with + GCC compiler
                            • +
                          • Remove - mso-fareast-font-family:"Times + Date and version + from header files
                            • +
                          • Update - New Roman"">)VAL() + macro
                            • +
                          • HAL + Generic update
                            • +
                              +
                            • stm32f4xx_hal_def.h - mso-fareast-font-family:"Times + file changes: 
                              • +
                                +
                              • Update + __weak and __packed defined + values for ARM compiler
                                • +
                              • Update + __ALIGN_BEGIN and + __ALIGN_END defined values + for ARM compiler
                                • +
                              +
                            • stm32f4xx_ll_system.h - New Roman"">: add clear - of the EXTI trigger before new - configuration
                              • -
                              • +
                            +
                          • HAL - mso-fareast-font-family:"Times + ADC update
                            • +
                              +
                            • Fix wrong + definition of ADC channel + temperature sensor for + STM32F413xx and STM32F423xx + devices.
                              • +
                            +
                          • HAL - New Roman"">Fix in HAL_PWR_EnterSTANDBYMode() - to not clear Wakeup flag - (WUF), which need to be - cleared at application level - before to call this functionupdate
                            • +
                              +
                            • Update values - New Roman"">
                              • -
                              • +
                            +
                          • HAL - New Roman"">HAL_PWR_update
                            • +
                              +
                            • Fix Extra + warning with SW4STM32 compiler
                              • +
                            • Fix DSI + display issue when using EWARM + w/ high level optimization 
                              • +
                            • Fix + MISRAC errors
                              • +
                            +
                          • HAL - New Roman"">EnterSLEEPMode(update
                            • +
                              +
                            • HAL_FLASH_Unlock() update to + return state error when the + FLASH is already unlocked
                              • +
                            +
                          • HAL - mso-fareast-font-family:"Times + FMPI2C update
                            • +
                              +
                            • Update + Interface APIs headers to + remove confusing message about + device address
                              • +
                            • Update + FMPI2C_WaitOnRXNEFlagUntilTimeout() + to resolve a race condition + between STOPF and RXNE Flags
                              • +
                            • Update + FMPI2C_TransferConfig() + to fix wrong bit management.
                              • +
                            • Update code + comments to use DMA stream + instead of DMA channel
                              • +
                            +
                          +
                            +
                          • HAL - New Roman"">)update
                            • +
                              +
                            • HAL_PWR_EnableWakeUpPin() update + description to add support of + PWR_WAKEUP_PIN2 and + PWR_WAKEUP_PIN3
                              • +
                            +
                          • HAL - New Roman"">
                            • -
                              -
                            • update
                              • +
                                +
                              • Add the + support of STM32F412Rx devices
                                • +
                              +
                            • HAL - mso-fareast-font-family:"Times + I2C update
                              • +
                                +
                              • Update + Interface APIs headers to + remove confusing mesage + about device address
                                • +
                              • Update + I2C_MasterReceive_RXNE() + and I2C_MasterReceive_BTF() + static APIs to fix bad + Handling of NACK in I2C master + receive process.
                                • +
                              +
                            +
                              +
                            • HAL - New Roman"">Remove - disable and enable of SysTick - Timerupdate
                              • +
                                +
                              • Update HAL_RCC_GetOscConfig() + API to:
                                • +
                                  +
                                • set PLLR in + the RCC_OscInitStruct
                                  • +
                                • check on + null pointer
                                  • +
                                +
                              • Update HAL_RCC_ClockConfig() + API to:
                                • +
                                  +
                                • check on + null pointer
                                  • +
                                • optimize code - New Roman"">
                                  • -
                                • bits
                                  • +
                                • update to use  - mso-fareast-font-family:"Times + __HAL_FLASH_GET_LATENCY() - New Roman"">Update - usage of __WFE() - in low power entry function: - if there is a pending event, - calling __WFE() will not - enter the CortexM4 core to - sleep mode. The solution is - to made the call below; the - first __WFE() - is always ignored and clears - the event if one was already - pending, the second is - always applied
                                  • + flash macro instead of using + direct register access + to LATENCY bits in + FLASH ACR register.
                                -
                              -
                            -
                            -

                            __SEV()
                            -                             __WFE()
                            -                             __WFE()

                            -
                            -
                              -
                                -
                              • Update HAL_RCC_DeInit() +  and LL_RCC_DeInit() - mso-fareast-font-family:"Times - + APIs to
                                • +
                                  +
                                • Be able to + return HAL/LL status
                                  • +
                                • Add checks + for HSI, PLL and PLLI2S +  ready + before modifying RCC CFGR + registers
                                  • +
                                • Clear all + interrupt falgs
                                  • +
                                • Initialize + systick + interrupt period
                                  • +
                                +
                              • Update HAL_RCC_GetSysClockFreq() + to avoid risk of rounding + error which may leads to a + wrong returned value. 
                                • +
                              +
                            +

                             

                            +

                             

                            +
                              +
                            • HAL - New Roman"">Add new macro - for software event generation - __HAL_PVD_EXTI_GENERATE_SWIT()update
                              • +
                                +
                              • HAL_RNG_Init() remove + Lock()/Unlock()
                                • +
                              +
                            • HAL - New Roman"">
                              • -
                            • update
                              • +
                                +
                              • HAL_MMC_Erase() + API: add missing () to + fix compilation warning + detected with SW4STM32 when + extra feature is enabled.
                                • +
                              +
                            • HAL - mso-fareast-font-family:"Times + RTC update
                              • +
                                +
                              • HAL_RTC_Init() API: update + to force the wait for synchro + before setting TAFCR register + when BYPSHAD bit in CR + register is 0.
                                • +
                              +
                            • HAL - New Roman"">Remove the - following defines form Generic - driver and add them under - extension driver because they - are only used within extension - functions.
                              • -
                                -
                              • update
                                • +
                                  +
                                • Update HAL_SAI_DMAStop() + API to flush fifo + after disabling SAI
                                  • +
                                +
                              • HAL + I2S update
                                • +
                                  +
                                • Update I2S + DMA fullduplex process to + handle I2S Rx and Tx DMA Half + transfer complete callback
                                  • +
                                +
                              • HAL - mso-fareast-font-family:"Times + TIM update
                                • +
                                  +
                                • Update HAL_TIMEx_OCN_xxxx() + and HAL_TIMEx_PWMN_xxx() - New Roman"">CR_FPDS_BB: - used within HAL_PWREx_EnableFlashPowerDown() - function
                                  • -
                                  • +
                                +
                              • LL - mso-fareast-font-family:"Times + DMA update
                                • +
                                  +
                                • Update to + clear DMA flags using WRITE_REG() + instead SET_REG() API to avoid + read access to the IFCR + register that is write only.
                                  • +
                                +
                              • LL - New Roman"">CSR_BRE_BB: - used within HAL_PWREx_EnableBkUpReg() - function
                                • -
                              -
                            • update
                              • +
                                +
                              • Fix warning + with static analyzer
                                • +
                              +
                            • LL - mso-fareast-font-family:"Times + USART update
                              • +
                                +
                              • Add assert + macros to check USART BaudRate + register
                                • +
                              +
                            • LL - New Roman"">Add the - support of STM32F411xx devices - add the define STM32F411xE
                              • -
                                -
                              • update
                                • +
                                  +
                                • Rename + IS_I2C_CLOCK_SPEED() + and IS_I2C_DUTY_CYCLE() + respectively to + IS_LL_I2C_CLOCK_SPEED() and + IS_LL_I2C_DUTY_CYCLE() to + avoid incompatible macros + redefinition.
                                  • +
                                +
                              • LL - mso-fareast-font-family:"Times + TIM update
                                • +
                                  +
                                • Update LL_TIM_EnableUpdateEvent() + API to clear UDIS bit in TIM + CR1 register instead of + setting it.
                                  • +
                                • Update LL_TIM_DisableUpdateEvent() + API to set UDIS bit in TIM CR1 + register instead of clearing + it.
                                  • +
                                +
                              • LL - New Roman"">For - STM32F401xC, STM32F401xE and - STM32F411xE devices add the - following functions used to - enable or disable the low - voltage mode for regulators
                                • -
                              + USART update +
                                +
                              • Fix MISRA + error w/ IS_LL_USART_BRR() + macro
                                • +
                              • Fix wrong + check when UART10 instance is + used
                            -
                              -
                                -
                                  -
                                    -
                                  • V1.7.1 - New Roman"">HAL_PWREx_ +

                                    Main Changes

                                    +
                                      +
                                    • Update - New Roman"">EnableMainRegulatorLowVoltage(UserManuals + to support LL drivers
                                      • +
                                    • General - mso-fareast-font-family:"Times + updates to fix known defects and + enhancements implementation
                                      • +
                                    • HAL - New Roman"">)
                                      • -
                                    • update
                                      • +
                                        +
                                      • Add + management of overrun + error. 
                                        • +
                                      • Allow + possibility to receive + messages from the 2 RX FIFOs + in parallel via interrupt.
                                        • +
                                      • Fix message - New Roman"">HAL_PWREx_
                                        • +
                                      • Handle + transmission failure with + error callback, when NART is + enabled.
                                        • +
                                      • Add + __HAL_CAN_CANCEL_TRANSMIT() + call to abort transmission + when timeout is reached
                                        • +
                                      +
                                    +
                                      +
                                    • HAL - New Roman"">DisableMainRegulatorLowVoltage(update
                                      • +
                                        +
                                      • HAL_PWREx_EnterUnderDriveSTOPMode() API: remove + check on UDRDY flag
                                        • +
                                      +
                                    +
                                      +
                                    • LL + ADC update
                                      • +
                                        +
                                      • Fix wrong ADC + group injected sequence configuration
                                        • +
                                          +
                                        • LL_ADC_INJ_SetSequencerRanks() and LL_ADC_INJ_GetSequencerRanks() - mso-fareast-font-family:"Times - New Roman"">)
                                          • -
                                          • +
                                        • Update + the defined values for + ADC group injected seqencer + ranks 
                                          • +
                                        +
                                      +
                                    +

                                    V1.7.0 - New Roman"">HAL_PWREx_

                                    +

                                    Main Changes

                                    +
                                      +
                                    • Add - New Roman"">EnableLowRegulatorLowVoltage(optimization
                                      • +
                                        +
                                      • Low Layer drivers + APIs provide register level + programming: require deep + knowledge of peripherals + described in STM32F4xx + Reference Manuals
                                        • +
                                      • Low Layer + drivers are available for: + ADC, Cortex, CRC, DAC, + DMA, DMA2D, EXTI, GPIO, I2C, + IWDG, LPTIM, PWR, RCC, RNG, + RTC, SPI, TIM, USART, WWDG + peripherals and additionnal + Low Level Bus, System and + Utilities APIs.
                                        • +
                                      • Low Layer drivers + APIs are implemented as static + inline function in new Inc/stm32f4xx_ll_ppp.h files - mso-fareast-font-family:"Times + for PPP peripherals, there is + no configuration file and each stm32f4xx_ll_ppp.h file - New Roman"">)
                                        • -
                                        • +
                                      +
                                    • General - New Roman"">HAL_PWREx_implementation
                                      • +
                                    • Fix extra - New Roman"">DisableLowRegulatorLowVoltage(compiler
                                      • +
                                    • HAL + drivers clean up: remove + double casting 'uint32_t' and 'U'
                                      • +
                                    • Add + new HAL - mso-fareast-font-family:"Times + MMC driver
                                      • +
                                    • The - New Roman"">)
                                      • + following changes done on the + HAL drivers require an update + on the application code based + on older HAL versions +
                                        +
                                      • HAL SD update
                                        • +
                                          +
                                        • Overall + rework of the driver for a + more + efficient implementation
                                          • +
                                            +
                                          • Modify + initialization API and structures
                                            • +
                                          • Modify + Read / Write sequences: + separate transfer process + and SD Cards state management 
                                            • +
                                          • Adding + interrupt mode for Read / + Write operations
                                            • +
                                          • Update + the HAL_SD_IRQHandler + function by optimizing the + management of interrupt errors
                                            • +
                                          +
                                        • Refer to + the following example to + identify the changes: BSP + example and USB_Device/MSC_Standalone + application
                                          • +
                                        +
                                      • HAL NAND update
                                        • +
                                          +
                                        • Modify NAND_AddressTypeDef, + NAND_DeviceConfigTypeDef + and NAND_HandleTypeDef + structures fields
                                          • +
                                        • Add new HAL_NAND_ConfigDevice + API
                                          • +
                                        +
                                      • HAL DFSDM update
                                        • +
                                          +
                                        • Add + support of Multichannel + Delay feature
                                          • +
                                            +
                                          • Add HAL_DFSDM_ConfigMultiChannelDelay + API
                                            • +
                                          • The + following APIs are moved + to internal static + functions: HAL_DFSDM_ClockIn_SourceSelection, + HAL_DFSDM_ClockOut_SourceSelection, + HAL_DFSDM_DataInX_SourceSelection + (X=0,2,4,6), HAL_DFSDM_BitStreamClkDistribution_Config
                                        -
                                      • HAL I2S update
                                        • +
                                          +
                                        • Add specific - mso-fareast-font-family:"Times - New Roman"">For - STM32F42xxx/43xxx devices, add - a new function for Under - Driver management as the macro - already added for this mode is - not sufficient: HAL_PWREx_EnterUnderDriveSTOPMode()
                                          • +
                                            +
                                          • HAL_I2S_TxCpltCallback() + and + HAL_I2S_RxCpltCallback() + API's will be replaced + with only + HAL_I2SEx_TxRxCpltCallback() + API. 
                                            • +
                                          +
                                        +
                                      +
                                    • HAL - New Roman"">
                                      • + update +
                                        +
                                      • Modifiy default HAL_Delay + implementation to guarantee + minimum delay 
                                      -
                                    -
                                      -
                                    • HAL + Cortex update
                                      • +
                                        +
                                      • Move HAL_MPU_Disable() + and HAL_MPU_Enable() - "Times New Roman"">HAL - RCC
                                        • +
                                      • Clear the + whole MPU control register + in HAL_MPU_Disable() + API
                                        • +
                                      +
                                    • HAL - New Roman"">update
                                      • -
                                        -
                                      • update
                                        • +
                                          +
                                        • IS_FLASH_ADDRESS() + macro update to support OTP + range
                                          • +
                                        • FLASH_Program_DoubleWord(): Replace + 64-bit accesses with 2 + double-words operations
                                          • +
                                        +
                                      • LL - mso-fareast-font-family:"Times + GPIO update
                                        • +
                                          +
                                        • Update + IS_GPIO_PIN() + macro implementation to be + more safe
                                          • +
                                        +
                                      • LL - New Roman"">In HAL_RCC_ClockConfig() - function: update the AHB clock - divider before clock switch to - new source
                                        • -
                                      • update
                                        • +
                                          +
                                        • Update + IS_RCC_PLLQ_VALUE() + macro implementation: the + minimum accepted value is + 2 instead of 4
                                          • +
                                        • Rename + RCC_LPTIM1CLKSOURCE_PCLK + define to + RCC_LPTIM1CLKSOURCE_PCLK1
                                          • +
                                        • Fix + compilation issue w/ + __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() + and + __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() + macros for STM32F401xx devices
                                          • +
                                        • Add the + following is clock + enabled macros for STM32F401xx + devices
                                          • +
                                            +
                                          •  __HAL_RCC_SDIO_IS_CLK_ENABLED()
                                            • +
                                          • __HAL_RCC_SPI4_IS_CLK_ENABLED()
                                            • +
                                          • __HAL_RCC_TIM10_IS_CLK_ENABLED()
                                            • +
                                          +
                                        • Add the + following is clock + enabled macros for STM32F410xx + devices
                                          • +
                                            +
                                          •  __HAL_RCC_CRC_IS_CLK_ENABLED()
                                            • +
                                          • __HAL_RCC_RNG_IS_CLK_ENABLED()
                                            • +
                                          +
                                        • Update HAL_RCC_DeInit() + to reset the RCC clock + configuration to the default + reset state.
                                          • +
                                        • Remove macros + to configure BKPSRAM from + STM32F401xx devices 
                                          • +
                                        • Update to + refer to AHBPrescTable[] + and APBPrescTable[] - mso-fareast-font-family:"Times + tables defined in + system_stm32f4xx.c file + instead of APBAHBPrescTable[] - New Roman"">Allow to - calibrate the HSI when it is - used as system clock source
                                          • +
                                        +
                                      • HAL - New Roman"">
                                        • -
                                      • update
                                        • +
                                          +
                                        • Add + FMPI2C_FIRST_AND_NEXT_FRAME + define in Sequential + Transfer Options
                                          • +
                                        +
                                      • HAL - mso-fareast-font-family:"Times + ADC update
                                        • +
                                          +
                                        • HAL_ADCEx_InjectedConfigChannel(): update the + external trigger injected + condition
                                          • +
                                        +
                                      • HAL - New Roman"">Rename the - following macros
                                        • -
                                          -
                                        • update
                                          • +
                                            +
                                          • HAL_DMA_Init(): update to + check compatibility between + FIFO threshold level and size + of the memory burst 
                                            • +
                                          +
                                        • HAL + QSPI update
                                          • +
                                            +
                                          • QSPI_HandleTypeDef structure: + Update transfer parameters on + uint32_t instead of uint16_t
                                            • +
                                          +
                                        • HAL - mso-fareast-font-family:"Times + UART/USART/IrDA/SMARTCARD update
                                          • +
                                            +
                                          • DMA Receive + process; the code has been + updated to clear the USART + OVR flag before + enabling DMA receive + request.
                                            • +
                                          • UART_SetConfig() update to + manage correctly USART6 + instance that is not available + on STM32F410Tx devices
                                            • +
                                          +
                                        • HAL - New Roman"">__OTGFS_FORCE_RESET + CAN update
                                          • +
                                            +
                                          • Remove Lock + mechanism from HAL_CAN_Transmit_IT() + and HAL_CAN_Receive_IT() - ()  by - __USB_OTG_FS_FORCE_RESET()
                                            • -
                                            • +
                                          +
                                        • HAL - mso-fareast-font-family:"Times + TIM update
                                          • +
                                            +
                                          • Add + __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() + macro to disable Master output + without check on TIM channel + state. 
                                            • +
                                          • Update HAL_TIMEx_ConfigBreakDeadTime() + to fix TIM BDTR register + corruption.
                                            • +
                                          +
                                        • HAL - New Roman"">__OTGFS_RELEASE_RESET + I2C update
                                          • +
                                            +
                                          • Update + HAL_I2C_Master_Transmit() + and HAL_I2C_Slave_Transmit() + to avoid sending extra + bytes at the end of the + transmit processes
                                            • +
                                          • Update + HAL_I2C_Mem_Read() + API to fix wrong check on + misused parameter �Size�
                                            • +
                                          • Update + I2C_MasterReceive_RXNE() + and I2C_MasterReceive_BTF() + static APIs to enhance Master + sequential reception process.
                                            • +
                                          +
                                        • HAL - ()  by  -__USB_OTG_FS_RELEASE_RESET()
                                          • -
                                        • update
                                          • +
                                            +
                                          • Add transfer + abort APIs and associated + callbacks in interrupt mode
                                            • +
                                              +
                                            • HAL_SPI_Abort()
                                              • +
                                            • HAL_SPI_Abort_IT()
                                              • +
                                            • HAL_SPI_AbortCpltCallback()
                                              • +
                                            +
                                          +
                                        • HAL - mso-fareast-font-family:"Times + I2S update
                                          • +
                                            +
                                          • Add specific - New Roman"">__OTGFS_CLK_SLEEP_ENABLE + callback API to manage I2S + full duplex end of transfer + process:
                                            • +
                                              +
                                            • HAL_I2S_TxCpltCallback() + and HAL_I2S_RxCpltCallback() + API's will be replaced with + only + HAL_I2SEx_TxRxCpltCallback() + API. 
                                              • +
                                            +
                                          • Update I2S + Transmit/Receive polling + process to manage Overrun + and Underrun errors
                                            • +
                                          • Move + the I2S clock input + frequency calculation to + HAL RCC driver.
                                            • +
                                          • Update the + HAL I2SEx driver to keep only + full duplex feature.
                                            • +
                                          • HAL_I2S_Init() + API updated to
                                            • +
                                              +
                                            • Fix wrong + I2S clock calculation when + PCM mode is used.
                                              • +
                                            • Return + state HAL_I2S_ERROR_PRESCALER when + the I2S clock is wrongly configured
                                              • +
                                            +
                                          +
                                        +
                                          +
                                        • HAL - ()  by  -__USB_OTG_FS_CLK_SLEEP_ENABLE()
                                          • -
                                        • update
                                          • +
                                            +
                                          • Optimize HAL_LTDC_IRQHandler() + function by using direct + register read
                                            • +
                                          • Rename the + following API's
                                            • +
                                              +
                                            • HAL_LTDC_Relaod() by HAL_LTDC_Reload() 
                                              • +
                                            • HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()
                                              • +
                                            • HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()
                                              • +
                                            +
                                          • Add new + defines for LTDC layers + (LTDC_LAYER_1 / LTDC_LAYER_2)
                                            • +
                                          • Remove unused + asserts
                                            • +
                                          +
                                        • HAL - mso-fareast-font-family:"Times + USB PCD + update
                                          • +
                                            +
                                          • Flush all TX + FIFOs on USB Reset
                                            • +
                                          • Remove Lock + mechanism from HAL_PCD_EP_Transmit() + and HAL_PCD_EP_Receive() - New Roman"">__OTGFS_CLK_SLEEP_DISABLE + API's
                                            • +
                                          +
                                        +
                                          +
                                        • LL - () by  __USB_OTG_FS_CLK_SLEEP_DISABLE() update
                                          • +
                                            +
                                          • Enable DMA + Burst mode for USB OTG HS
                                            • +
                                          • Fix SD card + detection issue
                                            • +
                                          +
                                        • LL - New Roman"">
                                          • -
                                        + SDMMC update +
                                          +
                                        • Add new SDMMC_CmdSDEraseStartAdd, + SDMMC_CmdSDEraseEndAdd, + SDMMC_CmdOpCondition + and SDMMC_CmdSwitch + functions
                                      -

                                       

                                      -
                                        -
                                          -
                                        • V1.6.0 + / 04-November-2016 +

                                          Main Changes

                                          +
                                            +
                                          • Add support of STM32F413xx + and STM32F423xx + devices
                                            • +
                                          • General - mso-fareast-font-family:"Times + updates to fix known defects and + enhancements implementation
                                            • +
                                          • HAL - New Roman"">Add new field - PLLI2SM in - RCC_PLLI2SInitTypeDef - structure, this division - factor is added for PLLI2S VCO - input clock only STM32F411xE - devices => the FW - compatibility is broken vs. - STM32F401xx devices
                                            • -
                                          • update
                                            • +
                                              +
                                            • Update to add + the support of 3 CAN management
                                              • +
                                            +
                                          • HAL - mso-fareast-font-family:"Times + CRYP update
                                            • +
                                              +
                                            • Update to add + the support of AES features
                                              • +
                                            +
                                          • HAL - New Roman"">Update HAL_RCCEx_PeriphCLKConfig() - and  HAL_RCCEx_GetPeriphCLKConfig()  + DFSDM update
                                            • +
                                              +
                                            • Add + definitions for new external + trigger filters
                                              • +
                                            • Add + definition for new Channels + 4, 5, 6 and 7
                                              • +
                                            • Add + functions and API for Filter + state configuration and management
                                              • +
                                            • Add new + functions: 
                                              • +
                                                +
                                              • HAL_DFSDM_BitstreamClock_Start()
                                                • +
                                              • HAL_DFSDM_BitstreamClock_Stop()
                                                • +
                                              • HAL_DFSDM_BitStreamClkDistribution_Config() 
                                                • +
                                              +
                                            +
                                          • HAL - functions to support the new - PLLI2SM
                                            • -
                                            • +
                                              +
                                            • Add the + support of DMA Channels from + 8 to 15
                                              • +
                                            • Update HAL_DMA_DeInit() + function with the check on + DMA stream instance
                                              • +
                                            +
                                          • HAL + DSI update
                                            • +
                                          +
                                            +
                                              +
                                            • Update HAL_DSI_ConfigHostTimeouts() + and HAL_DSI_Init() - mso-fareast-font-family:"Times - New Roman"">Add new - function to manage the new LSE - mode + functions to avoid scratch in + DSI_CCR register
                                              • +
                                            +
                                          • HAL + FLASH update
                                            • +
                                              +
                                            • Enhance FLASH_WaitForLastOperation() + function implementation
                                              • +
                                            • Update + __HAL_FLASH_GET_FLAG() + macro implementation
                                              • +
                                            +
                                          • HAL + - : HAL_RCCEx_SelectLSEMode() update
                                            • +
                                              +
                                            • Add + specific alternate functions + definitions
                                              • +
                                            +
                                          • HAL - New Roman"">
                                            • -
                                          • update
                                            • +
                                              +
                                            • Update I2C_DMAError() + function implementation to + ignore DMA FIFO error
                                              • +
                                            +
                                          • HAL - mso-fareast-font-family:"Times + I2S update
                                            • +
                                              +
                                            • Enhance + HAL_I2S_Init() + implementation to test on + PCM_SHORT and PCM_LONG + standards
                                              • +
                                            +
                                          • HAL - New Roman"">Reorganize - the macros depending from - Part number used and make them - more clear
                                            • + IRDA update +
                                              +
                                            • Add new + functions and call backs for + Transfer Abort
                                              • +
                                                +
                                              • HAL_IRDA_Abort()
                                                • +
                                              • HAL_IRDA_AbortTransmit()
                                                • +
                                              • HAL_IRDA_AbortReceive()
                                                • +
                                              • HAL_IRDA_Abort_IT()
                                                • +
                                              • HAL_IRDA_AbortTransmit_IT()
                                                • +
                                              • HAL_IRDA_AbortReceive_IT()
                                                • +
                                              • HAL_IRDA_AbortCpltCallback()
                                                • +
                                              • HAL_IRDA_AbortTransmitCpltCallback()
                                                • +
                                          -

                                          +

                                            +
                                              +
                                            • HAL_IRDA_AbortReceiveCpltCallback()
                                              • +
                                            +
                                          +
                                        • HAL + PCD update
                                          • +
                                        +
                                          +
                                            +
                                          • Update HAL_PCD_GetRxCount() +  function implementation
                                            • +
                                          +
                                        • HAL - color:black">�  HAL + RCC update
                                          • +
                                            +
                                          • Update + __HAL_RCC_HSE_CONFIG() + macro implementation
                                            • +
                                          • Update __HAL_RCC_LSE_CONFIG() + macro implementation
                                            • +
                                          +
                                        • HAL - UART update

                                          -
                                            -
                                              -
                                            •  update
                                              • +
                                            +
                                              +
                                                +
                                              • Add new + functions and call backs for + Transfer Abort
                                                • +
                                                  +
                                                • HAL_ SMARTCARD_Abort()
                                                  • +
                                                • HAL_ SMARTCARD_AbortTransmit()
                                                  • +
                                                • HAL_ SMARTCARD_AbortReceive()
                                                  • +
                                                • HAL_ SMARTCARD_Abort_IT()
                                                  • +
                                                • HAL_ SMARTCARD_AbortTransmit_IT()
                                                  • +
                                                • HAL_ SMARTCARD_AbortReceive_IT()
                                                  • +
                                                • HAL_ SMARTCARD_AbortCpltCallback()
                                                  • +
                                                • HAL_ SMARTCARD_AbortTransmitCpltCallback()
                                                  • +
                                                • HAL_ SMARTCARD_AbortReceiveCpltCallback()
                                                  • +
                                                +
                                              +
                                            • HAL - level2 lfo131;tab-stops: list - 1.0in"> update
                                              • +
                                                +
                                              • Update HAL_TIMEx_RemapConfig() + function to manage TIM + internal trigger remap: + LPTIM or TIM3_TRGO
                                                • +
                                              +
                                            • HAL - New Roman"">Add new - macros to control CTS and RTS update
                                              • +
                                                +
                                              • Add + Transfer abort functions and + callbacks
                                                • +
                                              +
                                            • HAL - New Roman"">
                                              • -
                                            •  update
                                              • +
                                                +
                                              • Add + Transfer abort functions and + callbacks
                                                • +
                                              +
                                            +

                                            V1.5.2 - mso-fareast-font-family:"Times + / 22-September-2016

                                            +

                                            Main Changes

                                            +
                                              +
                                            • HAL - New Roman"">Add specific - macros to manage the flags - cleared only by a software sequence update
                                              • +
                                                +
                                              • Fix wrong + behavior in consecutive + transfers in case of single + byte transmission + (Master/Memory Receive
                                                + interfaces)
                                                • +
                                              • Update + HAL_I2C_Master_Transmit_DMA() + / + HAL_I2C_Master_Receive_DMA()/ + HAL_I2C_Slave_Transmit_DMA()
                                                + and + HAL_I2C_Slave_Receive_DMA() to + manage addressing phase + through interruption instead + of polling
                                                • +
                                              • Add + a check on I2C handle + state at start of all I2C + API's to ensure that I2C is ready
                                                • +
                                              • Update I2C + API's (Polling, IT and DMA + interfaces) to manage I2C XferSize + and XferCount + handle parameters instead of + API size parameter to help + user to get information of + counter in case of + error. 
                                                • +
                                              • Update Abort + functionality to manage DMA + use case
                                                • +
                                              +
                                            • HAL - New Roman""> update
                                              • +
                                                +
                                              • Update to + disable Own Address + before setting the new Own + Address + configuration:
                                                • +
                                                  +
                                                • Update + HAL_FMPI2C_Init() + to disable FMPI2C_OARx_EN + bit before any + configuration in OARx + registers
                                                  • +
                                                +
                                              +
                                            • HAL - mso-fareast-font-family:"Times + CAN update
                                              • +
                                                +
                                              • Update CAN + receive processes to set CAN + RxMsg + FIFONumber + parameter
                                                • +
                                              +
                                            • HAL - New Roman"">
                                              • -
                                                -
                                              • update
                                                • +
                                                  +
                                                • Update UART + handle TxXferCount + and RxXferCount parameters - mso-fareast-font-family:"Times - New Roman"">__HAL_UART_CLEAR_PEFLAG()High Speed + optimization  
                                                  • +
                                                +
                                              +

                                              V1.5.1 - New Roman"">

                                              +

                                              Main Changes

                                              +
                                                +
                                              • HAL + GPIO update
                                                • +
                                                  +
                                                • HAL_GPIO_Init()/HAL_GPIO_DeInit() + API's: + update GPIO_GET_INDEX() + macro implementation to + support all GPIO's
                                                  • +
                                                +
                                              • HAL - mso-fareast-font-family:"Times + SPI update
                                                • +
                                                  +
                                                • Fix + regression issue: + retore HAL_SPI_DMAPause() + and HAL_SPI_DMAResume() API's +
                                                  • +
                                                +
                                              • HAL - New Roman"">
                                                • -
                                              • update
                                                • +
                                                  +
                                                • Fix FSMC + macros compilation warnings + with STM32F412Rx devices
                                                  • +
                                                +
                                              • HAL - mso-fareast-font-family:"Times + DMA update
                                                • +
                                                  +
                                                • HAL_DMA_PollFortransfer() API clean + up
                                                  +
                                                  +
                                                  • +
                                                +
                                              • HAL - New Roman"">__HAL_UART_CLEAR_FEFLAG()update(PPP refers to + IRDA, UART, USART and SMARTCARD)
                                                • +
                                                  +
                                                • Update - New Roman""> HAL_PPP_IRQHandler() + to add a check on interrupt + source before managing the + error 
                                                  • +
                                                +
                                              +
                                                +
                                              • HAL - mso-fareast-font-family:"Times + QSPI update
                                                • +
                                                  +
                                                • Implement + workaround to fix the + limitation pronounced - New Roman"">
                                                  • -
                                                • in + the Errata + sheet 2.1.8 section: + In some specific cases, + DMA2 data corruption + occurs when managing AHB + and APB2 peripherals in a + concurrent way
                                                  • +
                                                +
                                              +

                                              V1.5.0 + / 06-May-2016

                                              +

                                              Main Changes

                                              +
                                                +
                                              • Add support of STM32F412cx, - mso-fareast-font-family:"Times - New Roman"">__HAL_UART_CLEAR_NEFLAG()devices
                                                • +
                                              • General - New Roman""> implementation
                                                • +
                                              • Add + new HAL driver for DFSDM peripheral
                                                • +
                                              • Enhance + HAL delay and time base + implementation:
                                                • +
                                                  +
                                                • Add new + drivers + stm32f4xx_hal_timebase_rtc_alarm_template.c + and + stm32f4xx_hal_timebase_rtc_wakeup_template.c + which override the native HAL + time base functions (defined + as weak) to either use the RTC + as time base tick source. For + more details about the usage + of these drivers, please refer + to HAL\HAL_TimeBase_RTC + examples and - mso-fareast-font-family:"Times - New Roman"">
                                                  • -
                                                • FreeRTOS-based - mso-fareast-font-family:"Times + applications
                                                  • +
                                                +
                                              • The - New Roman"">__HAL_UART_CLEAR_OREFLAG()
                                                • +
                                                  +
                                                • HAL UART, + USART, IRDA, SMARTCARD, SPI, + I2C,FMPI2C, - New Roman"">  (referenced + as PPP here - mso-fareast-font-family:"Times + below) drivers
                                                  • +
                                                    +
                                                  • Add PPP + error management during DMA + process. This requires the + following updates + on user application:
                                                    • +
                                                      +
                                                    • Configure + and enable the PPP IRQ in + HAL_PPP_MspInit() + function
                                                      • +
                                                    • In stm32f4xx_it.c - New Roman"">
                                                      • -
                                                    •  PPP_IRQHandler() + function: add - mso-fareast-font-family:"Times + a call to HAL_PPP_IRQHandler() - New Roman"">__HAL_UART_CLEAR_IDLEFLAG()
                                                      • + function +
                                                    • Add and + customize the Error + Callback API: HAL_PPP_ErrorCallback()
                                                      • +
                                                  -
                                                • HAL I2C, FMPI2C (referenced + as PPP here - mso-fareast-font-family:"Times + below) drivers:
                                                  • +
                                                    +
                                                  • Update to + avoid waiting on STOPF/BTF/AF - New Roman"">Add several - enhancements without affecting - the driver functionalities -
                                                    • -
                                                      -
                                                    •  PPP - mso-fareast-font-family:"Times + end of transfer interrupt in + the DMA transfer process. This - New Roman"">Remove the - check on RXNE set after - reading the Data in the DR - register
                                                      • +
                                                        +
                                                      • Configure + and enable the PPP IRQ in + HAL_PPP_MspInit() + function
                                                        • +
                                                      • In stm32f4xx_it.c - mso-fareast-font-family:"Times + file, PPP_IRQHandler() + function: add - New Roman"">
                                                        • -
                                                      • HAL_PPP_IRQHandler() - mso-fareast-font-family:"Times + function
                                                        • +
                                                      +
                                                    +
                                                  • HAL I2C driver:
                                                    • +
                                                      +
                                                    • I2C + transfer processes IT + update: NACK during + addressing phase is managed + through I2C Error + interrupt instead of + HAL state
                                                      • +
                                                    +
                                                  +
                                                +
                                                  +
                                                    +
                                                  • HAL IWDG driver: + rework overall driver for + better implementation
                                                    • +
                                                      +
                                                    • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() - New Roman"">Update the - transmit processes to use - TXE instead of TC HAL_IWDG_GetState() APIs
                                                      • +
                                                    +
                                                  • HAL WWDG driver: + rework overall driver for + better implementation
                                                    • +
                                                      +
                                                    • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() - New Roman"">
                                                      • -
                                                    •  HAL_WWDG_GetState() - mso-fareast-font-family:"Times - New Roman"">Update HAL_UART_Transmit_IT() - to enable UART_IT_TXE - instead of UART_IT_TC
                                                      • +
                                                    • Update + the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, + uint32_t counter) +  function and API +  by removing the +  "counter" parameter
                                                      • +
                                                    +
                                                  • HAL QSPI + driver:  Enhance + the DMA transmit process + by using PPP TC + interrupt instead of waiting + on TC flag under DMA + ISR. This requires the + following updates on user + application:
                                                    • +
                                                      +
                                                    • Configure + and enable the QSPI IRQ + in HAL_QSPI_MspInit() + function
                                                      • +
                                                    • In stm32f4xx_it.c - New Roman"">
                                                      • -
                                                    -
                                                  -
                                                -

                                                �  + file, QSPI_IRQHandler() + function: add - HAL USART - update

                                                -
                                                  -
                                                    -
                                                  • HAL_QSPI_IRQHandler() - mso-fareast-font-family:"Times + function
                                                    • +
                                                  +
                                                • HAL CEC + driver:  Overall + driver rework with + compatibility break versus + previous HAL version
                                                  • +
                                                    +
                                                  • Remove HAL + CEC polling Process + functions: HAL_CEC_Transmit() + and HAL_CEC_Receive()
                                                    • +
                                                  • Remove HAL + CEC receive interrupt + process function HAL_CEC_Receive_IT() + and enable the "receive" +  mode during the Init + phase
                                                    • +
                                                  • Rename HAL_CEC_GetReceivedFrameSize() + funtion + to HAL_CEC_GetLastReceivedFrameSize()
                                                    • +
                                                  • Add new HAL + APIs: HAL_CEC_SetDeviceAddress() + and HAL_CEC_ChangeRxBuffer()
                                                    • +
                                                  • Remove + the 'InitiatorAddress' + field from the CEC_InitTypeDef + structure and manage + it as a parameter in + the HAL_CEC_Transmit_IT() + function
                                                    • +
                                                  • Add new + parameter 'RxFrameSize' + in HAL_CEC_RxCpltCallback() + function
                                                    • +
                                                  • Move CEC Rx + buffer pointer from CEC_HandleTypeDef + structure to CEC_InitTypeDef + structure
                                                    • +
                                                  +
                                                +
                                              +
                                                +
                                              • HAL - New Roman"">Add specific - macros to manage the flags - cleared only by a software sequenceupdate
                                                • +
                                                  +
                                                • Update HAL_RCC_ClockConfig() + function to adjust the SystemCoreClock
                                                  • +
                                                • Rename macros + and Literals:
                                                  • +
                                                    +
                                                  • RCC_PERIPHCLK_CK48 by RCC_PERIPHCLK_CLK48
                                                    • +
                                                  • IS_RCC_CK48CLKSOURCE by - New Roman"">
                                                    • -
                                                      -
                                                      • +
                                                    • RCC_CK48CLKSOURCE_PLLSAIP - mso-fareast-font-family:"Times + by RCC_CLK48CLKSOURCE_PLLSAIP
                                                      • +
                                                    • RCC_SDIOCLKSOURCE_CK48 - New Roman"">__HAL_USART_CLEAR_PEFLAG()
                                                      • +
                                                    • RCC_CK48CLKSOURCE_PLLQ - New Roman"">
                                                      • +
                                                    +
                                                  • Update HAL_RCCEx_GetPeriphCLKConfig() + and HAL_RCCEx_PeriphCLKConfig() - mso-fareast-font-family:"Times + functions to support TIM Prescaler + for STM32F411xx devices
                                                    • +
                                                  • HAL_RCCEx_PeriphCLKConfig() API: update + to fix the RTC clock + configuration issue
                                                    • +
                                                  +
                                                • HAL - New Roman"">
                                                  • -
                                                • update
                                                  • +
                                                    +
                                                  • Overall + driver rework with break + of compatibility with HAL + V1.4.4
                                                    • +
                                                      +
                                                    • Remove the + HAL CEC polling Process: HAL_CEC_Transmit() + and HAL_CEC_Receive()
                                                      • +
                                                    +
                                                  +
                                                +
                                                  +
                                                    +
                                                      +
                                                    • Remove the + HAL CEC receive interrupt + process (HAL_CEC_Receive_IT()) - mso-fareast-font-family:"Times + and manage the "Receive" + mode enable within the Init + phase
                                                      • +
                                                    • Rename HAL_CEC_GetReceivedFrameSize() + function to HAL_CEC_GetLastReceivedFrameSize() - New Roman"">__HAL_USART_CLEAR_FEFLAG()
                                                      • +
                                                    • Add new HAL + APIs: HAL_CEC_SetDeviceAddress() + and HAL_CEC_ChangeRxBuffer()
                                                      • +
                                                    • Remove + the 'InitiatorAddress' + field from the CEC_InitTypeDef + structure and manage + it as a parameter in + the HAL_CEC_Transmit_IT() + function
                                                      • +
                                                    • Add new + parameter 'RxFrameSize' + in HAL_CEC_RxCpltCallback() + function
                                                      • +
                                                    • Move CEC Rx + buffer pointer from CEC_HandleTypeDef + structure to CEC_InitTypeDef + structure
                                                      • +
                                                    +
                                                  • Update driver + to implement the new CEC state + machine:
                                                    • +
                                                      +
                                                    • Add + new "rxState" field - mso-fareast-font-family:"Times + in CEC_HandleTypeDef + structure to provide the CEC state - New Roman"">
                                                      • -
                                                    • Operations
                                                      • +
                                                    • Rename + "state" field in CEC_HandleTypeDef + structure to "gstate": - mso-fareast-font-family:"Times + CEC state - New Roman"">__HAL_USART_CLEAR_NEFLAG()Operations
                                                      • +
                                                    • Update CEC + process to manage the new + CEC states.
                                                      • +
                                                    • Update + __HAL_CEC_RESET_HANDLE_STATE() + macro to handle the new CEC + state parameters (gState, + rxState)
                                                      • +
                                                    +
                                                  +
                                                +
                                                  +
                                                • HAL - New Roman""> (referenced - mso-fareast-font-family:"Times + as PPP here below) update
                                                  • +
                                                    +
                                                  • Update + Polling management:
                                                    • +
                                                      +
                                                    • The user + Timeout value must be + estimated for the overall + process duration: the + Timeout measurement is + cumulative
                                                      • +
                                                    +
                                                  • Update DMA + process:
                                                    • +
                                                      +
                                                    • Update the + management of PPP peripheral + errors during DMA process. + This requires the following + updates in user application:
                                                      • +
                                                        +
                                                      • Configure + and enable the PPP IRQ in + HAL_PPP_MspInit() + function
                                                        • +
                                                      • In + stm32f4xx_it.c file, PPP_IRQHandler() + function: add a call to HAL_PPP_IRQHandler() - New Roman"">
                                                        • -
                                                        • +
                                                      • Add and + customize the Error + Callback API: HAL_PPP_ErrorCallback()
                                                        • +
                                                      +
                                                    +
                                                  +
                                                • HAL - mso-fareast-font-family:"Times + FMC update
                                                  • +
                                                    +
                                                  • Update FMC_NORSRAM_Init() + to remove the Burst access + mode configuration
                                                    • +
                                                  • Update FMC_SDRAM_Timing_Init() + to fix initialization issue + when configuring 2 SDRAM banks
                                                    • +
                                                  +
                                                • HAL - New Roman"">__HAL_USART_CLEAR_OREFLAG() update
                                                  • +
                                                    +
                                                  • Update HCD_Port_IRQHandler() + to unmask disconnect IT only + when the port is disabled
                                                    • +
                                                  +
                                                • HAL - New Roman""> + update
                                                  • +
                                                    +
                                                  • Update Polling - mso-fareast-font-family:"Times + management:
                                                    • +
                                                      +
                                                    • The Timeout + value must be estimated for + the overall process + duration: the + Timeout measurement is + cumulative
                                                      • +
                                                    +
                                                  • Add the + management of Abort + service: Abort DMA + transfer through interrupt
                                                    • +
                                                      +
                                                    • In the case + of Master Abort IT transfer + usage:
                                                      • +
                                                        +
                                                      • Add new - New Roman"">
                                                        • -
                                                      • AbortCpltCallback() + to inform user of the end + of abort process
                                                        • +
                                                      • A new + abort state is defined in + the HAL_I2C_StateTypeDef structure
                                                        • +
                                                      +
                                                    +
                                                  • Add the + management of I2C peripheral + errors, ACK failure and STOP + condition detection during DMA + process. This requires the + following updates on user + application:
                                                    • +
                                                      +
                                                    • Configure + and enable the I2C IRQ in + HAL_I2C_MspInit() + function
                                                      • +
                                                    • In + stm32f4xx_it.c file, I2C_IRQHandler() + function: add a call to + HAL_I2C_IRQHandler() + function
                                                      • +
                                                    • Add and + customize the Error Callback + API: HAL_I2C_ErrorCallback()
                                                      • +
                                                    • Refer to + the I2C_EEPROM or + I2C_TwoBoards_ComDMA project + examples usage of the API
                                                      • +
                                                    +
                                                  • NACK error + during addressing phase is + returned through interrupt + instead of previously through + I2C transfer API's
                                                    • +
                                                  • I2C + addressing phase is updated to + be managed using interrupt + instead of polling (Only + for HAL I2C driver)
                                                    • +
                                                      +
                                                    • Add new + static functions to manage + I2C SB, ADDR and ADD10 flags
                                                      • +
                                                    +
                                                  +
                                                • HAL + SPI update
                                                  • +
                                                +
                                                  +
                                                    +
                                                  • Overall + driver optimization to improve + performance in + polling/interrupt mode to + reach maximum peripheral frequency
                                                    • +
                                                      +
                                                    • Polling + mode:
                                                      • +
                                                        +
                                                      • Replace + the use of SPI_WaitOnFlagUnitTimeout() + function by "if" statement + to check on RXNE/TXE flage + while transferring data
                                                        • +
                                                      +
                                                    +
                                                  +
                                                +
                                                  +
                                                    +
                                                      +
                                                    •  Interrupt - mso-fareast-font-family:"Times + mode:
                                                      • +
                                                        +
                                                      • Minimize + access on SPI registers
                                                        • +
                                                      +
                                                    • All modes:
                                                      • +
                                                        +
                                                      • Add the + USE_SPI_CRC switch to + minimize the number of + statements when CRC + calculation is disabled
                                                        • +
                                                      • Update timeout - New Roman"">__HAL_USART_CLEAR_IDLEFLAG()
                                                        • + management to check on + global processes +
                                                      • Update + error code management in + all processes
                                                        • +
                                                    -
                                                  • Update DMA + process:
                                                    • +
                                                      +
                                                    • Add the + management of SPI peripheral + errors during DMA process. + This requires the following + updates in the user + application:
                                                      • +
                                                        +
                                                      • Configure + and enable the SPI IRQ in + HAL_SPI_MspInit() + function
                                                        • +
                                                      • In + stm32f4xx_it.c file, SPI_IRQHandler() + function: add a call to HAL_SPI_IRQHandler() - level2 lfo132;tab-stops: list - 1.0in">
                                                        • +
                                                      • Add and + customize the Error + Callback API: HAL_SPI_ErrorCallback()
                                                        • +
                                                      • Refer to + the following example + which describe the + changes: SPI_FullDuplex_ComDMA
                                                        • +
                                                      +
                                                    +
                                                  • Fix + regression in polling mode:
                                                    • +
                                                      +
                                                    • Add + preparing data to transmit + in case of slave mode in HAL_SPI_TransmitReceive() + and HAL_SPI_Transmit()
                                                      • +
                                                    • Add to + manage properly the overrun + flag at the end of a HAL_SPI_TransmitReceive()
                                                      • +
                                                    +
                                                  • Fix + regression in interrupt mode:
                                                    • +
                                                      +
                                                    • Add a wait + on TXE flag in SPI_CloseTx_ISR() + and in SPI_CloseTxRx_ISR()
                                                      • +
                                                    • Add to + manage properly + the overrun flag in SPI_CloseRxTx_ISR() + and SPI_CloseRx_ISR()
                                                      • +
                                                    +
                                                  +
                                                +
                                                  +
                                                • HAL - New Roman"">Update HAL_USART_Transmit_IT() - to enable USART_IT_TXE - instead of USART_IT_TC update
                                                  • +
                                                    +
                                                  • Update the + HAL_DMA2D_DeInit() + function to:
                                                    • +
                                                      +
                                                    • Abort + transfer in case of ongoing + DMA2D transfer
                                                      • +
                                                    • Reset DMA2D + control registers
                                                      • +
                                                    +
                                                  • Update + HAL_DMA2D_Abort() + to disable DMA2D interrupts + after stopping transfer
                                                    • +
                                                  • Optimize + HAL_DMA2D_IRQHandler() + by reading status registers + only once
                                                    • +
                                                  • Update + HAL_DMA2D_ProgramLineEvent() + function to:
                                                    • +
                                                      +
                                                    • Return HAL + error state in case of wrong + line value
                                                      • +
                                                    • Enable line + interrupt after setting the + line watermark configuration
                                                      • +
                                                    +
                                                  • Add new + HAL_DMA2D_CLUTLoad() + and HAL_DMA2D_CLUTLoad_IT() functions - New Roman"">
                                                    • -
                                                  -
                                                -

                                                �  + to start DMA2D CLUT loading +

                                                  +
                                                • HAL_DMA2D_CLUTLoading_Abort() + function to abort the DMA2D + CLUT loading
                                                  • +
                                                • HAL_DMA2D_CLUTLoading_Suspend() + function to suspend the + DMA2D CLUT loading
                                                  • +
                                                • HAL_DMA2D_CLUTLoading_Resume() + function to resume the DMA2D + CLUT loading
                                                  • +
                                                +
                                              • Add new DMA2D + dead time management:
                                                • +
                                                  +
                                                • HAL_DMA2D_EnableDeadTime() + function to enable DMA2D + dead time feature
                                                  • +
                                                • HAL_DMA2D_DisableDeadTime() + function to disable DMA2D + dead time feature
                                                  • +
                                                • HAL_DMA2D_ConfigDeadTime() + function to configure dead + time
                                                  • +
                                                +
                                              • Update the + name of DMA2D Input/Output + color mode defines to be more - HAL IRDA update

                                                -
                                                  -
                                                    -
                                                    • +
                                                  +
                                                +
                                                  +
                                                • HAL - mso-fareast-font-family:"Times + LTDC update
                                                  • +
                                                +
                                                  +
                                                    +
                                                  • Update HAL_LTDC_IRQHandler() + to manage the case of reload + interrupt
                                                    • +
                                                  • Add new + callback API HAL_LTDC_ReloadEventCallback()
                                                    • +
                                                  • Add HAL_LTDC_Reload() + to configure LTDC reload + feature
                                                    • +
                                                  • Add new No + Reload LTDC variant APIs
                                                    • +
                                                      +
                                                    • HAL_LTDC_ConfigLayer_NoReload() to + configure the LTDC Layer + according to the specified + without reloading
                                                      • +
                                                    • HAL_LTDC_SetWindowSize_NoReload() to set + the LTDC window size without + reloading
                                                      • +
                                                    • HAL_LTDC_SetWindowPosition_NoReload() to set + the LTDC window position + without reloading
                                                      • +
                                                    • HAL_LTDC_SetPixelFormat_NoReload() to + reconfigure the pixel format + without reloading
                                                      • +
                                                    • HAL_LTDC_SetAlpha_NoReload() to + reconfigure the layer alpha + value without reloading
                                                      • +
                                                    • HAL_LTDC_SetAddress_NoReload() to + reconfigure the frame buffer + Address without reloading
                                                      • +
                                                    • HAL_LTDC_SetPitch_NoReload() to + reconfigure the pitch for + specific cases
                                                      • +
                                                    • HAL_LTDC_ConfigColorKeying_NoReload() to + configure the color keying + without reloading
                                                      • +
                                                    • HAL_LTDC_EnableColorKeying_NoReload() to enable + the color keying without + reloading
                                                      • +
                                                    • HAL_LTDC_DisableColorKeying_NoReload() to + disable the color keying + without reloading
                                                      • +
                                                    • HAL_LTDC_EnableCLUT_NoReload() to enable + the color lookup table + without reloading
                                                      • +
                                                    • HAL_LTDC_DisableCLUT_NoReload() to + disable the color lookup + table without reloading
                                                      • +
                                                    • Note: Variant + functions with �_NoReload� + post fix allows to set the + LTDC configuration/settings + without immediate reload. + This is useful in case when + the program requires to + modify several LTDC settings + (on one or both layers) then + applying (reload) these + settings in one shot by + calling the function �HAL_LTDC_Reload�
                                                      • +
                                                    +
                                                  +
                                                • HAL - New Roman"">Add specific - macros to manage the flags - cleared only by a software sequence update 
                                                  • +
                                                    +
                                                  • Add new + timeout implementation based + on cpu + cycles + for ALRAWF, ALRBWF + and WUTWF flags
                                                    • +
                                                  +
                                                +
                                                  +
                                                • HAL - New Roman"">
                                                  • -
                                                    -
                                                  •  update
                                                    • +
                                                      +
                                                    • Update SAI + state in case of TIMEOUT error + within the HAL_SAI_Transmit() + / HAL_SAI_Receive()
                                                      • +
                                                    • Update HAL_SAI_IRQHandler:
                                                      • +
                                                        +
                                                      • Add error + management in case DMA + errors through XferAbortCallback() + and HAL_DMA_Abort_IT()
                                                        • +
                                                      • Add error + management in case of IT
                                                        • +
                                                      +
                                                    • Move SAI_BlockSynchroConfig() + and SAI_GetInputClock() - mso-fareast-font-family:"Times + functions to + stm32f4xx_hal_sai.c/.h files + (extension files are kept + empty for projects + compatibility reason)
                                                      • +
                                                    +
                                                  +
                                                    +
                                                  • HAL - New Roman"">__HAL_IRDA_CLEAR_PEFLAG() update
                                                    • +
                                                      +
                                                    • Rename DCMI_DMAConvCplt + to DCMI_DMAXferCplt
                                                      • +
                                                    • Update HAL_DCMI_Start_DMA() + function to Enable the + DCMI peripheral
                                                      • +
                                                    • Add new + timeout implementation based + on cpu + cycles for DCMI stop
                                                      • +
                                                    • Add HAL_DCMI_Suspend() + function to suspend DCMI + capture
                                                      • +
                                                    • Add HAL_DCMI_Resume() + function to resume capture + after DCMI suspend
                                                      • +
                                                    • Update lock + mechanism for DCMI process
                                                      • +
                                                    • Update HAL_DCMI_IRQHandler() + function to:
                                                      • +
                                                        +
                                                      • Add error + management in case DMA + errors through XferAbortCallback() + and HAL_DMA_Abort_IT()
                                                        • +
                                                      • Optimize + code by using direct + register read
                                                        • +
                                                      +
                                                    +
                                                  +
                                                    +
                                                  • HAL - New Roman""> + update
                                                    • +
                                                      +
                                                    • Add new APIs + HAL_DMA_RegisterCallback() + and HAL_DMA_UnRegisterCallback + to register/unregister the + different callbacks identified + by the enum + typedef HAL_DMA_CallbackIDTypeDef
                                                      • +
                                                    • Add new API HAL_DMA_Abort_IT() + to abort DMA transfer under + interrupt context
                                                      • +
                                                        +
                                                      • The new + registered Abort callback is + called when DMA transfer + abortion is completed
                                                        • +
                                                      +
                                                    • Add the check + of compatibility between FIFO + threshold level and size of + the memory burst in the HAL_DMA_Init() + API
                                                      • +
                                                    • Add new Error + Codes: HAL_DMA_ERROR_PARAM, + HAL_DMA_ERROR_NO_XFER and + HAL_DMA_ERROR_NOT_SUPPORTED
                                                      • +
                                                    • Remove all + DMA states related to + MEM0/MEM1 in HAL_DMA_StateTypeDef
                                                      • +
                                                    +
                                                  • HAL - mso-fareast-font-family:"Times + IWDG + update
                                                    • +
                                                      +
                                                    • Overall + rework of the driver for a + more + efficient implementation
                                                      • +
                                                        +
                                                      • Remove the + following APIs:
                                                        • +
                                                          +
                                                        • HAL_IWDG_Start()
                                                          • +
                                                        • HAL_IWDG_MspInit()
                                                          • +
                                                        • HAL_IWDG_GetState()
                                                          • +
                                                        +
                                                      • Update + implementation:
                                                        • +
                                                          +
                                                        • HAL_IWDG_Init(): this + function insures the + configuration and the + start of the IWDG counter
                                                          • +
                                                        • HAL_IWDG_Refresh(): this + function insures the + reload of the IWDG counter
                                                          • +
                                                        +
                                                      • Refer to + the following example to + identify the changes: IWDG_Example
                                                        • +
                                                      +
                                                    +
                                                  • HAL - New Roman"">
                                                    • -
                                                  • + update
                                                    • +
                                                      +
                                                    • Update HAL_LPTIM_TimeOut_Start_IT() + and HAL_LPTIM_Counter_Start_IT( + ) APIs to configure WakeUp + Timer EXTI interrupt to be + able to wakeup + MCU from low power mode by + pressing the EXTI line.
                                                      • +
                                                    • Update HAL_LPTIM_TimeOut_Stop_IT() + and HAL_LPTIM_Counter_Stop_IT( + ) APIs to disable WakeUp + Timer EXTI interrupt. 
                                                      • +
                                                    +
                                                  • HAL + NOR update
                                                    • +
                                                      +
                                                    • Update + NOR_ADDR_SHIFT macro implementation
                                                      • +
                                                    +
                                                  • HAL - mso-fareast-font-family:"Times + PCD update
                                                    • +
                                                      +
                                                    • Update HAL_PCD_IRQHandler() + to get HCLK frequency before + setting TRDT value
                                                      • +
                                                    +
                                                  • HAL - New Roman"">__HAL_ - IRDA _CLEAR_FEFLAG() + update
                                                    • +
                                                  +
                                                    +
                                                      +
                                                    • Update to + manage QSPI error management + during DMA process
                                                      • +
                                                    • Improve the + DMA transmit process by using + QSPI TC interrupt instead of + waiting loop on TC flag under + DMA ISR
                                                      • +
                                                    • These two + improvements require the + following updates on user + application:
                                                      • +
                                                        +
                                                      • Configure + and enable the QSPI IRQ in HAL_QSPI_MspInit() + function
                                                        • +
                                                      • In + stm32f4xx_it.c file, QSPI_IRQHandler() + function: add a call to HAL_QSPI_IRQHandler() - New Roman"">
                                                        • +
                                                      • Add and + customize the Error Callback + API: HAL_QSPI_ErrorCallback()
                                                        • +
                                                      +
                                                    • Add the + management of non-blocking + transfer abort service: HAL_QSPI_Abort_IT(). - mso-fareast-font-family:"Times + In this case the user must:
                                                      • +
                                                        +
                                                      • Add new + callback HAL_QSPI_AbortCpltCallback() + to inform user at the end of + abort process
                                                        • +
                                                      • A new value + of State in the HAL_QSPI_StateTypeDef + provides the current state + during the abort phase
                                                        • +
                                                      +
                                                    • Polling + management update:
                                                      • +
                                                        +
                                                      • The Timeout + value user must be estimated + for the overall process + duration: the + Timeout measurement is + cumulative. 
                                                        • +
                                                      +
                                                    • Refer to the + following examples, which + describe the changes:
                                                      • +
                                                        +
                                                      • QSPI_ReadWrite_DMA
                                                        • +
                                                      • QSPI_MemoryMapped
                                                        • +
                                                      • QSPI_ExecuteInPlace
                                                        • +
                                                      +
                                                    +
                                                  +
                                                    +
                                                      +
                                                    • Add two new + APIs for the QSPI fifo + threshold:
                                                      • +
                                                        +
                                                      • HAL_QSPI_SetFifoThreshold(): + configure the FIFO threshold + of the QSPI
                                                        • +
                                                      • HAL_QSPI_GetFifoThreshold(): give the + current FIFO threshold
                                                        • +
                                                      +
                                                    • Fix wrong + data size management in HAL_QSPI_Receive_DMA()
                                                      • +
                                                    +
                                                  +
                                                    +
                                                  • HAL - New Roman"">
                                                    • -
                                                  • update
                                                    • +
                                                      +
                                                    • Add new + __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() + macro for STM32F42x and + STM32F43x devices to + provide the possibility + to convert VrefInt + channel when both VrefInt + and Vbat + channels are selected.
                                                      • +
                                                    +
                                                  • HAL - mso-fareast-font-family:"Times + SPDIFRX update
                                                    • +
                                                      +
                                                    • Overall driver + update for wait on flag + management optimization 
                                                      • +
                                                    +
                                                  • HAL - New Roman"">__HAL_ - IRDA _CLEAR_NEFLAG() update 
                                                    • +
                                                      +
                                                    • Overall + rework of the driver for more + efficient implementation
                                                      • +
                                                        +
                                                      • Remove the + following APIs:
                                                        • +
                                                          +
                                                        • HAL_WWDG_Start()
                                                          • +
                                                        • HAL_WWDG_Start_IT()
                                                          • +
                                                        • HAL_WWDG_MspDeInit()
                                                          • +
                                                        • HAL_WWDG_GetState()
                                                          • +
                                                        +
                                                      • Update + implementation:
                                                        • +
                                                          +
                                                        • HAL_WWDG_Init()
                                                          • +
                                                            +
                                                          • A new - New Roman""> EWIMode
                                                            • +
                                                          +
                                                        • HAL_WWDG_MspInit()
                                                          • +
                                                        • HAL_WWDG_Refresh() 
                                                          • +
                                                            +
                                                          • This + function insures the + reload of the counter
                                                            • +
                                                          • The + "counter" parameter has + been removed
                                                            • +
                                                          +
                                                        • HAL_WWDG_IRQHandler()
                                                          • +
                                                        • HAL_WWDG_EarlyWakeupCallback() is the + new prototype of HAL_WWDG_WakeUpCallback()
                                                          • +
                                                        +
                                                      +
                                                    • Refer to the + following example to identify + the changes: WWDG_Example
                                                      • +
                                                    +
                                                  +

                                                  V1.4.4 - mso-fareast-font-family:"Times + / 22-January-2016

                                                  +

                                                  Main Changes

                                                  +
                                                    +
                                                  • HAL - New Roman"">
                                                    • -
                                                  • update
                                                    • +
                                                      +
                                                    • stm32f4xx_hal_conf_template.h
                                                      • +
                                                        +
                                                      • Optimize + HSE Startup Timeout value + from 5000ms to 100 ms
                                                        • +
                                                      • Add new + define LSE_STARTUP_TIMEOUT
                                                        • +
                                                      • Add new + define USE_SPI_CRC for code + cleanup when the CRC + calculation is disabled.
                                                        • +
                                                      +
                                                    • Update HAL + drivers to support MISRA C + 2004 rule 10.6
                                                      • +
                                                    • Add new + template driver to + configure timebase + using TIMER :
                                                      • +
                                                        +
                                                      • stm32f4xx_hal_timebase_tim_template.c
                                                        • +
                                                      +
                                                    +
                                                  +
                                                    +
                                                  • HAL + CAN update
                                                    • +
                                                      +
                                                    • Update HAL_CAN_Transmit() + and HAL_CAN_Transmit_IT() - mso-fareast-font-family:"Times - New Roman"">__HAL_ - IRDA _CLEAR_OREFLAG()
                                                      • +
                                                    +
                                                  +
                                                    +
                                                  • HAL - New Roman""> update
                                                    • +
                                                      +
                                                    • Update HAL_DSI_SetPHYTimings() + functions to use the correct + mask
                                                      • +
                                                    +
                                                  • HAL + UART update
                                                    • +
                                                      +
                                                    • Several + update on HAL UART driver to + implement the new UART state + machine: 
                                                      • +
                                                        +
                                                      • Add new + field in UART_HandleTypeDef + structure: "rxState", - mso-fareast-font-family:"Times - New Roman"">
                                                        • -
                                                      • Operations
                                                        • +
                                                      • Rename + "state" field in UART_HandleTypeDef + structure by "gstate": + UART state information + related to global Handle + management and Tx Operations
                                                        • +
                                                      • Update UART + process to manage the new + UART states.
                                                        • +
                                                      • Update + __HAL_UART_RESET_HANDLE_STATE() + macro to handle the new UART + state parameters (gState, + rxState)
                                                        • +
                                                      +
                                                    • Update + UART_BRR_SAMPLING16() and + UART_BRR_SAMPLING8() Macros to + fix wrong baudrate + calculation.
                                                      • +
                                                    +
                                                  +
                                                    +
                                                  • HAL - mso-fareast-font-family:"Times + IRDA update
                                                    • +
                                                      +
                                                    • Several + update on HAL IRDA driver to + implement the new UART state + machine: 
                                                      • +
                                                        +
                                                      • Add new + field in IRDA_HandleTypeDef + structure: "rxState", - New Roman"">__HAL_ - IRDA _CLEAR_IDLEFLAG() Operations
                                                        • +
                                                      • Rename + "state" field in UART_HandleTypeDef + structure by "gstate": + IRDA state information + related to global Handle + management and Tx Operations
                                                        • +
                                                      • Update IRDA + process to manage the new + UART states.
                                                        • +
                                                      • Update + __HAL_IRDA_RESET_HANDLE_STATE() + macro to handle the new IRDA + state parameters (gState, + rxState)
                                                        • +
                                                      +
                                                    • Removal of + IRDA_TIMEOUT_VALUE define
                                                      • +
                                                    • Update IRDA_BRR() + Macro to fix wrong baudrate + calculation
                                                      • +
                                                    +
                                                  • HAL - mso-fareast-font-family:"Times + SMARTCARD update
                                                    • +
                                                      +
                                                    • Several + update on HAL SMARTCARD driver + to implement the new UART + state machine: 
                                                      • +
                                                        +
                                                      • Add new + field in SMARTCARD_HandleTypeDef + structure: "rxState", - New Roman"">
                                                        • -
                                                      -
                                                    • SMARTCARDstate + information related to Rx Operations
                                                      • +
                                                    • Rename + "state" field in UART_HandleTypeDef + structure by "gstate": - mso-fareast-font-family:"Times + SMARTCARDstate + information related to + global Handle management and + Tx Operations
                                                      • +
                                                    • Update SMARTCARD - New Roman"">Add several - enhancements without affecting - the driver functionalities
                                                      • + process to manage the new + UART states. +
                                                    • Update + __HAL_SMARTCARD_RESET_HANDLE_STATE() + macro to handle the + new SMARTCARD state + parameters (gState, + rxState)
                                                      • +
                                                    +
                                                  • Update + SMARTCARD_BRR() + macro to fix wrong baudrate + calculation
                                                    • +
                                                  +
                                                +
                                                  +
                                                • HAL  + RCC + update
                                                  • +
                                                    +
                                                  • Add new + default define value for HSI + calibration + "RCC_HSICALIBRATION_DEFAULT"
                                                    • +
                                                  • Optimize + Internal oscillators and PLL + startup timeout 
                                                    • +
                                                  • Update to + avoid the disable for HSE/LSE + oscillators before setting the + new RCC HSE/LSE configuration + and add the following notes in + HAL_RCC_OscConfig() + API description:
                                                -
                                                  -
                                                    -
                                                      -
                                                    •      +       +     +     +     +       * + @note   Transitions LSE + Bypass to LSE On and LSE On to LSE + Bypass are not
                                                      +                                                           - mso-fareast-font-family:"Times - New Roman"">Remove the - check on RXNE set after - reading the Data in the DR - register
                                                      • -

                                                    • +                                                           + +     +     +     +     +     +      + *         +     first and then LSE + On or LSE Bypass.
                                                      +                                                           - mso-fareast-font-family:"Times - New Roman"">Update HAL_IRDA_Transmit_IT() - to enable IRDA_IT_TXE - instead of IRDA_IT_TC
                                                      +                                                           - New Roman"">
                                                      • -
                                                    -

                                                  • +                                                         - mso-fareast-font-family:"Times +     +     +     +         +      + *         +     first and then HSE + On or HSE Bypass.

                                                    +
                                                      +
                                                        +
                                                      • Optimize + the HAL_RCC_ClockConfig() + API implementation.
                                                        • +
                                                      +
                                                    +
                                                      +
                                                    • HAL - New Roman"">Add the - following APIs used within DMA - process -
                                                      • -
                                                        -
                                                      • update
                                                        • +
                                                          +
                                                        • Update + HAL_DMA2D_Abort() + Function to end current DMA2D + transfer properly
                                                          • +
                                                        • Update + HAL_DMA2D_PollForTransfer() + function to add poll for + background CLUT loading (layer + 0 and layer 1).
                                                          • +
                                                        • Update + HAL_DMA2D_PollForTransfer() + to set the corresponding ErrorCode + in case of error occurrence
                                                          • +
                                                        • Update + HAL_DMA2D_ConfigCLUT() + function to fix wrong CLUT + size and color mode settings
                                                          • +
                                                        • Removal of + useless macro __HAL_DMA2D_DISABLE()
                                                          • +
                                                        • Update + HAL_DMA2D_Suspend() + to manage correctly the case + where no transfer is on going
                                                          • +
                                                        • Update + HAL_DMA2D_Resume() to - New Roman"">HAL_StatusTypeDef
                                                          • +
                                                        • Update + HAL_DMA2D_Start_IT() + to enable all required + interrupts before enabling the + transfer.
                                                          • +
                                                        • Add + HAL_DMA2D_CLUTLoad_IT() + Function to allow loading a + CLUT with interruption model.
                                                          • +
                                                        •  Update + HAL_DMA2D_IRQHandler() + to manage the following + cases :
                                                          +
                                                          +
                                                          • +
                                                            +
                                                          • CLUT + transfer complete
                                                            • +
                                                          • CLUT access + error
                                                            • +
                                                          • Transfer + watermark reached
                                                            • +
                                                          +
                                                        • Add new + Callback APIs:
                                                          • +
                                                            +
                                                          •  HAL_DMA2D_LineEventCallback() + to signal a transfer + watermark reached event
                                                            • +
                                                          •  HAL_DMA2D_CLUTLoadingCpltCallback() + to signal a CLUT loading + complete event
                                                            • +
                                                          +
                                                        +
                                                      +
                                                        +
                                                          +
                                                        • Miscellaneous + Improvement:
                                                          • +
                                                            +
                                                          • Add + "HAL_DMA2D_ERROR_CAE" new + define for CLUT Access error + management.
                                                            • +
                                                          • Add     �assert_param� + used for parameters check is + now done on the top of the + exported functions : before + locking the process using + __HAL_LOCK
                                                            • +
                                                          +
                                                        +
                                                      +

                                                       

                                                      +
                                                        +
                                                      • HAL - mso-fareast-font-family:"Times + I2C update
                                                        • +
                                                          +
                                                        • Add support + of I2C repeated start feature:
                                                          • +
                                                            +
                                                          • With the + following new API's
                                                            • +
                                                              +
                                                            • HAL_I2C_Master_Sequential_Transmit_IT()
                                                              • +
                                                            • HAL_I2C_Master_Sequential_Receive_IT()
                                                              • +
                                                            • HAL_I2C_Master_Abort_IT()
                                                              • +
                                                            • HAL_I2C_Slave_Sequential_Transmit_IT()
                                                              • +
                                                            • HAL_I2C_Slave_Sequential_Receive_IT()
                                                              • +
                                                            • HAL_I2C_EnableListen_IT()
                                                              • +
                                                            • HAL_I2C_DisableListen_IT()
                                                              • +
                                                            +
                                                          • Add new + user callbacks:
                                                            • +
                                                              +
                                                            • HAL_I2C_ListenCpltCallback()
                                                              • +
                                                            • HAL_I2C_AddrCallback()
                                                              • +
                                                            +
                                                          +
                                                        • Update to + generate STOP condition when a + acknowledge failure error is detected
                                                          • +
                                                        • Several + update on HAL I2C driver to + implement the new I2C state + machine: 
                                                          • +
                                                            +
                                                          • Add new API + to get the I2C mode: + HAL_I2C_GetMode()
                                                            • +
                                                          • Update I2C + process to manage the new + I2C states.
                                                            • +
                                                          +
                                                        • Fix wrong behaviour + in single byte transmission 
                                                          • +
                                                        • Update I2C_WaitOnFlagUntilTimeout() to - New Roman""> HAL_IRDA_DMAPause(IRDA_HandleTypeDef - *hirda);
                                                          • +
                                                        • Update  I2C + transmission process to + support the case data size + equal 0
                                                          • +
                                                        +
                                                      +
                                                        +
                                                      • HAL - New Roman""> update
                                                        • +
                                                          +
                                                        • Add support + of FMPI2C repeated start + feature:
                                                          • +
                                                            +
                                                          • With the + following new API's
                                                            • +
                                                              +
                                                            • HAL_FMPI2C_Master_Sequential_Transmit_IT()
                                                              • +
                                                            • HAL_FMPI2C_Master_Sequential_Receive_IT()
                                                              • +
                                                            • HAL_FMPI2C_Master_Abort_IT()
                                                              • +
                                                            • HAL_FMPI2C_Slave_Sequential_Transmit_IT()
                                                              • +
                                                            • HAL_FMPI2C_Slave_Sequential_Receive_IT()
                                                              • +
                                                            • HAL_FMPI2C_EnableListen_IT()
                                                              • +
                                                            • HAL_FMPI2C_DisableListen_IT()
                                                              • +
                                                            +
                                                          • Add new + user callbacks:
                                                            • +
                                                              +
                                                            • HAL_FMPI2C_ListenCpltCallback()
                                                              • +
                                                            • HAL_FMPI2C_AddrCallback()
                                                              • +
                                                            +
                                                          +
                                                        • Several + update on HAL I2C driver to + implement the new I2C state + machine: 
                                                          • +
                                                            +
                                                          • Add new API + to get the FMPI2C mode: + HAL_FMPI2C_GetMode()
                                                            • +
                                                          • Update + FMPI2C process to manage the + new FMPI2C states.
                                                            • +
                                                          +
                                                        +
                                                      +
                                                        +
                                                      • HAL - mso-fareast-font-family:"Times + SPI update
                                                        • +
                                                          +
                                                        • Major Update + to improve performance in + polling/interrupt mode to + reach max frequency:
                                                          • +
                                                            +
                                                          • Polling mode - New Roman"">
                                                            • -
                                                            • +
                                                              +
                                                            • Replace + use of SPI_WaitOnFlagUnitTimeout() + funnction + by "if" statement to check + on RXNE/TXE flage + while transferring data.
                                                              • +
                                                            • Use API + data pointer instead of + SPI handle data pointer.
                                                              • +
                                                            • Use a Goto + implementation instead of + "if..else" + statements.
                                                              • +
                                                            +
                                                          +
                                                        +
                                                      +
                                                        +
                                                          +
                                                            +
                                                          • Interrupt + mode
                                                            • +
                                                              +
                                                            • Minimize + access on SPI registers.
                                                              • +
                                                            • Split the + SPI modes into dedicated + static functions to + minimize checking + statements under HAL_IRQHandler():
                                                              • +
                                                                +
                                                              • 1lines/2lines - New Roman"">HAL_StatusTypeDef
                                                                • +
                                                              • 8 bit/ + 16 bits data formats
                                                                • +
                                                              • CRC + calculation + enabled/disabled.
                                                                • +
                                                              +
                                                            • Remove + waiting loop under ISR + when closing - mso-fareast-font-family:"Times +  the + communication.
                                                              • +
                                                            +
                                                          • All + modes:  
                                                            • +
                                                              +
                                                            • Adding + switch USE_SPI_CRC to + minimize number of + statements when CRC + calculation is disabled.
                                                              • +
                                                            • Update + Timeout management to + check on global process.
                                                              • +
                                                            • Update + Error code management in + all processes.
                                                              • +
                                                            +
                                                          +
                                                        • Add note to + the max frequencies reached in + all modes.
                                                          • +
                                                        • Add note + about Master Receive mode restrictions :
                                                          • +
                                                            +
                                                          • Master - New Roman""> HAL_IRDA_DMAResume(IRDA_HandleTypeDef - *hirda);   + (#) In Master + unidirectional receive-only + mode (MSTR =1, BIDIMODE=0, + RXONLY=0) or
                                                            +           - New Roman"">
                                                            • -
                                                          • HAL_SPI_DeInit()
                                                            +           - New Roman"">HAL_StatusTypeDef                                                            HAL_SPI_Init() +
                                                            • +
                                                          +
                                                        +
                                                      +
                                                        +
                                                      • HAL - mso-fareast-font-family:"Times + SAI update
                                                        • +
                                                          +
                                                        • Update for + proper management of the + external synchronization input + selection
                                                          • +
                                                            +
                                                          • update + of HAL_SAI_Init + () funciton
                                                            • +
                                                          • update + definition of SAI_Block_SyncExt + and SAI_Block_Synchronization + groups
                                                            • +
                                                          +
                                                        • Update + SAI_SLOTACTIVE_X +  defines + values
                                                          • +
                                                        • Update HAL_SAI_Init() + function for proper companding + mode management
                                                          • +
                                                        • Update SAI_Transmit_ITxxBit() + functions to add the check on + transfer counter before + writing new data to SAIx_DR + registers
                                                          • +
                                                        • Update SAI_FillFifo() + function to avoid issue when + the number of data to transmit + is smaller than the FIFO size
                                                          • +
                                                        • Update HAL_SAI_EnableRxMuteMode() + function for proper mute + management
                                                          • +
                                                        • Update SAI_InitPCM() + function to support 24bits + configuration
                                                          • +
                                                        +
                                                      • HAL - New Roman""> HAL_IRDA_DMAStop(IRDA_HandleTypeDef - *hirda); -
                                                        • -
                                                      • update
                                                        • +
                                                          +
                                                        • Removal of + ETH MAC debug register defines
                                                          • +
                                                        +
                                                      • HAL - mso-fareast-font-family:"Times + FLASH update
                                                        • +
                                                          +
                                                        • Update FLASH_MassErase() + function to apply correctly + voltage range parameter
                                                          • +
                                                        +
                                                      • HAL - New Roman"">void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef - *hirda);update
                                                        • +
                                                          +
                                                        • Update I2S_DMATxCplt() + and I2S_DMARxCplt() to manage + properly FullDuplex + mode without any risk of + missing data.
                                                          • +
                                                        +
                                                      • LL - New Roman""> update
                                                        • +
                                                          +
                                                        • Update the FMC_NORSRAM_Init() + function to use BurstAccessMode + field properly
                                                          • +
                                                        +
                                                      • LL - mso-fareast-font-family:"Times + FSMC  - New Roman"">
                                                        • -
                                                      • update
                                                        • +
                                                          +
                                                        • Update the FSMC_NORSRAM_Init() + function to use BurstAccessMode + field properly
                                                          • +
                                                        +
                                                      +


                                                      +
                                                      +

                                                      +

                                                      V1.4.4 + / 11-December-2015

                                                      +

                                                      Main Changes

                                                      +
                                                        +
                                                      • HAL + Generic update
                                                        • +
                                                          +
                                                        • Update HAL + weak empty callbacks to + prevent unused argument + compilation warnings with some + compilers by calling the + following line:
                                                          • +
                                                            +
                                                          • UNUSED(hppp);
                                                            • +
                                                          +
                                                        • STM32Fxxx_User_Manual.chm - mso-fareast-font-family:"Times - New Roman"">void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef - *hirda);
                                                          • +
                                                        +
                                                      • HAL - New Roman"">
                                                        • -
                                                      + ETH update  +
                                                        +
                                                      • Update HAL_ETH_Init() + function to add timeout on the + Software reset management
                                                    -

                                                    �  +

                                                    V1.4.2 + / 10-November-2015

                                                    +

                                                    Main Changes

                                                    +
                                                      +
                                                    • General - HAL SMARTCARD - update

                                                      -
                                                        -
                                                          -
                                                        • implementation
                                                          • +
                                                        • One - mso-fareast-font-family:"Times + change done on the HAL CRYP + requires an update on the + application code based on HAL + V1.4.1
                                                          • +
                                                            +
                                                          • Update HAL_CRYP_DESECB_Decrypt() + API to invert pPlainData + and pCypherData + parameters
                                                            • +
                                                          +
                                                        • HAL - New Roman"">Add specific - macros to manage the flags - cleared only by a software sequence + update
                                                          • +
                                                            +
                                                          • Update HAL + weak empty callbacks to + prevent unused argument + compilation warnings with some + compilers by calling the + following line:
                                                            • +
                                                              +
                                                            • UNUSED(hppp);
                                                              • +
                                                            +
                                                          +
                                                        +
                                                          +
                                                        • HAL - New Roman"">
                                                          • -
                                                            -
                                                          • update
                                                            • +
                                                              +
                                                            • Remove + duplication for + __HAL_CORTEX_SYSTICKCLK_CONFIG() + macro
                                                              • +
                                                            +
                                                          +
                                                            +
                                                          • HAL - mso-fareast-font-family:"Times + HASH update
                                                            • +
                                                              +
                                                            • Rename HAL_HASH_STATETypeDef + to HAL_HASH_StateTypeDef
                                                              • +
                                                            • Rename HAL_HASH_PhaseTypeDef + to HAL_HASH_PhaseTypeDef
                                                              • +
                                                            +
                                                          • HAL - New Roman"">__HAL_SMARTCARD_CLEAR_PEFLAG()update
                                                            • +
                                                              +
                                                            • Add new + macros __HAL_RCC_PPP_IS_CLK_ENABLED() + to check on Clock + enable/disable status
                                                              • +
                                                            • Update + __HAL_RCC_USB_OTG_FS_CLK_DISABLE() + macro to remove the disable + for the SYSCFG
                                                              • +
                                                            • Update HAL_RCC_MCOConfig() + API to use new defines for the + GPIO Speed
                                                              • +
                                                            • Generic + update to improve the + PLL VCO min + value(100MHz): PLLN, PLLI2S + and PLLSAI min value is 50 + instead of 192
                                                              • +
                                                            +
                                                          • HAL - New Roman""> update
                                                            • +
                                                              +
                                                            • __HAL_FLASH_INSTRUCTION_CACHE_RESET() + macro: update to reset +  ICRST bit in + the ACR register after + setting it.
                                                              • +
                                                            • Update to + support until 15 FLASH wait + state (FLASH_LATENCY_15) for + STM32F446xx devices +
                                                              • +
                                                            +
                                                          +

                                                          �  - mso-fareast-font-family:"Times + HAL CRYP update

                                                          +
                                                            +
                                                              +
                                                            • Update HAL_CRYP_DESECB_Decrypt() + API to fix the inverted pPlainData + and pCypherData + parameters issue
                                                              • +
                                                            +
                                                          • HAL - New Roman"">
                                                            • -
                                                          • update
                                                            • +
                                                              +
                                                            • Update + HAL_I2S_Init() + API to call + __HAL_RCC_I2S_CONFIG() macro + when external I2S clock is + selected
                                                              • +
                                                            +
                                                          • HAL + LTDC update
                                                            • +
                                                              +
                                                            • Update HAL_LTDC_SetWindowPosition() + API to configure + Immediate reload register + instead of vertical blanking + reload register.
                                                              • +
                                                            +
                                                          • HAL - mso-fareast-font-family:"Times + TIM update
                                                            • +
                                                              +
                                                            • Update HAL_TIM_ConfigClockSource() + API to check only the + required parameters
                                                              • +
                                                            +
                                                          • HAL - New Roman"">__HAL_SMARTCARD_CLEAR_FEFLAG()update
                                                            • +
                                                              +
                                                            • Update + HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() + APIs to manage correctly the + NAND Page access
                                                              • +
                                                            +
                                                          • HAL - New Roman""> update
                                                            • +
                                                              +
                                                            • Update to use + "=" instead of "|=" to clear + flags in the MSR, TSR, RF0R + and RF1R registers
                                                              • +
                                                            +
                                                          • HAL - mso-fareast-font-family:"Times + HCD update
                                                            • +
                                                              +
                                                            • Fix typo in + __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() + macro implementation
                                                              • +
                                                            +
                                                          • HAL - New Roman"">
                                                            • -
                                                          • update
                                                            • +
                                                              +
                                                            • Update HAL_PCD_IRQHandler() + API to avoid issue + when DMA mode enabled for + Status Phase IN stage
                                                              • +
                                                            +
                                                          • LL - mso-fareast-font-family:"Times + FMC update
                                                            • +
                                                              +
                                                            • Update the FMC_NORSRAM_Extended_Timing_Init() + API to remove the check + on CLKDIvison + and DataLatency + parameters
                                                              • +
                                                            • Update the FMC_NORSRAM_Init() + API to add a check on the PageSize + parameter for STM32F42/43xx + devices
                                                              • +
                                                            +
                                                          • LL - New Roman"">__HAL_SMARTCARD_CLEAR_NEFLAG()update
                                                            • +
                                                              +
                                                            • Update the FSMC_NORSRAM_Extended_Timing_Init() + API to remove the check + on CLKDIvison + and DataLatency + parameters
                                                              • +
                                                            +
                                                          +

                                                          V1.4.1 - New Roman"">

                                                          +

                                                          Main Changes

                                                          +
                                                            +
                                                          • HAL + DSI update
                                                            • +
                                                              +
                                                            • Update TCCR + register assigned value + in HAL_DSI_ConfigHostTimeouts() + function
                                                              • +
                                                            • Update WPCR + register assigned value + in HAL_DSI_Init(), - mso-fareast-font-family:"Times - New Roman"">
                                                              • -
                                                            • HAL_DSI_SetSlewRateAndDelayTuning(), - mso-fareast-font-family:"Times + HAL_DSI_SetSlewRateAndDelayTuning(), - New Roman"">__HAL_SMARTCARD_CLEAR_OREFLAG()HAL_DSI_SetLowPowerRXFilter() - New Roman""> HAL_DSI_SetSDD(), - mso-fareast-font-family:"Times + HAL_DSI_SetLanePinsConfiguration(), - New Roman"">
                                                              • -
                                                            • HAL_DSI_SetPHYTimings(), - mso-fareast-font-family:"Times - New Roman"">__HAL_SMARTCARD_CLEAR_IDLEFLAG()HAL_DSI_ForceTXStopMode(), - New Roman""> HAL_DSI_ForceRXLowPower(), - mso-fareast-font-family:"Times + HAL_DSI_ForceDataLanesInRX(), - New Roman"">
                                                              • -
                                                            -
                                                          • HAL_DSI_SetPullDown() - mso-fareast-font-family:"Times + and HAL_DSI_SetContentionDetectionOff() - New Roman"">Add several - enhancements without affecting - the driver functionalities
                                                            • -
                                                              -
                                                              • +
                                                            • Update + DSI_HS_PM_ENABLE define value
                                                              • +
                                                            • Implement + workaround for the hardware + limitation: �The time to + activate the clock between HS + transmissions is not + calculated correctly�
                                                              • +
                                                            +
                                                          +

                                                          V1.4.0 + / 14-August-2015

                                                          +

                                                          Main Changes

                                                          +
                                                            +
                                                          • Add + support of STM32F469xx, STM32F479xx, + STM32F410Cx, STM32F410Rx + and STM32F410Tx  + devices
                                                            • +
                                                          • General - mso-fareast-font-family:"Times + updates to fix known defects and + enhancements implementation
                                                            • +
                                                          • Add + new HAL drivers for DSI and LPTIM - New Roman"">Add a new - state HAL_SMARTCARD_STATE_BUSY_TX_RX - and all processes has been - updated accordingly
                                                            • -
                                                            • +
                                                          +
                                                            +
                                                          • HAL - level3 lfo135;tab-stops: list - 1.5in">update
                                                            • +
                                                              +
                                                            • Rename + ADC_CLOCKPRESCALER_PCLK_DIV2 + define to + ADC_CLOCK_SYNC_PCLK_DIV2
                                                              • +
                                                            • Rename + ADC_CLOCKPRESCALER_PCLK_DIV4 + define to + ADC_CLOCK_SYNC_PCLK_DIV4
                                                              • +
                                                            • Rename + ADC_CLOCKPRESCALER_PCLK_DIV6 + define to + ADC_CLOCK_SYNC_PCLK_DIV6
                                                              • +
                                                            • Rename + ADC_CLOCKPRESCALER_PCLK_DIV8 + define to + ADC_CLOCK_SYNC_PCLK_DIV8
                                                              • +
                                                            +
                                                          • HAL - New Roman"">Update HAL_SMARTCARD_Transmit_IT() - to enable SMARTCARD_IT_TXE - instead of SMARTCARD_IT_TCupdate
                                                            • +
                                                              +
                                                            • Add specific + API for MPU management
                                                              • +
                                                                +
                                                              • add MPU_Region_InitTypeDef + structure
                                                                • +
                                                              • add new + function HAL_MPU_ConfigRegion()
                                                                • +
                                                              +
                                                            +
                                                          • HAL - New Roman"">
                                                            • + DMA update +
                                                              +
                                                            • Overall driver + update for code optimization
                                                              • +
                                                                +
                                                              • add StreamBaseAddress + and StreamIndex + new fields in the DMA_HandleTypeDef + structure
                                                                • +
                                                              • add DMA_Base_Registers + private structure
                                                                • +
                                                              • add static + function DMA_CalcBaseAndBitshift()
                                                                • +
                                                              • update HAL_DMA_Init() + function to use the new + added static function
                                                                • +
                                                              • update HAL_DMA_DeInit() + function to optimize clear + flag operations
                                                                • +
                                                              • update HAL_DMA_Start_IT() + function to optimize + interrupts enable
                                                                • +
                                                              • update HAL_DMA_PollForTransfer() + function to optimize check + on flags
                                                                • +
                                                              • update HAL_DMA_IRQHandler() + function to optimize + interrupt flag management
                                                            -
                                                          -
                                                            -
                                                          • HAL + FLASH update
                                                            • +
                                                              +
                                                            • update HAL_FLASH_Program_IT() + function by removing the + pending flag clear
                                                              • +
                                                            • update HAL_FLASH_IRQHandler() + function to improve erase + operation procedure
                                                              • +
                                                            • update FLASH_WaitForLastOperation() + function by checking on end of + operation flag
                                                              • +
                                                            +
                                                          • HAL - "Times New Roman"">HAL + GPIO update
                                                            • +
                                                              +
                                                            • Rename + GPIO_SPEED_LOW define to + GPIO_SPEED_FREQ_LOW
                                                              • +
                                                            • Rename + GPIO_SPEED_MEDIUM define to + GPIO_SPEED_FREQ_MEDIUM
                                                              • +
                                                            • Rename + GPIO_SPEED_FAST define to + GPIO_SPEED_FREQ_HIGH
                                                              • +
                                                            • Rename + GPIO_SPEED_HIGH define to + GPIO_SPEED_FREQ_VERY_HIGH
                                                              • +
                                                            +
                                                          • HAL - SPIupdate
                                                            • +
                                                              +
                                                            • Move + I2S_Clock_Source defines to + extension file to properly add + the support of STM32F410xx devices
                                                              • +
                                                            +
                                                          • HAL - New Roman""> updateupdate
                                                            • +
                                                              +
                                                            • rename HAL_LTDC_LineEvenCallback() + function to HAL_LTDC_LineEventCallback()
                                                              • +
                                                            • add new + function HAL_LTDC_SetPitch()
                                                              • +
                                                            • add new + functions HAL_LTDC_StructInitFromVideoConfig() + and HAL_LTDC_StructInitFromAdaptedCommandConfig() - New Roman"">
                                                              • +
                                                            +
                                                          • HAL - mso-fareast-font-family:"Times + PWR update
                                                            • +
                                                              +
                                                            • move + __HAL_PWR_VOLTAGESCALING_CONFIG() + macro to extension file
                                                              • +
                                                            • move + PWR_WAKEUP_PIN2 define to + extension file
                                                              • +
                                                            • add + PWR_WAKEUP_PIN3 define, + applicable only to STM32F10xx + devices
                                                              • +
                                                            • add new + functions HAL_PWREx_EnableWakeUpPinPolarityRisingEdge() + and HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(), - New Roman"">
                                                              • -
                                                                -
                                                                • +
                                                              +
                                                            +
                                                              +
                                                            • HAL - mso-fareast-font-family:"Times + RTC update
                                                              • +
                                                                +
                                                              • Update HAL_RTCEx_SetWakeUpTimer() + and HAL_RTCEx_SetWakeUpTimer_IT() - New Roman"">Bugs fix
                                                                • -
                                                                  -
                                                                  • +
                                                                +
                                                              • HAL + TIM update
                                                                • +
                                                                  +
                                                                • add new + defines TIM_SYSTEMBREAKINPUT_HARDFAULT,  - mso-fareast-font-family:"Times + TIM_SYSTEMBREAKINPUT_PVD - New Roman"">SPI - interface is used in - synchronous polling mode: at - high clock rates like SPI prescaler - 2 and 4, calling
                                                                  - HAL_SPI_TransmitReceive() - returns with error - HAL_TIMEOUT                                                                   -
                                                                  • -
                                                                • HAL_SPI_TransmitReceive_
                                                                  • +
                                                                +
                                                              +

                                                              V1.3.2 - New Roman"">DMA(

                                                              +

                                                              Main Changes

                                                              +
                                                                +
                                                              • General + updates to fix known defects and + enhancements implementation
                                                                • +
                                                              • One - mso-fareast-font-family:"Times + changes + done on the HAL may require an + update on the application code + based on HAL V1.3.1
                                                                • +
                                                                  +
                                                                • HASH IT + process: update to call the HAL_HASH_InCpltCallback() + at the end of the complete + buffer instead of every each + 512 bits
                                                                  • +
                                                                +
                                                              +
                                                                +
                                                              • HAL - New Roman"">)update
                                                                • +
                                                                  +
                                                                • HAL_RCCEx_PeriphCLKConfig() updates:
                                                                  • +
                                                                    +
                                                                  • Update the + LSE check condition after + backup domain reset: + update to check LSE + ready flag when LSE + oscillator is already + enabled instead of check on + LSE oscillator only when LSE + is used as RTC clock source
                                                                    • +
                                                                  • Use the + right macro to check the + PLLI2SQ parameters +
                                                                    • +
                                                                  +
                                                                +
                                                              +
                                                                +
                                                              • HAL - mso-fareast-font-family:"Times + RTC update
                                                                • +
                                                                  +
                                                                • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() + macro: fix implementation + issue
                                                                  • +
                                                                • __HAL_RTC_ALARM_GET_IT(), - New Roman""> does not - clean up the TX DMA, so any - subsequent SPI calls return - the DMA error
                                                                  • -
                                                                • HAL_SPI_Transmit_DMA(
                                                                  • +
                                                                • IS_RTC_TAMPER() + macro: update to use literal + instead of hardcoded + value 
                                                                  • +
                                                                • Add new + parameter SecondFraction + in RTC_TimeTypeDef + structure
                                                                  • +
                                                                • HAL_RTC_GetTime() API update + to support the new + parameter SecondFraction +
                                                                  • +
                                                                +
                                                              • HAL - mso-fareast-font-family:"Times + ADC update
                                                                • +
                                                                  +
                                                                • Add new + literal: + ADC_INJECTED_SOFTWARE_START to + be used as possible value for + the ExternalTrigInjecConvEdge + parameter in the ADC_InitTypeDef + structure to select the ADC + software trigger mode.
                                                                  • +
                                                                +
                                                              • HAL - New Roman"">)update
                                                                • +
                                                                  +
                                                                • FLASH_OB_GetRDP() API update + to return uint8_t instead of FlagStatus
                                                                  • +
                                                                •  __HAL_FLASH_GET_LATENCY() + new macro add to get the flash + latency
                                                                  • +
                                                                +
                                                              • HAL - mso-fareast-font-family:"Times + SPI update
                                                                • +
                                                                  +
                                                                • Fix the wrong + definition of + HAL_SPI_ERROR_FLAG literal
                                                                  • +
                                                                +
                                                              • HAL - New Roman""> is failing - when data size is equal to 1 - byte -
                                                                • -
                                                              -
                                                            • update
                                                              • +
                                                                +
                                                              • HAL_I2S_Transmit() + API update to check on busy + flag only for I2S slave mode
                                                                • +
                                                              +
                                                            • HAL - mso-fareast-font-family:"Times + CRC update
                                                              • +
                                                                +
                                                              • __HAL_CRC_SET_IDR() + macro implementation change to + use WRITE_REG() instead of + MODIFY_REG()
                                                                • +
                                                              +
                                                            • HAL - New Roman"">Add the - following APIs used within the - DMA processupdate
                                                              • +
                                                                +
                                                              • HAL_DMA2D_ConfigLayer() + API update to use "=" instead + of "|=" to erase BGCOLR and + FGCOLR registers before + setting the new configuration
                                                                • +
                                                              +
                                                            • HAL - New Roman""> update
                                                              • +
                                                                +
                                                              • HAL_HASH_MODE_Start_IT() (MODE + stands for MD5, SHA1, + SHA224 and SHA36) updates:
                                                                • +
                                                                  +
                                                                • Fix processing - mso-fareast-font-family:"Times - New Roman"">
                                                                  • + fail for small input buffers +
                                                                • Update to + unlock the process and + call return + HAL_OK at the end of + HASH processing to avoid + incorrectly repeating software
                                                                  • +
                                                                • Update to + properly manage the HashITCounter
                                                                  • +
                                                                • Update to + call the HAL_HASH_InCpltCallback() + at the end of the complete + buffer instead of every each + 512 bits
                                                                  • +
                                                                +
                                                              • __HAL_HASH_GET_FLAG() + update to  check the + right register when the DINNE + flag  is selected
                                                                • +
                                                              • HAL_HASH_SHA1_Accumulate() + updates:
                                                                • +
                                                                  +
                                                                • Add + a call to the new + IS_HASH_SHA1_BUFFER_SIZE() + macro to check the size + parameter. 
                                                                  • +
                                                                • Add the + following note in API description
                                                                  • +
                                                            -
                                                              -
                                                                -
                                                                  -
                                                                • HAL_StatusTypeDef +

                                                                   * - mso-fareast-font-family:"Times + @note  - New Roman""> HAL_SPI_DMAPause(SPI_HandleTypeDef - *hspi);

                                                                  • -
                                                                • HAL_StatusTypeDef

                                                                  + +
                                                                    +
                                                                  • HAL + RTC update
                                                                    • +
                                                                      +
                                                                    • Update to + define hardware + independent literals names:
                                                                      • +
                                                                        +
                                                                      • Rename + RTC_TAMPERPIN_PC13 by - mso-fareast-font-family:"Times +  RTC_TAMPERPIN_DEFAULT
                                                                        • +
                                                                      • Rename + RTC_TAMPERPIN_PA0 by + RTC_TAMPERPIN_POS1
                                                                        • +
                                                                      • Rename + RTC_TAMPERPIN_PI8 by + RTC_TAMPERPIN_POS1
                                                                        • +
                                                                      • Rename + RTC_TIMESTAMPPIN_PC13 by + RTC_TIMESTAMPPIN_DEFAULT
                                                                        • +
                                                                      • Rename + RTC_TIMESTAMPPIN_PA0 by + RTC_TIMESTAMPPIN_POS1
                                                                        • +
                                                                      • Rename + RTC_TIMESTAMPPIN_PI8 by + RTC_TIMESTAMPPIN_POS1
                                                                        • +
                                                                      +
                                                                    +
                                                                  • HAL - New Roman""> HAL_SPI_DMAResume(SPI_HandleTypeDef - *hspi);
                                                                    • -
                                                                  • update
                                                                    • +
                                                                      +
                                                                    • Remove + duplicated IS_ETH_DUPLEX_MODE() + and IS_ETH_RX_MODE() macros
                                                                      • +
                                                                    • Remove + illegal space + ETH_MAC_READCONTROLLER_FLUSHING + macro
                                                                      • +
                                                                    • Update + ETH_MAC_READCONTROLLER_XXX + defined values (XXX can be + IDLE, READING_DATA and + READING_STATUS)
                                                                      • +
                                                                    +
                                                                  • HAL - New Roman"">HAL_StatusTypeDefupdate
                                                                    • +
                                                                      +
                                                                    • HAL_PCD_IRQHandler API: fix the + bad Configuration of + Turnaround Time
                                                                      • +
                                                                    +
                                                                  • HAL - mso-fareast-font-family:"Times + HCD update
                                                                    • +
                                                                      +
                                                                    • Update to use + local variable in USB + Host channel re-activation
                                                                      • +
                                                                    +
                                                                  • LL - New Roman""> HAL_SPI_DMAStop(SPI_HandleTypeDef - *hspi);
                                                                    • -
                                                                  • update
                                                                    • +
                                                                      +
                                                                    • FMC_SDRAM_SendCommand() API: remove + the following line: return + HAL_ERROR;
                                                                      • +
                                                                    +
                                                                  • LL - mso-fareast-font-family:"Times + USB update
                                                                    • +
                                                                      +
                                                                    • USB_FlushTxFifo API: + update to flush all Tx FIFO
                                                                      • +
                                                                    • Update to use + local variable in USB + Host channel re-activation
                                                                      • +
                                                                    +
                                                                  +

                                                                  V1.3.1 - New Roman"">void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef - *hspi);

                                                                  • -
                                                                • +

                                                                  Main Changes

                                                                  +
                                                                    +
                                                                  • HAL + PWR update
                                                                    • +
                                                                      +
                                                                    • Fix + compilation issue with + STM32F417xx product: + update STM32F17xx + by STM32F417xx
                                                                      • +
                                                                    +
                                                                  • HAL - mso-fareast-font-family:"Times + SPI update
                                                                    • +
                                                                      +
                                                                    • Remove unused + variable to avoid warning with + TrueSTUDIO 
                                                                      • +
                                                                    +
                                                                  • HAL - New Roman"">void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef - *hspi);
                                                                    • -
                                                                  • update
                                                                    • +
                                                                      +
                                                                    • I2C + Polling/IT/DMA processes: move + the wait loop on busy + flag at the top of the + processes, to ensure that + software not perform any write + access to I2C_CR1 register + before hardware + clearing STOP bit and to + avoid - mso-fareast-font-family:"Times + also the + waiting loop on BUSY flag + under I2C/DMA ISR.
                                                                      • +
                                                                    • Update busy + flag Timeout value
                                                                      • +
                                                                    • I2C Master + Receive Processes update to + disable ACK before generate + the STOP 
                                                                      • +
                                                                    +
                                                                  • HAL - New Roman"">void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef - *hspi);update
                                                                    • +
                                                                      +
                                                                    • Fix V1.3.0 + regression issue with DAC + software trigger configuration
                                                                      • +
                                                                    +
                                                                  +

                                                                  V1.3.0 - mso-fareast-font-family:"Times + / 09-Mars-2015

                                                                  +

                                                                  Main Changes

                                                                  +
                                                                    +
                                                                  • Add + support of STM32F446xx devices
                                                                    • +
                                                                  • General - New Roman"">
                                                                    • -
                                                                  -
                                                                -
                                                              -
                                                                -
                                                              • implementation
                                                                • +
                                                              • Add + new HAL drivers for CEC, + QSPI, FMPI2C and SPDIFRX - "Times New Roman"">HAL + peripherals
                                                                • +
                                                              • Two - RNG
                                                                • +
                                                                  +
                                                                • Overall SAI + driver rework to have + exhaustive support of the + peripheral features: details + are provided in HAL SAI update - New Roman"">update
                                                                  • -
                                                                    -
                                                                      -
                                                                    • impacted
                                                                      • +
                                                                    • CRYP driver + updated to support multi instance,so + user must ensure that the + new parameter Instance is + initalized + in his application(CRYPHandle.Instance + = CRYP) 
                                                                      • +
                                                                    +
                                                                  +
                                                                    +
                                                                  • HAL - mso-fareast-font-family:"Times + Generic update
                                                                    • +
                                                                      +
                                                                    • stm32f4xx_hal_def.h
                                                                      • +
                                                                        +
                                                                      • Remove NULL + definition and add + include for stdio.h
                                                                        • +
                                                                      +
                                                                    • stm32_hal_legacy.h
                                                                      • +
                                                                        +
                                                                      • Update method - New Roman"">Add a - conditional define to make - this driver visible for all - STM32F4xx devices except - STM32F401xx and STM32F411xx - Devices.
                                                                        • + to manage deference in + alias implementation between + all STM32 families +
                                                                      +
                                                                    • stm32f4xx_hal_ppp.c
                                                                      • +
                                                                        +
                                                                      • HAL_PPP_Init(): update + to force the + HAL_PPP_STATE_RESET before + calling the HAL_PPP_MspInit()
                                                                    -
                                                                  • +
                                                                  • HAL - "Times New Roman"">HAL + RCC update
                                                                    • +
                                                                      +
                                                                    • Add new + function HAL_RCCEx_GetPeriphCLKFreq()
                                                                      • +
                                                                    • Move RCC_PLLInitTypeDef + structure to extension file + and add the new PLLR field + specific to STM32F446xx devices
                                                                      • +
                                                                    • Move the + following functions to + extension file and add a + __weak attribute in generic driver - CRC +
                                                                    • HAL_RCC_OscConfig()
                                                                      • +
                                                                    • HAL_RCC_GetSysClockFreq()
                                                                      • +
                                                                    • HAL_RCC_GetOscConfig()
                                                                      • +
                                                                    +
                                                                  • Move the + following macro to extension + file as they have device + dependent implementation
                                                                    • +
                                                                      +
                                                                    • __HAL_RCC_PLL_CONFIG()
                                                                      • +
                                                                    • __HAL_RCC_PLLI2S_CONFIG()
                                                                      • +
                                                                    • __HAL_RCC_I2S_CONFIG()
                                                                      • +
                                                                    +
                                                                  • Add new + structure RCC_PLLI2SInitTypeDef + containing new PLLI2S + division factors used only w/ + STM32F446xx devices
                                                                    • +
                                                                  • Add new + structure RCC_PLLSAIInitTypeDef + containing new PLLSAI + division factors used only w/ + STM32F446xx devices
                                                                    • +
                                                                  • Add new RCC_PeriphCLKInitTypeDef + to support the peripheral + source clock selection for (I2S, - New Roman"">updateUpdate the HAL_RCCEx_PeriphCLKConfig() + and HAL_RCCEx_GetPeriphCLKConfig() - New Roman"">
                                                                    • -
                                                                      -
                                                                        -
                                                                      • Add __HAL_RCC_PLL_CONFIG() + macro (the number of parameter + and the implementation depend + on the device part number)
                                                                        • +
                                                                      • Add __HAL_RCC_PLLI2S_CONFIG() + macro(the number of parameter + and the implementation depend + on device part number)
                                                                        • +
                                                                      • Update __HAL_RCC_PLLSAI_CONFIG() + macro to support new PLLSAI + factors (PLLSAIM and + PLLSAIP)
                                                                        • +
                                                                      • Add new + macros for clock + enable/Disable for the + following peripherals (CEC, - mso-fareast-font-family:"Times + SPDIFRX, SAI2, QUADSPI)
                                                                        • +
                                                                      • Add the + following new macros for clock + source selection - New Roman"">These - macros are added to - read/write the CRC IDR - register: __HAL_CRC_SET_IDR() - and __HAL_CRC_GET_IDR()
                                                                        • + : +
                                                                          +
                                                                        • __HAL_RCC_SAI1_CONFIG() + / + __HAL_RCC_GET_SAI1_SOURCE()
                                                                          • +
                                                                        • __HAL_RCC_SAI2_CONFIG() + / + __HAL_RCC_GET_SAI2_SOURCE()
                                                                          • +
                                                                        • __HAL_RCC_I2S1_CONFIG() + / + __HAL_RCC_GET_I2S1_SOURCE()
                                                                          • +
                                                                        • __HAL_RCC_I2S2_CONFIG() + / + __HAL_RCC_GET_I2S2_SOURCE()
                                                                          • +
                                                                        • __HAL_RCC_CEC_CONFIG() + / + __HAL_RCC__GET_CEC_SOURCE() +
                                                                          • +
                                                                        • __HAL_RCC_FMPI2C1_CONFIG() + / + __HAL_RCC_GET_FMPI2C1_SOURCE() +
                                                                          • +
                                                                        • __HAL_RCC_SDIO_CONFIG() + / + __HAL_RCC_GET_SDIO_SOURCE() +
                                                                          • +
                                                                        • __HAL_RCC_CLK48_CONFIG() + / + __HAL_RCC_GET_CLK48_SOURCE() +
                                                                          • +
                                                                        • __HAL_RCC_SPDIFRXCLK_CONFIG() + / + __HAL_RCC_GET_SPDIFRX_SOURCE()
                                                                        -
                                                                      -
                                                                    -
                                                                      -
                                                                    • __HAL_RCC_PPP_CLK_ENABLE(): - "Times New Roman"">HAL + Implement workaround to cover + RCC limitation regarding + peripheral enable delay
                                                                      • +
                                                                    • HAL_RCC_OscConfig() fix + issues: 
                                                                      • +
                                                                        +
                                                                      • Add a check + on LSERDY flag when + LSE_BYPASS is selected as + new state for LSE + oscillator.
                                                                        • +
                                                                      +
                                                                    • Add + new possible value RCC_PERIPHCLK_PLLI2S + + to be selected as PeriphClockSelection + parameter in the - DAC update
                                                                      • -
                                                                        -
                                                                      • RCC_PeriphCLKInitTypeDef + structure to allow the + possibility to output the + PLLI2S on MCO without + activating the I2S or the SAI.
                                                                        • +
                                                                      • __HAL_RCC_HSE_CONFIG() +  macro: add + the comment below:
                                                                        • +
                                                                      +
                                                                    +
                                                                    +

                                                                     * - mso-fareast-font-family:"Times + @note   Transition + HSE Bypass to HSE On and HSE + On to HSE Bypass are not + supported by this macro.
                                                                    +  *         - New Roman"">Enhance the - DMA channel configuration when - used with DAC                                                                     + User should request a + transition to HSE Off first + and then HSE On or HSE Bypass.

                                                                    +
                                                                    +
                                                                      +
                                                                        +
                                                                      • __HAL_RCC_LSE_CONFIG()  macro: add + the comment below:
                                                                      -
                                                                    • +

                                                                        * + + + + + @note   Transition + LSE Bypass to LSE On and LSE + On to LSE Bypass are not + supported by this macro.
                                                                      +   + *         + User should request a + transition to LSE Off first + and then LSE On or LSE Bypass.

                                                                      + +
                                                                        +
                                                                          +
                                                                        • Add the + following new macros for + PLL source and PLLM selection + :
                                                                          • +
                                                                            +
                                                                          • __HAL_RCC_PLL_PLLSOURCE_CONFIG()
                                                                            • +
                                                                          • __HAL_RCC_PLL_PLLM_CONFIG()
                                                                            • +
                                                                          +
                                                                        • Macros + rename:
                                                                          • +
                                                                            +
                                                                          • HAL_RCC_OTGHS_FORCE_RESET() +by HAL_RCC_USB_OTG_HS_FORCE_RESET()
                                                                            • +
                                                                          • HAL_RCC_OTGHS_RELEASE_RESET() +by HAL_RCC_USB_OTG_HS_RELEASE_RESET()
                                                                            • +
                                                                          • HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() +by HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()
                                                                            • +
                                                                          • HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() +by HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()
                                                                            • +
                                                                          • HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() +by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
                                                                            • +
                                                                          • HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() +by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
                                                                            • +
                                                                          +
                                                                        • Add __HAL_RCC_SYSCLK_CONFIG() + new macro to configure the + system clock source (SYSCLK)
                                                                          • +
                                                                        • __HAL_RCC_GET_SYSCLK_SOURCE() + updates:
                                                                          • +
                                                                            +
                                                                          • Add new RCC + Literals:
                                                                            • +
                                                                              +
                                                                            • RCC_SYSCLKSOURCE_STATUS_HSI
                                                                              • +
                                                                            • RCC_SYSCLKSOURCE_STATUS_HSE
                                                                              • +
                                                                            • RCC_SYSCLKSOURCE_STATUS_PLLCLK
                                                                              • +
                                                                            • RCC_SYSCLKSOURCE_STATUS_PLLRCLK
                                                                              • +
                                                                            +
                                                                          •  Update - "Times New Roman"">HAL + macro description to refer + to the literals above +
                                                                            • +
                                                                          +
                                                                        +
                                                                      • HAL - TIM update
                                                                        • +
                                                                          +
                                                                        • Add new + define PWR_WAKEUP_PIN2
                                                                          • +
                                                                        • Add new API + to Control/Get VOS bits + of CR register
                                                                          • +
                                                                            +
                                                                          • HAL_PWR_HAL_PWREx_ControlVoltageScaling()
                                                                            • +
                                                                          • HAL_PWREx_GetVoltageRange()
                                                                            • +
                                                                          +
                                                                        • __HAL_PWR_ + VOLTAGESCALING_CONFIG(): Implement + workaround to cover VOS + limitation delay when PLL is + enabled after setting the VOS + configuration
                                                                          • +
                                                                        +
                                                                      • HAL - New Roman"">updateupdate
                                                                        • +
                                                                          +
                                                                        • Add the new + Alternate functions literals + related to remap for SPI, - New Roman"">
                                                                          • -
                                                                            -
                                                                            • +
                                                                          • HAL_GPIO_DeInit(): - New Roman"">HAL_TIM_s
                                                                            • +
                                                                          +
                                                                        • HAL - New Roman"">IRQHandler(update
                                                                          • +
                                                                            +
                                                                          • __HAL_FLASH_INSTRUCTION_CACHE_RESET() + macro: update to reset +  ICRST bit in + the ACR register after + setting it.
                                                                            • +
                                                                          • __HAL_FLASH_DATA_CACHE_RESET() macro: - mso-fareast-font-family:"Times + update to reset +  DCRST bit in the ACR + register after setting it.
                                                                            • +
                                                                          +
                                                                        • HAL - New Roman"">): update to - check the input capture - channel 3 and 4 in CCMR2 - instead of CCMR1
                                                                          • -
                                                                        • update
                                                                          • +
                                                                            +
                                                                          • Add new + literal: ADC_SOFTWARE_START to + be used as possible value for + the ExternalTrigConv + parameter in the ADC_InitTypeDef + structure to select the ADC + software trigger mode.
                                                                            • +
                                                                          • IS_ADC_CHANNEL() + macro update to don't assert + stop the ADC_CHANNEL_TEMPSENSOR + value
                                                                            • +
                                                                          • HAL_ADC_PollForConversion(): update to + manage particular case when + ADC configured in DMA mode and + ADC sequencer with several + ranks and polling for end of + each conversion
                                                                            • +
                                                                          • HAL_ADC_Start()/HAL_ADC_Start_IT() + /HAL_ADC_Start_DMA() - mso-fareast-font-family:"Times + update:
                                                                            • +
                                                                              +
                                                                            • unlock the + process before starting the + ADC software conversion.
                                                                              • +
                                                                            • Optimize + the ADC stabilization delays
                                                                              • +
                                                                            +
                                                                          • __HAL_ADC_GET_IT_SOURCE() + update macro implementation
                                                                            • +
                                                                          • Add more + details in 'How to use this + driver' section
                                                                            • +
                                                                          +
                                                                        • HAL - New Roman"">__HAL_TIM_PRESCALER() - updated to use '=' instead of - '|='
                                                                          • -
                                                                        • update
                                                                          • +
                                                                            +
                                                                          • Add new macro + to check if the specified DAC + interrupt source is enabled or + disabled
                                                                            • +
                                                                              +
                                                                            • __HAL_DAC_GET_IT_SOURCE()
                                                                              • +
                                                                            +
                                                                          • HAL_DACEx_TriangleWaveGeneration() update to + use DAC CR bit mask definition
                                                                            • +
                                                                          • HAL_DACEx_NoiseWaveGeneration() update to + use DAC CR bit mask definition
                                                                            • +
                                                                          +
                                                                        • HAL - mso-fareast-font-family:"Times + CAN update
                                                                          • +
                                                                            +
                                                                          • CanTxMsgTypeDef structure: + update to use uint8_t Data[8] - New Roman"">Add the - following macro in TIM HAL - driver
                                                                            • -
                                                                              -
                                                                              • +
                                                                            • CanRxMsgTypeDef structure: + update to use uint8_t Data[8] + instead of + uint32_t Data[8]
                                                                              • +
                                                                            +
                                                                          +
                                                                            +
                                                                          • HAL - mso-fareast-font-family:"Times + RTC update
                                                                            • +
                                                                              +
                                                                            • Update to + use CMSIS mask definition + instead of hardcoded values (EXTI_IMR_IM17, + EXTI_IMR_IM19..)
                                                                              • +
                                                                            +
                                                                          • HAL - New Roman"">__HAL_TIM_GetCompare() -
                                                                            • -
                                                                          • update
                                                                            • +
                                                                              +
                                                                            • LTDC_SetConfig() update to + allow the drawing + of partial bitmap in + active layer.
                                                                              • +
                                                                            +
                                                                          • HAL - mso-fareast-font-family:"Times + USART update
                                                                            • +
                                                                              +
                                                                            • HAL_USART_Init() fix USART + baud rate configuration + issue: USART baud rate is + twice Higher than expected
                                                                              • +
                                                                            +
                                                                          • HAL - New Roman"">__HAL_TIM_GetCounter() -
                                                                            • -
                                                                          • update
                                                                            • +
                                                                              +
                                                                            • HAL_SMARTCARD_Transmit_IT() update to + force the disable for the ERR + interrupt to avoid the OVR + interrupt
                                                                              • +
                                                                            • HAL_SMARTCARD_IRQHandler() + update check condition + for transmission end
                                                                              • +
                                                                            • Clean up: + remove the following + literals that aren't used in + smartcard mode
                                                                              • +
                                                                                +
                                                                              • SMARTCARD_PARITY_NONE
                                                                                • +
                                                                              • SMARTCARD_WORDLENGTH_8B
                                                                                • +
                                                                              • SMARTCARD_STOPBITS_1
                                                                                • +
                                                                              • SMARTCADR_STOPBITS_2
                                                                                • +
                                                                              +
                                                                            +
                                                                          • HAL + SPI update
                                                                            • +
                                                                              +
                                                                            • HAL_SPI_Transmit_DMA()/HAL_SPI_Receive_DMA()/HAL_SPI_TarnsmitReceive_DMA() + update to unlock + the process before + enabling the SPI peripheral
                                                                              • +
                                                                            • HAL_SPI_Transmit_DMA() update to + manage correctly the DMA RX + stream in SPI Full duplex mode
                                                                              • +
                                                                            • Section + SPI_Exported_Functions_Group2 update + to remove duplication in *.chm + UM
                                                                              • +
                                                                            +
                                                                          • HAL - mso-fareast-font-family:"Times + CRYP update
                                                                            • +
                                                                              +
                                                                            • Update to + manage multi instance:
                                                                              • +
                                                                                +
                                                                              • Add new + parameter Instance in the CRYP_HandleTypeDef + Handle structure.
                                                                                • +
                                                                              • Add new + parameter in all HAL CRYP + macros
                                                                                • +
                                                                                  +
                                                                                • example: __HAL_CRYP_ENABLE() +  updated by + __HAL_CRYP_ENABLE(__HANDLE__)
                                                                                  • +
                                                                                +
                                                                              +
                                                                            +
                                                                          • HAL - New Roman"">__HAL_TIM_GetAutoreload() -
                                                                            • -
                                                                          • update
                                                                            • +
                                                                              +
                                                                            • Add an + extension + driver stm32f4xx_hal_dcmi_ex.c/h + to manage the support of new + Black and White feature +
                                                                              • +
                                                                            • Add  __weak attribute + for HAL_DCMI_Init() + function and add a new + implementation in the + extension driver to manage the + black and white configuration + only available in the  + STM32F446xx devices. +
                                                                              • +
                                                                            • Move DCMI_InitTypeDef + structure to extension driver + and add the + following new fields + related to black and white + feature: ByteSelectMode, ByteSelectStart, LineSelectMode + and LineSelectStart
                                                                              • +
                                                                            +
                                                                          • HAL - mso-fareast-font-family:"Times + PCD update
                                                                            • +
                                                                              +
                                                                            • Add the + support of LPM feature
                                                                              • +
                                                                                +
                                                                              • add PCD_LPM_StateTypeDef + enum
                                                                                • +
                                                                              • update PCD_HandleTypeDef + structure to support the LPM + feature
                                                                                • +
                                                                              • add new + functions HAL_PCDEx_ActivateLPM(), - New Roman"">__HAL_TIM_GetClockDivision() -
                                                                                • -
                                                                              • HAL_PCDEx_DeActivateLPM() - mso-fareast-font-family:"Times + and HAL_PCDEx_LPM_Callback() - New Roman"">__HAL_TIM_GetICPrescaler()
                                                                                • + in the + stm32f4xx_hal_pcd_ex.h/.c + files
                                                                            -
                                                                          • HAL + TIM update
                                                                            • +
                                                                              +
                                                                            • Add  + TIM_TIM11_SPDIFRX - "Times New Roman"">HAL + define
                                                                              • +
                                                                            +
                                                                          • HAL - SDMMC update
                                                                            • +
                                                                              +
                                                                            • Add + stm32f4xx_hal_sai_ex.h/.c + files for the SAI_BlockSynchroConfig() + and the SAI_GetInputClock() - New Roman"">update
                                                                              • -
                                                                            -
                                                                              -
                                                                                -
                                                                                • +
                                                                              • Add new + defines HAL_SAI_ERROR_AFSDET, + HAL_SAI_ERROR_LFSDET, + HAL_SAI_ERROR_CNREADY, + HAL_SAI_ERROR_WCKCFG, + HAL_SAI_ERROR_TIMEOUT in the SAI_Error_Code + group
                                                                                • +
                                                                              • Add new + defines SAI_SYNCEXT_DISABLE, + SAI_SYNCEXT_IN_ENABLE, + SAI_SYNCEXT_OUTBLOCKA_ENABLE, + SAI_SYNCEXT_OUTBLOCKB_ENABLE + for the SAI External + synchronization
                                                                                • +
                                                                              • Add new + defines SAI_I2S_STANDARD, + SAI_I2S_MSBJUSTIFIED, + SAI_I2S_LSBJUSTIFIED, + SAI_PCM_LONG and SAI_PCM_SHORT + for the SAI Supported protocol
                                                                                • +
                                                                              • Add new + defines + SAI_PROTOCOL_DATASIZE_16BIT, + SAI_PROTOCOL_DATASIZE_16BITEXTENDED, + SAI_PROTOCOL_DATASIZE_24BIT + and + SAI_PROTOCOL_DATASIZE_32BIT + for SAI protocol data size
                                                                                • +
                                                                              • Add SAI + Callback prototype definition
                                                                                • +
                                                                              • Update SAI_InitTypeDef + structure by adding new + fields: SynchroExt, + Mckdiv, + MonoStereoMode, + CompandingMode, + TriState
                                                                                • +
                                                                              • Update SAI_HandleTypeDef + structure:
                                                                                • +
                                                                                  +
                                                                                • remove + uint16_t *pTxBuffPtr, + *pRxBuffPtr, + TxXferSize, + RxXferSize, + TxXferCount + and RxXferCount + and replace them + respectively by uint8_t *pBuffPtr, + uint16_t XferSize and - mso-fareast-font-family:"Times + uint16_t XferCount
                                                                                  • +
                                                                                • add mutecallback + field
                                                                                  • +
                                                                                • add struct + __SAI_HandleTypeDef + *hsai field
                                                                                  • +
                                                                                +
                                                                              • Remove + SAI_CLKSOURCE_PLLR and + SAI_CLOCK_PLLSRC defines
                                                                                • +
                                                                              • Add + SAI_CLKSOURCE_NA define
                                                                                • +
                                                                              • Add + SAI_AUDIO_FREQUENCY_MCKDIV + define
                                                                                • +
                                                                              • Add + SAI_SPDIF_PROTOCOL define
                                                                                • +
                                                                              • Add + SAI_SYNCHRONOUS_EXT define
                                                                                • +
                                                                              • Add new + functions HAL_SAI_InitProtocol(), - New Roman"">Use of CMSIS - constants instead of magic valuesHAL_SAI_Abort(), - New Roman"">
                                                                                • -
                                                                              • HAL_SAI_EnableTxMuteMode(), - mso-fareast-font-family:"Times + HAL_SAI_DisableTxMuteMode(), - New Roman"">Miscellaneous - update in functions internal - coding
                                                                                • -
                                                                              -
                                                                            • HAL_SAI_EnableRxMuteMode(), - "Times New Roman"">HAL - NAND HAL_SAI_DisableRxMuteMode()
                                                                              • +
                                                                            • Update HAL_SAI_Transmit(), - New Roman"">updateHAL_SAI_Receive(), - New Roman"">
                                                                              • -
                                                                                -
                                                                              • HAL_SAI_Transmit_IT(), - mso-fareast-font-family:"Times + HAL_SAI_Receive_IT(), - New Roman";color:black">Fix - issue of macros returning - wrong address for NAND blocksHAL_SAI_Transmit_DMA(), - New Roman"">
                                                                                • -
                                                                              • HAL_SAI_Receive_DMA() - mso-fareast-font-family:"Times + functions to use uint8_t *pData + instead of uint16_t *pData + --> This update is mainly + impacting the compatibility + with previous driver + version.
                                                                                • +
                                                                              +
                                                                            • HAL - New Roman";color:black">Fix + I2S update
                                                                              • +
                                                                                +
                                                                              • Split the + following + functions between Generic + and Extended API based on full + duplex management and add the + attribute __weak in the + Generic API
                                                                                • +
                                                                                  +
                                                                                • HAL_I2S_Init(), +HAL_I2S_DMAPause(), HAL_I2S_DMAStop(), HAL_I2S_DMAResume(), HAL_I2S_IRQHandle() +
                                                                                  • +
                                                                                +
                                                                              • Move the + following static functions + from generic to extension driver
                                                                                • +
                                                                                  +
                                                                                •  I2S_DMARxCplt() + and I2S_DMATxCplt()
                                                                                  • +
                                                                                +
                                                                              • Remove static + attribute from I2S_Transmit_IT() + and I2S_Receive_IT() functions
                                                                                • +
                                                                              • Move I2SxEXT() + macro to extension file
                                                                                • +
                                                                              • Add + I2S_CLOCK_PLLR and + I2S_CLOCK_PLLSRC defines for + I2S clock source
                                                                                • +
                                                                              • Add new + function I2S_GetInputClock()
                                                                                • +
                                                                              +
                                                                            • HAL - issue for read/write NAND - page/spare areaupdate
                                                                              • +
                                                                                +
                                                                              • Add WriteFifo + and PageSize + fields in the FMC_NORSRAM_InitTypeDef + structure
                                                                                • +
                                                                              • Add + FMC_PAGE_SIZE_NONE, + FMC_PAGE_SIZE_128, + FMC_PAGE_SIZE_256, + FMC_PAGE_SIZE_1024, + FMC_WRITE_FIFO_DISABLE, + FMC_WRITE_FIFO_ENABLE defines
                                                                                • +
                                                                              • Update FMC_NORSRAM_Init(), - New Roman"">
                                                                                • -
                                                                              -
                                                                            • FMC_NORSRAM_DeInit() - "Times New Roman"">HAL + and FMC_NORSRAM_Extended_Timing_Init() functions
                                                                              • +
                                                                            +
                                                                          • HAL - NOR update
                                                                            • +
                                                                              +
                                                                            • Update USB_OTG_CfgTypeDef + structure to support LPM, lpm_enable + field added
                                                                              • +
                                                                            • Update USB_HostInit() + and USB_DevInit() - New Roman"">update
                                                                              • -
                                                                                -
                                                                                • +
                                                                              +
                                                                            +

                                                                            V1.2.0 + / 26-December-2014

                                                                            +

                                                                            Main Changes

                                                                            +
                                                                              +
                                                                            • Maintenance - mso-fareast-font-family:"Times + release to fix known defects + and enhancements implementation
                                                                              • +
                                                                            +
                                                                              +
                                                                            • Macros - New Roman";color:black">Add + and literals renaming to + ensure compatibles across + STM32 series, + backward compatibility + maintained thanks to new added + file stm32_hal_legacy.h under - the NOR address bank macro - used within the APILegacy
                                                                              • +
                                                                            • Add + *.chm UM for all drivers, a UM + is provided for each superset RPN
                                                                              • +
                                                                            • Update - mso-fareast-font-family:"Times + drivers to be C++ compliant
                                                                              • +
                                                                            • Several - New Roman"">
                                                                              • -
                                                                            • i.e. + Doxygen + tags updated)
                                                                              • +
                                                                            • Two - mso-fareast-font-family:"Times + changes done on the HAL + requires an update on the + application code based on HAL + V1.1.0
                                                                              • +
                                                                                +
                                                                              • LSI_VALUE constant has + been corrected in + stm32f4xx_hal_conf.h file, its + value changed from 40 KHz + to 32 KHz
                                                                                • +
                                                                              • UART, USART, + IRDA and SMARTCARD + (referenced as PPP + here below) drivers: + in DMA transmit process, the + code has been updated to avoid + waiting on TC flag under DMA + ISR, PPP TC interrupt + is used instead. Below the + update to be done on user + application:
                                                                                • +
                                                                                  +
                                                                                • Configure + and enable the USART IRQ in + HAL_PPP_MspInit() + function
                                                                                  • +
                                                                                • In + stm32f4xx_it.c file, PPP_IRQHandler() + function: add a call to HAL_PPP_IRQHandler() - New Roman";color:black">Update + function
                                                                                  • +
                                                                                +
                                                                              +
                                                                            +
                                                                              +
                                                                            • HAL - NOR API implementation to - avoid the use of NOR address - bank hard coded + update
                                                                              • +
                                                                            +
                                                                              +
                                                                                +
                                                                              • stm32f4xx_hal_def.h
                                                                                • +
                                                                                  +
                                                                                • Update NULL + definition to fix C++ + compilation issue
                                                                                  • +
                                                                                • Add UNUSED() + macro
                                                                                  • +
                                                                                • Add a new + define __NOINLINE to be used + for the no inline code + independent from tool chain
                                                                                  • +
                                                                                +
                                                                              • stm32f4xx_hal_conf_template.h
                                                                                • +
                                                                                  +
                                                                                • LSI_VALUE constant + has been corrected, + its value changed from 40 KHz + to 32 KHz
                                                                                  • +
                                                                                +
                                                                              +
                                                                            +
                                                                              +
                                                                                +
                                                                              • Update all + macros and literals naming to + be uper + case
                                                                                • +
                                                                              • ErrorCode parameter in + PPP_HandleTypeDef + structure updated + to uint32_t instead + of enum HAL_PPP_ErrorTypeDef
                                                                                • +
                                                                              • Remove the + unused FLAG and IT assert macros
                                                                                • +
                                                                              +
                                                                            • HAL - mso-fareast-font-family:"Times + ADC update
                                                                              • +
                                                                                +
                                                                              • Fix temperature - New Roman"">
                                                                                • -
                                                                              -
                                                                            • xx - "Times New Roman"">HAL - HCD update
                                                                              • +
                                                                            +
                                                                          • HAL - New Roman"">
                                                                            • -
                                                                              -
                                                                            • update
                                                                              • +
                                                                                +
                                                                              • HAL_DAC_ConfigChannel(): update the + access to the DAC peripheral + registers via the hdac + handle instance
                                                                                • +
                                                                              • HAL_DAC_IRQHandler(): update to + check on both DAC_FLAG_DMAUDR1 + and DAC_FLAG_DMAUDR2
                                                                                • +
                                                                              • HAL_DACEx_NoiseWaveGenerate(): update to + reset DAC CR register before + setting the new DAC + configuration
                                                                                • +
                                                                              • HAL_DACEx_TriangleWaveGenerate(): update to + reset DAC CR register before + setting the new DAC + configuration
                                                                                • +
                                                                              +
                                                                            • HAL - New Roman"">HCD_StateTypeDefupdate
                                                                              • +
                                                                                +
                                                                              • Unlock the + CAN process when communication + error occurred
                                                                                • +
                                                                              +
                                                                            • HAL + CORTEX update
                                                                              • +
                                                                                +
                                                                              • Add new macro + IS_NVIC_DEVICE_IRQ() + to check on negative values of + IRQn + parameter
                                                                                • +
                                                                              +
                                                                            +

                                                                            �  - mso-fareast-font-family:"Times - New Roman""> structure - members renamedHAL CRYP update

                                                                            +
                                                                              +
                                                                                +
                                                                              • HAL_CRYP_DESECB_Decrypt_DMA(): fix the + inverted pPlainData + and pCypherData + parameters issue
                                                                                • +
                                                                              • CRYPEx_GCMCCM_SetInitVector(): remove + the IVSize + parameter as the key length + 192bits and 256bits are not + supported by this version
                                                                                • +
                                                                              • Add restriction for - New Roman"">
                                                                                • -
                                                                              • only DataType + equal to 8bits is supported
                                                                                • +
                                                                              • HAL_CRYPEx_AESGCM_Finish():
                                                                                • +
                                                                                  +
                                                                                • Add restriction - New Roman"">These macrolength  (Plain/Cyphertext, - mso-fareast-font-family:"Times + Header) compared with GCM stadards + specifications (800-38D)
                                                                                  • +
                                                                                • Update Size + parameter on 32bits instead + of 16bits
                                                                                  • +
                                                                                • Fix issue + with 16-bit Data Type: + update to use intrinsic __ROR() + instead of __REV16()
                                                                                  • +
                                                                                +
                                                                              +
                                                                            +

                                                                            �  - New Roman""> are renamedHAL DCMI update

                                                                            +
                                                                              +
                                                                                +
                                                                              • HAL_DCMI_ConfigCROP(): Invert + assert macros to check Y0 and + Ysize + parameters
                                                                                • +
                                                                              +
                                                                            +

                                                                            �  - New Roman""> -

                                                                              -
                                                                            • HAL DMA update

                                                                              +
                                                                                +
                                                                                  +
                                                                                • HAL_DMA_Init(): Update to - mso-fareast-font-family:"Times - New Roman"">__HAL_GET_FLAG(__HANDLE__, + clear the DBM bit in the + SxCR + register before setting the + new configuration
                                                                                  • +
                                                                                • DMA_SetConfig(): + add to clear the DBM + bit in the SxCR + register
                                                                                  • +
                                                                                +
                                                                              +

                                                                              �  - __INTERRUPT__)    + HAL FLASH update

                                                                              +
                                                                                +
                                                                                  +
                                                                                • Add "HAL_" + prefix in the defined values + for the FLASH error code
                                                                                  • +
                                                                                    +
                                                                                  • Example: FLASH_ERROR_PGP + renamed by HAL_FLASH_ERROR_PGP
                                                                                    • +
                                                                                  +
                                                                                • Clear the - by - __HAL_HCD_GET_FLAG(__HANDLE__, - __INTERRUPT__)
                                                                                  • -
                                                                                • ErrorCode + in the FLASH_WaitForLastOperation() + function
                                                                                  • +
                                                                                • Update FLASH_SetErrorCode() + function to use "|=" + operant to update the Flash ErrorCode + parameter in the FLASH handle
                                                                                  • +
                                                                                • IS_FLASH_ADDRESS(): Update the + macro check using '<=' + condition instead of '<'
                                                                                  • +
                                                                                • IS_OPTIONBYTE(): Update the + macro check using '<=' + condition instead of '<'
                                                                                  • +
                                                                                • Add "FLASH_" - mso-fareast-font-family:"Times + prefix in the defined values + of FLASH Type Program + parameter
                                                                                  • +
                                                                                    +
                                                                                  • Example: TYPEPROGRAM_BYTE + renamed by FLASH_TYPEPROGRAM_BYTE
                                                                                    • +
                                                                                  +
                                                                                • Add "FLASH_" - New Roman"">__HAL_CLEAR_FLAG(__HANDLE__, + prefix in the defined values + of FLASH Type Erase parameter
                                                                                  • +
                                                                                    +
                                                                                  • Example: TYPEERASE_SECTORS + renamed by FLASH_TYPEERASE_SECTORS
                                                                                    • +
                                                                                  +
                                                                                • Add "FLASH_" - __INTERRUPT__) by - __HAL_HCD_CLEAR_FLAG(__HANDLE__, - __INTERRUPT__) 
                                                                                  • +
                                                                                    +
                                                                                  • Example: VOLTAGE_RANGE_1 + renamed by FLASH_VOLTAGE_RANGE_1
                                                                                    • +
                                                                                  +
                                                                                • Add "OB_" - "Times New Roman"">
                                                                                  • -
                                                                                  • +
                                                                                    +
                                                                                  • Example: WRPSTATE_ENABLE + renamed by OB_WRPSTATE_ENABLE
                                                                                    • +
                                                                                  +
                                                                                • Add "OB_" - mso-fareast-font-family:"Times + prefix in the defined values + of the FLASH PCROP State + parameter
                                                                                  • +
                                                                                    +
                                                                                  • PCROPSTATE_DISABLE  + updated by OB_PCROP_STATE_DISABLE
                                                                                    • +
                                                                                  • PCROPSTATE_ENABLE +  updated by OB_PCROP_STATE_ENABLE
                                                                                    • +
                                                                                  +
                                                                                • Change + "OBEX" prefix by + "OPTIONBYTE" prefix in these + defines:
                                                                                  • +
                                                                                    +
                                                                                  • OBEX_PCROP - New Roman"">__HAL_IS_INVALID_INTERRUPT(__HANDLE__)  + by OPTIONBYTE_PCROP 
                                                                                    • +
                                                                                  • OBEX_BOOTCONFIG - by - __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)  -
                                                                                    • + by OPTIONBYTE_BOOTCONFIG
                                                                                -
                                                                              • HAL - - +
                                                                              +

                                                                              �  - PCD updateHAL ETH update

                                                                              +
                                                                                +
                                                                                  +
                                                                                • Fix macros + naming typo
                                                                                  • +
                                                                                +
                                                                              +
                                                                                +
                                                                                  +
                                                                                    +
                                                                                  • Update + __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() + by + __HAL_ETH_EXTI_SET_RISING_EDGE_TRIGGER()
                                                                                    • +
                                                                                  • Update + __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() +by __HAL_ETH_EXTI_SET_FALLING_EDGE_TRIGGER()
                                                                                    • +
                                                                                  +
                                                                                +
                                                                              +

                                                                              �  - New Roman"">

                                                                              • -
                                                                                -
                                                                              • HAL PWR update

                                                                                +
                                                                                  +
                                                                                    +
                                                                                  • Add new API + to manage SLEEPONEXIT and + SEVONPEND bits of SCR register
                                                                                    • +
                                                                                      +
                                                                                    • HAL_PWR_DisableSleepOnExit()
                                                                                      • +
                                                                                    • HAL_PWR_EnableSleepOnExit()
                                                                                      • +
                                                                                    • HAL_PWR_EnableSEVOnPend()
                                                                                      • +
                                                                                    • HAL_PWR_DisableSEVOnPend()
                                                                                      • +
                                                                                    +
                                                                                  • HAL_PWR_EnterSTOPMode()
                                                                                    • +
                                                                                      +
                                                                                    • Update to - New Roman"">HAL_PCD_mode
                                                                                      • +
                                                                                    • Update + usage of __WFE() + in low power entry function: + if there is a pending event, + calling __WFE() will not + enter the CortexM4 core to + sleep mode. The solution is + to made the call below; the + first __WFE() + is always ignored and clears + the event if one was already + pending, the second is + always applied
                                                                                      • +
                                                                                    +
                                                                                  +
                                                                                +
                                                                                +

                                                                                __SEV()
                                                                                +                                                                                 __WFE()
                                                                                +                                                                                 __WFE()

                                                                                +
                                                                                +
                                                                                  +
                                                                                    +
                                                                                  • Add + new PVD configuration modes
                                                                                    • +
                                                                                      +
                                                                                    • PWR_PVD_MODE_NORMAL
                                                                                      • +
                                                                                    • PWR_PVD_MODE_EVENT_RISING 
                                                                                      • +
                                                                                    • PWR_PVD_MODE_EVENT_FALLING
                                                                                      • +
                                                                                    • PWR_PVD_MODE_EVENT_RISING_FALLING
                                                                                      • +
                                                                                    +
                                                                                  • Add new + macros to manage PVD Trigger
                                                                                    • +
                                                                                      +
                                                                                    • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()
                                                                                      • +
                                                                                    • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(
                                                                                      • +
                                                                                    • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()
                                                                                      • +
                                                                                    • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
                                                                                      • +
                                                                                    • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
                                                                                      • +
                                                                                    • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
                                                                                      • +
                                                                                    +
                                                                                  • PVD macros:
                                                                                    • +
                                                                                      +
                                                                                    • Remove the + __EXTILINE__ parameter
                                                                                      • +
                                                                                    • Update to + use prefix "__HAL_PWR_PVD_" + instead of  prefix + "__HAL_PVD"
                                                                                      • +
                                                                                    +
                                                                                  +
                                                                                +
                                                                                  +
                                                                                    +
                                                                                  • Rename HAL_PWR_PVDConfig() + by HAL_PWR_ConfigPVD()
                                                                                    • +
                                                                                  • Rename HAL_PWREx_ActivateOverDrive() + by HAL_PWREx_EnableOverDrive() - New Roman"">SetTxFiFo(
                                                                                    • +
                                                                                  • Rename HAL_PWREx_DeactivateOverDrive() + by HAL_PWREx_DisableOverDrive() - mso-fareast-font-family:"Times +
                                                                                    • +
                                                                                  +
                                                                                • HAL - New Roman"">) and HAL_PCD_SetRxFiFo() + GPIO update
                                                                                  • +
                                                                                    +
                                                                                  • HAL_GPIO_Init()/HAL_GPIO_DeInit(): add a call + to the CMSIS assert macro + to check GPIO instance: + IS_GPIO_ALL_INSTANCE() 
                                                                                    • +
                                                                                  • HAL_GPIO_WritePin(): update to + write in BSRR register
                                                                                    • +
                                                                                  • Rename GPIO_GET_SOURCE() + by GET_GPIO_INDEX() and - renamed into HAL_PCDEx_SetTxFiFo() + move this later to file  + stm32f4xx_hal_gpio_ex.h
                                                                                    • +
                                                                                  • Add new + define for alternate function + GPIO_AF5_SPI3 for + STM32F429xx/439xx and + STM32F427xx/437xx devices
                                                                                    • +
                                                                                  +
                                                                                • HAL - and HAL_PCDEx_SetRxFiFo() + HASH update
                                                                                  • +
                                                                                    +
                                                                                  • HAL_HASH_MD5_Start_IT(): - and moved to the extension - files - stm32f4xx_hal_pcd_ex.h/.cfix input + address management issue
                                                                                    • +
                                                                                  +
                                                                                • HAL - New Roman"">
                                                                                  • -
                                                                                • update
                                                                                  • +
                                                                                    +
                                                                                  • Rename the + following Macros
                                                                                    • +
                                                                                      +
                                                                                    • __PPP_CLK_ENABLE()  - New Roman"">PCD_StateTypeDef
                                                                                      • +
                                                                                    • __PPP_CLK_DISABLE()  - mso-fareast-font-family:"Times + by + __HAL_RCC_PPP_CLK_DISABLE()
                                                                                      • +
                                                                                    • __PPP_FORCE_RESET()  - New Roman""> structure - members renamed
                                                                                      • +
                                                                                    • __PPP_RELEASE_RESET()  - New Roman"">
                                                                                      • -
                                                                                      • +
                                                                                    • __PPP_CLK_SLEEP_ENABLE() + by + __HAL_RCC_PPP_CLK_SLEEP_ENABLE()
                                                                                      • +
                                                                                    • __PPP_CLK_SLEEP_DISABLE() + by + __HAL_RCC_PPP_CLK_SLEEP_DISABLE()
                                                                                      • +
                                                                                    +
                                                                                  • IS_RCC_PLLSAIN_VALUE() + macro: update the check + condition
                                                                                    • +
                                                                                  • Add + description of RCC known Limitations
                                                                                    • +
                                                                                  • Rename HAL_RCC_CCSCallback() + by HAL_RCC_CSSCallback()
                                                                                    • +
                                                                                  • HAL_RCC_OscConfig() fix + issues: 
                                                                                    • +
                                                                                      +
                                                                                    • Remove the + disable of HSE + oscillator when + HSE_BYPASS is used as + system clock source or as + PPL clock source
                                                                                      • +
                                                                                    • Add a check + on HSERDY flag + when HSE_BYPASS is + selected as new state + for HSE oscillator.
                                                                                      • +
                                                                                    +
                                                                                  • Rename + __HAL_RCC_I2SCLK() + by __HAL_RCC_I2S_Config()
                                                                                    • +
                                                                                  +
                                                                                +

                                                                                �  - mso-fareast-font-family:"Times - New Roman"">Fix incorrect - masking of TxFIFOEmptyHAL I2S update

                                                                                +
                                                                                  +
                                                                                    +
                                                                                  • HAL_I2S_Init(): add check + on I2S instance + using CMSIS macro IS_I2S_ALL_INSTANCE() 
                                                                                    • +
                                                                                  • HAL_I2S_IRQHandler() + update for compliancy w/ C++
                                                                                    • +
                                                                                  • Add use + of tmpreg + variable in __HAL_I2S_CLEAR_OVRFLAG() + and __HAL_I2S_CLEAR_UDRFLAG() + macro for compliancy with C++
                                                                                    • +
                                                                                  • HAL_I2S_GetError(): update to + return uint32_t instead of + HAL_I2S_ErrorTypeDef + enumeration
                                                                                    • +
                                                                                  +
                                                                                +

                                                                                �  - New Roman"">

                                                                                • -
                                                                              • HAL I2C update

                                                                                +
                                                                                  +
                                                                                    +
                                                                                  • Update to - mso-fareast-font-family:"Times + clear the POS bit in the + CR1 register at the end + of HAL_I2C_Master_Read_IT() + and HAL_I2C_Mem_Read_IT() + process
                                                                                    • +
                                                                                  • Rename + HAL_I2CEx_DigitalFilter_Config()  - New Roman"">stm32f4xx_ll_usb.c: + by + HAL_I2CEx_ConfigDigitalFilter() +
                                                                                    • +
                                                                                  • Rename + HAL_I2CEx_AnalogFilter_Config()  - fix issue in HS mode
                                                                                    • +
                                                                                  • Add use + of tmpreg + variable in __HAL_I2C_CLEAR_ADDRFLAG() + and __HAL_I2C_CLEAR_STOPFLAG() + macro for compliancy with + C++
                                                                                    • +
                                                                                  +
                                                                                • HAL - New Roman"">
                                                                                  • -
                                                                                • update
                                                                                  • +
                                                                                    +
                                                                                  • DMA transmit + process; the code has been + updated to avoid waiting on TC + flag under DMA ISR, IrDA TC + interrupt is used instead. + Below the update to be done on + user application:
                                                                                    • +
                                                                                      +
                                                                                    • Configure + and enable the USART IRQ in + HAL_IRDA_MspInit() + function
                                                                                      • +
                                                                                    • In + stm32f4xx_it.c file, UASRTx_IRQHandler() + function: add a call to HAL_IRDA_IRQHandler() - mso-fareast-font-family:"Times + function
                                                                                      • +
                                                                                    +
                                                                                  • IT transmit + process; the code has been + updated to avoid waiting on TC + flag under IRDA ISR, IrDA TC + interrupt is used instead. No + impact on user application
                                                                                    • +
                                                                                  • Rename + Macros: add prefix "__HAL"
                                                                                    • +
                                                                                      +
                                                                                    • __IRDA_ENABLE() + by __HAL_IRDA_ENABLE()
                                                                                      • +
                                                                                    • __IRDA_DISABLE() + by __HAL_IRDA_DISABLE()
                                                                                      • +
                                                                                    +
                                                                                  • Add new user + macros to manage the sample + method feature
                                                                                    • +
                                                                                      +
                                                                                    • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE()
                                                                                      • +
                                                                                    • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE()
                                                                                      • +
                                                                                    +
                                                                                  • HAL_IRDA_Transmit_IT(): update to + remove the enable of the + parity error interrupt
                                                                                    • +
                                                                                  • Add use + of tmpreg + variable in __HAL_IRDA_CLEAR_PEFLAG() + macro for compliancy with + C++
                                                                                    • +
                                                                                  • HAL_IRDA_Transmit_DMA() update to + follow the + right procedure + "Transmission using DMA"  + in the reference manual
                                                                                    • +
                                                                                      +
                                                                                    • Add clear + the TC flag in the SR + register before enabling the + DMA transmit + request
                                                                                      • +
                                                                                    +
                                                                                  +
                                                                                • HAL - New Roman"">New macros addedupdate
                                                                                  • +
                                                                                    +
                                                                                  • Rename the + defined IWDG keys: 
                                                                                    • +
                                                                                      +
                                                                                    • KR_KEY_RELOAD - New Roman"">
                                                                                      • -
                                                                                        -
                                                                                        • +
                                                                                      • KR_KEY_ENABLE + by IWDG_KEY_ENABLE
                                                                                        • +
                                                                                      • KR_KEY_EWA + by + IWDG_KEY_WRITE_ACCESS_ENABLE
                                                                                        • +
                                                                                      • KR_KEY_DWA + by + IWDG_KEY_WRITE_ACCESS_DISABLE
                                                                                        • +
                                                                                      +
                                                                                    •  Add new + macros + __HAL_IWDG_RESET_HANDLE_STATE() + and + __HAL_IWDG_CLEAR_FLAG() 
                                                                                      • +
                                                                                    • Update + __HAL_IWDG_ENABLE_WRITE_ACCESS() + and + __HAL_IWDG_DISABLE_WRITE_ACCESS() + as private macro
                                                                                      • +
                                                                                    +
                                                                                  +

                                                                                  �  - mso-fareast-font-family:"Times - New Roman"">__HAL_PCD_IS_PHY_SUSPENDED()HAL SPI update

                                                                                  +
                                                                                    +
                                                                                      +
                                                                                    • HAL_SPI_TransmitReceive_DMA() update to + remove the  DMA Tx Error + Callback initialization when + SPI RxOnly + mode is selected
                                                                                      • +
                                                                                    • Add use of UNUSED(tmpreg) + in __HAL_SPI_CLEAR_MODFFLAG(), + __HAL_SPI_CLEAR_OVRFLAG(), + __HAL_SPI_CLEAR_FREFLAG() to + fix "Unused variable" warning + with TrueSTUDIO.
                                                                                      • +
                                                                                    • Rename + Literals: remove "D" from + "DISABLED" and "ENABLED"
                                                                                      • +
                                                                                        +
                                                                                      • SPI_TIMODE_DISABLED by - New Roman"">
                                                                                        • -
                                                                                        • +
                                                                                      • SPI_TIMODE_ENABLED by SPI_TIMODE_ENABLE
                                                                                        • +
                                                                                      • SPI_CRCCALCULATION_DISABLED + by - mso-fareast-font-family:"Times +  SPI_CRCCALCULATION_DISABLE
                                                                                        • +
                                                                                      • SPI_CRCCALCULATION_ENABLED + by - New Roman"">__HAL_USB_HS_EXTI_GENERATE_SWIT()
                                                                                        • +
                                                                                      +
                                                                                    • Add use + of tmpreg + variable in __HAL_SPI_CLEAR_MODFFLAG(), - New Roman"">
                                                                                      • -
                                                                                      • +
                                                                                    +
                                                                                  +

                                                                                  �  - mso-fareast-font-family:"Times - New Roman"">__HAL_USB_FS_EXTI_GENERATE_SWIT()HAL SDMMC update

                                                                                  +
                                                                                    +
                                                                                      +
                                                                                    • IS_SDIO_ALL_INSTANCE() +  macro moved to CMSIS + files
                                                                                      • +
                                                                                    +
                                                                                  • HAL - New Roman"">
                                                                                    • + LTDC update +
                                                                                      +
                                                                                    • HAL_LTDC_ConfigCLUT: optimize + the function when pixel format +is LTDC_PIXEL_FORMAT_AL44 
                                                                                      • +
                                                                                        +
                                                                                      • Update the + size of color look up table + to 16 instead of 256 when + the pixel format + is LTDC_PIXEL_FORMAT_AL44 +
                                                                                      -
                                                                                    • HAL - New Roman"">These macroupdate
                                                                                      • +
                                                                                        +
                                                                                      • Rename NAND + Address structure to NAND_AddressTypeDef + instead of NAND_AddressTypedef
                                                                                        • +
                                                                                      • Update the + used algorithm of these functions
                                                                                        • +
                                                                                          +
                                                                                        • HAL_NAND_Read_Page()
                                                                                          • +
                                                                                        • HAL_NAND_Write_Page()
                                                                                          • +
                                                                                        • HAL_NAND_Read_SpareArea()
                                                                                          • +
                                                                                        • HAL_NAND_Write_SpareArea()
                                                                                          • +
                                                                                        +
                                                                                      • HAL_NAND_Write_Page(): move + initialization of tickstart + before while loop
                                                                                        • +
                                                                                      • HAL_NAND_Erase_Block(): add whait + until NAND status is ready + before exiting this function
                                                                                        • +
                                                                                      +
                                                                                    • HAL - mso-fareast-font-family:"Times + NOR update
                                                                                      • +
                                                                                        +
                                                                                      • Rename NOR + Address structure to NOR_AddressTypeDef + instead of NOR_AddressTypedef
                                                                                        • +
                                                                                      • NOR Status + literals renamed
                                                                                        • +
                                                                                          +
                                                                                        • NOR_SUCCESS + by HAL_NOR_STATUS_SUCCESS
                                                                                          • +
                                                                                        • NOR_ONGOING + by HAL_NOR_STATUS_ONGOING
                                                                                          • +
                                                                                        • NOR_ERROR + by HAL_NOR_STATUS_ERROR
                                                                                          • +
                                                                                        • NOR_TIMEOUT + by HAL_NOR_STATUS_TIMEOUT
                                                                                          • +
                                                                                        +
                                                                                      • HAL_NOR_GetStatus() update to + fix Timeout issue + and exit from waiting + loop when timeout occurred
                                                                                        • +
                                                                                      +
                                                                                    • HAL + + + + PCCARD update
                                                                                      • +
                                                                                        +
                                                                                      • Rename PCCARD + Address structure to HAL_PCCARD_StatusTypeDef + instead of CF_StatusTypedef
                                                                                        • +
                                                                                      • PCCARD Status + literals renamed
                                                                                        • +
                                                                                          +
                                                                                        • CF_SUCCESS + by HAL_PCCARD_STATUS_SUCCESS
                                                                                          • +
                                                                                        • CF_ONGOING + by HAL_PCCARD_STATUS_ONGOING
                                                                                          • +
                                                                                        • CF_ERROR + by HAL_PCCARD_STATUS_ERROR
                                                                                          • +
                                                                                        • CF_TIMEOUT + by HAL_PCCARD_STATUS_TIMEOUT
                                                                                          • +
                                                                                        +
                                                                                      • Update "CF" + by "PCCARD" in functions, + literals + and macros
                                                                                        • +
                                                                                      +
                                                                                    • HAL - New Roman""> are renamedupdate
                                                                                      • +
                                                                                        +
                                                                                      • Rename functions
                                                                                        • +
                                                                                          +
                                                                                        • HAL_PCD_ActiveRemoteWakeup() by HAL_PCD_ActivateRemoteWakeup()
                                                                                          • +
                                                                                        • HAL_PCD_DeActiveRemoteWakeup() by HAL_PCD_DeActivateRemoteWakeup()
                                                                                          • +
                                                                                        +
                                                                                      • Rename literals
                                                                                        • +
                                                                                          +
                                                                                        • USB_FS_EXTI_TRIGGER_RISING_EDGE - New Roman"">
                                                                                          • -
                                                                                            -
                                                                                            • +
                                                                                          • USB_FS_EXTI_TRIGGER_FALLING_EDGE - mso-fareast-font-family:"Times + by + USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
                                                                                            • +
                                                                                          • USB_FS_EXTI_TRIGGER_BOTH_EDGE() + by + USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
                                                                                            • +
                                                                                          • USB_HS_EXTI_TRIGGER_RISING_EDGE - New Roman"">__HAL_GET_FLAG(__HANDLE__, + by + USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 
                                                                                            • +
                                                                                          • USB_HS_EXTI_TRIGGER_FALLING_EDGE - __INTERRUPT__)    by - __HAL_PCD_GET_FLAG(__HANDLE__, - __INTERRUPT__)
                                                                                            • -
                                                                                            • +
                                                                                          • USB_HS_EXTI_TRIGGER_BOTH_EDGE - mso-fareast-font-family:"Times + by + USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
                                                                                            • +
                                                                                          • USB_HS_EXTI_LINE_WAKEUP + - New Roman"">__HAL_CLEAR_FLAG(__HANDLE__, + by + USB_OTG_HS_EXTI_LINE_WAKEUP
                                                                                            • +
                                                                                          • USB_FS_EXTI_LINE_WAKEUP - __INTERRUPT__) by - __HAL_PCD_CLEAR_FLAG(__HANDLE__, - __INTERRUPT__) 
                                                                                            • +
                                                                                          +
                                                                                        • Rename USB + EXTI macros (FS, HS + referenced as SUBBLOCK + here below)
                                                                                          • +
                                                                                            +
                                                                                          • __HAL_USB_SUBBLOCK_EXTI_ENABLE_IT() +  by  + __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_IT()  
                                                                                            • +
                                                                                          • __HAL_USB_SUBBLOCK_EXTI_DISABLE_IT() + by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_DISABLE_IT()
                                                                                            • +
                                                                                          • __HAL_USB_SUBBLOCK_EXTI_GET_FLAG() + by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GET_FLAG() 
                                                                                            • +
                                                                                          • __HAL_USB_SUBBLOCK_EXTI_CLEAR_FLAG() + by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_CLEAR_FLAG()
                                                                                            • +
                                                                                          • __HAL_USB_SUBBLOCK_EXTI_SET_RISING_EGDE_TRIGGER() + by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_EDGE()
                                                                                            • +
                                                                                          • __HAL_USB_SUBBLOCK_EXTI_SET_FALLING_EGDE_TRIGGER() + by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
                                                                                            • +
                                                                                          • __HAL_USB_SUBBLOCK_EXTI_SET_FALLINGRISING_TRIGGER() + by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
                                                                                            • +
                                                                                          • __HAL_USB_SUBBLOCK_EXTI_GENERATE_SWIT()  - "Times New Roman"">
                                                                                            • -
                                                                                          •                                     +
                                                                                            • +
                                                                                          +
                                                                                        +
                                                                                      +
                                                                                        +
                                                                                      • HAL - mso-fareast-font-family:"Times + RNG update
                                                                                        • +
                                                                                          +
                                                                                        • Add new functions
                                                                                          • +
                                                                                            +
                                                                                          • HAL_RNG_GenerateRandomNumber(): to + generate a 32-bits random + number, + return + random value in argument and + return HAL status.
                                                                                            • +
                                                                                          • HAL_RNG_GenerateRandomNumber_IT(): to +  start generation of + the 32-bits random + number, user should call + the HAL_RNG_ReadLastRandomNumber() - New Roman"">__HAL_IS_INVALID_INTERRUPT(__HANDLE__)  + function under the HAL_RNG_ReadyCallback() - by - __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)  -
                                                                                            • -
                                                                                            • +
                                                                                          • HAL_RNG_ReadLastRandomNumber(): to + return the last random value + stored in the RNG handle
                                                                                            • +
                                                                                          +
                                                                                        • HAL_RNG_GetRandomNumber(): return + value update (obsolete), + replaced by HAL_RNG_GenerateRandomNumber()
                                                                                          • +
                                                                                        • HAL_RNG_GetRandomNumber_IT(): wrong + implementation (obsolete), + replaced by HAL_RNG_GenerateRandomNumber_IT()
                                                                                          • +
                                                                                        • __HAL_RNG_CLEAR_FLAG() + macro (obsolete), replaced by + new __HAL_RNG_CLEAR_IT() macro
                                                                                          • +
                                                                                        • Add new + define for RNG ready + interrupt:  RNG_IT_DRDY
                                                                                          • +
                                                                                        +
                                                                                      • HAL - mso-fareast-font-family:"Times + RTC update
                                                                                        • +
                                                                                          +
                                                                                        • HAL_RTC_GetTime() and HAL_RTC_GetDate(): - New Roman"">__HAL_PCD_UNGATE_CLOCK(__HANDLE__) + add the comment below
                                                                                          • +
                                                                                        +
                                                                                      +
                                                                                      +
                                                                                      +

                                                                                        - by - __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)HAL_RTC_GetDate() + after HAL_RTC_GetTime() - New Roman""> -


                                                                                    • +                                                                                         - mso-fareast-font-family:"Times - New Roman"">__HAL_PCD_GATE_CLOCK(__HANDLE__) + * in the higher-order + calendar shadow registers to + ensure consistency between + the time and date values.
                                                                                      +                                                                                         - by - __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)

                                                                                      +
                                                                                      • +
                                                                                      +
                                                                                        +
                                                                                          +
                                                                                        • Rename + literals: add prefix "__HAL"
                                                                                          • +
                                                                                            +
                                                                                          • FORMAT_BIN by HAL_FORMAT_BIN
                                                                                            • +
                                                                                          • FORMAT_BCD + by HAL_FORMAT_BCD
                                                                                            • +
                                                                                          +
                                                                                        • Rename macros + (ALARM, WAKEUPTIMER and + TIMESTAMP referenced + as SUBBLOCK here + below)
                                                                                          • +
                                                                                            +
                                                                                          • __HAL_RTC_EXTI_ENABLE_IT() + by  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_IT()
                                                                                            • +
                                                                                          • __HAL_RTC_EXTI_DISABLE_IT() + by  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_IT()
                                                                                            • +
                                                                                          • __HAL_RTC_EXTI_CLEAR_FLAG() + by  __HAL_RTC_SUBBLOCK_EXTI_CLEAR_FLAG()
                                                                                            • +
                                                                                          • __HAL_RTC_EXTI_GENERATE_SWIT() + by __HAL_RTC_SUBBLOCK_EXTI_GENERATE_SWIT()
                                                                                            • +
                                                                                          +
                                                                                        • Add new + macros (ALARM, + WAKEUPTIMER and TAMPER_TIMESTAMP - New Roman"">
                                                                                          • + referenced as SUBBLOCK + here below) +
                                                                                            +
                                                                                          • __HAL_RTC_SUBBLOCK_GET_IT_SOURCE() 
                                                                                            • +
                                                                                          • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_EVENT()
                                                                                            • +
                                                                                          • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_EVENT()
                                                                                            • +
                                                                                          • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_FALLING_EDGE()
                                                                                            • +
                                                                                          • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_FALLING_EDGE()
                                                                                            • +
                                                                                          • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_EDGE()
                                                                                            • +
                                                                                          • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_EDGE()
                                                                                            • +
                                                                                          •  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_FALLING_EDGE()
                                                                                            • +
                                                                                          •  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_FALLING_EDGE()
                                                                                            • +
                                                                                          •  __HAL_RTC_SUBBLOCK_EXTI_GET_FLAG()
                                                                                        -
                                                                                      • HAL - - - - ETH HAL - New Roman"">update
                                                                                        • -
                                                                                          -
                                                                                        • update
                                                                                          • +
                                                                                            +
                                                                                          • Update + SAI_STREOMODE by SAI_STEREOMODE
                                                                                            • +
                                                                                          • Update FIFO + status Level defines in upper + case
                                                                                            • +
                                                                                          • Rename + literals: remove "D" from + "DISABLED" and "ENABLED"
                                                                                            • +
                                                                                              +
                                                                                            • SAI_OUTPUTDRIVE_DISABLED - mso-fareast-font-family:"Times +  by + SAI_OUTPUTDRIVE_DISABLE
                                                                                              • +
                                                                                            • SAI_OUTPUTDRIVE_ENABLED - New Roman"">Update HAL_ETH_GetReceivedFrame_IT() - function to return HAL_ERROR - if the received packet is not - complete
                                                                                              • -
                                                                                              • +
                                                                                            • SAI_MASTERDIVIDER_ENABLED  by + SAI_MASTERDIVIDER_ENABLE
                                                                                              • +
                                                                                            • SAI_MASTERDIVIDER_DISABLED  by + SAI_MASTERDIVIDER_DISABLE
                                                                                              • +
                                                                                            +
                                                                                          +
                                                                                        +
                                                                                          +
                                                                                        • HAL - mso-fareast-font-family:"Times + SD update
                                                                                          • +
                                                                                            +
                                                                                          • Rename + SD_CMD_SD_APP_STAUS by SD_CMD_SD_APP_STATUS
                                                                                            • +
                                                                                          • SD_PowerON() updated to + add 1ms required power up + waiting time before starting + the SD initialization sequence
                                                                                            • +
                                                                                          • SD_DMA_RxCplt()/SD_DMA_TxCplt(): - New Roman"">Use HAL_Delay() - instead of counting loopadd a call to + HAL_DMA_Abort()
                                                                                            • +
                                                                                          • HAL_SD_ReadBlocks() update to + set the defined + DATA_BLOCK_SIZE as SDIO DataBlockSize + parameter
                                                                                            • +
                                                                                          • HAL_SD_ReadBlocks_DMA()/HAL_SD_WriteBlocks_DMA() + update to call the HAL_DMA_Start_IT() - "Times New Roman"">
                                                                                            • -
                                                                                          • Datalength + set to BlockSize/4  - mso-fareast-font-family:"Times + as the DMA is + configured in word 
                                                                                            • +
                                                                                          +
                                                                                        • HAL - New Roman""> __HAL_ETH_MAC_CLEAR_FLAG() - macro is removed: the MACSR - register is read onlyupdate 
                                                                                          • +
                                                                                            +
                                                                                          • DMA transmit + process; the code has been + updated to avoid waiting on TC + flag under DMA ISR, SMARTCARD + TC interrupt is used instead. + Below the update to be done on + user application:
                                                                                            • +
                                                                                              +
                                                                                            • Configure + and enable the USART IRQ in + HAL_SAMRTCARD_MspInit() + function
                                                                                              • +
                                                                                            • In + stm32f4xx_it.c file, UASRTx_IRQHandler() + function: add a call to HAL_SMARTCARD_IRQHandler() - New Roman"">
                                                                                              • -
                                                                                              • +
                                                                                            +
                                                                                          • IT transmit + process; the code has been + updated to avoid waiting on TC + flag under SMARTCARD + ISR, SMARTCARD TC + interrupt is used instead. No + impact on user application
                                                                                            • +
                                                                                          • Rename + macros: add prefix "__HAL"
                                                                                            • +
                                                                                              +
                                                                                            • __SMARTCARD_ENABLE() + by __HAL_SMARTCARD_ENABLE()
                                                                                              • +
                                                                                            • __SMARTCARD_DISABLE() + by __HAL_SMARTCARD_DISABLE()
                                                                                              • +
                                                                                            • __SMARTCARD_ENABLE_IT() + by + __HAL_SMARTCARD_ENABLE_IT()
                                                                                              • +
                                                                                            • __SMARTCARD_DISABLE_IT() + by + __HAL_SMARTCARD_DISABLE_IT()
                                                                                              • +
                                                                                            • __SMARTCARD_DMA_REQUEST_ENABLE() + by + __HAL_SMARTCARD_DMA_REQUEST_ENABLE()
                                                                                              • +
                                                                                            • __SMARTCARD_DMA_REQUEST_DISABLE() + by + __HAL_SMARTCARD_DMA_REQUEST_DISABLE()
                                                                                              • +
                                                                                            +
                                                                                          • Rename + literals: remove "D" from + "DISABLED" and "ENABLED"
                                                                                            • +
                                                                                              +
                                                                                            • SMARTCARD_NACK_ENABLED by - mso-fareast-font-family:"Times - New Roman"">Add the - following macros used to Wake - up the device from STOP mode - by Ethernet event + SMARTCARD_NACK_ENABLE
                                                                                              • +
                                                                                            • SMARTCARD_NACK_DISABLED by SMARTCARD_NACK_DISABLE
                                                                                              • +
                                                                                            +
                                                                                          • Add new user + macros to manage the sample + method feature
                                                                                            • +
                                                                                              +
                                                                                            • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE()
                                                                                              • +
                                                                                            • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE()
                                                                                              • +
                                                                                            +
                                                                                          • Add use + of tmpreg + variable in + __HAL_SMARTCARD_CLEAR_PEFLAG() + macro for compliancy with + C++
                                                                                            • +
                                                                                          • HAL_SMARTCARD_Transmit_DMA() update to + follow the + right procedure + "Transmission using DMA"  + in the reference manual
                                                                                            • +
                                                                                              +
                                                                                            • Add clear + the TC flag in the SR + register before enabling the + DMA transmit + request
                                                                                              • +
                                                                                            +
                                                                                          +
                                                                                        • HAL - :update
                                                                                          • +
                                                                                            +
                                                                                          • Add + TIM_CHANNEL_ALL as possible + value for all Encoder + Start/Stop APIs Description
                                                                                            • +
                                                                                          • HAL_TIM_OC_ConfigChannel() remove call + to IS_TIM_FAST_STATE() assert + macro
                                                                                            • +
                                                                                          • HAL_TIM_PWM_ConfigChannel() add a call + to IS_TIM_FAST_STATE() assert + macro to check the OCFastMode + parameter
                                                                                            • +
                                                                                          • HAL_TIM_DMADelayPulseCplt() Update to + set the TIM Channel before to + call  HAL_TIM_PWM_PulseFinishedCallback()
                                                                                            • +
                                                                                          • HAL_TIM_DMACaptureCplt() update to + set the TIM Channel before to + call  HAL_TIM_IC_CaptureCallback()
                                                                                            • +
                                                                                          • TIM_ICx_ConfigChannel() update + to fix Timer CCMR1 register + corruption when setting ICFilter + parameter
                                                                                            • +
                                                                                          • HAL_TIM_DMABurst_WriteStop()/HAL_TIM_DMABurst_ReadStop() + update to abort the DMA + transfer for the specifc + TIM channel
                                                                                            • +
                                                                                          • Add new + function for TIM Slave + configuration in IT mode: + HAL_TIM_SlaveConfigSynchronization_IT() 
                                                                                            • +
                                                                                          • HAL_TIMEx_ConfigBreakDeadTime() add an + assert check on Break & DeadTime + parameters values
                                                                                            • +
                                                                                          • HAL_TIMEx_OCN_Start_IT() add the + enable of Break Interrupt for + all output modes
                                                                                            • +
                                                                                          • Add new + macros to ENABLE/DISABLE URS + bit in TIM CR1 register:
                                                                                            • +
                                                                                              +
                                                                                            • __HAL_TIM_URS_ENABLE()
                                                                                              • +
                                                                                            • __HAL_TIM_URS_DISABLE()
                                                                                              • +
                                                                                            +
                                                                                          • Add new macro + for TIM Edge modification: + __HAL_TIM_SET_CAPTUREPOLARITY()
                                                                                            • +
                                                                                          +
                                                                                        • HAL - New Roman"">
                                                                                          • -
                                                                                            -
                                                                                          • update
                                                                                            • +
                                                                                              +
                                                                                            • Add IS_LIN_WORD_LENGTH() + and + IS_LIN_OVERSAMPLING()  + macros: to check respectively + WordLength + and OverSampling + parameters in LIN mode
                                                                                              • +
                                                                                            • DMA transmit + process; the code has been + updated to avoid waiting on TC + flag under DMA ISR, UART TC + interrupt is used instead. + Below the update to be done on + user application:
                                                                                              • +
                                                                                                +
                                                                                              • Configure + and enable the USART IRQ in + HAL_UART_MspInit() + function
                                                                                                • +
                                                                                              • In + stm32f4xx_it.c file, USARTx_IRQHandler() + function: add a call to HAL_UART_IRQHandler() + function
                                                                                                • +
                                                                                              +
                                                                                            • IT transmit + process; the code has been + updated to avoid waiting on TC + flag under UART ISR, UART + TC interrupt is used instead. + No impact on user application
                                                                                              • +
                                                                                            • Rename + macros:
                                                                                              • +
                                                                                                +
                                                                                              • __HAL_UART_ONEBIT_ENABLE() + by + __HAL_UART_ONE_BIT_SAMPLE_ENABLE()
                                                                                                • +
                                                                                              • __HAL_UART_ONEBIT_DISABLE() + by + __HAL_UART_ONE_BIT_SAMPLE_DISABLE()
                                                                                                • +
                                                                                              +
                                                                                            • Rename + literals:
                                                                                              • +
                                                                                                +
                                                                                              • UART_WAKEUPMETHODE_IDLELINE by - mso-fareast-font-family:"Times - New Roman"">__HAL_ETH_EXTI_ENABLE_IT()
                                                                                                • -
                                                                                                • +
                                                                                              • UART_WAKEUPMETHODE_ADDRESSMARK by +UART_WAKEUPMETHOD_ADDRESSMARK
                                                                                                • +
                                                                                              +
                                                                                            • Add use + of tmpreg + variable in __HAL_UART_CLEAR_PEFLAG() + macro for compliancy with + C++
                                                                                              • +
                                                                                            • HAL_UART_Transmit_DMA() update to + follow the right procedure + "Transmission using DMA" in + the reference manual
                                                                                              • +
                                                                                                +
                                                                                              • Add clear + the TC flag in the SR + register before enabling the + DMA transmit + request
                                                                                                • +
                                                                                              +
                                                                                            +
                                                                                          • HAL + USART update
                                                                                            • +
                                                                                              +
                                                                                            • DMA transmit + process; the code has been + updated to avoid waiting on TC + flag under DMA ISR, USART TC + interrupt is used instead. + Below the update to be done on + user application:
                                                                                              • +
                                                                                                +
                                                                                              • Configure + and enable the USART IRQ in + HAL_USART_MspInit() + function
                                                                                                • +
                                                                                              • In + stm32f4xx_it.c file, USARTx_IRQHandler() + function: add a call to HAL_USART_IRQHandler() - mso-fareast-font-family:"Times - New Roman"">__HAL_ETH_EXTI_DISABLE_IT()
                                                                                                • -
                                                                                                • +
                                                                                              +
                                                                                            • IT transmit + process; the code has been + updated to avoid waiting on TC + flag under USART ISR, + USART TC interrupt is used + instead. No impact on user + application
                                                                                              • +
                                                                                            • HAL_USART_Init() update + to enable the USART + oversampling by 8 by default + in order to reach max USART + frequencies
                                                                                              • +
                                                                                            • USART_DMAReceiveCplt() update + to set the new USART state + after checking on the + old state
                                                                                              • +
                                                                                            • HAL_USART_Transmit_DMA()/HAL_USART_TransmitReceive_DMA() + update to + follow the + right procedure + "Transmission using DMA"  + in the reference manual
                                                                                              • +
                                                                                                +
                                                                                              • Add clear + the TC flag in the SR + register before enabling the + DMA transmit + request
                                                                                                • +
                                                                                              +
                                                                                            • Rename + macros:
                                                                                              • +
                                                                                                +
                                                                                              • __USART_ENABLE() + by __HAL_USART_ENABLE()
                                                                                                • +
                                                                                              • __USART_DISABLE() + by __HAL_USART_DISABLE()
                                                                                                • +
                                                                                              • __USART_ENABLE_IT() + by __HAL_USART_ENABLE_IT()
                                                                                                • +
                                                                                              • __USART_DISABLE_IT() + by __HAL_USART_DISABLE_IT()
                                                                                                • +
                                                                                              +
                                                                                            • Rename + literals: remove "D" from + "DISABLED" and "ENABLED"
                                                                                              • +
                                                                                                +
                                                                                              • USART_CLOCK_DISABLED by - mso-fareast-font-family:"Times + USART_CLOCK_DISABLE
                                                                                                • +
                                                                                              • USART_CLOCK_ENABLED by - New Roman"">__HAL_ETH_EXTI_GET_FLAG()
                                                                                                • -
                                                                                                • +
                                                                                              • USARTNACK_ENABLED - mso-fareast-font-family:"Times + by USART_NACK_ENABLE
                                                                                                • +
                                                                                              • USARTNACK_DISABLED - New Roman"">__HAL_ETH_EXTI_CLEAR_FLAG()
                                                                                                • +
                                                                                              +
                                                                                            • Add new user + macros to manage the sample + method feature
                                                                                              • +
                                                                                                +
                                                                                              • __HAL_USART_ONE_BIT_SAMPLE_ENABLE()
                                                                                                • +
                                                                                              • __HAL_USART_ONE_BIT_SAMPLE_DISABLE()
                                                                                                • +
                                                                                              +
                                                                                            • Add use + of tmpreg + variable in __HAL_USART_CLEAR_PEFLAG() + macro for compliancy with + C++
                                                                                              • +
                                                                                            +
                                                                                          • HAL + WWDG update
                                                                                            • +
                                                                                              +
                                                                                            • Add new + parameter in + __HAL_WWDG_ENABLE_IT() + macro
                                                                                              • +
                                                                                            • Add new + macros to manage WWDG IT & + correction:
                                                                                              • +
                                                                                                +
                                                                                              • __HAL_WWDG_DISABLE()
                                                                                                • +
                                                                                              • __HAL_WWDG_DISABLE_IT()
                                                                                                • +
                                                                                              • __HAL_WWDG_GET_IT()
                                                                                                • +
                                                                                              • __HAL_WWDG_GET_IT_SOURCE()
                                                                                                • +
                                                                                              +
                                                                                            +
                                                                                          +

                                                                                          V1.1.0 - mso-fareast-font-family:"Times + / 19-June-2014

                                                                                          +

                                                                                          Main Changes

                                                                                          +
                                                                                            +
                                                                                          • Add + support of STM32F411xE devices
                                                                                            • +
                                                                                          +
                                                                                            +
                                                                                          • HAL - New Roman"">
                                                                                            • -
                                                                                          • + update
                                                                                            • +
                                                                                              +
                                                                                            • Enhance HAL + delay and time base implementation
                                                                                              • +
                                                                                                +
                                                                                              • Systick timer is + used by default as source of + time base, but user can + eventually implement his + proper time base source (a general - mso-fareast-font-family:"Times + purpose + timer for example or other + time source)
                                                                                                • +
                                                                                              • Functions + affecting time base + configurations are declared + as __Weak to make override + possible in case of other + implementations in user + file, for more details + please refer to HAL_TimeBase + example
                                                                                                • +
                                                                                              +
                                                                                            • Fix flag + clear procedure: use atomic + write operation "=" instead of + ready-modify-write operation + "|=" or "&="
                                                                                              • +
                                                                                            • Fix on + Timeout management, Timeout + value set to 0 passed to API + automatically exits the + function after checking the + flag without any wait
                                                                                              • +
                                                                                            • Common update + for the following + communication peripherals: + SPI, UART, USART and IRDA
                                                                                              • +
                                                                                                +
                                                                                              • Add DMA + circular mode support
                                                                                                • +
                                                                                              • Remove lock + from recursive process
                                                                                                • +
                                                                                              +
                                                                                            • Add new macro + __HAL_RESET_HANDLE_STATE to + reset a given handle state
                                                                                              • +
                                                                                            • Add a new + attribute for functions + executed from internal SRAM + and depending from + Compiler implementation
                                                                                              • +
                                                                                            • When USE_RTOS + == 1 (in + stm32l0xx_hal_conf.h), the + __HAL_LOCK() + is not defined instead of + being defined empty
                                                                                              • +
                                                                                            • Miscellaneous + comments and formatting update
                                                                                              • +
                                                                                            • stm32f4xx_hal_conf_template.h
                                                                                              • +
                                                                                                +
                                                                                              • Add a new + define for LSI default value + LSI_VALUE
                                                                                                • +
                                                                                              • Add a new + define for LSE default value + LSE_VALUE
                                                                                                • +
                                                                                              • Add a new + define for Tick interrupt + priority TICK_INT_PRIORITY + (needed for the enhanced + time base implementation)
                                                                                                • +
                                                                                              +
                                                                                            • Important - New Roman"">__HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER()
                                                                                              • -
                                                                                            • + aliases has been added for any + API naming change, to keep + compatibility with previous version
                                                                                              • +
                                                                                            +
                                                                                          • HAL - mso-fareast-font-family:"Times + GPIO update
                                                                                            • +
                                                                                          +
                                                                                            +
                                                                                              +
                                                                                            • Add a new + macro __HAL_GPIO_EXTI_GENERATE_SWIT() + to manage the generation of + software interrupt on selected + EXTI line
                                                                                              • +
                                                                                            • HAL_GPIO_Init(): use + temporary variable when + modifying the registers, to + avoid unexpected transition in + the GPIO pin configuration
                                                                                              • +
                                                                                            • Remove + IS_GET_GPIO_PIN macro
                                                                                              • +
                                                                                            • Add a new + function HAL_GPIO_LockPin()
                                                                                              • +
                                                                                            • Private Macro + __HAL_GET_GPIO_SOURCE renamed + into GET_GPIO_SOURCE
                                                                                              • +
                                                                                            • Add the + support of STM32F411xx devices - New Roman"">__HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER()
                                                                                              • +
                                                                                            • Update the + following HAL GPIO macros + description: rename EXTI_Linex + by GPIO_PIN_x
                                                                                              • +
                                                                                                +
                                                                                              • __HAL_GPIO_EXTI_CLEAR_IT()
                                                                                                • +
                                                                                              • __HAL_GPIO_EXTI_GET_IT()
                                                                                                • +
                                                                                              • __HAL_GPIO_EXTI_CLEAR_FLAG()
                                                                                                • +
                                                                                              • __HAL_GPIO_EXTI_GET_FLAG()
                                                                                                • +
                                                                                              +
                                                                                            +
                                                                                          +

                                                                                          �  - New Roman""> -

                                                                                        • HAL DMA update

                                                                                          +
                                                                                            +
                                                                                              +
                                                                                            • Fix in HAL_DMA_PollForTransfer() + to:
                                                                                              • +
                                                                                                +
                                                                                              • set DMA + error code in case of + HAL_ERROR status
                                                                                                • +
                                                                                              • set HAL + Unlock before DMA state update
                                                                                                • +
                                                                                              +
                                                                                            +
                                                                                          +

                                                                                          �  - mso-fareast-font-family:"Times - New Roman"">__HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER()HAL DMA2D + update

                                                                                          +
                                                                                            +
                                                                                              +
                                                                                            • Add + configuration of source + address in case of A8 or A4 + M2M_PFC DMA2D mode
                                                                                              • +
                                                                                            +
                                                                                          • HAL - New Roman"">
                                                                                            • + FLASH update +
                                                                                          +
                                                                                            +
                                                                                              +
                                                                                            • Functions + reorganization update, + depending on the features + supported by each STM32F4 device
                                                                                              • +
                                                                                            • Add new + driver + (stm32f4xx_hal_flash_ramfunc.h/.c) + to manage function executed + from RAM, these functions are + available only for STM32F411xx + Devices
                                                                                              • +
                                                                                                +
                                                                                              • FLASH_StopFlashInterfaceClk()  : + Stop the flash interface + while System Run
                                                                                                • +
                                                                                              • FLASH_StartFlashInterfaceClk() : Stop the + flash interface while System + Run
                                                                                                • +
                                                                                              • FLASH_EnableFlashSleepMode() : Enable + the flash sleep while System + Run
                                                                                                • +
                                                                                              • FLASH_DisableFlashSleepMode() :  + Disable the flash sleep + while System Run
                                                                                            -
                                                                                          • HAL +
                                                                                          +
                                                                                            +
                                                                                          • HAL - WWDGupdate
                                                                                            • +
                                                                                          +
                                                                                            +
                                                                                              +
                                                                                            • HAL_PWR_PVDConfig(): add clear + of the EXTI trigger before new + configuration
                                                                                              • +
                                                                                            • Fix in HAL_PWR_EnterSTANDBYMode() + to not clear Wakeup flag + (WUF), which need to be + cleared at application level + before to call this function
                                                                                              • +
                                                                                            • HAL_PWR_EnterSLEEPMode()
                                                                                              • +
                                                                                                +
                                                                                              • Remove + disable and enable of SysTick + Timer
                                                                                                • +
                                                                                              • Update + usage of __WFE() + in low power entry function: + if there is a pending event, + calling __WFE() will not + enter the CortexM4 core to + sleep mode. The solution is + to made the call below; the + first __WFE() + is always ignored and clears + the event if one was already + pending, the second is + always applied
                                                                                                • +
                                                                                              +
                                                                                            +
                                                                                          +
                                                                                          +

                                                                                          __SEV()
                                                                                          +                                                                                           __WFE()
                                                                                          +                                                                                           __WFE()

                                                                                          +
                                                                                          +
                                                                                            +
                                                                                              +
                                                                                            • Add new macro + for software event generation + __HAL_PVD_EXTI_GENERATE_SWIT()
                                                                                              • +
                                                                                            • Remove the + following defines form Generic + driver and add them under + extension driver because they + are only used within extension + functions.
                                                                                              • +
                                                                                                +
                                                                                              • CR_FPDS_BB: + used within HAL_PWREx_EnableFlashPowerDown() + function
                                                                                                • +
                                                                                              • CSR_BRE_BB: + used within HAL_PWREx_EnableBkUpReg() + function
                                                                                                • +
                                                                                              +
                                                                                            • Add the + support of STM32F411xx devices + add the define STM32F411xE
                                                                                              • +
                                                                                                +
                                                                                              • For + STM32F401xC, STM32F401xE and + STM32F411xE devices add the + following functions used to + enable or disable the low + voltage mode for regulators
                                                                                                • +
                                                                                              +
                                                                                            +
                                                                                          +
                                                                                            +
                                                                                              +
                                                                                                +
                                                                                                  +
                                                                                                • HAL_PWREx_EnableMainRegulatorLowVoltage()
                                                                                                  • +
                                                                                                • HAL_PWREx_DisableMainRegulatorLowVoltage()
                                                                                                  • +
                                                                                                • HAL_PWREx_EnableLowRegulatorLowVoltage()
                                                                                                  • +
                                                                                                • HAL_PWREx_DisableLowRegulatorLowVoltage()
                                                                                                  • +
                                                                                                +
                                                                                              +
                                                                                            • For + STM32F42xxx/43xxx devices, add + a new function for Under + Driver management as the macro + already added for this mode is + not sufficient: HAL_PWREx_EnterUnderDriveSTOPMode()
                                                                                              • +
                                                                                            +
                                                                                          +
                                                                                            +
                                                                                          • HAL - New Roman""> update update
                                                                                            • +
                                                                                              +
                                                                                            • In HAL_RCC_ClockConfig() + function: update the AHB clock + divider before clock switch to + new source
                                                                                              • +
                                                                                            • Allow to + calibrate the HSI when it is + used as system clock source
                                                                                              • +
                                                                                            • Rename the + following macros
                                                                                              • +
                                                                                                +
                                                                                              • __OTGFS_FORCE_RESET - New Roman"">
                                                                                                • -
                                                                                                  -
                                                                                                • ()  by + __USB_OTG_FS_FORCE_RESET()
                                                                                                  • +
                                                                                                • __OTGFS_RELEASE_RESET + ()  by  +__USB_OTG_FS_RELEASE_RESET()
                                                                                                  • +
                                                                                                • __OTGFS_CLK_SLEEP_ENABLE - mso-fareast-font-family:"Times - New Roman"">Update macro - parameters to use underscore: - __XXX__
                                                                                                  • -
                                                                                                • ()  by  +__USB_OTG_FS_CLK_SLEEP_ENABLE()
                                                                                                  • +
                                                                                                • __OTGFS_CLK_SLEEP_DISABLE - mso-fareast-font-family:"Times + () by  __USB_OTG_FS_CLK_SLEEP_DISABLE()
                                                                                                  • +
                                                                                                +
                                                                                              +
                                                                                            +

                                                                                             

                                                                                            +
                                                                                              +
                                                                                                +
                                                                                              • Add new field + PLLI2SM in + RCC_PLLI2SInitTypeDef + structure, this division + factor is added for PLLI2S VCO + input clock only STM32F411xE + devices => the FW + compatibility is broken vs. + STM32F401xx devices
                                                                                                • +
                                                                                              • Update HAL_RCCEx_PeriphCLKConfig() + and  HAL_RCCEx_GetPeriphCLKConfig()  - New Roman"">Use of CMSIS - constants instead of magic valuesAdd new + function to manage the new LSE + mode - New Roman"">
                                                                                                • -
                                                                                              • HAL_RCCEx_SelectLSEMode()
                                                                                                • +
                                                                                              • Reorganize + the macros depending from + Part number used and make them + more clear
                                                                                                • +
                                                                                              +
                                                                                            +

                                                                                            �  HAL - mso-fareast-font-family:"Times + UART update

                                                                                            +
                                                                                              +
                                                                                                +
                                                                                              • Add new + macros to control CTS and RTS
                                                                                                • +
                                                                                              • Add specific + macros to manage the flags + cleared only by a software sequence
                                                                                                • +
                                                                                                  +
                                                                                                • __HAL_UART_CLEAR_PEFLAG()
                                                                                                  • +
                                                                                                • __HAL_UART_CLEAR_FEFLAG()
                                                                                                  • +
                                                                                                • __HAL_UART_CLEAR_NEFLAG()
                                                                                                  • +
                                                                                                • __HAL_UART_CLEAR_OREFLAG()
                                                                                                  • +
                                                                                                • __HAL_UART_CLEAR_IDLEFLAG()
                                                                                                  • +
                                                                                                +
                                                                                              • Add several + enhancements without affecting + the driver functionalities +
                                                                                                • +
                                                                                                  +
                                                                                                • Remove the + check on RXNE set after + reading the Data in the DR + register
                                                                                                  • +
                                                                                                • Update the + transmit processes to use + TXE instead of TC
                                                                                                  • +
                                                                                                • Update HAL_UART_Transmit_IT() + to enable UART_IT_TXE + instead of UART_IT_TC
                                                                                                  • +
                                                                                                +
                                                                                              +
                                                                                            +

                                                                                            �  - New Roman"">Use - MODIFY_REG macro in HAL_WWDG_Init()HAL USART + update

                                                                                            +
                                                                                              +
                                                                                                +
                                                                                              • Add specific + macros to manage the flags + cleared only by a software sequence
                                                                                                • +
                                                                                                  +
                                                                                                • __HAL_USART_CLEAR_PEFLAG()
                                                                                                  • +
                                                                                                • __HAL_USART_CLEAR_FEFLAG()
                                                                                                  • +
                                                                                                • __HAL_USART_CLEAR_NEFLAG()
                                                                                                  • +
                                                                                                • __HAL_USART_CLEAR_OREFLAG()
                                                                                                  • +
                                                                                                • __HAL_USART_CLEAR_IDLEFLAG()
                                                                                                  • +
                                                                                                +
                                                                                              • Update HAL_USART_Transmit_IT() + to enable USART_IT_TXE + instead of USART_IT_TC
                                                                                                • +
                                                                                              +
                                                                                            +

                                                                                            �  - New Roman""> -

                                                                                          • HAL IRDA update

                                                                                            +
                                                                                              +
                                                                                                +
                                                                                              • Add specific + macros to manage the flags + cleared only by a software sequence
                                                                                                • +
                                                                                                  +
                                                                                                • __HAL_IRDA_CLEAR_PEFLAG()
                                                                                                  • +
                                                                                                • __HAL_ + IRDA _CLEAR_FEFLAG()
                                                                                                  • +
                                                                                                • __HAL_ + IRDA _CLEAR_NEFLAG()
                                                                                                  • +
                                                                                                • __HAL_ + IRDA _CLEAR_OREFLAG()
                                                                                                  • +
                                                                                                • __HAL_ + IRDA _CLEAR_IDLEFLAG()
                                                                                                  • +
                                                                                                +
                                                                                              • Add several + enhancements without affecting + the driver functionalities
                                                                                                • +
                                                                                              +
                                                                                            +
                                                                                              +
                                                                                                +
                                                                                                  +
                                                                                                • Remove the + check on RXNE set after + reading the Data in the DR + register
                                                                                                  • +
                                                                                                • Update HAL_IRDA_Transmit_IT() + to enable IRDA_IT_TXE + instead of IRDA_IT_TC
                                                                                                  • +
                                                                                                +
                                                                                              • Add the + following APIs used within DMA + process +
                                                                                                • +
                                                                                                  +
                                                                                                • HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef + *hirda);
                                                                                                  • +
                                                                                                • HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef + *hirda);
                                                                                                  • +
                                                                                                • HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef + *hirda); +
                                                                                                  • +
                                                                                                • void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef + *hirda);
                                                                                                  • +
                                                                                                • void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef + *hirda);
                                                                                                  • +
                                                                                                +
                                                                                              +
                                                                                            +

                                                                                            �  - mso-fareast-font-family:"Times - New Roman"">Add - IS_WWDG_ALL_INSTANCE in HAL_WWDG_Init() - and HAL_WWDG_DeInit()HAL SMARTCARD + update

                                                                                            +
                                                                                              +
                                                                                                +
                                                                                              • Add specific + macros to manage the flags + cleared only by a software sequence
                                                                                                • +
                                                                                                  +
                                                                                                • __HAL_SMARTCARD_CLEAR_PEFLAG()
                                                                                                  • +
                                                                                                • __HAL_SMARTCARD_CLEAR_FEFLAG()
                                                                                                  • +
                                                                                                • __HAL_SMARTCARD_CLEAR_NEFLAG()
                                                                                                  • +
                                                                                                • __HAL_SMARTCARD_CLEAR_OREFLAG()
                                                                                                  • +
                                                                                                • __HAL_SMARTCARD_CLEAR_IDLEFLAG()
                                                                                                  • +
                                                                                                +
                                                                                              • Add several + enhancements without affecting + the driver functionalities
                                                                                                • +
                                                                                                  +
                                                                                                • Add a new + state HAL_SMARTCARD_STATE_BUSY_TX_RX + and all processes has been + updated accordingly
                                                                                                  • +
                                                                                                • Update HAL_SMARTCARD_Transmit_IT() + to enable SMARTCARD_IT_TXE + instead of SMARTCARD_IT_TC
                                                                                                  • +
                                                                                                +
                                                                                              +
                                                                                            +
                                                                                              +
                                                                                            • HAL - New Roman"">
                                                                                              • + SPI update +
                                                                                                +
                                                                                              • Bugs fix
                                                                                                • +
                                                                                                  +
                                                                                                • SPI + interface is used in + synchronous polling mode: at + high clock rates like SPI prescaler + 2 and 4, calling
                                                                                                  + HAL_SPI_TransmitReceive() + returns with error + HAL_TIMEOUT                                                                                                   +
                                                                                                  • +
                                                                                                • HAL_SPI_TransmitReceive_DMA() does not + clean up the TX DMA, so any + subsequent SPI calls return + the DMA error
                                                                                                  • +
                                                                                                • HAL_SPI_Transmit_DMA() is failing + when data size is equal to 1 + byte +
                                                                                                  • +
                                                                                                +
                                                                                              • Add the + following APIs used within the + DMA process
                                                                                              -
                                                                                            • +
                                                                                                +
                                                                                                  +
                                                                                                • HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef + *hspi);
                                                                                                  • +
                                                                                                • HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef + *hspi);
                                                                                                  • +
                                                                                                • HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef + *hspi);
                                                                                                  • +
                                                                                                • void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef + *hspi);
                                                                                                  • +
                                                                                                • void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef + *hspi);
                                                                                                  • +
                                                                                                • void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef + *hspi);
                                                                                                  • +
                                                                                                +
                                                                                              +
                                                                                            +
                                                                                              +
                                                                                            • HAL - "Times New Roman"">HAL + RNG update
                                                                                              • +
                                                                                                +
                                                                                                  +
                                                                                                • Add a + conditional define to make + this driver visible for all + STM32F4xx devices except + STM32F401xx and STM32F411xx + Devices.
                                                                                                  • +
                                                                                                +
                                                                                              +
                                                                                            • HAL - IWDGupdate
                                                                                              • +
                                                                                                +
                                                                                                  +
                                                                                                • These + macros are added to + read/write the CRC IDR + register: __HAL_CRC_SET_IDR() + and __HAL_CRC_GET_IDR()
                                                                                                  • +
                                                                                                +
                                                                                              +
                                                                                            +
                                                                                              +
                                                                                            • HAL - New Roman""> updateupdate
                                                                                              • +
                                                                                                +
                                                                                              • Enhance the + DMA channel configuration when + used with DAC
                                                                                                • +
                                                                                              +
                                                                                            • HAL - New Roman"">
                                                                                              • -
                                                                                                -
                                                                                              • update
                                                                                                • +
                                                                                                  +
                                                                                                • HAL_TIM_IRQHandler(): update to + check the input capture + channel 3 and 4 in CCMR2 + instead of CCMR1
                                                                                                  • +
                                                                                                • __HAL_TIM_PRESCALER() + updated to use '=' instead of + '|='
                                                                                                  • +
                                                                                                • Add the + following macro in TIM HAL + driver
                                                                                                  • +
                                                                                                    +
                                                                                                  • __HAL_TIM_GetCompare() +
                                                                                                    • +
                                                                                                  • __HAL_TIM_GetCounter() +
                                                                                                    • +
                                                                                                  • __HAL_TIM_GetAutoreload() +
                                                                                                    • +
                                                                                                  • __HAL_TIM_GetClockDivision() +
                                                                                                    • +
                                                                                                  • __HAL_TIM_GetICPrescaler()
                                                                                                    • +
                                                                                                  +
                                                                                                +
                                                                                              • HAL - mso-fareast-font-family:"Times + SDMMC update
                                                                                                • +
                                                                                              +
                                                                                                +
                                                                                                  +
                                                                                                • Use of CMSIS + constants instead of magic values
                                                                                                  • +
                                                                                                • Miscellaneous + update in functions internal + coding
                                                                                                  • +
                                                                                                +
                                                                                              • HAL - New Roman"">Use WRITE_REG - instead of SET_BIT for all - IWDG macrosupdate
                                                                                                • +
                                                                                                  +
                                                                                                • Fix - New Roman"">
                                                                                                  • -
                                                                                                • blocks
                                                                                                  • +
                                                                                                • Fix + issue for read/write NAND + page/spare area
                                                                                                  • +
                                                                                                +
                                                                                              • HAL - mso-fareast-font-family:"Times + NOR update
                                                                                                • +
                                                                                                  +
                                                                                                • Add - New Roman"">__HAL_IWDG_CLEAR_FLAG + the NOR address bank macro + used within the API
                                                                                                  • +
                                                                                                • Update - removed: no IWDG flag cleared - by access to SR registercoded
                                                                                                  • +
                                                                                                +
                                                                                              • HAL - New Roman"">
                                                                                                • -
                                                                                              • update
                                                                                                • +
                                                                                                  +
                                                                                                • HCD_StateTypeDef structure + members renamed
                                                                                                  • +
                                                                                                • These macro are renamed
                                                                                                  • +
                                                                                                    +
                                                                                                  • __HAL_GET_FLAG(__HANDLE__, - mso-fareast-font-family:"Times + __INTERRUPT__)    - New Roman"">Use - MODIFY_REG macro in HAL_IWDG_Init()
                                                                                                    • +
                                                                                                  • __HAL_CLEAR_FLAG(__HANDLE__, - New Roman"">
                                                                                                    • -
                                                                                                    • +
                                                                                                  • __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  - mso-fareast-font-family:"Times + by + __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)  +
                                                                                                    • +
                                                                                                  +
                                                                                                +
                                                                                              • HAL - New Roman"">Add - IS_IWDG_ALL_INSTANCE in HAL_IWDG_Init()Add + PCD update
                                                                                                • +
                                                                                                  +
                                                                                                • HAL_PCD_SetTxFiFo() and HAL_PCD_SetRxFiFo() - the following macros used to - Wake
                                                                                                  • -
                                                                                                -
                                                                                              -

                                                                                              HAL_PCDEx_SetTxFiFo() - New Roman";color:white">V1.0.0 - / 18-February-2014

                                                                                              -

                                                                                              Main Changes

                                                                                              -
                                                                                                -
                                                                                              • HAL_PCDEx_SetRxFiFo() - "Times New Roman"">First + and moved to the extension + files + stm32f4xx_hal_pcd_ex.h/.c
                                                                                                • +
                                                                                              • PCD_StateTypeDef structure + members renamed
                                                                                                • +
                                                                                              • Fix incorrect + masking of TxFIFOEmpty
                                                                                                • +
                                                                                              • stm32f4xx_ll_usb.c: - official release
                                                                                                • -
                                                                                              -

                                                                                              +
                                                                                            • New macros added
                                                                                              • +
                                                                                                +
                                                                                              • __HAL_PCD_IS_PHY_SUSPENDED()
                                                                                                • +
                                                                                              • __HAL_USB_HS_EXTI_GENERATE_SWIT()
                                                                                                • +
                                                                                              • __HAL_USB_FS_EXTI_GENERATE_SWIT()
                                                                                                • +
                                                                                              +
                                                                                            • These macro are renamed
                                                                                              • +
                                                                                                +
                                                                                              • __HAL_GET_FLAG(__HANDLE__, - New Roman"; color:white">License

                                                                                              -

                                                                                              Redistribution + __INTERRUPT__)    - and use in source and binary - forms, with or without - modification, are permitted - provided that the following - conditions are met:

                                                                                              -
                                                                                                -
                                                                                                2. +
                                                                                              2. __HAL_CLEAR_FLAG(__HANDLE__, - level1 lfo142;tab-stops:list .5in">
                                                                                                3. +
                                                                                              3. __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  - "Times New Roman"">Redistributions + by + __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)  +
                                                                                                4. +
                                                                                              4. __HAL_PCD_UNGATE_CLOCK(__HANDLE__) - of source code must retain the - above copyright notice, this - list of conditions and the - following disclaimer.
                                                                                                5. +
                                                                                              5. __HAL_PCD_GATE_CLOCK(__HANDLE__) - "Times New Roman"">
                                                                                                6. -
                                                                                                7. +
                                                                                            +
                                                                                          +
                                                                                        • HAL - level1 lfo142;tab-stops:list .5in">update
                                                                                          • +
                                                                                            +
                                                                                          • Update HAL_ETH_GetReceivedFrame_IT() + function to return HAL_ERROR + if the received packet is not + complete
                                                                                            • +
                                                                                          • Use HAL_Delay() + instead of counting loop
                                                                                            • +
                                                                                          •  __HAL_ETH_MAC_CLEAR_FLAG() + macro is removed: the MACSR + register is read only
                                                                                            • +
                                                                                          • Add the + following macros used to Wake + up the device from STOP mode + by Ethernet event - "Times New Roman"">Redistributions + :
                                                                                            • +
                                                                                              +
                                                                                            • __HAL_ETH_EXTI_ENABLE_IT()
                                                                                              • +
                                                                                            • __HAL_ETH_EXTI_DISABLE_IT()
                                                                                              • +
                                                                                            • __HAL_ETH_EXTI_GET_FLAG()
                                                                                              • +
                                                                                            • __HAL_ETH_EXTI_CLEAR_FLAG()
                                                                                              • +
                                                                                            • __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER()
                                                                                              • +
                                                                                            • __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER()
                                                                                              • +
                                                                                            • __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER()
                                                                                              • +
                                                                                            +
                                                                                          +
                                                                                        • HAL - in binary form must reproduce - the above copyright notice, this - list of conditions and the - following disclaimer in the - documentation and/or other - materials provided with the - distribution.
                                                                                          • -
                                                                                        • update
                                                                                          • +
                                                                                            +
                                                                                          • Update macro + parameters to use underscore: + __XXX__
                                                                                            • +
                                                                                          • Use of CMSIS + constants instead of magic values
                                                                                            • +
                                                                                          • Use + MODIFY_REG macro in HAL_WWDG_Init()
                                                                                            • +
                                                                                          • Add + IS_WWDG_ALL_INSTANCE in HAL_WWDG_Init() + and HAL_WWDG_DeInit()
                                                                                            • +
                                                                                          +
                                                                                        • HAL - level1 lfo142;tab-stops:list .5in"> update
                                                                                          • +
                                                                                            +
                                                                                          • Use WRITE_REG + instead of SET_BIT for all + IWDG macros
                                                                                            • +
                                                                                          • __HAL_IWDG_CLEAR_FLAG - "Times New Roman"">Neither + removed: no IWDG flag cleared + by access to SR register
                                                                                            • +
                                                                                          • Use + MODIFY_REG macro in HAL_IWDG_Init()
                                                                                            • +
                                                                                          • Add + IS_IWDG_ALL_INSTANCE in HAL_IWDG_Init()Add - the name of STMicroelectronics - nor the names of its - contributors may be used to - endorse or promote products - derived
                                                                                            • - -

                                                                                                   + the following macros used to + Wake +

                                                                                          +
                                                                                        +

                                                                                        V1.0.0 - from this software without - specific prior written permission.
                                                                                        -
                                                                                        -                                                                                         THIS + / 18-February-2014

                                                                                        +

                                                                                        Main Changes

                                                                                        +
                                                                                          +
                                                                                        • First - SOFTWARE IS PROVIDED BY THE - COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED - WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES - OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE - COPYRIGHT HOLDER OR CONTRIBUTORS - BE LIABLE FOR ANY DIRECT, - INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL - DAMAGES (INCLUDING, BUT NOT - LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS - OF USE, DATA, OR PROFITS; OR - BUSINESS INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, - STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR - OTHERWISE) ARISING IN ANY WAY OUT - OF THE USE OF THIS SOFTWARE, EVEN - IF ADVISED OF THE POSSIBILITY OF - SUCH DAMAGE.

                                                                                          -
                                                                                          -
                                                                                          -

                                                                                          For + official release 

                                                                                          • +
                                                                                        +
                                                                                        +

                                                                                        For - complete documentation on STM32 - Microcontrollers visit www.st.com/STM32

                                                                                        + complete documentation on STM32 + Microcontrollers visit www.st.com/STM32
    -

     

    +
    +

     
    -

    +

    -

     

    +

     

    - - + \ No newline at end of file diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/Legacy/stm32f4xx_hal_can.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/Legacy/stm32f4xx_hal_can.c index 398c643931..1c5757dec7 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/Legacy/stm32f4xx_hal_can.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/Legacy/stm32f4xx_hal_can.c @@ -9,6 +9,17 @@ * + Peripheral Control functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### User NOTE ##### @@ -79,33 +90,6 @@ @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ****************************************************************************** */ @@ -1693,5 +1677,3 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/Legacy/stm32f4xx_hal_eth.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/Legacy/stm32f4xx_hal_eth.c new file mode 100644 index 0000000000..8de9453a8b --- /dev/null +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/Legacy/stm32f4xx_hal_eth.c @@ -0,0 +1,2307 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_eth.c + * @author MCD Application Team + * @brief ETH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Ethernet (ETH) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Declare a ETH_HandleTypeDef handle structure, for example: + ETH_HandleTypeDef heth; + + (#)Fill parameters of Init structure in heth handle + + (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) + + (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: + (##) Enable the Ethernet interface clock using + (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); + (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); + (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); + + (##) Initialize the related GPIO clocks + (##) Configure Ethernet pin-out + (##) Configure Ethernet NVIC interrupt (IT mode) + + (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: + (##) HAL_ETH_DMATxDescListInit(); for Transmission process + (##) HAL_ETH_DMARxDescListInit(); for Reception process + + (#)Enable MAC and DMA transmission and reception: + (##) HAL_ETH_Start(); + + (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer + the frame to MAC TX FIFO: + (##) HAL_ETH_TransmitFrame(); + + (#)Poll for a received frame in ETH RX DMA Descriptors and get received + frame parameters + (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) + + (#) Get a received frame when an ETH RX interrupt occurs: + (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) + + (#) Communicate with external PHY device: + (##) Read a specific register from the PHY + HAL_ETH_ReadPHYRegister(); + (##) Write data to a specific RHY register: + HAL_ETH_WritePHYRegister(); + + (#) Configure the Ethernet MAC after ETH peripheral initialization + HAL_ETH_ConfigMAC(); all MAC parameters should be filled. + + (#) Configure the Ethernet DMA after ETH peripheral initialization + HAL_ETH_ConfigDMA(); all DMA parameters should be filled. + + -@- The PTP protocol and the DMA descriptors ring mode are not supported + in this driver +*** Callback registration *** + ============================================= + + The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback. + + Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) DMAErrorCallback : DMA Error Callback. + (+) MspInitCallback : MspInit Callback. + (+) MspDeInitCallback: MspDeInit Callback. + + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) DMAErrorCallback : DMA Error Callback. + (+) MspInitCallback : MspInit Callback. + (+) MspDeInitCallback: MspDeInit Callback. + + By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit + or HAL_ETH_Init function. + + When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup ETH ETH + * @brief ETH HAL module driver + * @{ + */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + +#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ETH_Private_Constants ETH Private Constants + * @{ + */ +#define ETH_TIMEOUT_SWRESET 500U +#define ETH_TIMEOUT_LINKED_STATE 5000U +#define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ETH_Private_Functions ETH Private Functions + * @{ + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err); +static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr); +static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth); +static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth); +static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth); +static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth); +static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth); +static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth); +static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth); +static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth); +static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); +static void ETH_Delay(uint32_t mdelay); +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ETH_Exported_Functions ETH Exported Functions + * @{ + */ + +/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the Ethernet peripheral + (+) De-initialize the Ethernet peripheral + + @endverbatim + * @{ + */ + +/** + * @brief Initializes the Ethernet MAC and DMA according to default + * parameters. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) +{ + uint32_t tmpreg1 = 0U, phyreg = 0U; + uint32_t hclk = 60000000U; + uint32_t tickstart = 0U; + uint32_t err = ETH_SUCCESS; + + /* Check the ETH peripheral state */ + if(heth == NULL) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation)); + assert_param(IS_ETH_RX_MODE(heth->Init.RxMode)); + assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode)); + assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); + + if(heth->State == HAL_ETH_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + heth->Lock = HAL_UNLOCKED; +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + ETH_InitCallbacksToDefault(heth); + + if(heth->MspInitCallback == NULL) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC. */ + heth->MspInitCallback = HAL_ETH_MspInit; + } + heth->MspInitCallback(heth); + +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspInit(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Select MII or RMII Mode*/ + SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); + SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; + + /* Ethernet Software reset */ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + (heth->Instance)->DMABMR |= ETH_DMABMR_SR; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for software reset */ + while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET) + { + heth->State= HAL_ETH_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are + not available, please check your external PHY or the IO configuration */ + return HAL_TIMEOUT; + } + } + + /*-------------------------------- MAC Initialization ----------------------*/ + /* Get the ETHERNET MACMIIAR value */ + tmpreg1 = (heth->Instance)->MACMIIAR; + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg1 &= ETH_MACMIIAR_CR_MASK; + + /* Get hclk frequency value */ + hclk = HAL_RCC_GetHCLKFreq(); + + /* Set CR bits depending on hclk value */ + if((hclk >= 20000000U)&&(hclk < 35000000U)) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16; + } + else if((hclk >= 35000000U)&&(hclk < 60000000U)) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26; + } + else if((hclk >= 60000000U)&&(hclk < 100000000U)) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + else if((hclk >= 100000000U)&&(hclk < 150000000U)) + { + /* CSR Clock Range between 100-150 MHz */ + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62; + } + else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */ + { + /* CSR Clock Range between 150-183 MHz */ + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102; + } + + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ + (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1; + + /*-------------------- PHY initialization and configuration ----------------*/ + /* Put the PHY in reset mode */ + if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + /* Set the ETH peripheral state to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Return HAL_ERROR */ + return HAL_ERROR; + } + + /* Delay to assure PHY reset */ + HAL_Delay(PHY_RESET_DELAY); + + if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* We wait for linked status */ + do + { + HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); + + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + return HAL_TIMEOUT; + } + } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS)); + + + /* Enable Auto-Negotiation */ + if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + /* Set the ETH peripheral state to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Return HAL_ERROR */ + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the auto-negotiation will be completed */ + do + { + HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); + + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + return HAL_TIMEOUT; + } + + } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE)); + + /* Read the result of the auto-negotiation */ + if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + /* Set the ETH peripheral state to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Return HAL_ERROR */ + return HAL_ERROR; + } + + /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */ + if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET) + { + /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */ + (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; + } + else + { + /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */ + (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; + } + /* Configure the MAC with the speed fixed by the auto-negotiation process */ + if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS) + { + /* Set Ethernet speed to 10M following the auto-negotiation */ + (heth->Init).Speed = ETH_SPEED_10M; + } + else + { + /* Set Ethernet speed to 100M following the auto-negotiation */ + (heth->Init).Speed = ETH_SPEED_100M; + } + } + else /* AutoNegotiation Disable */ + { + /* Check parameters */ + assert_param(IS_ETH_SPEED(heth->Init.Speed)); + assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); + + /* Set MAC Speed and Duplex Mode */ + if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) | + (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + /* Set the ETH peripheral state to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Return HAL_ERROR */ + return HAL_ERROR; + } + + /* Delay to assure PHY configuration */ + HAL_Delay(PHY_CONFIG_DELAY); + } + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + /* Set ETH HAL State to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief De-Initializes the ETH peripheral. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) +{ + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + if(heth->MspDeInitCallback == NULL) + { + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + } + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ + heth->MspDeInitCallback(heth); +#else + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspDeInit(heth); +#endif + + /* Set ETH HAL state to Disabled */ + heth->State= HAL_ETH_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the DMA Tx descriptors in chain mode. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param DMATxDescTab Pointer to the first Tx desc list + * @param TxBuff Pointer to the first TxBuffer list + * @param TxBuffCount Number of the used Tx desc in the list + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0U; + ETH_DMADescTypeDef *dmatxdesc; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + heth->TxDesc = DMATxDescTab; + + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0U; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + dmatxdesc = DMATxDescTab + i; + + /* Set Second Address Chained bit */ + dmatxdesc->Status = ETH_DMATXDESC_TCH; + + /* Set Buffer1 address pointer */ + dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]); + + if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) + { + /* Set the DMA Tx descriptors checksum insertion */ + dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; + } + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + if(i < (TxBuffCount-1U)) + { + /* Set next descriptor address register with next descriptor base address */ + dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + } + } + + /* Set Transmit Descriptor List Address Register */ + (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab; + + /* Set ETH HAL State to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param DMARxDescTab Pointer to the first Rx desc list + * @param RxBuff Pointer to the first RxBuffer list + * @param RxBuffCount Number of the used Rx desc in the list + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0U; + ETH_DMADescTypeDef *DMARxDesc; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */ + heth->RxDesc = DMARxDescTab; + + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0U; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARXDESC_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; + + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]); + + if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) + { + /* Enable Ethernet DMA Rx Descriptor interrupt */ + DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC; + } + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + if(i < (RxBuffCount-1U)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + /* Set Receive Descriptor List Address Register */ + (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab; + + /* Set ETH HAL State to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the ETH MSP. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes ETH MSP. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ETH Callback + * To be used instead of the weak predefined callback + * @param heth eth handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID + * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(heth); + + if(heth->State == HAL_ETH_STATE_READY) + { + switch (CallbackID) + { + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = pCallback; + break; + + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = pCallback; + break; + + case HAL_ETH_DMA_ERROR_CB_ID : + heth->DMAErrorCallback = pCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(heth->State == HAL_ETH_STATE_RESET) + { + switch (CallbackID) + { + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(heth); + + return status; +} + +/** + * @brief Unregister an ETH Callback + * ETH callabck is redirected to the weak predefined callback + * @param heth eth handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID + * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(heth); + + if(heth->State == HAL_ETH_STATE_READY) + { + switch (CallbackID) + { + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = HAL_ETH_TxCpltCallback; + break; + + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = HAL_ETH_RxCpltCallback; + break; + + case HAL_ETH_DMA_ERROR_CB_ID : + heth->DMAErrorCallback = HAL_ETH_ErrorCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(heth->State == HAL_ETH_STATE_RESET) + { + switch (CallbackID) + { + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(heth); + + return status; +} +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * + @verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Transmit a frame + HAL_ETH_TransmitFrame(); + (+) Receive a frame + HAL_ETH_GetReceivedFrame(); + HAL_ETH_GetReceivedFrame_IT(); + (+) Read from an External PHY register + HAL_ETH_ReadPHYRegister(); + (+) Write to an External PHY register + HAL_ETH_WritePHYRegister(); + + @endverbatim + + * @{ + */ + +/** + * @brief Sends an Ethernet frame. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param FrameLength Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) +{ + uint32_t bufcount = 0U, size = 0U, i = 0U; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + if (FrameLength == 0U) + { + /* Set ETH HAL state to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + return HAL_ERROR; + } + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) + { + /* OWN bit set */ + heth->State = HAL_ETH_STATE_BUSY_TX; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + return HAL_ERROR; + } + + /* Get the number of needed Tx buffers for the current frame */ + if (FrameLength > ETH_TX_BUF_SIZE) + { + bufcount = FrameLength/ETH_TX_BUF_SIZE; + if (FrameLength % ETH_TX_BUF_SIZE) + { + bufcount++; + } + } + else + { + bufcount = 1U; + } + if (bufcount == 1U) + { + /* Set LAST and FIRST segment */ + heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS; + /* Set frame size */ + heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1); + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + heth->TxDesc->Status |= ETH_DMATXDESC_OWN; + /* Point to next descriptor */ + heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); + } + else + { + for (i=0U; i< bufcount; i++) + { + /* Clear FIRST and LAST segment bits */ + heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); + + if (i == 0U) + { + /* Setting the first segment bit */ + heth->TxDesc->Status |= ETH_DMATXDESC_FS; + } + + /* Program size */ + heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1); + + if (i == (bufcount-1U)) + { + /* Setting the last segment bit */ + heth->TxDesc->Status |= ETH_DMATXDESC_LS; + size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE; + heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); + } + + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + heth->TxDesc->Status |= ETH_DMATXDESC_OWN; + /* point to next descriptor */ + heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); + } + } + + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + (heth->Instance)->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + (heth->Instance)->DMATPDR = 0U; + } + + /* Set ETH HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Checks for received frames. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) +{ + uint32_t framelength = 0U; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Check the ETH state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Check if segment is not owned by DMA */ + /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */ + if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET)) + { + /* Check if last segment */ + if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) + { + /* increment segment count */ + (heth->RxFrameInfos).SegCount++; + + /* Check if last segment is first segment: one segment contains the frame */ + if ((heth->RxFrameInfos).SegCount == 1U) + { + (heth->RxFrameInfos).FSRxDesc =heth->RxDesc; + } + + heth->RxFrameInfos.LSRxDesc = heth->RxDesc; + + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; + heth->RxFrameInfos.length = framelength; + + /* Get the address of the buffer start address */ + heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; + /* point to next descriptor */ + heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr); + + /* Set HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; + } + /* Check if first segment */ + else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) + { + (heth->RxFrameInfos).FSRxDesc = heth->RxDesc; + (heth->RxFrameInfos).LSRxDesc = NULL; + (heth->RxFrameInfos).SegCount = 1U; + /* Point to next descriptor */ + heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); + } + /* Check if intermediate segment */ + else + { + (heth->RxFrameInfos).SegCount++; + /* Point to next descriptor */ + heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); + } + } + + /* Set ETH HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_ERROR; +} + +/** + * @brief Gets the Received frame in interrupt mode. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) +{ + uint32_t descriptorscancounter = 0U; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set ETH HAL State to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Scan descriptors owned by CPU */ + while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB)) + { + /* Just for security */ + descriptorscancounter++; + + /* Check if first segment in frame */ + /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ + if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS) + { + heth->RxFrameInfos.FSRxDesc = heth->RxDesc; + heth->RxFrameInfos.SegCount = 1U; + /* Point to next descriptor */ + heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); + } + /* Check if intermediate segment */ + /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */ + else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET) + { + /* Increment segment count */ + (heth->RxFrameInfos.SegCount)++; + /* Point to next descriptor */ + heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr); + } + /* Should be last segment */ + else + { + /* Last segment */ + heth->RxFrameInfos.LSRxDesc = heth->RxDesc; + + /* Increment segment count */ + (heth->RxFrameInfos.SegCount)++; + + /* Check if last segment is first segment: one segment contains the frame */ + if ((heth->RxFrameInfos.SegCount) == 1U) + { + heth->RxFrameInfos.FSRxDesc = heth->RxDesc; + } + + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; + + /* Get the address of the buffer start address */ + heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; + + /* Point to next descriptor */ + heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); + + /* Set HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; + } + } + + /* Set HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_ERROR; +} + +/** + * @brief This function handles ETH interrupt request. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) +{ + /* Frame received */ + if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) + { +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Receive complete callback*/ + heth->RxCpltCallback(heth); +#else + /* Receive complete callback */ + HAL_ETH_RxCpltCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Clear the Eth DMA Rx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R); + + /* Set HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + } + /* Frame transmitted */ + else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) + { +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call resgistered Transfer complete callback*/ + heth->TxCpltCallback(heth); +#else + /* Transfer complete callback */ + HAL_ETH_TxCpltCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Clear the Eth DMA Tx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T); + + /* Set HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + } + + /* Clear the interrupt flags */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS); + + /* ETH DMA Error */ + if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS)) + { +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->DMAErrorCallback(heth); +#else + /* Ethernet Error callback */ + HAL_ETH_ErrorCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Clear the interrupt flags */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS); + + /* Set HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Ethernet transfer error callbacks + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Reads a PHY register + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Basic Control Register, + * PHY_BSR: Transceiver Basic Status Register. + * More PHY register could be read depending on the used PHY + * @param RegValue PHY register value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) +{ + uint32_t tmpreg1 = 0U; + uint32_t tickstart = 0U; + + /* Check parameters */ + assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); + + /* Check the ETH peripheral state */ + if(heth->State == HAL_ETH_STATE_BUSY_RD) + { + return HAL_BUSY; + } + /* Set ETH HAL State to BUSY_RD */ + heth->State = HAL_ETH_STATE_BUSY_RD; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg1 = heth->Instance->MACMIIAR; + + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; + + /* Prepare the MII address register value */ + tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + + /* Write the result value into the MII Address register */ + heth->Instance->MACMIIAR = tmpreg1; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check for the Busy flag */ + while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > PHY_READ_TO) + { + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + return HAL_TIMEOUT; + } + + tmpreg1 = heth->Instance->MACMIIAR; + } + + /* Get MACMIIDR value */ + *RegValue = (uint16_t)(heth->Instance->MACMIIDR); + + /* Set ETH HAL State to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Writes to a PHY register. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Control Register. + * More PHY register could be written depending on the used PHY + * @param RegValue the value to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) +{ + uint32_t tmpreg1 = 0U; + uint32_t tickstart = 0U; + + /* Check parameters */ + assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); + + /* Check the ETH peripheral state */ + if(heth->State == HAL_ETH_STATE_BUSY_WR) + { + return HAL_BUSY; + } + /* Set ETH HAL State to BUSY_WR */ + heth->State = HAL_ETH_STATE_BUSY_WR; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg1 = heth->Instance->MACMIIAR; + + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; + + /* Prepare the MII register address value */ + tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + + /* Give the value to the MII data register */ + heth->Instance->MACMIIDR = (uint16_t)RegValue; + + /* Write the result value into the MII Address register */ + heth->Instance->MACMIIAR = tmpreg1; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check for the Busy flag */ + while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO) + { + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + return HAL_TIMEOUT; + } + + tmpreg1 = heth->Instance->MACMIIAR; + } + + /* Set ETH HAL State to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable MAC and DMA transmission and reception. + HAL_ETH_Start(); + (+) Disable MAC and DMA transmission and reception. + HAL_ETH_Stop(); + (+) Set the MAC configuration in runtime mode + HAL_ETH_ConfigMAC(); + (+) Set the DMA configuration in runtime mode + HAL_ETH_ConfigDMA(); + +@endverbatim + * @{ + */ + + /** + * @brief Enables Ethernet MAC and DMA reception/transmission + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) +{ + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Enable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionEnable(heth); + + /* Enable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionEnable(heth); + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); + + /* Start DMA transmission */ + ETH_DMATransmissionEnable(heth); + + /* Start DMA reception */ + ETH_DMAReceptionEnable(heth); + + /* Set the ETH state to READY*/ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop Ethernet MAC and DMA reception/transmission + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) +{ + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Stop DMA transmission */ + ETH_DMATransmissionDisable(heth); + + /* Stop DMA reception */ + ETH_DMAReceptionDisable(heth); + + /* Disable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionDisable(heth); + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); + + /* Disable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionDisable(heth); + + /* Set the ETH state*/ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set ETH MAC Configuration. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param macconf MAC Configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) +{ + uint32_t tmpreg1 = 0U; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State= HAL_ETH_STATE_BUSY; + + assert_param(IS_ETH_SPEED(heth->Init.Speed)); + assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); + + if (macconf != NULL) + { + /* Check the parameters */ + assert_param(IS_ETH_WATCHDOG(macconf->Watchdog)); + assert_param(IS_ETH_JABBER(macconf->Jabber)); + assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap)); + assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense)); + assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn)); + assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode)); + assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload)); + assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission)); + assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip)); + assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit)); + assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck)); + assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll)); + assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter)); + assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames)); + assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception)); + assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter)); + assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode)); + assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter)); + assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter)); + assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime)); + assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause)); + assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold)); + assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect)); + assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl)); + assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl)); + assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison)); + assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier)); + + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg1 = (heth->Instance)->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg1 &= ETH_MACCR_CLEAR_MASK; + + tmpreg1 |= (uint32_t)(macconf->Watchdog | + macconf->Jabber | + macconf->InterFrameGap | + macconf->CarrierSense | + (heth->Init).Speed | + macconf->ReceiveOwn | + macconf->LoopbackMode | + (heth->Init).DuplexMode | + macconf->ChecksumOffload | + macconf->RetryTransmission | + macconf->AutomaticPadCRCStrip | + macconf->BackOffLimit | + macconf->DeferralCheck); + + /* Write to ETHERNET MACCR */ + (heth->Instance)->MACCR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Write to ETHERNET MACFFR */ + (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | + macconf->SourceAddrFilter | + macconf->PassControlFrames | + macconf->BroadcastFramesReception | + macconf->DestinationAddrFilter | + macconf->PromiscuousMode | + macconf->MulticastFramesFilter | + macconf->UnicastFramesFilter); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACFFR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACFFR = tmpreg1; + + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ + /* Write to ETHERNET MACHTHR */ + (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh; + + /* Write to ETHERNET MACHTLR */ + (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + + /* Get the ETHERNET MACFCR value */ + tmpreg1 = (heth->Instance)->MACFCR; + /* Clear xx bits */ + tmpreg1 &= ETH_MACFCR_CLEAR_MASK; + + tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | + macconf->ZeroQuantaPause | + macconf->PauseLowThreshold | + macconf->UnicastPauseFrameDetect | + macconf->ReceiveFlowControl | + macconf->TransmitFlowControl); + + /* Write to ETHERNET MACFCR */ + (heth->Instance)->MACFCR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACFCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACFCR = tmpreg1; + + /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ + (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | + macconf->VLANTagIdentifier); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACVLANTR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACVLANTR = tmpreg1; + } + else /* macconf == NULL : here we just configure Speed and Duplex mode */ + { + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg1 = (heth->Instance)->MACCR; + + /* Clear FES and DM bits */ + tmpreg1 &= ~(0x00004800U); + + tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); + + /* Write to ETHERNET MACCR */ + (heth->Instance)->MACCR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + } + + /* Set the ETH state to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Sets ETH DMA Configuration. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param dmaconf DMA Configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) +{ + uint32_t tmpreg1 = 0U; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State= HAL_ETH_STATE_BUSY; + + /* Check parameters */ + assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame)); + assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward)); + assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame)); + assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward)); + assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl)); + assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames)); + assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames)); + assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl)); + assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate)); + assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats)); + assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst)); + assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength)); + assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength)); + assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat)); + assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength)); + assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration)); + + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg1 = (heth->Instance)->DMAOMR; + /* Clear xx bits */ + tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; + + tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | + dmaconf->ReceiveStoreForward | + dmaconf->FlushReceivedFrame | + dmaconf->TransmitStoreForward | + dmaconf->TransmitThresholdControl | + dmaconf->ForwardErrorFrames | + dmaconf->ForwardUndersizedGoodFrames | + dmaconf->ReceiveThresholdControl | + dmaconf->SecondFrameOperate); + + /* Write to ETHERNET DMAOMR */ + (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMAOMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMAOMR = tmpreg1; + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | + dmaconf->FixedBurst | + dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + dmaconf->TxDMABurstLength | + dmaconf->EnhancedDescriptorFormat | + (dmaconf->DescriptorSkipLength << 2U) | + dmaconf->DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMABMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMABMR = tmpreg1; + + /* Set the ETH state to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * + @verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + (+) Get the ETH handle state: + HAL_ETH_GetState(); + + + @endverbatim + * @{ + */ + +/** + * @brief Return the ETH HAL state + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL state + */ +HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) +{ + /* Return ETH state */ + return heth->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup ETH_Private_Functions + * @{ + */ + +/** + * @brief Configures Ethernet MAC and DMA with default parameters. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param err Ethernet Init error + * @retval HAL status + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) +{ + ETH_MACInitTypeDef macinit; + ETH_DMAInitTypeDef dmainit; + uint32_t tmpreg1 = 0U; + + if (err != ETH_SUCCESS) /* Auto-negotiation failed */ + { + /* Set Ethernet duplex mode to Full-duplex */ + (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; + + /* Set Ethernet speed to 100M */ + (heth->Init).Speed = ETH_SPEED_100M; + } + + /* Ethernet MAC default initialization **************************************/ + macinit.Watchdog = ETH_WATCHDOG_ENABLE; + macinit.Jabber = ETH_JABBER_ENABLE; + macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT; + macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE; + macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE; + macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE; + if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) + { + macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; + } + else + { + macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; + } + macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE; + macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; + macinit.BackOffLimit = ETH_BACKOFFLIMIT_10; + macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE; + macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE; + macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; + macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; + macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; + macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; + macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; + macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; + macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; + macinit.HashTableHigh = 0x0U; + macinit.HashTableLow = 0x0U; + macinit.PauseTime = 0x0U; + macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; + macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; + macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; + macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; + macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; + macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; + macinit.VLANTagIdentifier = 0x0U; + + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg1 = (heth->Instance)->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg1 &= ETH_MACCR_CLEAR_MASK; + /* Set the WD bit according to ETH Watchdog value */ + /* Set the JD: bit according to ETH Jabber value */ + /* Set the IFG bit according to ETH InterFrameGap value */ + /* Set the DCRS bit according to ETH CarrierSense value */ + /* Set the FES bit according to ETH Speed value */ + /* Set the DO bit according to ETH ReceiveOwn value */ + /* Set the LM bit according to ETH LoopbackMode value */ + /* Set the DM bit according to ETH Mode value */ + /* Set the IPCO bit according to ETH ChecksumOffload value */ + /* Set the DR bit according to ETH RetryTransmission value */ + /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ + /* Set the BL bit according to ETH BackOffLimit value */ + /* Set the DC bit according to ETH DeferralCheck value */ + tmpreg1 |= (uint32_t)(macinit.Watchdog | + macinit.Jabber | + macinit.InterFrameGap | + macinit.CarrierSense | + (heth->Init).Speed | + macinit.ReceiveOwn | + macinit.LoopbackMode | + (heth->Init).DuplexMode | + macinit.ChecksumOffload | + macinit.RetryTransmission | + macinit.AutomaticPadCRCStrip | + macinit.BackOffLimit | + macinit.DeferralCheck); + + /* Write to ETHERNET MACCR */ + (heth->Instance)->MACCR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Set the RA bit according to ETH ReceiveAll value */ + /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ + /* Set the PCF bit according to ETH PassControlFrames value */ + /* Set the DBF bit according to ETH BroadcastFramesReception value */ + /* Set the DAIF bit according to ETH DestinationAddrFilter value */ + /* Set the PR bit according to ETH PromiscuousMode value */ + /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ + /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ + /* Write to ETHERNET MACFFR */ + (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | + macinit.SourceAddrFilter | + macinit.PassControlFrames | + macinit.BroadcastFramesReception | + macinit.DestinationAddrFilter | + macinit.PromiscuousMode | + macinit.MulticastFramesFilter | + macinit.UnicastFramesFilter); + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACFFR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACFFR = tmpreg1; + + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ + /* Write to ETHERNET MACHTHR */ + (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh; + + /* Write to ETHERNET MACHTLR */ + (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration -------------------*/ + + /* Get the ETHERNET MACFCR value */ + tmpreg1 = (heth->Instance)->MACFCR; + /* Clear xx bits */ + tmpreg1 &= ETH_MACFCR_CLEAR_MASK; + + /* Set the PT bit according to ETH PauseTime value */ + /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ + /* Set the PLT bit according to ETH PauseLowThreshold value */ + /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ + /* Set the RFE bit according to ETH ReceiveFlowControl value */ + /* Set the TFE bit according to ETH TransmitFlowControl value */ + tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) | + macinit.ZeroQuantaPause | + macinit.PauseLowThreshold | + macinit.UnicastPauseFrameDetect | + macinit.ReceiveFlowControl | + macinit.TransmitFlowControl); + + /* Write to ETHERNET MACFCR */ + (heth->Instance)->MACFCR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACFCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACFCR = tmpreg1; + + /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ + /* Set the ETV bit according to ETH VLANTagComparison value */ + /* Set the VL bit according to ETH VLANTagIdentifier value */ + (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | + macinit.VLANTagIdentifier); + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACVLANTR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACVLANTR = tmpreg1; + + /* Ethernet DMA default initialization ************************************/ + dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; + dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; + dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; + dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; + dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; + dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; + dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; + dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; + dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE; + dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; + dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE; + dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE; + dmainit.DescriptorSkipLength = 0x0U; + dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; + + /* Get the ETHERNET DMAOMR value */ + tmpreg1 = (heth->Instance)->DMAOMR; + /* Clear xx bits */ + tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; + + /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ + /* Set the RSF bit according to ETH ReceiveStoreForward value */ + /* Set the DFF bit according to ETH FlushReceivedFrame value */ + /* Set the TSF bit according to ETH TransmitStoreForward value */ + /* Set the TTC bit according to ETH TransmitThresholdControl value */ + /* Set the FEF bit according to ETH ForwardErrorFrames value */ + /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ + /* Set the RTC bit according to ETH ReceiveThresholdControl value */ + /* Set the OSF bit according to ETH SecondFrameOperate value */ + tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | + dmainit.ReceiveStoreForward | + dmainit.FlushReceivedFrame | + dmainit.TransmitStoreForward | + dmainit.TransmitThresholdControl | + dmainit.ForwardErrorFrames | + dmainit.ForwardUndersizedGoodFrames | + dmainit.ReceiveThresholdControl | + dmainit.SecondFrameOperate); + + /* Write to ETHERNET DMAOMR */ + (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMAOMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMAOMR = tmpreg1; + + /*----------------------- ETHERNET DMABMR Configuration ------------------*/ + /* Set the AAL bit according to ETH AddressAlignedBeats value */ + /* Set the FB bit according to ETH FixedBurst value */ + /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */ + /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */ + /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/ + /* Set the DSL bit according to ETH DesciptorSkipLength value */ + /* Set the PR and DA bits according to ETH DMAArbitration value */ + (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | + dmainit.FixedBurst | + dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + dmainit.TxDMABurstLength | + dmainit.EnhancedDescriptorFormat | + (dmainit.DescriptorSkipLength << 2U) | + dmainit.DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMABMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMABMR = tmpreg1; + + if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) + { + /* Enable the Ethernet Rx Interrupt */ + __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R); + } + + /* Initialize MAC address in ethernet MAC */ + ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); +} + +/** + * @brief Configures the selected MAC address. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param MacAddr The MAC address to configure + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0: MAC Address0 + * @arg ETH_MAC_Address1: MAC Address1 + * @arg ETH_MAC_Address2: MAC Address2 + * @arg ETH_MAC_Address3: MAC Address3 + * @param Addr Pointer to MAC address buffer data (6 bytes) + * @retval HAL status + */ +static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg1; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Calculate the selected MAC address high register */ + tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; + /* Load the selected MAC address high register */ + (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; + /* Calculate the selected MAC address low register */ + tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U]; + + /* Load the selected MAC address low register */ + (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; +} + +/** + * @brief Enables the MAC transmission. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg1 = 0U; + + /* Enable the MAC transmission */ + (heth->Instance)->MACCR |= ETH_MACCR_TE; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; +} + +/** + * @brief Disables the MAC transmission. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg1 = 0U; + + /* Disable the MAC transmission */ + (heth->Instance)->MACCR &= ~ETH_MACCR_TE; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; +} + +/** + * @brief Enables the MAC reception. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg1 = 0U; + + /* Enable the MAC reception */ + (heth->Instance)->MACCR |= ETH_MACCR_RE; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; +} + +/** + * @brief Disables the MAC reception. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg1 = 0U; + + /* Disable the MAC reception */ + (heth->Instance)->MACCR &= ~ETH_MACCR_RE; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; +} + +/** + * @brief Enables the DMA transmission. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) +{ + /* Enable the DMA transmission */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; +} + +/** + * @brief Disables the DMA transmission. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) +{ + /* Disable the DMA transmission */ + (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST; +} + +/** + * @brief Enables the DMA reception. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) +{ + /* Enable the DMA reception */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; +} + +/** + * @brief Disables the DMA reception. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) +{ + /* Disable the DMA reception */ + (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR; +} + +/** + * @brief Clears the ETHERNET transmit FIFO. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg1 = 0U; + + /* Set the Flush Transmit FIFO bit */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMAOMR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMAOMR = tmpreg1; +} + +/** + * @brief This function provides delay (in milliseconds) based on CPU cycles method. + * @param mdelay specifies the delay time length, in milliseconds. + * @retval None + */ +static void ETH_Delay(uint32_t mdelay) +{ + __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); + do + { + __NOP(); + } + while (Delay --); +} + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) +{ + /* Init the ETH Callback settings */ + heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */ + heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */ + heth->DMAErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak DMAErrorCallback */ +} +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ + STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED*/ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c index fc6c475ff3..a6d2a928e0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -5,6 +5,17 @@ * @brief HAL module driver. * This is the common part of the HAL initialization * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,17 +30,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -50,11 +50,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.7.13 + * @brief STM32F4xx HAL Driver version number V1.8.0 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x0DU) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ @@ -612,4 +612,3 @@ void HAL_DisableMemorySwappingBank(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c index af8ed59eb8..128b23608a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c @@ -5,9 +5,20 @@ * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Converter (ADC) peripheral: * + Initialization and de-initialization functions - * + IO operation functions - * + State and errors functions + * + Peripheral Control functions + * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### ADC Peripheral features ##### @@ -231,18 +242,6 @@ are set to the corresponding weak functions. @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1201,13 +1200,16 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { uint32_t tmp1 = 0U, tmp2 = 0U; + uint32_t tmp_sr = hadc->Instance->SR; + uint32_t tmp_cr1 = hadc->Instance->CR1; + /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); - tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC); - tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC); + tmp1 = tmp_sr & ADC_FLAG_EOC; + tmp2 = tmp_cr1 & ADC_IT_EOC; /* Check End of conversion flag for regular channels */ if(tmp1 && tmp2) { @@ -1255,8 +1257,8 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); } - tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC); - tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC); + tmp1 = tmp_sr & ADC_FLAG_JEOC; + tmp2 = tmp_cr1 & ADC_IT_JEOC; /* Check End of conversion flag for injected channels */ if(tmp1 && tmp2) { @@ -1302,8 +1304,8 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); } - tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD); - tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD); + tmp1 = tmp_sr & ADC_FLAG_AWD; + tmp2 = tmp_cr1 & ADC_IT_AWD; /* Check Analog watchdog flag */ if(tmp1 && tmp2) { @@ -1324,8 +1326,8 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) } } - tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR); - tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR); + tmp1 = tmp_sr & ADC_FLAG_OVR; + tmp2 = tmp_cr1 & ADC_IT_OVR; /* Check Overrun flag */ if(tmp1 && tmp2) { @@ -1617,7 +1619,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) /** * @brief Error ADC callback. * @note In case of error due to overrun when using ADC with DMA transfer - * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" @@ -2106,4 +2108,3 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c index c17b3ba363..cff0760cdc 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c @@ -6,6 +6,17 @@ * functionalities of the ADC extension peripheral: * + Extended features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -69,18 +80,6 @@ @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1111,4 +1110,3 @@ static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c index 3e03475802..4abdc60a9a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c @@ -12,6 +12,17 @@ * + Callbacks functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -196,17 +207,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -675,7 +675,7 @@ HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Call /** * @brief Unregister a CAN CallBack. - * CAN callabck is redirected to the weak predefined callback + * CAN callback is redirected to the weak predefined callback * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for CAN module * @param CallbackID ID of the callback to be unregistered @@ -2460,5 +2460,3 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c index c599bcfc4a..56e6e8489f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c @@ -11,6 +11,17 @@ * + Peripheral Control function * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -96,17 +107,6 @@ are set to the corresponding weak functions. @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -497,7 +497,7 @@ HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_Call /** * @brief Unregister an CEC Callback - * CEC callabck is redirected to the weak predefined callback + * CEC callback is redirected to the weak predefined callback * @param hcec uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -994,4 +994,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c index e59e2a0755..54d44b49ec 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c @@ -68,14 +68,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -502,4 +500,3 @@ __weak void HAL_SYSTICK_Callback(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c index 652eeda37d..2e86b2b6a2 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c @@ -9,6 +9,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -29,17 +40,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -326,5 +326,3 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c index 2c9009c020..65ad59dfcd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c @@ -11,6 +11,17 @@ * + CRYP IRQ handler management * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -148,10 +159,10 @@ The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() + Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() to register an interrupt callback. - Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks: + Function HAL_CRYP_RegisterCallback() allows to register following callbacks: (+) InCpltCallback : Input FIFO transfer completed callback. (+) OutCpltCallback : Output FIFO transfer completed callback. (+) ErrorCallback : callback for error detection. @@ -160,9 +171,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default + Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) InCpltCallback : Input FIFO transfer completed callback. @@ -171,13 +182,13 @@ (+) MspInitCallback : CRYP MspInit. (+) MspDeInitCallback : CRYP MspDeInit. - By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET + By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET all callbacks are set to the corresponding weak functions : - examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback(). + examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when + reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit() keep and use the user MspInit/MspDeInit functions (registered beforehand) Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only. @@ -185,8 +196,8 @@ in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit() - or @ref HAL_CRYP_Init() function. + using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit() + or HAL_CRYP_Init() function. When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -241,17 +252,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -470,7 +470,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ - /* Set the key size(This bit field is don�t care in the DES or TDES modes) data type and Algorithm */ + /* Set the key size(This bit field is don't care in the DES or TDES modes) data type and Algorithm */ #if defined (CRYP) MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, @@ -589,7 +589,7 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; - /* Set the key size(This bit field is don�t care in the DES or TDES modes) data type, AlgoMode and operating mode*/ + /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/ #if defined (CRYP) MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, @@ -7130,4 +7130,3 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c index 43b238a13b..3a828473b5 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c @@ -7,6 +7,17 @@ * functionalities of CRYP extension peripheral: * + Extended AES processing functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -20,17 +31,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -177,7 +177,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Select final phase */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); - /*ALGODIR bit must be set to �0�.*/ + /*ALGODIR bit must be set to '0'.*/ hcryp->Instance->CR &= ~CRYP_CR_ALGODIR; /* Enable the CRYP peripheral */ @@ -395,7 +395,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Disable CRYP to start the final phase */ __HAL_CRYP_DISABLE(hcryp); - /* Select final phase & ALGODIR bit must be set to �0�. */ + /* Select final phase & ALGODIR bit must be set to '0'. */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT); /* Enable the CRYP peripheral */ @@ -678,4 +678,3 @@ void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c index eeddffa431..f6883eea39 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c @@ -11,6 +11,17 @@ * + Peripheral State and Errors functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### DAC Peripheral features ##### @@ -205,17 +216,6 @@ (@) You can refer to the DAC HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -1339,4 +1339,3 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c index 4a05998fef..343dd98682 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c @@ -7,6 +7,17 @@ * functionalities of the DAC peripheral. * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -28,17 +39,6 @@ (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -493,4 +493,3 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c index fbb6839856..67a8e102b1 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c @@ -10,6 +10,16 @@ * + Peripheral Control functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -109,17 +119,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1160,5 +1159,3 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi_ex.c index b21454c90d..bbc64c6aab 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi_ex.c @@ -7,6 +7,16 @@ * functionalities of DCMI extension peripheral: * + Extension features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** @verbatim ============================================================================== ##### DCMI peripheral extension features ##### @@ -23,17 +33,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -181,5 +180,3 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c index f981b9b3bd..5279edf0a8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c @@ -16,6 +16,17 @@ * + Clock absence detector feature * + Break generation on analog watchdog or short-circuit event * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -251,17 +262,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -4421,5 +4421,3 @@ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c index 11e89a6431..0b8dc19e02 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c @@ -83,13 +83,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -602,7 +601,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param CompleteLevel Specifies the DMA level complete. - * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. + * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. * This model could be used for debug purpose. * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). * @param Timeout Timeout duration. @@ -959,9 +958,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) * @brief Register callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifer + * @param CallbackID User Callback identifier * a DMA_HandleTypeDef structure as parameter. - * @param pCallback pointer to private callbacsk function which has pointer to + * @param pCallback pointer to private callback function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ @@ -1002,6 +1001,8 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call break; default: + /* Return error status */ + status = HAL_ERROR; break; } } @@ -1021,7 +1022,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call * @brief UnRegister callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifer + * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ @@ -1302,4 +1303,3 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c index f3582b643d..4cfac40613 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -94,9 +105,9 @@ [..] (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use function HAL_DMA2D_RegisterCallback() to register a user callback. + Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback. - (#) Function HAL_DMA2D_RegisterCallback() allows to register following callbacks: + (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks: (+) XferCpltCallback : callback for transfer complete. (+) XferErrorCallback : callback for transfer error. (+) LineEventCallback : callback for line event. @@ -106,9 +117,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - (#) Use function HAL_DMA2D_UnRegisterCallback() to reset a callback to the default + (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, + @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) XferCpltCallback : callback for transfer complete. @@ -118,13 +129,13 @@ (+) MspInitCallback : DMA2D MspInit. (+) MspDeInitCallback : DMA2D MspDeInit. - (#) By default, after the HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET + (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions: - examples HAL_DMA2D_LineEventCallback(), HAL_DMA2D_CLUTLoadingCpltCallback() + examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback() Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DMA2D_Init - and HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand) - If not, MspInit or MspDeInit are not null, the HAL_DMA2D_Init and HAL_DMA2D_DeInit + reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init + and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Exception as well for Transfer Completion and Transfer Error callbacks that are not defined @@ -135,8 +146,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using HAL_DMA2D_RegisterCallback before calling HAL_DMA2D_DeInit - or HAL_DMA2D_Init function. + using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit + or @ref HAL_DMA2D_Init function. When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -147,17 +158,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -2124,5 +2124,3 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ */ #endif /* DMA2D */ #endif /* HAL_DMA2D_MODULE_ENABLED */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c index e5c1b483a0..55e6df0a7f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c @@ -25,13 +25,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -312,4 +311,3 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c index da57a8fa69..bde68610e0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c @@ -9,6 +9,17 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -140,17 +151,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -200,12 +200,14 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32 uint32_t Data1); static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, - uint32_t ChannelID, - uint32_t Mode, - uint32_t Param1, - uint32_t Param2); - + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2); /* Private functions ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Functions DSI Private Functions + * @{ + */ /** * @brief Generic DSI packet header configuration * @param DSIx Pointer to DSI register base @@ -255,10 +257,10 @@ static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, tickstart = HAL_GetTick(); /* Wait for Command FIFO Empty */ - while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) + while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -271,6 +273,10 @@ static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, return HAL_OK; } +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup DSI_Exported_Functions * @{ @@ -365,11 +371,17 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI /* Set the PLL division factors */ hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); - hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << 2U) | ((PLLInit->PLLIDF) << 11U) | ((PLLInit->PLLODF) << 16U)); + hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \ + ((PLLInit->PLLIDF) << DSI_WRPCR_PLL_IDF_Pos) | \ + ((PLLInit->PLLODF) << DSI_WRPCR_PLL_ODF_Pos)); /* Enable the DSI PLL */ __HAL_DSI_PLL_ENABLE(hdsi); + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + /* Get tick */ tickstart = HAL_GetTick(); @@ -419,7 +431,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI hdsi->Instance->IER[1U] = 0U; hdsi->ErrorMsk = 0U; - /* Initialise the error code */ + /* Initialize the error code */ hdsi->ErrorCode = HAL_DSI_ERROR_NONE; /* Initialize the DSI state*/ @@ -473,7 +485,7 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) HAL_DSI_MspDeInit(hdsi); #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ - /* Initialise the error code */ + /* Initialize the error code */ hdsi->ErrorCode = HAL_DSI_ERROR_NONE; /* Initialize the DSI state*/ @@ -698,7 +710,7 @@ HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Call /** * @brief Unregister a DSI Callback - * DSI callabck is redirected to the weak predefined callback + * DSI callback is redirected to the weak predefined callback * @param hdsi dsi handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -733,11 +745,11 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca break; case HAL_DSI_MSPINIT_CB_ID : - hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */ break; case HAL_DSI_MSPDEINIT_CB_ID : - hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */ break; default : @@ -753,11 +765,11 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca switch (CallbackID) { case HAL_DSI_MSPINIT_CB_ID : - hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */ break; case HAL_DSI_MSPDEINIT_CB_ID : - hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */ break; default : @@ -808,7 +820,8 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca */ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) { - uint32_t ErrorStatus0, ErrorStatus1; + uint32_t ErrorStatus0; + uint32_t ErrorStatus1; /* Tearing Effect Interrupt management ***************************************/ if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U) @@ -1365,7 +1378,8 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT High-Speed transmission. To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed to Low-Power and from Low-Power to High-Speed. - This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR). + This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration + Register (DSI_CLTCR). But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. @@ -1587,7 +1601,7 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, /* Process locked */ __HAL_LOCK(hdsi); - status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2); + status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2); /* Process unlocked */ __HAL_UNLOCK(hdsi); @@ -1616,7 +1630,9 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Param1, uint8_t *ParametersTable) { - uint32_t uicounter, nbBytes, count; + uint32_t uicounter; + uint32_t nbBytes; + uint32_t count; uint32_t tickstart; uint32_t fifoword; uint8_t *pparams = ParametersTable; @@ -1721,7 +1737,7 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, { /* set max return packet size */ if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU), - (((datasize) >> 8U) & 0xFFU)) != HAL_OK) + (((datasize) >> 8U) & 0xFFU)) != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1782,6 +1798,21 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, return HAL_TIMEOUT; } + + /* Software workaround to avoid HAL_TIMEOUT when a DSI read command is */ + /* issued to the panel and the read data is not captured by the DSI Host */ + /* which returns Packet Size Error. */ + /* Need to ensure that the Read command has finished before checking PSE */ + if ((hdsi->Instance->GPSR & DSI_GPSR_RCB) == 0U) + { + if ((hdsi->Instance->ISR[1U] & DSI_ISR1_PSE) == DSI_ISR1_PSE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } } /* Process unlocked */ @@ -2077,7 +2108,7 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) /* De-assert the ULPM requests and the ULPM exit bits */ hdsi->Instance->PUCR = 0U; - /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */ + /* Switch the lane byte clock source in the RCC from system PLL to D-PHY */ __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY); /* Restore clock lane configuration to HS */ @@ -2727,5 +2758,3 @@ uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c index 2b6567b1a4..9cf3e6c2f5 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c @@ -5,16 +5,29 @@ * @brief ETH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: - * + Initialization and de-initialization functions + * + Initialization and deinitialization functions * + IO operation functions * + Peripheral Control functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] + [..] + The ETH HAL driver can be used as follows: + (#)Declare a ETH_HandleTypeDef handle structure, for example: ETH_HandleTypeDef heth; @@ -24,81 +37,125 @@ (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: (##) Enable the Ethernet interface clock using - (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); - (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); - (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); + (+++) __HAL_RCC_ETH1MAC_CLK_ENABLE() + (+++) __HAL_RCC_ETH1TX_CLK_ENABLE() + (+++) __HAL_RCC_ETH1RX_CLK_ENABLE() (##) Initialize the related GPIO clocks - (##) Configure Ethernet pin-out - (##) Configure Ethernet NVIC interrupt (IT mode) - - (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: - (##) HAL_ETH_DMATxDescListInit(); for Transmission process - (##) HAL_ETH_DMARxDescListInit(); for Reception process + (##) Configure Ethernet pinout + (##) Configure Ethernet NVIC interrupt (in Interrupt mode) + + (#) Ethernet data reception is asynchronous, so call the following API + to start the listening mode: + (##) HAL_ETH_Start(): + This API starts the MAC and DMA transmission and reception process, + without enabling end of transfer interrupts, in this mode user + has to poll for data reception by calling HAL_ETH_ReadData() + (##) HAL_ETH_Start_IT(): + This API starts the MAC and DMA transmission and reception process, + end of transfer interrupts are enabled in this mode, + HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received + + (#) When data is received user can call the following API to get received data: + (##) HAL_ETH_ReadData(): Read a received packet + + (#) For transmission path, two APIs are available: + (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode + (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode, + HAL_ETH_TxCpltCallback() will be executed when end of transfer occur + + (#) Communication with an external PHY device: + (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY + (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register - (#)Enable MAC and DMA transmission and reception: - (##) HAL_ETH_Start(); - - (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer - the frame to MAC TX FIFO: - (##) HAL_ETH_TransmitFrame(); - - (#)Poll for a received frame in ETH RX DMA Descriptors and get received - frame parameters - (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) + (#) Configure the Ethernet MAC after ETH peripheral initialization + (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef + (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef - (#) Get a received frame when an ETH RX interrupt occurs: - (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) + (#) Configure the Ethernet DMA after ETH peripheral initialization + (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef + (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef - (#) Communicate with external PHY device: - (##) Read a specific register from the PHY - HAL_ETH_ReadPHYRegister(); - (##) Write data to a specific RHY register: - HAL_ETH_WritePHYRegister(); + (#) Configure the Ethernet PTP after ETH peripheral initialization + (##) Define HAL_ETH_USE_PTP to use PTP APIs. + (##) HAL_ETH_PTP_GetConfig(): Get PTP actual configuration into ETH_PTP_ConfigTypeDef + (##) HAL_ETH_PTP_SetConfig(): Set PTP configuration based on ETH_PTP_ConfigTypeDef + (##) HAL_ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers + (##) HAL_ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers + (##) HAL_ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers + (##) HAL_ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission + (##) HAL_ETH_PTP_GetTxTimestamp(): Get transmission timestamp + (##) HAL_ETH_PTP_GetRxTimestamp(): Get reception timestamp - (#) Configure the Ethernet MAC after ETH peripheral initialization - HAL_ETH_ConfigMAC(); all MAC parameters should be filled. + -@- The ARP offload feature is not supported in this driver. - (#) Configure the Ethernet DMA after ETH peripheral initialization - HAL_ETH_ConfigDMA(); all DMA parameters should be filled. + -@- The PTP offload feature is not supported in this driver. - -@- The PTP protocol and the DMA descriptors ring mode are not supported - in this driver -*** Callback registration *** + *** Callback registration *** ============================================= The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback. + Use Function HAL_ETH_RegisterCallback() to register an interrupt callback. - Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks: + Function HAL_ETH_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. - (+) DMAErrorCallback : DMA Error Callback. + (+) ErrorCallback : Error Callback. + (+) PMTCallback : Power Management Callback + (+) EEECallback : EEE Callback. + (+) WakeUpCallback : Wake UP Callback (+) MspInitCallback : MspInit Callback. (+) MspDeInitCallback: MspDeInit Callback. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default + For specific callbacks RxAllocateCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterRxAllocateCallback(). + + For specific callbacks RxLinkCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterRxLinkCallback(). + + For specific callbacks TxFreeCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterTxFreeCallback(). + + For specific callbacks TxPtpCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterTxPtpCallback(). + + Use function HAL_ETH_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. - (+) DMAErrorCallback : DMA Error Callback. + (+) ErrorCallback : Error Callback. + (+) PMTCallback : Power Management Callback + (+) EEECallback : EEE Callback. + (+) WakeUpCallback : Wake UP Callback (+) MspInitCallback : MspInit Callback. (+) MspDeInitCallback: MspDeInit Callback. + For specific callbacks RxAllocateCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterRxAllocateCallback(). + + For specific callbacks RxLinkCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterRxLinkCallback(). + + For specific callbacks TxFreeCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterTxFreeCallback(). + + For specific callbacks TxPtpCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterTxPtpCallback(). + By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback(). + examples HAL_ETH_TxCpltCallback(), HAL_ETH_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when + reset to the legacy weak function in the HAL_ETH_Init/ HAL_ETH_DeInit only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit + if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ HAL_ETH_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only. @@ -106,7 +163,7 @@ in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit + using HAL_ETH_RegisterCallback() before calling HAL_ETH_DeInit or HAL_ETH_Init function. When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or @@ -115,17 +172,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -134,525 +180,266 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ +#ifdef HAL_ETH_MODULE_ENABLED + +#if defined(ETH) /** @defgroup ETH ETH * @brief ETH HAL module driver * @{ */ -#ifdef HAL_ETH_MODULE_ENABLED - -#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup ETH_Private_Constants ETH Private Constants +/** @addtogroup ETH_Private_Constants ETH Private Constants * @{ */ -#define ETH_TIMEOUT_SWRESET 500U -#define ETH_TIMEOUT_LINKED_STATE 5000U -#define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U +#define ETH_MACCR_MASK ((uint32_t)0xFFFB7F7CU) +#define ETH_MACECR_MASK ((uint32_t)0x3F077FFFU) +#define ETH_MACFFR_MASK ((uint32_t)0x800007FFU) +#define ETH_MACWTR_MASK ((uint32_t)0x0000010FU) +#define ETH_MACTFCR_MASK ((uint32_t)0xFFFF00F2U) +#define ETH_MACRFCR_MASK ((uint32_t)0x00000003U) +#define ETH_MTLTQOMR_MASK ((uint32_t)0x00000072U) +#define ETH_MTLRQOMR_MASK ((uint32_t)0x0000007BU) +#define ETH_DMAMR_MASK ((uint32_t)0x00007802U) +#define ETH_DMASBMR_MASK ((uint32_t)0x0000D001U) +#define ETH_DMACCR_MASK ((uint32_t)0x00013FFFU) +#define ETH_DMACTCR_MASK ((uint32_t)0x003F1010U) +#define ETH_DMACRCR_MASK ((uint32_t)0x803F0000U) +#define ETH_MACPMTCSR_MASK (ETH_MACPMTCSR_PD | ETH_MACPMTCSR_WFE | \ + ETH_MACPMTCSR_MPE | ETH_MACPMTCSR_GU) + +/* Timeout values */ +#define ETH_SWRESET_TIMEOUT ((uint32_t)500U) +#define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U) + +#define ETH_DMARXDESC_ERRORS_MASK ((uint32_t)(ETH_DMARXDESC_DBE | ETH_DMARXDESC_RE | \ + ETH_DMARXDESC_OE | ETH_DMARXDESC_RWT |\ + ETH_DMARXDESC_LC | ETH_DMARXDESC_CE |\ + ETH_DMARXDESC_DE | ETH_DMARXDESC_IPV4HCE)) + +#define ETH_MAC_US_TICK ((uint32_t)1000000U) + +#define ETH_MACTSCR_MASK ((uint32_t)0x0087FF2FU) + +#define ETH_PTPTSHR_VALUE ((uint32_t)0xFFFFFFFFU) +#define ETH_PTPTSLR_VALUE ((uint32_t)0xBB9ACA00U) + +/* Ethernet MACMIIAR register Mask */ +#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U) + +/* Delay to wait when writing to some Ethernet registers */ +#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U) + +/* ETHERNET MACCR register Mask */ +#define ETH_MACCR_CLEAR_MASK 0xFF20810FU + +/* ETHERNET MACFCR register Mask */ +#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U + +/* ETHERNET DMAOMR register Mask */ +#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U + +/* ETHERNET MAC address offsets */ +#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ + +/* ETHERNET DMA Rx descriptors Frame length Shift */ +#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ETH_Private_Macros ETH Private Macros + * @{ + */ +/* Helper macros for TX descriptor handling */ +#define INCR_TX_DESC_INDEX(inx, offset) do {\ + (inx) += (offset);\ + if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\ + (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\ + } while (0) + +/* Helper macros for RX descriptor handling */ +#define INCR_RX_DESC_INDEX(inx, offset) do {\ + (inx) += (offset);\ + if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\ + (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\ + } while (0) /** * @} */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup ETH_Private_Functions ETH Private Functions +/** @defgroup ETH_Private_Functions ETH Private Functions * @{ */ -static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err); -static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr); -static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth); -static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth); -static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth); -static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth); -static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth); -static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth); -static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth); -static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth); +static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth); +static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth); +static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth); +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode); +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth); static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); -static void ETH_Delay(uint32_t mdelay); +static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr); + #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - /** * @} */ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ /** @defgroup ETH_Exported_Functions ETH Exported Functions * @{ */ -/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions + * @brief Initialization and Configuration functions * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the Ethernet peripheral - (+) De-initialize the Ethernet peripheral +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the ETH peripheral: - @endverbatim + (+) User must Implement HAL_ETH_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO and NVIC ). + + (+) Call the function HAL_ETH_Init() to configure the selected device with + the selected configuration: + (++) MAC address + (++) Media interface (MII or RMII) + (++) Rx DMA Descriptors Tab + (++) Tx DMA Descriptors Tab + (++) Length of Rx Buffers + + (+) Call the function HAL_ETH_DeInit() to restore the default configuration + of the selected ETH peripheral. + +@endverbatim * @{ */ /** - * @brief Initializes the Ethernet MAC and DMA according to default - * parameters. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Initialize the Ethernet peripheral registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) { - uint32_t tmpreg1 = 0U, phyreg = 0U; - uint32_t hclk = 60000000U; - uint32_t tickstart = 0U; - uint32_t err = ETH_SUCCESS; + uint32_t tickstart; - /* Check the ETH peripheral state */ - if(heth == NULL) + if (heth == NULL) { return HAL_ERROR; } - - /* Check parameters */ - assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation)); - assert_param(IS_ETH_RX_MODE(heth->Init.RxMode)); - assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode)); - assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); - - if(heth->State == HAL_ETH_STATE_RESET) + if (heth->gState == HAL_ETH_STATE_RESET) { - /* Allocate lock resource and initialize it */ - heth->Lock = HAL_UNLOCKED; + heth->gState = HAL_ETH_STATE_BUSY; + #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + ETH_InitCallbacksToDefault(heth); - if(heth->MspInitCallback == NULL) + if (heth->MspInitCallback == NULL) { - /* Init the low level hardware : GPIO, CLOCK, NVIC. */ heth->MspInitCallback = HAL_ETH_MspInit; } - heth->MspInitCallback(heth); + /* Init the low level hardware */ + heth->MspInitCallback(heth); #else /* Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspInit(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ } - /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); /* Select MII or RMII Mode*/ SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; + /* Dummy read to sync SYSCFG with ETH */ + (void)SYSCFG->PMC; /* Ethernet Software reset */ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ /* After reset all the registers holds their respective reset values */ - (heth->Instance)->DMABMR |= ETH_DMABMR_SR; + SET_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR); /* Get tick */ tickstart = HAL_GetTick(); /* Wait for software reset */ - while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET) - { - heth->State= HAL_ETH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are - not available, please check your external PHY or the IO configuration */ - return HAL_TIMEOUT; - } - } - - /*-------------------------------- MAC Initialization ----------------------*/ - /* Get the ETHERNET MACMIIAR value */ - tmpreg1 = (heth->Instance)->MACMIIAR; - /* Clear CSR Clock Range CR[2:0] bits */ - tmpreg1 &= ETH_MACMIIAR_CR_MASK; - - /* Get hclk frequency value */ - hclk = HAL_RCC_GetHCLKFreq(); - - /* Set CR bits depending on hclk value */ - if((hclk >= 20000000U)&&(hclk < 35000000U)) - { - /* CSR Clock Range between 20-35 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16; - } - else if((hclk >= 35000000U)&&(hclk < 60000000U)) - { - /* CSR Clock Range between 35-60 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26; - } - else if((hclk >= 60000000U)&&(hclk < 100000000U)) - { - /* CSR Clock Range between 60-100 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42; - } - else if((hclk >= 100000000U)&&(hclk < 150000000U)) - { - /* CSR Clock Range between 100-150 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62; - } - else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */ - { - /* CSR Clock Range between 150-183 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102; - } - - /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ - (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1; - - /*-------------------- PHY initialization and configuration ----------------*/ - /* Put the PHY in reset mode */ - if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Delay to assure PHY reset */ - HAL_Delay(PHY_RESET_DELAY); - - if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE) + while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U) { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* We wait for linked status */ - do - { - HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS)); - - - /* Enable Auto-Negotiation */ - if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until the auto-negotiation will be completed */ - do - { - HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - - } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE)); - - /* Read the result of the auto-negotiation */ - if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK) + if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT)) { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ + /* Set Error Code */ + heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT; + /* Set State as Error */ + heth->gState = HAL_ETH_STATE_ERROR; + /* Return Error */ return HAL_ERROR; } - - /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */ - if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET) - { - /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; - } - else - { - /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; - } - /* Configure the MAC with the speed fixed by the auto-negotiation process */ - if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS) - { - /* Set Ethernet speed to 10M following the auto-negotiation */ - (heth->Init).Speed = ETH_SPEED_10M; - } - else - { - /* Set Ethernet speed to 100M following the auto-negotiation */ - (heth->Init).Speed = ETH_SPEED_100M; - } } - else /* AutoNegotiation Disable */ - { - /* Check parameters */ - assert_param(IS_ETH_SPEED(heth->Init.Speed)); - assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - /* Set MAC Speed and Duplex Mode */ - if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) | - (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); + /*------------------ MAC, MTL and DMA default Configuration ----------------*/ + ETH_MACDMAConfig(heth); - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - /* Return HAL_ERROR */ - return HAL_ERROR; - } + /*------------------ DMA Tx Descriptors Configuration ----------------------*/ + ETH_DMATxDescListInit(heth); - /* Delay to assure PHY configuration */ - HAL_Delay(PHY_CONFIG_DELAY); - } + /*------------------ DMA Rx Descriptors Configuration ----------------------*/ + ETH_DMARxDescListInit(heth); - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); + /*--------------------- ETHERNET MAC Address Configuration ------------------*/ + ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; + heth->ErrorCode = HAL_ETH_ERROR_NONE; + heth->gState = HAL_ETH_STATE_READY; - /* Return function status */ return HAL_OK; } /** - * @brief De-Initializes the ETH peripheral. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief DeInitializes the ETH peripheral. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) { /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; + heth->gState = HAL_ETH_STATE_BUSY; #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - if(heth->MspDeInitCallback == NULL) + + if (heth->MspDeInitCallback == NULL) { heth->MspDeInitCallback = HAL_ETH_MspDeInit; } - /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ + /* DeInit the low level hardware */ heth->MspDeInitCallback(heth); #else + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspDeInit(heth); -#endif - - /* Set ETH HAL state to Disabled */ - heth->State= HAL_ETH_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the DMA Tx descriptors in chain mode. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMATxDescTab Pointer to the first Tx desc list - * @param TxBuff Pointer to the first TxBuffer list - * @param TxBuffCount Number of the used Tx desc in the list - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) -{ - uint32_t i = 0U; - ETH_DMADescTypeDef *dmatxdesc; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ - heth->TxDesc = DMATxDescTab; - - /* Fill each DMATxDesc descriptor with the right values */ - for(i=0U; i < TxBuffCount; i++) - { - /* Get the pointer on the ith member of the Tx Desc list */ - dmatxdesc = DMATxDescTab + i; - - /* Set Second Address Chained bit */ - dmatxdesc->Status = ETH_DMATXDESC_TCH; - - /* Set Buffer1 address pointer */ - dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]); - - if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) - { - /* Set the DMA Tx descriptors checksum insertion */ - dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; - } - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (TxBuffCount-1U)) - { - /* Set next descriptor address register with next descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; - } - } - - /* Set Transmit Descriptor List Address Register */ - (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab; - - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the DMA Rx descriptors in chain mode. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMARxDescTab Pointer to the first Rx desc list - * @param RxBuff Pointer to the first RxBuffer list - * @param RxBuffCount Number of the used Rx desc in the list - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) -{ - uint32_t i = 0U; - ETH_DMADescTypeDef *DMARxDesc; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */ - heth->RxDesc = DMARxDescTab; - - /* Fill each DMARxDesc descriptor with the right values */ - for(i=0U; i < RxBuffCount; i++) - { - /* Get the pointer on the ith member of the Rx Desc list */ - DMARxDesc = DMARxDescTab+i; - - /* Set Own bit of the Rx descriptor Status */ - DMARxDesc->Status = ETH_DMARXDESC_OWN; - - /* Set Buffer1 size and Second Address Chained bit */ - DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; - - /* Set Buffer1 address pointer */ - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]); - - if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) - { - /* Enable Ethernet DMA Rx Descriptor interrupt */ - DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC; - } - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (RxBuffCount-1U)) - { - /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); - } - } - /* Set Receive Descriptor List Address Register */ - (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab; +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); + /* Set ETH HAL state to Disabled */ + heth->gState = HAL_ETH_STATE_RESET; /* Return function status */ return HAL_OK; @@ -660,7 +447,7 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc /** * @brief Initializes the ETH MSP. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -675,7 +462,7 @@ __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) /** * @brief DeInitializes ETH MSP. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -697,80 +484,96 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) * This parameter can be one of the following values: * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID + * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID + * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, + pETH_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(heth); - if(heth->State == HAL_ETH_STATE_READY) + if (heth->gState == HAL_ETH_STATE_READY) { switch (CallbackID) { - case HAL_ETH_TX_COMPLETE_CB_ID : - heth->TxCpltCallback = pCallback; - break; - - case HAL_ETH_RX_COMPLETE_CB_ID : - heth->RxCpltCallback = pCallback; - break; - - case HAL_ETH_DMA_ERROR_CB_ID : - heth->DMAErrorCallback = pCallback; - break; - - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = pCallback; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = pCallback; + break; + + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = pCallback; + break; + + case HAL_ETH_ERROR_CB_ID : + heth->ErrorCallback = pCallback; + break; + + case HAL_ETH_PMT_CB_ID : + heth->PMTCallback = pCallback; + break; + + + case HAL_ETH_WAKEUP_CB_ID : + heth->WakeUpCallback = pCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(heth->State == HAL_ETH_STATE_RESET) + else if (heth->gState == HAL_ETH_STATE_RESET) { switch (CallbackID) { - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = pCallback; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else { + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(heth); - return status; } @@ -782,7 +585,9 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call * This parameter can be one of the following values: * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID + * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID + * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID * @retval status @@ -791,66 +596,75 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(heth); - - if(heth->State == HAL_ETH_STATE_READY) + if (heth->gState == HAL_ETH_STATE_READY) { switch (CallbackID) { - case HAL_ETH_TX_COMPLETE_CB_ID : - heth->TxCpltCallback = HAL_ETH_TxCpltCallback; - break; + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = HAL_ETH_TxCpltCallback; + break; - case HAL_ETH_RX_COMPLETE_CB_ID : - heth->RxCpltCallback = HAL_ETH_RxCpltCallback; - break; + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = HAL_ETH_RxCpltCallback; + break; - case HAL_ETH_DMA_ERROR_CB_ID : - heth->DMAErrorCallback = HAL_ETH_ErrorCallback; - break; + case HAL_ETH_ERROR_CB_ID : + heth->ErrorCallback = HAL_ETH_ErrorCallback; + break; - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = HAL_ETH_MspInit; - break; + case HAL_ETH_PMT_CB_ID : + heth->PMTCallback = HAL_ETH_PMTCallback; + break; - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - break; - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_ETH_WAKEUP_CB_ID : + heth->WakeUpCallback = HAL_ETH_WakeUpCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(heth->State == HAL_ETH_STATE_RESET) + else if (heth->gState == HAL_ETH_STATE_RESET) { switch (CallbackID) { - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = HAL_ETH_MspInit; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else { + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(heth); - return status; } #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ @@ -860,525 +674,1394 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Ca */ /** @defgroup ETH_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions + * @brief ETH Transmit and Receive functions * - @verbatim +@verbatim ============================================================================== - ##### IO operation functions ##### + ##### IO operation functions ##### ============================================================================== - [..] This section provides functions allowing to: - (+) Transmit a frame - HAL_ETH_TransmitFrame(); - (+) Receive a frame - HAL_ETH_GetReceivedFrame(); - HAL_ETH_GetReceivedFrame_IT(); - (+) Read from an External PHY register - HAL_ETH_ReadPHYRegister(); - (+) Write to an External PHY register - HAL_ETH_WritePHYRegister(); - - @endverbatim + [..] + This subsection provides a set of functions allowing to manage the ETH + data transfer. +@endverbatim * @{ */ /** - * @brief Sends an Ethernet frame. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Enables Ethernet MAC and DMA reception and transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param FrameLength Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) { - uint32_t bufcount = 0U, size = 0U, i = 0U; + if (heth->gState == HAL_ETH_STATE_READY) + { + heth->gState = HAL_ETH_STATE_BUSY; - /* Process Locked */ - __HAL_LOCK(heth); + /* Set nombre of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); - if (FrameLength == 0U) - { - /* Set ETH HAL state to READY */ - heth->State = HAL_ETH_STATE_READY; + /* Enable the MAC transmission */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); - /* Process Unlocked */ - __HAL_UNLOCK(heth); + /* Enable the MAC reception */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); - return HAL_ERROR; - } + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); - /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ - if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) - { - /* OWN bit set */ - heth->State = HAL_ETH_STATE_BUSY_TX; + /* Enable the DMA transmission */ + SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); - /* Process Unlocked */ - __HAL_UNLOCK(heth); + /* Enable the DMA reception */ + SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); + heth->gState = HAL_ETH_STATE_STARTED; + + return HAL_OK; + } + else + { return HAL_ERROR; } +} - /* Get the number of needed Tx buffers for the current frame */ - if (FrameLength > ETH_TX_BUF_SIZE) +/** + * @brief Enables Ethernet MAC and DMA reception/transmission in Interrupt mode + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) +{ + if (heth->gState == HAL_ETH_STATE_READY) { - bufcount = FrameLength/ETH_TX_BUF_SIZE; - if (FrameLength % ETH_TX_BUF_SIZE) - { - bufcount++; - } + heth->gState = HAL_ETH_STATE_BUSY; + + /* save IT mode to ETH Handle */ + heth->RxDescList.ItMode = 1U; + /* Disable MMC Interrupts */ + SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM); + + /* Disable Rx MMC Interrupts */ + SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | \ + ETH_MMCRIMR_RFCEM); + + /* Disable Tx MMC Interrupts */ + SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | \ + ETH_MMCTIMR_TGFSCM); + + /* Set nombre of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; + + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); + + /* Enable the MAC transmission */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + /* Enable the MAC reception */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); + + /* Enable the DMA transmission */ + SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); + + /* Enable the DMA reception */ + SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); + + /* Enable ETH DMA interrupts: + - Tx complete interrupt + - Rx complete interrupt + - Fatal bus interrupt + */ + __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE | + ETH_DMAIER_FBEIE | ETH_DMAIER_AISE | ETH_DMAIER_RBUIE)); + + heth->gState = HAL_ETH_STATE_STARTED; + return HAL_OK; } else { - bufcount = 1U; + return HAL_ERROR; } - if (bufcount == 1U) +} + +/** + * @brief Stop Ethernet MAC and DMA reception/transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) +{ + if (heth->gState == HAL_ETH_STATE_STARTED) { - /* Set LAST and FIRST segment */ - heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS; - /* Set frame size */ - heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1); - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - heth->TxDesc->Status |= ETH_DMATXDESC_OWN; - /* Point to next descriptor */ - heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); + /* Set the ETH peripheral state to BUSY */ + heth->gState = HAL_ETH_STATE_BUSY; + /* Disable the DMA transmission */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + /* Disable the DMA reception */ + CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); + + /* Disable the MAC reception */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); + + /* Disable the MAC transmission */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + heth->gState = HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; } else { - for (i=0U; i< bufcount; i++) - { - /* Clear FIRST and LAST segment bits */ - heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); + return HAL_ERROR; + } +} - if (i == 0U) - { - /* Setting the first segment bit */ - heth->TxDesc->Status |= ETH_DMATXDESC_FS; - } +/** + * @brief Stop Ethernet MAC and DMA reception/transmission in Interrupt mode + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) +{ + ETH_DMADescTypeDef *dmarxdesc; + uint32_t descindex; - /* Program size */ - heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1); + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Set the ETH peripheral state to BUSY */ + heth->gState = HAL_ETH_STATE_BUSY; - if (i == (bufcount-1U)) - { - /* Setting the last segment bit */ - heth->TxDesc->Status |= ETH_DMATXDESC_LS; - size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE; - heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); - } + __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE | + ETH_DMAIER_FBEIE | ETH_DMAIER_AISE | ETH_DMAIER_RBUIE)); - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - heth->TxDesc->Status |= ETH_DMATXDESC_OWN; - /* point to next descriptor */ - heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); - } - } + /* Disable the DMA transmission */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); - /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ - if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) - { - /* Clear TBUS ETHERNET DMA flag */ - (heth->Instance)->DMASR = ETH_DMASR_TBUS; - /* Resume DMA transmission*/ - (heth->Instance)->DMATPDR = 0U; - } + /* Disable the DMA reception */ + CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); - /* Set ETH HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; + /* Disable the MAC reception */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); - /* Process Unlocked */ - __HAL_UNLOCK(heth); + /* Disable the MAC transmission */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); - /* Return function status */ - return HAL_OK; + /* Clear IOC bit to all Rx descriptors */ + for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) + { + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex]; + SET_BIT(dmarxdesc->DESC1, ETH_DMARXDESC_DIC); + } + + heth->RxDescList.ItMode = 0U; + + heth->gState = HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } } /** - * @brief Checks for received frames. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Sends an Ethernet Packet in polling mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module + * @param pTxConfig: Hold the configuration of packet to be transmitted + * @param Timeout: timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout) { - uint32_t framelength = 0U; - - /* Process Locked */ - __HAL_LOCK(heth); + uint32_t tickstart; + ETH_DMADescTypeDef *dmatxdesc; - /* Check the ETH state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; + if (pTxConfig == NULL) + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + return HAL_ERROR; + } - /* Check if segment is not owned by DMA */ - /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */ - if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET)) + if (heth->gState == HAL_ETH_STATE_STARTED) { - /* Check if last segment */ - if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) + /* Config DMA Tx descriptor by Tx Packet info */ + if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE) { - /* increment segment count */ - (heth->RxFrameInfos).SegCount++; + /* Set the ETH error code */ + heth->ErrorCode |= HAL_ETH_ERROR_BUSY; + return HAL_ERROR; + } - /* Check if last segment is first segment: one segment contains the frame */ - if ((heth->RxFrameInfos).SegCount == 1U) - { - (heth->RxFrameInfos).FSRxDesc =heth->RxDesc; - } + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); - heth->RxFrameInfos.LSRxDesc = heth->RxDesc; + dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc]; - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; - heth->RxFrameInfos.length = framelength; + /* Incr current tx desc index */ + INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); - /* Get the address of the buffer start address */ - heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; - /* point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr); + /* Start transmission */ + /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ + WRITE_REG(heth->Instance->DMATPDR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc])); - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; + tickstart = HAL_GetTick(); - /* Process Unlocked */ - __HAL_UNLOCK(heth); + /* Wait for data to be transmitted or timeout occurred */ + while ((dmatxdesc->DESC0 & ETH_DMATXDESC_OWN) != (uint32_t)RESET) + { + if ((heth->Instance->DMASR & ETH_DMASR_FBES) != (uint32_t)RESET) + { + heth->ErrorCode |= HAL_ETH_ERROR_DMA; + heth->DMAErrorCode = heth->Instance->DMASR; + /* Return function status */ + return HAL_ERROR; + } - /* Return function status */ - return HAL_OK; + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT; + /* Clear TX descriptor so that we can proceed */ + dmatxdesc->DESC0 = (ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); + return HAL_ERROR; + } + } } - /* Check if first segment */ - else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sends an Ethernet Packet in interrupt mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pTxConfig: Hold the configuration of packet to be transmitted + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig) +{ + if (pTxConfig == NULL) + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Save the packet pointer to release. */ + heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData; + + /* Config DMA Tx descriptor by Tx Packet info */ + if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE) { - (heth->RxFrameInfos).FSRxDesc = heth->RxDesc; - (heth->RxFrameInfos).LSRxDesc = NULL; - (heth->RxFrameInfos).SegCount = 1U; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); + heth->ErrorCode |= HAL_ETH_ERROR_BUSY; + return HAL_ERROR; } - /* Check if intermediate segment */ - else + + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); + + /* Incr current tx desc index */ + INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); + + /* Start transmission */ + /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ + if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) { - (heth->RxFrameInfos).SegCount++; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); + /* Clear TBUS ETHERNET DMA flag */ + (heth->Instance)->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + (heth->Instance)->DMATPDR = 0U; } - } - /* Set ETH HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; + return HAL_OK; - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_ERROR; + } + else + { + return HAL_ERROR; + } } /** - * @brief Gets the Received frame in interrupt mode. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Read a received packet. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module + * @param pAppBuff: Pointer to an application buffer to receive the packet. * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) +HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) { - uint32_t descriptorscancounter = 0U; + uint32_t descidx; + ETH_DMADescTypeDef *dmarxdesc; + uint32_t desccnt = 0U; + uint32_t desccntmax; + uint32_t bufflength; + uint8_t rxdataready = 0U; - /* Process Locked */ - __HAL_LOCK(heth); - /* Set ETH HAL State to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; + if (pAppBuff == NULL) + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + return HAL_ERROR; + } - /* Scan descriptors owned by CPU */ - while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB)) + if (heth->gState != HAL_ETH_STATE_STARTED) { - /* Just for security */ - descriptorscancounter++; + return HAL_ERROR; + } - /* Check if first segment in frame */ - /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ - if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS) - { - heth->RxFrameInfos.FSRxDesc = heth->RxDesc; - heth->RxFrameInfos.SegCount = 1U; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } - /* Check if intermediate segment */ - /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */ - else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET) + descidx = heth->RxDescList.RxDescIdx; + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt; + + /* Check if descriptor is not owned by DMA */ + while ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) + && (rxdataready == 0U)) + { + if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_LS) != (uint32_t)RESET) { - /* Increment segment count */ - (heth->RxFrameInfos.SegCount)++; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr); + /* Get timestamp high */ + heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC6; + /* Get timestamp low */ + heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC7; } - /* Should be last segment */ - else + if ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_FS) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL)) { - /* Last segment */ - heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - - /* Increment segment count */ - (heth->RxFrameInfos.SegCount)++; - - /* Check if last segment is first segment: one segment contains the frame */ - if ((heth->RxFrameInfos.SegCount) == 1U) + /* Check first descriptor */ + if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_FS) != (uint32_t)RESET) { - heth->RxFrameInfos.FSRxDesc = heth->RxDesc; + heth->RxDescList.RxDescCnt = 0; + heth->RxDescList.RxDataLength = 0; } - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; + /* Check if last descriptor */ + bufflength = heth->Init.RxBuffLen; + if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_LS) != (uint32_t)RESET) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + bufflength = ((dmarxdesc->DESC0 & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; - /* Get the address of the buffer start address */ - heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; + /* Save Last descriptor index */ + heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC0; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); + /* Packet ready */ + rxdataready = 1; + } - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; + /* Link data */ + WRITE_REG(dmarxdesc->BackupAddr0, dmarxdesc->DESC2); +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Link callback*/ + heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + (uint8_t *)dmarxdesc->BackupAddr0, bufflength); +#else + /* Link callback */ + HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + heth->RxDescList.RxDescCnt++; + heth->RxDescList.RxDataLength += bufflength; + + /* Clear buffer pointer */ + dmarxdesc->BackupAddr0 = 0; + } - /* Process Unlocked */ - __HAL_UNLOCK(heth); + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccnt++; + } - /* Return function status */ - return HAL_OK; - } + heth->RxDescList.RxBuildDescCnt += desccnt; + if ((heth->RxDescList.RxBuildDescCnt) != 0U) + { + /* Update Descriptors */ + ETH_UpdateDescriptor(heth); } - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; + heth->RxDescList.RxDescIdx = descidx; - /* Process Unlocked */ - __HAL_UNLOCK(heth); + if (rxdataready == 1U) + { + /* Return received packet */ + *pAppBuff = heth->RxDescList.pRxStart; + /* Reset first element */ + heth->RxDescList.pRxStart = NULL; - /* Return function status */ + return HAL_OK; + } + + /* Packet not ready */ return HAL_ERROR; } /** - * @brief This function handles ETH interrupt request. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief This function gives back Rx Desc of the last received Packet + * to the DMA, so ETH DMA will be able to use these descriptors + * to receive next Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ -void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) { - /* Frame received */ - if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) + uint32_t descidx; + uint32_t desccount; + ETH_DMADescTypeDef *dmarxdesc; + uint8_t *buff = NULL; + uint8_t allocStatus = 1U; + + descidx = heth->RxDescList.RxBuildDescIdx; + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccount = heth->RxDescList.RxBuildDescCnt; + + while ((desccount > 0U) && (allocStatus != 0U)) { + /* Check if a buffer's attached the descriptor */ + if (READ_REG(dmarxdesc->BackupAddr0) == 0U) + { + /* Get a new buffer. */ #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /*Call registered Receive complete callback*/ - heth->RxCpltCallback(heth); + /*Call registered Allocate callback*/ + heth->rxAllocateCallback(&buff); #else - /* Receive complete callback */ - HAL_ETH_RxCpltCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + /* Allocate callback */ + HAL_ETH_RxAllocateCallback(&buff); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + if (buff == NULL) + { + allocStatus = 0U; + } + else + { + WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff); + WRITE_REG(dmarxdesc->DESC2, (uint32_t)buff); + } + } - /* Clear the Eth DMA Rx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R); + if (allocStatus != 0U) + { + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; + WRITE_REG(dmarxdesc->DESC0, ETH_DMARXDESC_OWN); - /* Process Unlocked */ - __HAL_UNLOCK(heth); + if (heth->RxDescList.ItMode == 0U) + { + WRITE_REG(dmarxdesc->DESC1, ETH_DMARXDESC_DIC | 1000U | ETH_DMARXDESC_RCH); + } + else + { + WRITE_REG(dmarxdesc->DESC1, 1000U | ETH_DMARXDESC_RCH); + } + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccount--; + } } - /* Frame transmitted */ - else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) - { -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /* Call resgistered Transfer complete callback*/ - heth->TxCpltCallback(heth); -#else - /* Transfer complete callback */ - HAL_ETH_TxCpltCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /* Clear the Eth DMA Tx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T); - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; + if (heth->RxDescList.RxBuildDescCnt != desccount) + { + /* Set the Tail pointer address */ + WRITE_REG(heth->Instance->DMARPDR, 0); - /* Process Unlocked */ - __HAL_UNLOCK(heth); + heth->RxDescList.RxBuildDescIdx = descidx; + heth->RxDescList.RxBuildDescCnt = desccount; } +} - /* Clear the interrupt flags */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS); - - /* ETH DMA Error */ - if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS)) +/** + * @brief Register the Rx alloc callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param rxAllocateCallback: pointer to function to alloc buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, + pETH_rxAllocateCallbackTypeDef rxAllocateCallback) +{ + if (rxAllocateCallback == NULL) { -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - heth->DMAErrorCallback(heth); -#else - /* Ethernet Error callback */ - HAL_ETH_ErrorCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /* Clear the interrupt flags */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS); + /* No buffer to save */ + return HAL_ERROR; + } - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; + /* Set function to allocate buffer */ + heth->rxAllocateCallback = rxAllocateCallback; - /* Process Unlocked */ - __HAL_UNLOCK(heth); - } + return HAL_OK; } /** - * @brief Tx Transfer completed callbacks. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Unregister the Rx alloc callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @retval None + * @retval HAL status */ -__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file - */ + /* Set function to allocate buffer */ + heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; + + return HAL_OK; } /** - * @brief Rx Transfer completed callbacks. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * @brief Rx Allocate callback. + * @param buff: pointer to allocated buffer * @retval None */ -__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +__weak void HAL_ETH_RxAllocateCallback(uint8_t **buff) { /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); + UNUSED(buff); /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file + the HAL_ETH_RxAllocateCallback could be implemented in the user file */ } /** - * @brief Ethernet transfer error callbacks - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * @brief Rx Link callback. + * @param pStart: pointer to packet start + * @param pStart: pointer to packet end + * @param buff: pointer to received data + * @param Length: received data length * @retval None */ -__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) +__weak void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) { /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); + UNUSED(pStart); + UNUSED(pEnd); + UNUSED(buff); + UNUSED(Length); /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file + the HAL_ETH_RxLinkCallback could be implemented in the user file */ } /** - * @brief Reads a PHY register - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Set the Rx link data function. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param PHYReg PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Basic Control Register, - * PHY_BSR: Transceiver Basic Status Register. - * More PHY register could be read depending on the used PHY - * @param RegValue PHY register value + * @param rxLinkCallback: pointer to function to link data * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) +HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback) { - uint32_t tmpreg1 = 0U; - uint32_t tickstart = 0U; - - /* Check parameters */ - assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - - /* Check the ETH peripheral state */ - if(heth->State == HAL_ETH_STATE_BUSY_RD) + if (rxLinkCallback == NULL) { - return HAL_BUSY; + /* No buffer to save */ + return HAL_ERROR; } - /* Set ETH HAL State to BUSY_RD */ - heth->State = HAL_ETH_STATE_BUSY_RD; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg1 = heth->Instance->MACMIIAR; - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; + /* Set function to link data */ + heth->rxLinkCallback = rxLinkCallback; - /* Prepare the MII address register value */ - tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */ - tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + return HAL_OK; +} - /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg1; +/** + * @brief Unregister the Rx link callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->rxLinkCallback = HAL_ETH_RxLinkCallback; - /* Get tick */ - tickstart = HAL_GetTick(); + return HAL_OK; +} - /* Check for the Busy flag */ - while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > PHY_READ_TO) +/** + * @brief Get the error state of the last received packet. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pErrorCode: pointer to uint32_t to hold the error code + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode) +{ + /* Get error bits. */ + *pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXDESC_ERRORS_MASK); + + return HAL_OK; +} + +/** + * @brief Set the Tx free function. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txFreeCallback: pointer to function to release the packet + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback) +{ + if (txFreeCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + + /* Set function to free transmmitted packet */ + heth->txFreeCallback = txFreeCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Tx free callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->txFreeCallback = HAL_ETH_TxFreeCallback; + + return HAL_OK; +} + +/** + * @brief Tx Free callback. + * @param buff: pointer to buffer to free + * @retval None + */ +__weak void HAL_ETH_TxFreeCallback(uint32_t *buff) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxFreeCallback could be implemented in the user file + */ +} + +/** + * @brief Release transmitted Tx packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t numOfBuf = dmatxdesclist->BuffersInUse; + uint32_t idx = dmatxdesclist->releaseIndex; + uint8_t pktTxStatus = 1U; + uint8_t pktInUse; +#ifdef HAL_ETH_USE_PTP + ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp; +#endif /* HAL_ETH_USE_PTP */ + + /* Loop through buffers in use. */ + while ((numOfBuf != 0U) && (pktTxStatus != 0U)) + { + pktInUse = 1U; + numOfBuf--; + /* If no packet, just examine the next packet. */ + if (dmatxdesclist->PacketAddress[idx] == NULL) { - heth->State= HAL_ETH_STATE_READY; + /* No packet in use, skip to next. */ + idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); + pktInUse = 0U; + } + + if (pktInUse != 0U) + { + /* Determine if the packet has been transmitted. */ + if ((heth->Init.TxDesc[idx].DESC0 & ETH_DMATXDESC_OWN) == 0U) + { +#ifdef HAL_ETH_USE_PTP + /* Get timestamp low */ + timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC6; + /* Get timestamp high */ + timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC7; +#endif /* HAL_ETH_USE_PTP */ + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered callbacks*/ +#ifdef HAL_ETH_USE_PTP + /* Handle Ptp */ + heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); +#endif /* HAL_ETH_USE_PTP */ + /* Release the packet. */ + heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]); +#else + /* Call callbacks */ +#ifdef HAL_ETH_USE_PTP + /* Handle Ptp */ + HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); +#endif /* HAL_ETH_USE_PTP */ + /* Release the packet. */ + HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Clear the entry in the in-use array. */ + dmatxdesclist->PacketAddress[idx] = NULL; + + /* Update the transmit relesae index and number of buffers in use. */ + idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); + dmatxdesclist->BuffersInUse = numOfBuf; + dmatxdesclist->releaseIndex = idx; + } + else + { + /* Get out of the loop! */ + pktTxStatus = 0U; + } + } + } + return HAL_OK; +} + +#ifdef HAL_ETH_USE_PTP +/** + * @brief Set the Ethernet PTP configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains + * the configuration information for PTP + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) +{ + uint32_t tmpTSCR; + ETH_TimeTypeDef time; + + if (ptpconfig == NULL) + { + return HAL_ERROR; + } + + tmpTSCR = ptpconfig->Timestamp | + ((uint32_t)ptpconfig->TimestampUpdate << ETH_PTPTSCR_TSFCU_Pos) | + ((uint32_t)ptpconfig->TimestampAll << ETH_PTPTSCR_TSSARFE_Pos) | + ((uint32_t)ptpconfig->TimestampRolloverMode << ETH_PTPTSCR_TSSSR_Pos) | + ((uint32_t)ptpconfig->TimestampV2 << ETH_PTPTSCR_TSPTPPSV2E_Pos) | + ((uint32_t)ptpconfig->TimestampEthernet << ETH_PTPTSCR_TSSPTPOEFE_Pos) | + ((uint32_t)ptpconfig->TimestampIPv6 << ETH_PTPTSCR_TSSIPV6FE_Pos) | + ((uint32_t)ptpconfig->TimestampIPv4 << ETH_PTPTSCR_TSSIPV4FE_Pos) | + ((uint32_t)ptpconfig->TimestampEvent << ETH_PTPTSCR_TSSEME_Pos) | + ((uint32_t)ptpconfig->TimestampMaster << ETH_PTPTSCR_TSSMRME_Pos) | + ((uint32_t)ptpconfig->TimestampFilter << ETH_PTPTSCR_TSPFFMAE_Pos) | + ((uint32_t)ptpconfig->TimestampClockType << ETH_PTPTSCR_TSCNT_Pos); + + /* Write to MACTSCR */ + MODIFY_REG(heth->Instance->PTPTSCR, ETH_MACTSCR_MASK, tmpTSCR); + + /* Enable Timestamp */ + SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSE); + WRITE_REG(heth->Instance->PTPSSIR, ptpconfig->TimestampSubsecondInc); + WRITE_REG(heth->Instance->PTPTSAR, ptpconfig->TimestampAddend); + + /* Enable Timestamp */ + if (ptpconfig->TimestampAddendUpdate == ENABLE) + { + SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSARU); + while ((heth->Instance->PTPTSCR & ETH_PTPTSCR_TSARU) != 0) {} + } + + /* Enable Update mode */ + if (ptpconfig->TimestampUpdateMode == ENABLE) + { + SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSFCU); + } + + /* Initialize Time */ + time.Seconds = 0; + time.NanoSeconds = 0; + HAL_ETH_PTP_SetTime(heth, &time); + + /* Ptp Init */ + SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSTI); + + /* Set PTP Configuration done */ + heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURATED; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Get the Ethernet PTP configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains + * the configuration information for PTP + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) +{ + if (ptpconfig == NULL) + { + return HAL_ERROR; + } + ptpconfig->Timestamp = READ_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSE); + ptpconfig->TimestampUpdate = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSFCU) >> ETH_PTPTSCR_TSFCU_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampAll = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSARFE) >> ETH_PTPTSCR_TSSARFE_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampRolloverMode = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSSR) >> ETH_PTPTSCR_TSSSR_Pos) > 0U) + ? ENABLE : DISABLE; + ptpconfig->TimestampV2 = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSPTPPSV2E) >> ETH_PTPTSCR_TSPTPPSV2E_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampEthernet = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSPTPOEFE) >> ETH_PTPTSCR_TSSPTPOEFE_Pos) > 0U) + ? ENABLE : DISABLE; + ptpconfig->TimestampIPv6 = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSIPV6FE) >> ETH_PTPTSCR_TSSIPV6FE_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampIPv4 = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSIPV4FE) >> ETH_PTPTSCR_TSSIPV4FE_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampEvent = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSEME) >> ETH_PTPTSCR_TSSEME_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampMaster = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSMRME) >> ETH_PTPTSCR_TSSMRME_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampFilter = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSPFFMAE) >> ETH_PTPTSCR_TSPFFMAE_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampClockType = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSCNT) >> ETH_PTPTSCR_TSCNT_Pos) > 0U) ? ENABLE : DISABLE; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set Seconds and Nanoseconds for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param heth: pointer to a ETH_TimeTypeDef structure that contains + * time to set + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Set Seconds */ + heth->Instance->PTPTSHUR = time->Seconds; + + /* Set NanoSeconds */ + heth->Instance->PTPTSLUR = time->NanoSeconds; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Get Seconds and Nanoseconds for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param heth: pointer to a ETH_TimeTypeDef structure that contains + * time to get + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Get Seconds */ + time->Seconds = heth->Instance->PTPTSHR; + + /* Get NanoSeconds */ + time->NanoSeconds = heth->Instance->PTPTSLR; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Update time for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timeupdate: pointer to a ETH_TIMEUPDATETypeDef structure that contains + * the time update information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, + ETH_TimeTypeDef *timeoffset) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE) + { + /* Set Seconds update */ + heth->Instance->PTPTSHUR = ETH_PTPTSHR_VALUE - timeoffset->Seconds + 1U; + + if (READ_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSSR) == ETH_PTPTSCR_TSSSR) + { + /* Set nanoSeconds update */ + heth->Instance->PTPTSLUR = ETH_PTPTSLR_VALUE - timeoffset->NanoSeconds; + } + else + { + heth->Instance->PTPTSLUR = ETH_PTPTSHR_VALUE - timeoffset->NanoSeconds + 1U; + } + } + else + { + /* Set Seconds update */ + heth->Instance->PTPTSHUR = timeoffset->Seconds; + /* Set nanoSeconds update */ + heth->Instance->PTPTSLUR = timeoffset->NanoSeconds; + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Insert Timestamp in transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txtimestampconf: Enable or Disable timestamp in transmission + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t descidx = dmatxdesclist->CurTxDesc; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Enable Time Stamp transmission */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TTSE); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Get transmission timestamp. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains + * transmission timestamp + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t idx = dmatxdesclist->releaseIndex; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx]; + + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Get timestamp low */ + timestamp->TimeStampLow = dmatxdesc->DESC0; + /* Get timestamp high */ + timestamp->TimeStampHigh = dmatxdesc->DESC1; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Get receive timestamp. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains + * receive timestamp + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Get timestamp low */ + timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow; + /* Get timestamp high */ + timestamp->TimeStampHigh = heth->RxDescList.TimeStamp.TimeStampHigh; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Register the Tx Ptp callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txPtpCallback: Function to handle Ptp transmission + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback) +{ + if (txPtpCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + /* Set Function to handle Tx Ptp */ + heth->txPtpCallback = txPtpCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Tx Ptp callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->txPtpCallback = HAL_ETH_TxPtpCallback; + + return HAL_OK; +} + +/** + * @brief Tx Ptp callback. + * @param buff: pointer to application buffer + * @retval None + */ +__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxPtpCallback could be implemented in the user file + */ +} +#endif /* HAL_ETH_USE_PTP */ + +/** + * @brief This function handles ETH interrupt request. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) +{ + /* Packet received */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_RS)) + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_RIE)) + { + /* Clear the Eth DMA Rx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_RS | ETH_DMASR_NIS); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Receive complete callback*/ + heth->RxCpltCallback(heth); +#else + /* Receive complete callback */ + HAL_ETH_RxCpltCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + } + + /* Packet transmitted */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_TS)) + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_TIE)) + { + /* Clear the Eth DMA Tx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_TS | ETH_DMASR_NIS); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Transmit complete callback*/ + heth->TxCpltCallback(heth); +#else + /* Transfer complete callback */ + HAL_ETH_TxCpltCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + } + + + /* ETH DMA Error */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_AIS)) + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_AISE)) + { + heth->ErrorCode |= HAL_ETH_ERROR_DMA; + + /* if fatal bus error occurred */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_FBES)) + { + /* Get DMA error code */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_FBES | ETH_DMASR_TPS | ETH_DMASR_RPS)); + + /* Disable all interrupts */ + __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMAIER_NISE | ETH_DMAIER_AISE); + + /* Set HAL state to ERROR */ + heth->gState = HAL_ETH_STATE_ERROR; + } + else + { + /* Get DMA error status */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_ETS | ETH_DMASR_RWTS | + ETH_DMASR_RBUS | ETH_DMASR_AIS)); + + /* Clear the interrupt summary flag */ + __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMASR_ETS | ETH_DMASR_RWTS | + ETH_DMASR_RBUS | ETH_DMASR_AIS)); + } +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered Error callback*/ + heth->ErrorCallback(heth); +#else + /* Ethernet DMA Error callback */ + HAL_ETH_ErrorCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + } + } + + + /* ETH PMT IT */ + if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT)) + { + /* Get MAC Wake-up source and clear the status register pending bit */ + heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPMTCSR, (ETH_MACPMTCSR_WFR | ETH_MACPMTCSR_MPR)); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered PMT callback*/ + heth->PMTCallback(heth); +#else + /* Ethernet PMT callback */ + HAL_ETH_PMTCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + heth->MACWakeUpEvent = (uint32_t)(0x0U); + } + + + /* check ETH WAKEUP exti flag */ + if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) + { + /* Clear ETH WAKEUP Exti pending bit */ + __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered WakeUp callback*/ + heth->WakeUpCallback(heth); +#else + /* ETH WAKEUP callback */ + HAL_ETH_WakeUpCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Ethernet transfer error callbacks + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Ethernet Power Management module IT callback + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_PMTCallback could be implemented in the user file + */ +} + + +/** + * @brief ETH WAKEUP interrupt callback + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_WakeUpCallback could be implemented in the user file + */ +} + +/** + * @brief Read a PHY register + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYAddr: PHY port address, must be a value from 0 to 31 + * @param PHYReg: PHY register address, must be a value from 0 to 31 + * @param pRegValue: parameter to hold read value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t *pRegValue) +{ + uint32_t tmpreg1; + uint32_t tickstart; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg1 = heth->Instance->MACMIIAR; + + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; - /* Process Unlocked */ - __HAL_UNLOCK(heth); + /* Prepare the MII address register value */ + tmpreg1 |= ((PHYAddr << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + + /* Write the result value into the MII Address register */ + heth->Instance->MACMIIAR = tmpreg1; + + + tickstart = HAL_GetTick(); - return HAL_TIMEOUT; + /* Check for the Busy flag */ + while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > PHY_READ_TO) + { + return HAL_ERROR; } tmpreg1 = heth->Instance->MACMIIAR; } /* Get MACMIIDR value */ - *RegValue = (uint16_t)(heth->Instance->MACMIIDR); + *pRegValue = (uint16_t)(heth->Instance->MACMIIDR); - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ return HAL_OK; } + /** * @brief Writes to a PHY register. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param PHYReg PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Control Register. - * More PHY register could be written depending on the used PHY - * @param RegValue the value to write + * @param PHYAddr: PHY port address, must be a value from 0 to 31 + * @param PHYReg: PHY register address, must be a value from 0 to 31 + * @param RegValue: the value to write * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t RegValue) { - uint32_t tmpreg1 = 0U; - uint32_t tickstart = 0U; - - /* Check parameters */ - assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - - /* Check the ETH peripheral state */ - if(heth->State == HAL_ETH_STATE_BUSY_WR) - { - return HAL_BUSY; - } - /* Set ETH HAL State to BUSY_WR */ - heth->State = HAL_ETH_STATE_BUSY_WR; + uint32_t tmpreg1; + uint32_t tickstart; /* Get the ETHERNET MACMIIAR value */ tmpreg1 = heth->Instance->MACMIIAR; @@ -1387,8 +2070,8 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; /* Prepare the MII register address value */ - tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg1 |= ((PHYAddr << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ @@ -1402,26 +2085,17 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY tickstart = HAL_GetTick(); /* Check for the Busy flag */ - while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO) + if ((HAL_GetTick() - tickstart) > PHY_WRITE_TO) { - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; + return HAL_ERROR; } tmpreg1 = heth->Instance->MACMIIAR; } - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ return HAL_OK; } @@ -1430,389 +2104,497 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY */ /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * + * @brief ETH control functions + * @verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Enable MAC and DMA transmission and reception. - HAL_ETH_Start(); - (+) Disable MAC and DMA transmission and reception. - HAL_ETH_Stop(); - (+) Set the MAC configuration in runtime mode - HAL_ETH_ConfigMAC(); - (+) Set the DMA configuration in runtime mode - HAL_ETH_ConfigDMA(); + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the ETH + peripheral. @endverbatim * @{ */ - - /** - * @brief Enables Ethernet MAC and DMA reception/transmission - * @param heth pointer to a ETH_HandleTypeDef structure that contains +/** + * @brief Get the configuration of the MAC and MTL subsystems. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @retval HAL status + * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold + * the configuration of the MAC. + * @retval HAL Status */ -HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) +HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) { - /* Process Locked */ - __HAL_LOCK(heth); + if (macconf == NULL) + { + return HAL_ERROR; + } - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; + /* Get MAC parameters */ + macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE; + macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL); + macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_RD) >> 9) == 0U) ? ENABLE : DISABLE; + macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CSD) >> 16) > 0U) + ? ENABLE : DISABLE; + macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ROD) >> 13) == 0U) ? ENABLE : DISABLE; + macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE; + macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM); + macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES); + macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 22) == 0U) ? ENABLE : DISABLE; + macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 23) == 0U) ? ENABLE : DISABLE; + macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_APCS) >> 7) > 0U) ? ENABLE : DISABLE; + macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IFG); + macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPCO) >> 27) > 0U) ? ENABLE : DISABLE; + + + macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_TFCE) >> 1) > 0U) ? ENABLE : DISABLE; + macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_ZQPD) >> 7) == 0U) ? ENABLE : DISABLE; + macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_PLT); + macconf->PauseTime = (READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_PT) >> 16); + macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_RFCE) > 0U) ? ENABLE : DISABLE; + macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_UPFD) >> 1) > 0U) + ? ENABLE : DISABLE; - /* Enable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionEnable(heth); + return HAL_OK; +} + +/** + * @brief Get the configuration of the DMA. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold + * the configuration of the ETH DMA. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +{ + if (dmaconf == NULL) + { + return HAL_ERROR; + } - /* Enable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionEnable(heth); + dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_DSL) >> 2; + dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_AAB) >> 12) > 0U) ? ENABLE : DISABLE; + dmaconf->BurstMode = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_FB | ETH_DMABMR_MB); + dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_RDP); + dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_PBL); + dmaconf->EnhancedDescriptorFormat = ((READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_EDE) >> 7) > 0U) ? ENABLE : DISABLE; + dmaconf->DescriptorSkipLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_DSL) >> 2; + + dmaconf->DropTCPIPChecksumErrorFrame = ((READ_BIT(heth->Instance->DMAOMR, + ETH_DMAOMR_DTCEFD) >> 26) > 0U) ? DISABLE : ENABLE; + dmaconf->ReceiveStoreForward = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_RSF) >> 25) > 0U) ? ENABLE : DISABLE; + dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_FTF) >> 20) > 0U) ? DISABLE : ENABLE; + dmaconf->TransmitStoreForward = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_TSF) >> 21) > 0U) ? ENABLE : DISABLE; + dmaconf->TransmitThresholdControl = READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_TTC); + dmaconf->ForwardErrorFrames = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_FEF) >> 7) > 0U) ? ENABLE : DISABLE; + dmaconf->ForwardUndersizedGoodFrames = ((READ_BIT(heth->Instance->DMAOMR, + ETH_DMAOMR_FUGF) >> 6) > 0U) ? ENABLE : DISABLE; + dmaconf->ReceiveThresholdControl = READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_RTC); + dmaconf->SecondFrameOperate = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_OSF) >> 2) > 0U) ? ENABLE : DISABLE; + return HAL_OK; +} - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); +/** + * @brief Set the MAC configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains + * the configuration of the MAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + if (macconf == NULL) + { + return HAL_ERROR; + } - /* Start DMA transmission */ - ETH_DMATransmissionEnable(heth); + if (heth->gState == HAL_ETH_STATE_READY) + { + ETH_SetMACConfig(heth, macconf); - /* Start DMA reception */ - ETH_DMAReceptionEnable(heth); + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} - /* Set the ETH state to READY*/ - heth->State= HAL_ETH_STATE_READY; +/** + * @brief Set the ETH DMA configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold + * the configuration of the ETH DMA. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +{ + if (dmaconf == NULL) + { + return HAL_ERROR; + } - /* Process Unlocked */ - __HAL_UNLOCK(heth); + if (heth->gState == HAL_ETH_STATE_READY) + { + ETH_SetDMAConfig(heth, dmaconf); - /* Return function status */ - return HAL_OK; + return HAL_OK; + } + else + { + return HAL_ERROR; + } } /** - * @brief Stop Ethernet MAC and DMA reception/transmission - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Configures the Clock range of ETH MDIO interface. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @retval HAL status + * @retval None */ -HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) +void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) { - /* Process Locked */ - __HAL_LOCK(heth); + uint32_t hclk; + uint32_t tmpreg; - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; + /* Get the ETHERNET MACMIIAR value */ + tmpreg = (heth->Instance)->MACMIIAR; + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg &= ETH_MACMIIAR_CR_MASK; - /* Stop DMA transmission */ - ETH_DMATransmissionDisable(heth); + /* Get hclk frequency value */ + hclk = HAL_RCC_GetHCLKFreq(); - /* Stop DMA reception */ - ETH_DMAReceptionDisable(heth); + /* Set CR bits depending on hclk value */ + if ((hclk >= 20000000U) && (hclk < 35000000U)) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; + } + else if ((hclk >= 35000000U) && (hclk < 60000000U)) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; + } + else if ((hclk >= 60000000U) && (hclk < 100000000U)) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + else if ((hclk >= 100000000U) && (hclk < 150000000U)) + { + /* CSR Clock Range between 100-150 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; + } + else /* ((hclk >= 150000000)&&(hclk <= 183000000))*/ + { + /* CSR Clock Range between 150-183 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; + } - /* Disable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionDisable(heth); + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ + (heth->Instance)->MACMIIAR = (uint32_t)tmpreg; +} - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); +/** + * @brief Set the ETH MAC (L2) Filters configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains + * the configuration of the ETH MAC filters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) +{ + uint32_t filterconfig; - /* Disable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionDisable(heth); + if (pFilterConfig == NULL) + { + return HAL_ERROR; + } - /* Set the ETH state*/ - heth->State = HAL_ETH_STATE_READY; + filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode | + ((uint32_t)pFilterConfig->HashUnicast << 1) | + ((uint32_t)pFilterConfig->HashMulticast << 2) | + ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | + ((uint32_t)pFilterConfig->PassAllMulticast << 4) | + ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | + ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | + ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | + ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | + ((uint32_t)pFilterConfig->ReceiveAllMode << 31) | + pFilterConfig->ControlPacketsFilter); - /* Process Unlocked */ - __HAL_UNLOCK(heth); + MODIFY_REG(heth->Instance->MACFFR, ETH_MACFFR_MASK, filterconfig); - /* Return function status */ return HAL_OK; } /** - * @brief Set ETH MAC Configuration. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Get the ETH MAC (L2) Filters configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param macconf MAC Configuration structure + * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold + * the configuration of the ETH MAC filters. * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) +HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) { - uint32_t tmpreg1 = 0U; + if (pFilterConfig == NULL) + { + return HAL_ERROR; + } - /* Process Locked */ - __HAL_LOCK(heth); + pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PM)) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_HU) >> 1) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_HM) >> 2) > 0U) ? ENABLE : DISABLE; + pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACFFR, + ETH_MACFFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; + pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PAM) >> 4) > 0U) ? ENABLE : DISABLE; + pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_BFD) >> 5) == 0U) ? ENABLE : DISABLE; + pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PCF); + pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACFFR, + ETH_MACFFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; + pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_HPF) >> 10) > 0U) + ? ENABLE : DISABLE; + pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_RA) >> 31) > 0U) ? ENABLE : DISABLE; - /* Set the ETH peripheral state to BUSY */ - heth->State= HAL_ETH_STATE_BUSY; - - assert_param(IS_ETH_SPEED(heth->Init.Speed)); - assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - - if (macconf != NULL) - { - /* Check the parameters */ - assert_param(IS_ETH_WATCHDOG(macconf->Watchdog)); - assert_param(IS_ETH_JABBER(macconf->Jabber)); - assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap)); - assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense)); - assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn)); - assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode)); - assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload)); - assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission)); - assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip)); - assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit)); - assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck)); - assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll)); - assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter)); - assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames)); - assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception)); - assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter)); - assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode)); - assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter)); - assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter)); - assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime)); - assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause)); - assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold)); - assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect)); - assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl)); - assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl)); - assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison)); - assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier)); - - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg1 = (heth->Instance)->MACCR; - /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg1 &= ETH_MACCR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)(macconf->Watchdog | - macconf->Jabber | - macconf->InterFrameGap | - macconf->CarrierSense | - (heth->Init).Speed | - macconf->ReceiveOwn | - macconf->LoopbackMode | - (heth->Init).DuplexMode | - macconf->ChecksumOffload | - macconf->RetryTransmission | - macconf->AutomaticPadCRCStrip | - macconf->BackOffLimit | - macconf->DeferralCheck); - - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | - macconf->SourceAddrFilter | - macconf->PassControlFrames | - macconf->BroadcastFramesReception | - macconf->DestinationAddrFilter | - macconf->PromiscuousMode | - macconf->MulticastFramesFilter | - macconf->UnicastFramesFilter); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFFR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFFR = tmpreg1; - - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ - /* Write to ETHERNET MACHTHR */ - (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh; - - /* Write to ETHERNET MACHTLR */ - (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration --------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg1 = (heth->Instance)->MACFCR; - /* Clear xx bits */ - tmpreg1 &= ETH_MACFCR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | - macconf->ZeroQuantaPause | - macconf->PauseLowThreshold | - macconf->UnicastPauseFrameDetect | - macconf->ReceiveFlowControl | - macconf->TransmitFlowControl); - - /* Write to ETHERNET MACFCR */ - (heth->Instance)->MACFCR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFCR = tmpreg1; + return HAL_OK; +} - /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ - (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | - macconf->VLANTagIdentifier); +/** + * @brief Set the source MAC Address to be matched. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param AddrNbr: The MAC address to configure + * This parameter must be a value of the following: + * ETH_MAC_ADDRESS1 + * ETH_MAC_ADDRESS2 + * ETH_MAC_ADDRESS3 + * @param pMACAddr: Pointer to MAC address buffer data (6 bytes) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr) +{ + uint32_t macaddrlr; + uint32_t macaddrhr; - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACVLANTR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACVLANTR = tmpreg1; - } - else /* macconf == NULL : here we just configure Speed and Duplex mode */ + if (pMACAddr == NULL) { - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg1 = (heth->Instance)->MACCR; + return HAL_ERROR; + } - /* Clear FES and DM bits */ - tmpreg1 &= ~(0x00004800U); + /* Get mac addr high reg offset */ + macaddrhr = ((uint32_t) &(heth->Instance->MACA0HR) + AddrNbr); + /* Get mac addr low reg offset */ + macaddrlr = ((uint32_t) &(heth->Instance->MACA0LR) + AddrNbr); - tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); + /* Set MAC addr bits 32 to 47 */ + (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]); + /* Set MAC addr bits 0 to 31 */ + (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) | + ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]); - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg1; + /* Enable address and set source address bit */ + (*(__IO uint32_t *)macaddrhr) |= (ETH_MACA1HR_AE | ETH_MACA1HR_SA); - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - } + return HAL_OK; +} - /* Set the ETH state to Ready */ - heth->State= HAL_ETH_STATE_READY; +/** + * @brief Set the ETH Hash Table Value. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pHashTable: pointer to a table of two 32 bit values, that contains + * the 64 bits of the hash table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable) +{ + if (pHashTable == NULL) + { + return HAL_ERROR; + } - /* Process Unlocked */ - __HAL_UNLOCK(heth); + heth->Instance->MACHTHR = pHashTable[0]; + heth->Instance->MACHTLR = pHashTable[1]; - /* Return function status */ return HAL_OK; } /** - * @brief Sets ETH DMA Configuration. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Set the VLAN Identifier for Rx packets + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param dmaconf DMA Configuration structure - * @retval HAL status + * @param ComparisonBits: 12 or 16 bit comparison mode + must be a value of @ref ETH_VLAN_Tag_Comparison + * @param VLANIdentifier: VLAN Identifier value + * @retval None */ -HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) +void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier) { - uint32_t tmpreg1 = 0U; + MODIFY_REG(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTI, VLANIdentifier); + if (ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT) + { + CLEAR_BIT(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTC); + } + else + { + SET_BIT(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTC); + } +} - /* Process Locked */ - __HAL_LOCK(heth); +/** + * @brief Enters the Power down mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure + * that contains the Power Down configuration + * @retval None. + */ +void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig) +{ + uint32_t powerdownconfig; - /* Set the ETH peripheral state to BUSY */ - heth->State= HAL_ETH_STATE_BUSY; - - /* Check parameters */ - assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame)); - assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward)); - assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame)); - assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward)); - assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl)); - assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames)); - assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames)); - assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl)); - assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate)); - assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats)); - assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst)); - assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength)); - assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength)); - assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat)); - assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength)); - assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration)); + powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << ETH_MACPMTCSR_MPE_Pos) | + ((uint32_t)pPowerDownConfig->WakeUpPacket << ETH_MACPMTCSR_WFE_Pos) | + ((uint32_t)pPowerDownConfig->GlobalUnicast << ETH_MACPMTCSR_GU_Pos) | + ETH_MACPMTCSR_PD); - /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ - /* Get the ETHERNET DMAOMR value */ - tmpreg1 = (heth->Instance)->DMAOMR; - /* Clear xx bits */ - tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; + MODIFY_REG(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_MASK, powerdownconfig); +} - tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | - dmaconf->ReceiveStoreForward | - dmaconf->FlushReceivedFrame | - dmaconf->TransmitStoreForward | - dmaconf->TransmitThresholdControl | - dmaconf->ForwardErrorFrames | - dmaconf->ForwardUndersizedGoodFrames | - dmaconf->ReceiveThresholdControl | - dmaconf->SecondFrameOperate); +/** + * @brief Exits from the Power down mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None. + */ +void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth) +{ + /* clear wake up sources */ + CLEAR_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_WFE | ETH_MACPMTCSR_MPE | ETH_MACPMTCSR_GU); - /* Write to ETHERNET DMAOMR */ - (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; + if (READ_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_PD) != 0U) + { + /* Exit power down mode */ + CLEAR_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_PD); + } - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMAOMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg1; + /* Disable PMT interrupt */ + SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_PMTIM); +} - /*----------------------- ETHERNET DMABMR Configuration --------------------*/ - (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | - dmaconf->FixedBurst | - dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - dmaconf->TxDMABurstLength | - dmaconf->EnhancedDescriptorFormat | - (dmaconf->DescriptorSkipLength << 2U) | - dmaconf->DMAArbitration | - ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ +/** + * @brief Set the WakeUp filter. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pFilter: pointer to filter registers values + * @param Count: number of filter registers, must be from 1 to 8. + * @retval None. + */ +HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count) +{ + uint32_t regindex; - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMABMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMABMR = tmpreg1; + if (pFilter == NULL) + { + return HAL_ERROR; + } - /* Set the ETH state to Ready */ - heth->State= HAL_ETH_STATE_READY; + /* Reset Filter Pointer */ + SET_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_WFFRPR); - /* Process Unlocked */ - __HAL_UNLOCK(heth); + /* Wake up packet filter config */ + for (regindex = 0; regindex < Count; regindex++) + { + /* Write filter regs */ + WRITE_REG(heth->Instance->MACRWUFFR, pFilter[regindex]); + } - /* Return function status */ - return HAL_OK; + return HAL_OK; } /** * @} */ -/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief ETH State and Errors functions * - @verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - (+) Get the ETH handle state: - HAL_ETH_GetState(); +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + ETH communication process, return Peripheral Errors occurred during communication + process - @endverbatim +@endverbatim * @{ */ /** - * @brief Return the ETH HAL state - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Returns the ETH state. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL state */ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) { - /* Return ETH state */ - return heth->State; + return heth->gState; +} + +/** + * @brief Returns the ETH error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH Error Code + */ +uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth) +{ + return heth->ErrorCode; +} + +/** + * @brief Returns the ETH DMA error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH DMA Error Code + */ +uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth) +{ + return heth->DMAErrorCode; +} + +/** + * @brief Returns the ETH MAC error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH MAC Error Code + */ +uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth) +{ + return heth->MACErrorCode; +} + +/** + * @brief Returns the ETH MAC WakeUp event source + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH MAC WakeUp event source + */ +uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth) +{ + return heth->MACWakeUpEvent; } /** @@ -1823,265 +2605,190 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) * @} */ -/** @addtogroup ETH_Private_Functions +/** @addtogroup ETH_Private_Functions ETH Private Functions * @{ */ /** - * @brief Configures Ethernet MAC and DMA with default parameters. + * @brief Clears the ETHERNET transmit FIFO. * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param err Ethernet Init error - * @retval HAL status + * @retval None */ -static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) +static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) { - ETH_MACInitTypeDef macinit; - ETH_DMAInitTypeDef dmainit; - uint32_t tmpreg1 = 0U; + __IO uint32_t tmpreg = 0; - if (err != ETH_SUCCESS) /* Auto-negotiation failed */ - { - /* Set Ethernet duplex mode to Full-duplex */ - (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; + /* Set the Flush Transmit FIFO bit */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; - /* Set Ethernet speed to 100M */ - (heth->Init).Speed = ETH_SPEED_100M; - } + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = (heth->Instance)->DMAOMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMAOMR = tmpreg; +} - /* Ethernet MAC default initialization **************************************/ - macinit.Watchdog = ETH_WATCHDOG_ENABLE; - macinit.Jabber = ETH_JABBER_ENABLE; - macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT; - macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE; - macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE; - macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE; - if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) - { - macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; - } - else - { - macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; - } - macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE; - macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; - macinit.BackOffLimit = ETH_BACKOFFLIMIT_10; - macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE; - macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE; - macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; - macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; - macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; - macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; - macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; - macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; - macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; - macinit.HashTableHigh = 0x0U; - macinit.HashTableLow = 0x0U; - macinit.PauseTime = 0x0U; - macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; - macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; - macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; - macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; - macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; - macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; - macinit.VLANTagIdentifier = 0x0U; +static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + uint32_t tmpreg1; /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ tmpreg1 = (heth->Instance)->MACCR; /* Clear WD, PCE, PS, TE and RE bits */ tmpreg1 &= ETH_MACCR_CLEAR_MASK; - /* Set the WD bit according to ETH Watchdog value */ - /* Set the JD: bit according to ETH Jabber value */ - /* Set the IFG bit according to ETH InterFrameGap value */ - /* Set the DCRS bit according to ETH CarrierSense value */ - /* Set the FES bit according to ETH Speed value */ - /* Set the DO bit according to ETH ReceiveOwn value */ - /* Set the LM bit according to ETH LoopbackMode value */ - /* Set the DM bit according to ETH Mode value */ - /* Set the IPCO bit according to ETH ChecksumOffload value */ - /* Set the DR bit according to ETH RetryTransmission value */ - /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ - /* Set the BL bit according to ETH BackOffLimit value */ - /* Set the DC bit according to ETH DeferralCheck value */ - tmpreg1 |= (uint32_t)(macinit.Watchdog | - macinit.Jabber | - macinit.InterFrameGap | - macinit.CarrierSense | - (heth->Init).Speed | - macinit.ReceiveOwn | - macinit.LoopbackMode | - (heth->Init).DuplexMode | - macinit.ChecksumOffload | - macinit.RetryTransmission | - macinit.AutomaticPadCRCStrip | - macinit.BackOffLimit | - macinit.DeferralCheck); + + tmpreg1 |= (uint32_t)(((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) | + ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) | + (uint32_t)macconf->InterPacketGapVal | + ((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) | + macconf->Speed | + ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) | + ((uint32_t)macconf->LoopbackMode << 12U) | + macconf->DuplexMode | + ((uint32_t)macconf->ChecksumOffload << 10U) | + ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) | + ((uint32_t)macconf->AutomaticPadCRCStrip << 7U) | + macconf->BackOffLimit | + ((uint32_t)macconf->DeferralCheck << 4U)); /* Write to ETHERNET MACCR */ (heth->Instance)->MACCR = (uint32_t)tmpreg1; - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ tmpreg1 = (heth->Instance)->MACCR; HAL_Delay(ETH_REG_WRITE_DELAY); (heth->Instance)->MACCR = tmpreg1; - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Set the RA bit according to ETH ReceiveAll value */ - /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ - /* Set the PCF bit according to ETH PassControlFrames value */ - /* Set the DBF bit according to ETH BroadcastFramesReception value */ - /* Set the DAIF bit according to ETH DestinationAddrFilter value */ - /* Set the PR bit according to ETH PromiscuousMode value */ - /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ - /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | - macinit.SourceAddrFilter | - macinit.PassControlFrames | - macinit.BroadcastFramesReception | - macinit.DestinationAddrFilter | - macinit.PromiscuousMode | - macinit.MulticastFramesFilter | - macinit.UnicastFramesFilter); - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFFR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFFR = tmpreg1; - - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ - /* Write to ETHERNET MACHTHR */ - (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh; - - /* Write to ETHERNET MACHTLR */ - (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration -------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg1 = (heth->Instance)->MACFCR; - /* Clear xx bits */ - tmpreg1 &= ETH_MACFCR_CLEAR_MASK; - - /* Set the PT bit according to ETH PauseTime value */ - /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ - /* Set the PLT bit according to ETH PauseLowThreshold value */ - /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ - /* Set the RFE bit according to ETH ReceiveFlowControl value */ - /* Set the TFE bit according to ETH TransmitFlowControl value */ - tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) | - macinit.ZeroQuantaPause | - macinit.PauseLowThreshold | - macinit.UnicastPauseFrameDetect | - macinit.ReceiveFlowControl | - macinit.TransmitFlowControl); - - /* Write to ETHERNET MACFCR */ - (heth->Instance)->MACFCR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFCR = tmpreg1; - - /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ - /* Set the ETV bit according to ETH VLANTagComparison value */ - /* Set the VL bit according to ETH VLANTagIdentifier value */ - (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | - macinit.VLANTagIdentifier); - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACVLANTR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACVLANTR = tmpreg1; - - /* Ethernet DMA default initialization ************************************/ - dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; - dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; - dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; - dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; - dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; - dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; - dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; - dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; - dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE; - dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; - dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE; - dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; - dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; - dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE; - dmainit.DescriptorSkipLength = 0x0U; - dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; - - /* Get the ETHERNET DMAOMR value */ - tmpreg1 = (heth->Instance)->DMAOMR; - /* Clear xx bits */ - tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; - - /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ - /* Set the RSF bit according to ETH ReceiveStoreForward value */ - /* Set the DFF bit according to ETH FlushReceivedFrame value */ - /* Set the TSF bit according to ETH TransmitStoreForward value */ - /* Set the TTC bit according to ETH TransmitThresholdControl value */ - /* Set the FEF bit according to ETH ForwardErrorFrames value */ - /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ - /* Set the RTC bit according to ETH ReceiveThresholdControl value */ - /* Set the OSF bit according to ETH SecondFrameOperate value */ - tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | - dmainit.ReceiveStoreForward | - dmainit.FlushReceivedFrame | - dmainit.TransmitStoreForward | - dmainit.TransmitThresholdControl | - dmainit.ForwardErrorFrames | - dmainit.ForwardUndersizedGoodFrames | - dmainit.ReceiveThresholdControl | - dmainit.SecondFrameOperate); - - /* Write to ETHERNET DMAOMR */ - (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMAOMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg1; - - /*----------------------- ETHERNET DMABMR Configuration ------------------*/ - /* Set the AAL bit according to ETH AddressAlignedBeats value */ - /* Set the FB bit according to ETH FixedBurst value */ - /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */ - /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */ - /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/ - /* Set the DSL bit according to ETH DesciptorSkipLength value */ - /* Set the PR and DA bits according to ETH DMAArbitration value */ - (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | - dmainit.FixedBurst | - dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - dmainit.TxDMABurstLength | - dmainit.EnhancedDescriptorFormat | - (dmainit.DescriptorSkipLength << 2U) | - dmainit.DMAArbitration | - ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMABMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMABMR = tmpreg1; - - if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) - { - /* Enable the Ethernet Rx Interrupt */ - __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R); - } - - /* Initialize MAC address in ethernet MAC */ - ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + + /* Get the ETHERNET MACFCR value */ + tmpreg1 = (heth->Instance)->MACFCR; + /* Clear xx bits */ + tmpreg1 &= ETH_MACFCR_CLEAR_MASK; + + tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | + (uint32_t)macconf->ZeroQuantaPause | + macconf->PauseLowThreshold | + (uint32_t)macconf->UnicastSlowProtocolPacketDetect | + (uint32_t)macconf->ReceiveFlowControl | + (uint32_t)macconf->TransmitFlowControl); + + /* Write to ETHERNET MACFCR */ + (heth->Instance)->MACFCR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACFCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACFCR = tmpreg1; +} + +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +{ + uint32_t tmpreg1; + + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg1 = (heth->Instance)->DMAOMR; + /* Clear xx bits */ + tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; + + tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) | + ((uint32_t)dmaconf->ReceiveStoreForward << 25U) | + ((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) | + ((uint32_t)dmaconf->TransmitStoreForward << 21U) | + dmaconf->TransmitThresholdControl | + ((uint32_t)dmaconf->ForwardErrorFrames << 7U) | + ((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) | + dmaconf->ReceiveThresholdControl | + ((uint32_t)dmaconf->SecondFrameOperate << 2U)); + + /* Write to ETHERNET DMAOMR */ + (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMAOMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMAOMR = tmpreg1; + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + (heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) | + dmaconf->BurstMode | + dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or + Rx it is applied for the other */ + dmaconf->TxDMABurstLength | + ((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) | + (dmaconf->DescriptorSkipLength << 2U) | + dmaconf->DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMABMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMABMR = tmpreg1; +} + +/** + * @brief Configures Ethernet MAC and DMA with default parameters. + * called by HAL_ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) +{ + ETH_MACConfigTypeDef macDefaultConf; + ETH_DMAConfigTypeDef dmaDefaultConf; + + /*--------------- ETHERNET MAC registers default Configuration --------------*/ + macDefaultConf.Watchdog = ENABLE; + macDefaultConf.Jabber = ENABLE; + macDefaultConf.InterPacketGapVal = ETH_INTERFRAMEGAP_96BIT; + macDefaultConf.CarrierSenseDuringTransmit = DISABLE; + macDefaultConf.ReceiveOwn = ENABLE; + macDefaultConf.LoopbackMode = DISABLE; + macDefaultConf.ChecksumOffload = ENABLE; + macDefaultConf.RetryTransmission = DISABLE; + macDefaultConf.AutomaticPadCRCStrip = DISABLE; + macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10; + macDefaultConf.DeferralCheck = DISABLE; + macDefaultConf.PauseTime = 0x0U; + macDefaultConf.ZeroQuantaPause = DISABLE; + macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; + macDefaultConf.ReceiveFlowControl = DISABLE; + macDefaultConf.TransmitFlowControl = DISABLE; + macDefaultConf.Speed = ETH_SPEED_100M; + macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE; + macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE; + + /* MAC default configuration */ + ETH_SetMACConfig(heth, &macDefaultConf); + + /*--------------- ETHERNET DMA registers default Configuration --------------*/ + dmaDefaultConf.DropTCPIPChecksumErrorFrame = ENABLE; + dmaDefaultConf.ReceiveStoreForward = ENABLE; + dmaDefaultConf.FlushRxPacket = ENABLE; + dmaDefaultConf.TransmitStoreForward = ENABLE; + dmaDefaultConf.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; + dmaDefaultConf.ForwardErrorFrames = DISABLE; + dmaDefaultConf.ForwardUndersizedGoodFrames = DISABLE; + dmaDefaultConf.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; + dmaDefaultConf.SecondFrameOperate = ENABLE; + dmaDefaultConf.AddressAlignedBeats = ENABLE; + dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED; + dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + dmaDefaultConf.EnhancedDescriptorFormat = ENABLE; + dmaDefaultConf.DescriptorSkipLength = 0x0U; + dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; + + /* DMA default configuration */ + ETH_SetDMAConfig(heth, &dmaDefaultConf); } /** @@ -2104,9 +2811,6 @@ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint /* Prevent unused argument(s) compilation warning */ UNUSED(heth); - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - /* Calculate the selected MAC address high register */ tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; /* Load the selected MAC address high register */ @@ -2119,175 +2823,274 @@ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint } /** - * @brief Enables the MAC transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Initializes the DMA Tx descriptors. + * called by HAL_ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ -static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) +static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) { - __IO uint32_t tmpreg1 = 0U; + ETH_DMADescTypeDef *dmatxdesc; + uint32_t i; - /* Enable the MAC transmission */ - (heth->Instance)->MACCR |= ETH_MACCR_TE; + /* Fill each DMATxDesc descriptor with the right values */ + for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) + { + dmatxdesc = heth->Init.TxDesc + i; - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; -} + WRITE_REG(dmatxdesc->DESC0, 0x0); + WRITE_REG(dmatxdesc->DESC1, 0x0); + WRITE_REG(dmatxdesc->DESC2, 0x0); + WRITE_REG(dmatxdesc->DESC3, 0x0); -/** - * @brief Disables the MAC transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg1 = 0U; + WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); - /* Disable the MAC transmission */ - (heth->Instance)->MACCR &= ~ETH_MACCR_TE; + /* Set Second Address Chained bit */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TCH); - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; -} + if (i < ((uint32_t)ETH_TX_DESC_CNT - 1U)) + { + WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc + i + 1U)); + } + else + { + WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc)); + } -/** - * @brief Enables the MAC reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg1 = 0U; + /* Set the DMA Tx descriptors checksum insertion */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL); + } - /* Enable the MAC reception */ - (heth->Instance)->MACCR |= ETH_MACCR_RE; + heth->TxDescList.CurTxDesc = 0; - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; + /* Set Transmit Descriptor List Address */ + WRITE_REG(heth->Instance->DMATDLAR, (uint32_t) heth->Init.TxDesc); } /** - * @brief Disables the MAC reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Initializes the DMA Rx descriptors in chain mode. + * called by HAL_ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ -static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) +static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) { - __IO uint32_t tmpreg1 = 0U; + ETH_DMADescTypeDef *dmarxdesc; + uint32_t i; - /* Disable the MAC reception */ - (heth->Instance)->MACCR &= ~ETH_MACCR_RE; + for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) + { + dmarxdesc = heth->Init.RxDesc + i; - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; -} + WRITE_REG(dmarxdesc->DESC0, 0x0); + WRITE_REG(dmarxdesc->DESC1, 0x0); + WRITE_REG(dmarxdesc->DESC2, 0x0); + WRITE_REG(dmarxdesc->DESC3, 0x0); + WRITE_REG(dmarxdesc->BackupAddr0, 0x0); + WRITE_REG(dmarxdesc->BackupAddr1, 0x0); -/** - * @brief Enables the DMA transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) -{ - /* Enable the DMA transmission */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; -} + /* Set Own bit of the Rx descriptor Status */ + dmarxdesc->DESC0 = ETH_DMARXDESC_OWN; -/** - * @brief Disables the DMA transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) -{ - /* Disable the DMA transmission */ - (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST; -} + /* Set Buffer1 size and Second Address Chained bit */ + dmarxdesc->DESC1 = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; -/** - * @brief Enables the DMA reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) -{ - /* Enable the DMA reception */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; -} + /* Enable Ethernet DMA Rx Descriptor interrupt */ + dmarxdesc->DESC1 &= ~ETH_DMARXDESC_DIC; -/** - * @brief Disables the DMA reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) -{ - /* Disable the DMA reception */ - (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR; + /* Set Rx descritors addresses */ + WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); + + if (i < ((uint32_t)ETH_RX_DESC_CNT - 1U)) + { + WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc + i + 1U)); + } + else + { + WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc)); + } + } + + WRITE_REG(heth->RxDescList.RxDescIdx, 0); + WRITE_REG(heth->RxDescList.RxDescCnt, 0); + WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0); + WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0); + WRITE_REG(heth->RxDescList.ItMode, 0); + + /* Set Receive Descriptor List Address */ + WRITE_REG(heth->Instance->DMARDLAR, (uint32_t) heth->Init.RxDesc); } /** - * @brief Clears the ETHERNET transmit FIFO. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Prepare Tx DMA descriptor before transmission. + * called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @retval None + * @param pTxConfig: Tx packet configuration + * @param ItMode: Enable or disable Tx EOT interrept + * @retval Status */ -static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode) { - __IO uint32_t tmpreg1 = 0U; + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t descidx = dmatxdesclist->CurTxDesc; + uint32_t firstdescidx = dmatxdesclist->CurTxDesc; + uint32_t idx; + uint32_t descnbr = 0; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer; + uint32_t bd_count = 0; + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((READ_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN) == ETH_DMATXDESC_OWN) + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + { + return HAL_ETH_ERROR_BUSY; + } - /* Set the Flush Transmit FIFO bit */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMAOMR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg1; -} + descnbr += 1U; -/** - * @brief This function provides delay (in milliseconds) based on CPU cycles method. - * @param mdelay specifies the delay time length, in milliseconds. - * @retval None - */ -static void ETH_Delay(uint32_t mdelay) -{ - __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); - do + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer); + + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC1, ETH_DMATXDESC_TBS1, txbuffer->len); + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U) + { + MODIFY_REG(dmatxdesc->DESC0, ETH_DMATXDESC_CIC, pTxConfig->ChecksumCtrl); + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U) + { + MODIFY_REG(dmatxdesc->DESC0, ETH_CRC_PAD_DISABLE, pTxConfig->CRCPadCtrl); + } + + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U) + { + /* Set Vlan Type */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_VF); + } + + /* Mark it as First Descriptor */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_FS); + + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* set OWN bit of FIRST descriptor */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN); + + /* only if the packet is split into more than one descriptors > 1 */ + while (txbuffer->next != NULL) + { + /* Clear the LD bit of previous descriptor */ + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_LS); + if (ItMode != ((uint32_t)RESET)) + { + /* Set Interrupt on completion bit */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); + } + else + { + /* Clear Interrupt on completion bit */ + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); + } + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + /* Clear the FD bit of new Descriptor */ + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_FS); + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((READ_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN) == ETH_DMATXDESC_OWN) + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + { + descidx = firstdescidx; + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + /* clear previous desc own bit */ + for (idx = 0; idx < descnbr; idx ++) + { + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN); + + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + } + + return HAL_ETH_ERROR_BUSY; + } + + descnbr += 1U; + + /* Get the next Tx buffer in the list */ + txbuffer = txbuffer->next; + + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer); + + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC1, ETH_DMATXDESC_TBS1, txbuffer->len); + + bd_count += 1U; + + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Set Own bit */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN); + } + + if (ItMode != ((uint32_t)RESET)) + { + /* Set Interrupt on completion bit */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); + } + else { - __NOP(); + /* Clear Interrupt on completion bit */ + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); } - while (Delay --); + + /* Mark it as LAST descriptor */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_LS); + /* Save the current packet address to expose it to the application */ + dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress; + + dmatxdesclist->CurTxDesc = descidx; + + /* disable the interrupt */ + __disable_irq(); + + dmatxdesclist->BuffersInUse += bd_count + 1U; + + /* Enable interrupts back */ + __enable_irq(); + + + /* Return function status */ + return HAL_ETH_ERROR_NONE; } #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) { /* Init the ETH Callback settings */ - heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */ - heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */ - heth->DMAErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak DMAErrorCallback */ + heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */ + heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */ + heth->ErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak ErrorCallback */ + heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */ + heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */ } #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ @@ -2295,15 +3098,15 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ - STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -#endif /* HAL_ETH_MODULE_ENABLED */ /** * @} */ +#endif /* ETH */ + +#endif /* HAL_ETH_MODULE_ENABLED */ + /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c index 099bf1ea25..04b5215fdd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### EXTI Peripheral features ##### @@ -69,18 +80,6 @@ (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -301,8 +300,8 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT { assert_param(IS_EXTI_GPIO_PIN(linepos)); - regval = SYSCFG->EXTICR[linepos >> 2u]; - pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + regval = (SYSCFG->EXTICR[linepos >> 2u] << 16u ); + pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 28u); } } @@ -546,4 +545,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c index 726e2b329f..ab7fcd5c1c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c @@ -63,14 +63,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -775,4 +773,3 @@ static void FLASH_SetErrorCode(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c index 5c72eaaba4..d99eacec3a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c @@ -49,14 +49,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -1347,4 +1345,3 @@ void FLASH_FlushCaches(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c index 2931b20f76..e6ab3ac863 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c @@ -34,14 +34,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -172,4 +170,3 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c index f62aa27c16..d079dd07e7 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c @@ -9,6 +9,17 @@ * + IO operation functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -66,22 +77,22 @@ =================================== [..] (+) Transmit in master mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Transmit_IT() - (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback() + (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Receive_IT() - (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() + (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Transmit_IT() - (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback() + (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Receive_IT() - (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback() + (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_ErrorCallback() (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT() - (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() + (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -94,12 +105,14 @@ [..] (+) A specific option field manage the different steps of a sequential transfer (+) Option field values are defined through FMPI2C_XFEROPTIONS and are listed below: - (++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode + (++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode (++) FMPI2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition - (++) FMPI2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like HAL_FMPI2C_Master_Seq_Transmit_IT() then HAL_FMPI2C_Master_Seq_Transmit_IT() + (++) FMPI2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_FMPI2C_Master_Seq_Transmit_IT() then HAL_FMPI2C_Master_Seq_Transmit_IT() or HAL_FMPI2C_Master_Seq_Transmit_DMA() then HAL_FMPI2C_Master_Seq_Transmit_DMA()) (++) FMPI2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address and with new data to transfer if the direction change or manage only the new data to @@ -135,32 +148,34 @@ generation of STOP condition. (+) Different sequential FMPI2C interfaces are listed below: - (++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Seq_Transmit_IT() - or using HAL_FMPI2C_Master_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback() - (++) Sequential receive in master FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Seq_Receive_IT() - or using HAL_FMPI2C_Master_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() + (++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using + HAL_FMPI2C_Master_Seq_Transmit_IT() or using HAL_FMPI2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback() + (++) Sequential receive in master FMPI2C mode an amount of data in non-blocking mode using + HAL_FMPI2C_Master_Seq_Receive_IT() or using HAL_FMPI2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() (++) Abort a master IT or DMA FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT() - (+++) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave FMPI2C mode using HAL_FMPI2C_EnableListen_IT() HAL_FMPI2C_DisableListen_IT() - (+++) When address slave FMPI2C match, HAL_FMPI2C_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end HAL_FMPI2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_ListenCpltCallback() - (++) Sequential transmit in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Seq_Transmit_IT() - or using HAL_FMPI2C_Slave_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback() - (++) Sequential receive in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Seq_Receive_IT() - or using HAL_FMPI2C_Slave_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback() - (++) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback() + (+++) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave FMPI2C mode using HAL_FMPI2C_EnableListen_IT() + HAL_FMPI2C_DisableListen_IT() + (+++) When address slave FMPI2C match, HAL_FMPI2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_FMPI2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_ListenCpltCallback() + (++) Sequential transmit in slave FMPI2C mode an amount of data in non-blocking mode using + HAL_FMPI2C_Slave_Seq_Transmit_IT() or using HAL_FMPI2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback() + (++) Sequential receive in slave FMPI2C mode an amount of data in non-blocking mode using + HAL_FMPI2C_Slave_Seq_Receive_IT() or using HAL_FMPI2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_ErrorCallback() (++) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -169,39 +184,39 @@ [..] (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using HAL_FMPI2C_Mem_Write_IT() - (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback() + (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using HAL_FMPI2C_Mem_Read_IT() - (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback() + (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using HAL_FMPI2C_Master_Transmit_DMA() - (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback() + (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using HAL_FMPI2C_Master_Receive_DMA() - (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() + (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using HAL_FMPI2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback() + (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using HAL_FMPI2C_Slave_Receive_DMA() - (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback() + (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_ErrorCallback() (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT() - (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() + (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -210,14 +225,14 @@ [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using HAL_FMPI2C_Mem_Write_DMA() - (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback() + (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using HAL_FMPI2C_Mem_Read_DMA() - (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback() + (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_ErrorCallback() *** FMPI2C HAL driver macros list *** @@ -302,18 +317,6 @@ (@) You can refer to the FMPI2C HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -424,33 +427,33 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart); + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart); + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); /* Private functions for FMPI2C transfer IRQ handler */ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources); + uint32_t ITSources); static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources); + uint32_t ITSources); static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources); + uint32_t ITSources); static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources); + uint32_t ITSources); /* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart); + uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart); + uint32_t Tickstart); static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart); + uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest); @@ -464,7 +467,7 @@ static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c); /* Private function to handle start, restart or stop a transfer */ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request); + uint32_t Request); /* Private function to Convert Specific options */ static void FMPI2C_ConvertOtherXferOptions(FMPI2C_HandleTypeDef *hfmpi2c); @@ -603,7 +606,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c) /* Configure FMPI2Cx: Dual mode and Own Address2 */ hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | \ - (hfmpi2c->Init.OwnAddress2Masks << 8)); + (hfmpi2c->Init.OwnAddress2Masks << 8)); /*---------------------------- FMPI2Cx CR1 Configuration ----------------------*/ /* Configure FMPI2Cx: Generalcall and NoStretch mode */ @@ -1110,7 +1113,7 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout) + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1142,13 +1145,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_GENERATE_START_WRITE); + FMPI2C_GENERATE_START_WRITE); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_WRITE); + FMPI2C_GENERATE_START_WRITE); } while (hfmpi2c->XferCount > 0U) @@ -1179,13 +1182,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } } } @@ -1229,7 +1232,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout) + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1261,13 +1264,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); } while (hfmpi2c->XferCount > 0U) @@ -1299,13 +1302,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } } } @@ -1347,7 +1350,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout) + uint32_t Timeout) { uint32_t tickstart; @@ -1485,7 +1488,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout) + uint32_t Timeout) { uint32_t tickstart; @@ -1967,7 +1970,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_WRITE); + FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2114,7 +2117,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2442,13 +2445,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } } @@ -2544,13 +2547,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); } do @@ -2582,13 +2585,13 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De { hfmpi2c->XferSize = MAX_NBYTE_SIZE; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t) hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_NO_STARTSTOP); + FMPI2C_NO_STARTSTOP); } } } while (hfmpi2c->XferCount > 0U); @@ -3108,7 +3111,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ * @retval HAL status */ HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout) + uint32_t Timeout) { uint32_t tickstart; @@ -3289,7 +3292,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 do not generate Restart Condition */ /* Mean Previous state is same as current state */ if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && \ - (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = FMPI2C_NO_STARTSTOP; } @@ -3377,7 +3380,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi do not generate Restart Condition */ /* Mean Previous state is same as current state */ if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && \ - (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = FMPI2C_NO_STARTSTOP; } @@ -3469,7 +3472,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_WRITE); + FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3544,7 +3547,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c do not generate Restart Condition */ /* Mean Previous state is same as current state */ if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && \ - (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = FMPI2C_NO_STARTSTOP; } @@ -3632,7 +3635,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 do not generate Restart Condition */ /* Mean Previous state is same as current state */ if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && \ - (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = FMPI2C_NO_STARTSTOP; } @@ -3724,7 +3727,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, - FMPI2C_GENERATE_START_READ); + FMPI2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -4453,7 +4456,7 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) /* FMPI2C Bus error interrupt occurred ------------------------------------*/ if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_BERR) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) + (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_BERR; @@ -4463,7 +4466,7 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) /* FMPI2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_OVR) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) + (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_OVR; @@ -4473,7 +4476,7 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) /* FMPI2C Arbitration Loss error interrupt occurred -------------------------------------*/ if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_ARLO) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) + (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_ARLO; @@ -4728,7 +4731,7 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c) * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint16_t devaddress; uint32_t tmpITFlags = ITFlags; @@ -4737,7 +4740,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm __HAL_LOCK(hfmpi2c); if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); @@ -4795,12 +4798,12 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) { FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, - hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP); + hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP); } else { FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, - FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); } } } @@ -4853,7 +4856,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm } if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Master complete process */ FMPI2C_ITMasterCplt(hfmpi2c, tmpITFlags); @@ -4874,7 +4877,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint32_t tmpoptions = hfmpi2c->XferOptions; uint32_t tmpITFlags = ITFlags; @@ -4884,14 +4887,14 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp /* Check if STOPF is set */ if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Slave complete process */ FMPI2C_ITSlaveCplt(hfmpi2c, tmpITFlags); } if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Check that FMPI2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5015,7 +5018,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint16_t devaddress; uint32_t xfermode; @@ -5024,7 +5027,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf __HAL_LOCK(hfmpi2c); if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); @@ -5041,7 +5044,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf FMPI2C_Flush_TXDR(hfmpi2c); } else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TCR) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_FMPI2C_DISABLE_IT(hfmpi2c, FMPI2C_IT_TCI); @@ -5103,7 +5106,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf } } else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TC) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) { if (hfmpi2c->XferCount == 0U) { @@ -5155,7 +5158,7 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, - uint32_t ITSources) + uint32_t ITSources) { uint32_t tmpoptions = hfmpi2c->XferOptions; uint32_t treatdmanack = 0U; @@ -5166,14 +5169,14 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm /* Check if STOPF is set */ if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Slave complete process */ FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags); } if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Check that FMPI2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5272,7 +5275,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm } } else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_ADDR) != RESET) && \ - (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_ADDRI) != RESET)) + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_ADDRI) != RESET)) { FMPI2C_ITAddrCplt(hfmpi2c, ITFlags); } @@ -5300,8 +5303,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart) + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); @@ -5355,8 +5358,8 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart) + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE); @@ -6363,11 +6366,12 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma) } /** - * @brief This function handles FMPI2C Communication Timeout. + * @brief This function handles FMPI2C Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. * @param Flag Specifies the FMPI2C flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status @@ -6404,12 +6408,12 @@ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfm * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart) + uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET) { - /* Check if a NACK is detected */ - if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6442,12 +6446,12 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart) + uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) { - /* Check if a NACK is detected */ - if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6477,12 +6481,12 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef * @retval HAL status */ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, - uint32_t Tickstart) + uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET) { - /* Check if a NACK is detected */ - if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6533,16 +6537,20 @@ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef } /** - * @brief This function handles Acknowledge failed detection during an FMPI2C Communication. + * @brief This function handles errors detection during an FMPI2C Communication. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) { - if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hfmpi2c->Instance->ISR; + uint32_t error_code = 0; + + if (HAL_IS_BIT_SET(itflag, FMPI2C_FLAG_AF)) { /* In case of Soft End condition, generate the STOP condition */ if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE) @@ -6550,49 +6558,92 @@ static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2 /* Generate Stop */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP; } - /* Wait until STOP Flag is reset */ + + /* Wait until STOP Flag is set or timeout occurred */ /* AutoEnd should be initiate after AF */ - while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) + while ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + error_code |= HAL_FMPI2C_ERROR_TIMEOUT; - return HAL_ERROR; + status = HAL_ERROR; } } } + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); + } + /* Clear NACKF Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); - /* Clear STOP Flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); + error_code |= HAL_FMPI2C_ERROR_AF; + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hfmpi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, FMPI2C_FLAG_BERR)) + { + error_code |= HAL_FMPI2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_BERR); + + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, FMPI2C_FLAG_OVR)) + { + error_code |= HAL_FMPI2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, FMPI2C_FLAG_ARLO)) + { + error_code |= HAL_FMPI2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { /* Flush TX register */ FMPI2C_Flush_TXDR(hfmpi2c); /* Clear Configuration Register 2 */ FMPI2C_RESET_CR2(hfmpi2c); - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; + hfmpi2c->ErrorCode |= error_code; hfmpi2c->State = HAL_FMPI2C_STATE_READY; hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); - - return HAL_ERROR; } - return HAL_OK; + + return status; } /** @@ -6622,14 +6673,16 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAdd assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | \ + (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + /* update CR2 register */ - MODIFY_REG(hfmpi2c->Instance->CR2, + MODIFY_REG(hfmpi2c->Instance->CR2, \ ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | \ (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | \ - FMPI2C_CR2_START | FMPI2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | \ - (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request)); + FMPI2C_CR2_START | FMPI2C_CR2_STOP)), tmp); } /** @@ -6809,5 +6862,3 @@ static void FMPI2C_ConvertOtherXferOptions(FMPI2C_HandleTypeDef *hfmpi2c) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c index 0a8f72ccf7..267a9ef13d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c @@ -8,6 +8,17 @@ * + Filter Mode Functions * + FastModePlus Functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### FMPI2C peripheral Extended features ##### @@ -29,18 +40,6 @@ (++) HAL_FMPI2CEx_EnableFastModePlus() (++) HAL_FMPI2CEx_DisableFastModePlus() @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -257,5 +256,3 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c index 578ecc5bfc..700f25af05 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c @@ -10,6 +10,17 @@ * + IO operation functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -44,35 +55,41 @@ *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master/host FMPSMBUS mode an amount of data in non-blocking mode using HAL_FMPSMBUS_Master_Transmit_IT() - (++) At transmission end of transfer HAL_FMPSMBUS_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPSMBUS_MasterTxCpltCallback() - (+) Receive in master/host FMPSMBUS mode an amount of data in non-blocking mode using HAL_FMPSMBUS_Master_Receive_IT() - (++) At reception end of transfer HAL_FMPSMBUS_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPSMBUS_MasterRxCpltCallback() + (+) Transmit in master/host FMPSMBUS mode an amount of data in non-blocking mode + using HAL_FMPSMBUS_Master_Transmit_IT() + (++) At transmission end of transfer HAL_FMPSMBUS_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_MasterTxCpltCallback() + (+) Receive in master/host FMPSMBUS mode an amount of data in non-blocking mode + using HAL_FMPSMBUS_Master_Receive_IT() + (++) At reception end of transfer HAL_FMPSMBUS_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_MasterRxCpltCallback() (+) Abort a master/host FMPSMBUS process communication with Interrupt using HAL_FMPSMBUS_Master_Abort_IT() (++) The associated previous transfer callback is called at the end of abort process (++) mean HAL_FMPSMBUS_MasterTxCpltCallback() in case of previous state was master transmit (++) mean HAL_FMPSMBUS_MasterRxCpltCallback() in case of previous state was master receive (+) Enable/disable the Address listen mode in slave/device or host/slave FMPSMBUS mode using HAL_FMPSMBUS_EnableListen_IT() HAL_FMPSMBUS_DisableListen_IT() - (++) When address slave/device FMPSMBUS match, HAL_FMPSMBUS_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). - (++) At Listen mode end HAL_FMPSMBUS_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPSMBUS_ListenCpltCallback() - (+) Transmit in slave/device FMPSMBUS mode an amount of data in non-blocking mode using HAL_FMPSMBUS_Slave_Transmit_IT() - (++) At transmission end of transfer HAL_FMPSMBUS_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPSMBUS_SlaveTxCpltCallback() - (+) Receive in slave/device FMPSMBUS mode an amount of data in non-blocking mode using HAL_FMPSMBUS_Slave_Receive_IT() - (++) At reception end of transfer HAL_FMPSMBUS_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPSMBUS_SlaveRxCpltCallback() - (+) Enable/Disable the FMPSMBUS alert mode using HAL_FMPSMBUS_EnableAlert_IT() HAL_FMPSMBUS_DisableAlert_IT() - (++) When FMPSMBUS Alert is generated HAL_FMPSMBUS_ErrorCallback() is executed and user can - add his own code by customization of function pointer HAL_FMPSMBUS_ErrorCallback() + (++) When address slave/device FMPSMBUS match, HAL_FMPSMBUS_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction + request by master/host (Write/Read). + (++) At Listen mode end HAL_FMPSMBUS_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_ListenCpltCallback() + (+) Transmit in slave/device FMPSMBUS mode an amount of data in non-blocking mode + using HAL_FMPSMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer HAL_FMPSMBUS_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device FMPSMBUS mode an amount of data in non-blocking mode + using HAL_FMPSMBUS_Slave_Receive_IT() + (++) At reception end of transfer HAL_FMPSMBUS_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the FMPSMBUS alert mode using + HAL_FMPSMBUS_EnableAlert_IT() or HAL_FMPSMBUS_DisableAlert_IT() + (++) When FMPSMBUS Alert is generated HAL_FMPSMBUS_ErrorCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_ErrorCallback() to check the Alert Error Code using function HAL_FMPSMBUS_GetError() (+) Get HAL state machine or error values using HAL_FMPSMBUS_GetState() or HAL_FMPSMBUS_GetError() - (+) In case of transfer Error, HAL_FMPSMBUS_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_FMPSMBUS_ErrorCallback() + (+) In case of transfer Error, HAL_FMPSMBUS_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_ErrorCallback() to check the Error Code using function HAL_FMPSMBUS_GetError() *** FMPSMBUS HAL driver macros list *** @@ -150,18 +167,6 @@ (@) You can refer to the FMPSMBUS HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -205,7 +210,7 @@ * @{ */ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, - FlagStatus Status, uint32_t Timeout); + FlagStatus Status, uint32_t Timeout); static void FMPSMBUS_Enable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); static void FMPSMBUS_Disable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); @@ -217,7 +222,7 @@ static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus); static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, - uint32_t Mode, uint32_t Request); + uint32_t Mode, uint32_t Request); /** * @} */ @@ -588,8 +593,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, - pFMPSMBUS_CallbackTypeDef pCallback) + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, + pFMPSMBUS_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -703,7 +708,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbu * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - HAL_FMPSMBUS_CallbackIDTypeDef CallbackID) + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -799,7 +804,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsm * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, - pFMPSMBUS_AddrCallbackTypeDef pCallback) + pFMPSMBUS_AddrCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -924,7 +929,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf * @retval HAL status */ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, - uint8_t *pData, uint16_t Size, uint32_t XferOptions) + uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -979,7 +984,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -1086,7 +1091,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -1248,7 +1253,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmb { /* Set NBYTE to transmit */ FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ @@ -1335,7 +1340,7 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbu if (((FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) && (hfmpsmbus->XferSize == 2U)) || (hfmpsmbus->XferSize == 1U)) { FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); } else { @@ -1599,7 +1604,7 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) /* FMPSMBUS in mode Transmitter ---------------------------------------------------*/ if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | - FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) && + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TXIS) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || @@ -1624,7 +1629,7 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) /* FMPSMBUS in mode Receiver ----------------------------------------------------*/ if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | - FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) && + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_RXNE) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || @@ -1745,7 +1750,7 @@ __weak void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) * @retval None */ __weak void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, - uint16_t AddrMatchCode) + uint16_t AddrMatchCode) { /* Prevent unused argument(s) compilation warning */ UNUSED(hfmpsmbus); @@ -2000,7 +2005,7 @@ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, { hfmpsmbus->XferSize = hfmpsmbus->XferCount; FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) @@ -2275,7 +2280,7 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u { hfmpsmbus->XferSize = hfmpsmbus->XferCount; FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, - FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) @@ -2620,7 +2625,7 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) * @retval HAL status */ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, - FlagStatus Status, uint32_t Timeout) + FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2670,7 +2675,7 @@ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef * @retval None */ static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, - uint32_t Mode, uint32_t Request) + uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance)); @@ -2742,5 +2747,3 @@ static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus_ex.c index e5147ca66a..14ca0b4244 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus_ex.c @@ -7,6 +7,17 @@ * functionalities of FMPSMBUS Extended peripheral: * + Extended features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### FMPSMBUS peripheral Extended features ##### @@ -23,18 +34,6 @@ (++) HAL_FMPSMBUSEx_EnableFastModePlus() (++) HAL_FMPSMBUSEx_DisableFastModePlus() @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -144,5 +143,3 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c index cc28b03844..8d3b3e8daf 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### GPIO Peripheral features ##### @@ -91,17 +102,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -245,39 +245,39 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); SYSCFG->EXTICR[position >> 2U] = temp; - /* Clear EXTI line configuration */ - temp = EXTI->IMR; + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & EXTI_IT) != 0x00U) + if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) { temp |= iocurrent; } - EXTI->IMR = temp; + EXTI->RTSR = temp; - temp = EXTI->EMR; + temp = EXTI->FTSR; temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) { temp |= iocurrent; } - EXTI->EMR = temp; + EXTI->FTSR = temp; - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR; + temp = EXTI->EMR; temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) { temp |= iocurrent; } - EXTI->RTSR = temp; + EXTI->EMR = temp; - temp = EXTI->FTSR; + /* Clear EXTI line configuration */ + temp = EXTI->IMR; temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + if((GPIO_Init->Mode & EXTI_IT) != 0x00U) { temp |= iocurrent; } - EXTI->FTSR = temp; + EXTI->IMR = temp; } } } @@ -321,8 +321,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) EXTI->EMR &= ~((uint32_t)iocurrent); /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~((uint32_t)iocurrent); EXTI->FTSR &= ~((uint32_t)iocurrent); + EXTI->RTSR &= ~((uint32_t)iocurrent); /* Configure the External Interrupt or event for the current IO */ tmp = 0x0FU << (4U * (position & 0x03U)); @@ -437,7 +437,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - /* get current Ouput Data Register value */ + /* get current Output Data Register value */ odr = GPIOx->ODR; /* Set selected pins that were at low level, and reset ones that were high */ @@ -531,4 +531,3 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c index c901e19d61..f3aafe0a57 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c @@ -12,6 +12,17 @@ * + Peripheral State methods * + HASH or HMAC processing suspension/resumption * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -147,9 +158,9 @@ [..] (#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use function @ref HAL_HASH_RegisterCallback() to register a user callback. + Use function HAL_HASH_RegisterCallback() to register a user callback. - (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks: + (#) Function HAL_HASH_RegisterCallback() allows to register following callbacks: (+) InCpltCallback : callback for input completion. (+) DgstCpltCallback : callback for digest computation completion. (+) ErrorCallback : callback for error. @@ -158,9 +169,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default + (#) Use function HAL_HASH_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) InCpltCallback : callback for input completion. @@ -169,13 +180,13 @@ (+) MspInitCallback : HASH MspInit. (+) MspDeInitCallback : HASH MspDeInit. - (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET + (#) By default, after the HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions: - examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback() + examples HAL_HASH_InCpltCallback(), HAL_HASH_DgstCpltCallback() Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init - and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand) - If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit + reset to the legacy weak (surcharged) functions in the HAL_HASH_Init + and HAL_HASH_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the HAL_HASH_Init and HAL_HASH_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Callbacks can be registered/unregistered in READY state only. @@ -183,8 +194,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit - or @ref HAL_HASH_Init function. + using HAL_HASH_RegisterCallback before calling HAL_HASH_DeInit + or HAL_HASH_Init function. When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -192,17 +203,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1769,8 +1769,6 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) (((buffersize % 4U) != 0U) ? ((buffersize + (4U - (buffersize % 4U))) / 4U) : \ (buffersize / 4U))); - - /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); @@ -2909,8 +2907,8 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u Update HashInCount and pHashInBuffPtr accordingly. */ hhash->HashInCount = SizeVar; hhash->pHashInBuffPtr = (uint8_t *)inputaddr; - __HAL_HASH_SET_NBVALIDBITS( - SizeVar); /* Update the configuration of the number of valid bits in last word of the message */ + /* Update the configuration of the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(SizeVar); hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ if (initialization_skipped == 1U) { @@ -2978,11 +2976,11 @@ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, HAL_StatusTypeDef status ; HAL_HASH_StateTypeDef State_tmp = hhash->State; - #if defined (HASH_CR_MDMAT) +#if defined (HASH_CR_MDMAT) /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set (case of multi-buffer HASH processing) */ assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size)); - #endif /* MDMA defined*/ +#endif /* MDMA defined*/ /* If State is ready or suspended, start or resume polling-based HASH processing */ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { @@ -3478,6 +3476,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \ (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \ : (inputSize / 4U))); + /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); @@ -3513,6 +3512,3 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @} */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash_ex.c index e733f5ad77..63cb38eaa2 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash_ex.c @@ -14,6 +14,17 @@ * and SHA-256. * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### HASH peripheral extended features ##### @@ -69,17 +80,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1038,6 +1038,3 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @} */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c index 6ab4a3d37b..c7c5b70b90 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -40,17 +51,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1192,13 +1192,13 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR); hhcd->hc[ch_num].state = HC_BBLERR; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) @@ -1207,26 +1207,21 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - hhcd->hc[ch_num].state = HC_STALL; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + hhcd->hc[ch_num].state = HC_STALL; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - hhcd->hc[ch_num].state = HC_DATATGLERR; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + hhcd->hc[ch_num].state = HC_DATATGLERR; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); hhcd->hc[ch_num].state = HC_XACTERR; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); } else { @@ -1235,7 +1230,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); } @@ -1254,26 +1248,15 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); } - else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)) { USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; hhcd->hc[ch_num].urb_state = URB_DONE; -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); -#else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } - else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC) - { - hhcd->hc[ch_num].urb_state = URB_DONE; - hhcd->hc[ch_num].toggle_in ^= 1U; - #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); #else @@ -1299,8 +1282,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(ch_num); - if (hhcd->hc[ch_num].state == HC_XFRC) { hhcd->hc[ch_num].urb_state = URB_DONE; @@ -1349,14 +1330,18 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* ... */ } __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) { if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) { hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || @@ -1367,7 +1352,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->Init.dma_enable == 0U) { hhcd->hc[ch_num].state = HC_NAK; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } @@ -1401,7 +1385,8 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) { @@ -1410,16 +1395,14 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->hc[ch_num].do_ping == 1U) { hhcd->hc[ch_num].do_ping = 0U; - hhcd->hc[ch_num].urb_state = URB_NOTREADY; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].urb_state = URB_NOTREADY; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) { @@ -1431,26 +1414,23 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) hhcd->hc[ch_num].do_ping = 1U; __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); } - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); hhcd->hc[ch_num].state = HC_XFRC; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) { hhcd->hc[ch_num].state = HC_NYET; hhcd->hc[ch_num].do_ping = 1U; hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); hhcd->hc[ch_num].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) { @@ -1465,7 +1445,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } } - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); } @@ -1474,7 +1453,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->Init.dma_enable == 0U) { hhcd->hc[ch_num].state = HC_XACTERR; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else @@ -1484,8 +1462,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { hhcd->hc[ch_num].ErrCnt = 0U; hhcd->hc[ch_num].urb_state = URB_ERROR; - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, - hhcd->hc[ch_num].urb_state); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { @@ -1496,16 +1478,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_DATATGLERR; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); - hhcd->hc[ch_num].state = HC_DATATGLERR; } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(ch_num); - if (hhcd->hc[ch_num].state == HC_XFRC) { hhcd->hc[ch_num].urb_state = URB_DONE; @@ -1566,7 +1544,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { @@ -1743,5 +1726,3 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c index dfe5e62370..c2a8eb7543 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c @@ -9,6 +9,17 @@ * + IO operation functions * + Peripheral State, Mode and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -284,18 +295,6 @@ (@) You can refer to the I2C HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -3421,7 +3420,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd { /* Get tick */ uint32_t tickstart = HAL_GetTick(); - uint32_t I2C_Trials = 1U; + uint32_t I2C_Trials = 0U; FlagStatus tmp1; FlagStatus tmp2; @@ -5612,7 +5611,9 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) } else { - /* Do nothing */ + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); } } } @@ -7521,4 +7522,3 @@ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c index ed50332005..64aabaa46e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c @@ -7,6 +7,17 @@ * functionalities of I2C extension peripheral: * + Extension features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### I2C peripheral extension features ##### @@ -25,18 +36,6 @@ (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config() @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -181,4 +180,3 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c index 332b6c2cae..700a0cae4d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -169,18 +180,7 @@ and weak (surcharged) callbacks are used. @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ @@ -2092,4 +2092,3 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, #endif /* HAL_I2S_MODULE_ENABLED */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c index cd0db5e90a..643bf74d12 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c @@ -6,7 +6,17 @@ * This file provides firmware functions to manage the following * functionalities of I2S extension peripheral: * + Extension features Functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### I2S Extension features ##### @@ -73,18 +83,6 @@ | | I2Sx_ext |------------------->I2Sx_extSD(in/out) +----->| | +-----------------------+ - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1135,4 +1133,3 @@ static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTyp * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c index 29974d61b3..47b44ffdb1 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c @@ -9,6 +9,18 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -185,17 +197,6 @@ | 1 | 1 | | SB | 8 bit data | PB | 1 STB | | +-------------------------------------------------------------+ ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -767,9 +768,9 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD * @param Timeout Specify timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t *tmp; + const uint16_t *tmp; uint32_t tickstart = 0U; /* Check that a Tx process is not already ongoing */ @@ -800,7 +801,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u { return HAL_TIMEOUT; } - tmp = (uint16_t *) pData; + tmp = (const uint16_t *) pData; hirda->Instance->DR = (*tmp & (uint16_t)0x01FF); if (hirda->Init.Parity == IRDA_PARITY_NONE) { @@ -942,7 +943,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (hirda->gState == HAL_IRDA_STATE_READY) @@ -1010,8 +1011,16 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the IRDA Parity Error and Data Register Not Empty Interrupts */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the IRDA Parity Error and Data Register Not Empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + } + else + { + /* Enable the IRDA Data Register Not Empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE); + } /* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -1035,9 +1044,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) { - uint32_t *tmp; + const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (hirda->gState == HAL_IRDA_STATE_READY) @@ -1070,8 +1079,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat hirda->hdmatx->XferAbortCallback = NULL; /* Enable the IRDA transmit DMA stream */ - tmp = (uint32_t *)&pData; - HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t *)tmp, (uint32_t)&hirda->Instance->DR, Size); + tmp = (const uint32_t *)&pData; + HAL_DMA_Start_IT(hirda->hdmatx, *(const uint32_t *)tmp, (uint32_t)&hirda->Instance->DR, Size); /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC); @@ -1146,8 +1155,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the IRDA Parity Error Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the IRDA Parity Error Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } /* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -1224,7 +1236,10 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) __HAL_IRDA_CLEAR_OREFLAG(hirda); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Enable the IRDA DMA Rx request */ @@ -2215,11 +2230,12 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) } /** - * @brief This function handles IRDA Communication Timeout. + * @brief This function handles IRDA Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA. * @param Flag specifies the IRDA flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status @@ -2451,14 +2467,14 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { - uint16_t *tmp; + const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) { if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B) { - tmp = (uint16_t *) hirda->pTxBuffPtr; + tmp = (const uint16_t *) hirda->pTxBuffPtr; hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); if (hirda->Init.Parity == IRDA_PARITY_NONE) { @@ -2669,4 +2685,3 @@ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c index 5f376dac6c..c01eb29c0e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c @@ -8,6 +8,17 @@ * + Initialization and Start functions * + IO operation functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### IWDG Generic features ##### @@ -80,18 +91,6 @@ the reload register @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -119,7 +118,7 @@ the LSI_VALUE constant. The value of this constant can be changed by the user to take into account possible LSI clock period variations. The timeout value is multiplied by 1000 to be converted in milliseconds. - LSI startup time is also considered here by adding LSI_STARTUP_TIMEOUT + LSI startup time is also considered here by adding LSI_STARTUP_TIME converted in milliseconds. */ #define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_RVU | IWDG_SR_PVU) @@ -261,5 +260,3 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c index 0ed761721e..7b569513ce 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c @@ -11,6 +11,17 @@ * + Reading operation functions. * + Peripheral State functions. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -140,17 +151,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -444,7 +444,7 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM PWM generation. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -492,7 +492,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -509,7 +509,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ @@ -520,7 +520,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -531,7 +531,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM PWM generation in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF + * This parameter must be a value between 0x0001 and 0xFFFF * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF * @retval HAL status @@ -609,7 +609,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -626,7 +626,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ @@ -656,7 +656,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -667,7 +667,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM One pulse generation. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -715,7 +715,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -743,7 +743,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -754,7 +754,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM One pulse generation in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -832,7 +832,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -852,6 +852,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Set the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -879,7 +880,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -890,7 +891,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM in Set once mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -938,7 +939,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -966,7 +967,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1055,7 +1056,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1102,7 +1103,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the LPTIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1113,7 +1114,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the Encoder interface. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1163,7 +1164,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1194,7 +1195,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1273,7 +1274,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1310,7 +1311,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable "switch to up direction" interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1323,7 +1324,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) * trigger event will reset the counter and the timer restarts. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -1371,7 +1372,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1402,7 +1403,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1415,7 +1416,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) * trigger event will reset the counter and the timer restarts. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -1484,7 +1485,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1501,8 +1502,6 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; #if defined(EXTI_IMR_MR23) /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); @@ -1511,6 +1510,9 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1525,7 +1527,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable Compare match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1536,7 +1538,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the Counter mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1576,7 +1578,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1604,7 +1606,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1615,7 +1617,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the Counter mode in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1679,7 +1681,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1696,8 +1698,6 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; #if defined(EXTI_IMR_MR23) /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); @@ -1706,6 +1706,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1719,7 +1722,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -2368,9 +2371,12 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) uint32_t tmpCFGR; uint32_t tmpCMP; uint32_t tmpARR; + uint32_t primask_bit; uint32_t tmpOR; - __disable_irq(); + /* Enter critical section */ + primask_bit = __get_PRIMASK(); + __set_PRIMASK(1) ; /*********** Save LPTIM Config ***********/ /* Save LPTIM source clock */ @@ -2460,7 +2466,8 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) hlptim->Instance->CFGR = tmpCFGR; hlptim->Instance->OR = tmpOR; - __enable_irq(); + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); } /** * @} @@ -2475,5 +2482,3 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c index 7e4413067f..fcc5fa1611 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -146,17 +157,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -178,6 +178,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#define LTDC_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -211,7 +212,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay */ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) { - uint32_t tmp, tmp1; + uint32_t tmp; + uint32_t tmp1; /* Check the LTDC peripheral state */ if (hltdc == NULL) @@ -320,6 +322,44 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) { + uint32_t tickstart; + + /* Check the LTDC peripheral state */ + if (hltdc == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); + + /* Disable LTDC Layer 1 */ + __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_1); + +#if defined(LTDC_Layer2_BASE) + /* Disable LTDC Layer 2 */ + __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_2); +#endif /* LTDC_Layer2_BASE */ + + /* Reload during vertical blanking period */ + __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(hltdc); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for VSYNC Interrupt */ + while (READ_BIT(hltdc->Instance->CDSR, LTDC_CDSR_VSYNCS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > LTDC_TIMEOUT_VALUE) + { + break; + } + } + + /* Disable LTDC */ + __HAL_LTDC_DISABLE(hltdc); + #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) if (hltdc->MspDeInitCallback == NULL) { @@ -391,7 +431,8 @@ __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, + pLTDC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -473,7 +514,7 @@ HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_ /** * @brief Unregister an LTDC Callback - * LTDC callabck is redirected to the weak predefined callback + * LTDC callback is redirected to the weak predefined callback * @param hltdc ltdc handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -887,11 +928,13 @@ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT { if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) { - tmp = (((counter + (16U*counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + tmp = (((counter + (16U * counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ + ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); } else { - tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ + ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); } pcolorlut++; @@ -1345,12 +1388,14 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres } /** - * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is - * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we - * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels - * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). - * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch - * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width + * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to + * layer for which we want to read and display on screen only a portion 320x240 taken in the center + * of the buffer. + * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous + * call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default + * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. @@ -1504,7 +1549,8 @@ HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadTyp * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, + uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); @@ -1553,7 +1599,8 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, + uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; @@ -1607,7 +1654,8 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, + uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; @@ -1774,12 +1822,14 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32 } /** - * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is - * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we - * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels - * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). - * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch - * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width + * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to + * layer for which we want to read and display on screen only a portion 320x240 taken in the center + * of the buffer. + * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by + * previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default + * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). * Variant of the function HAL_LTDC_SetPitch without immediate reload. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. @@ -2082,7 +2132,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay /* Configure the horizontal start and stop position */ tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); - LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); /* Configure the vertical start and stop position */ tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); @@ -2097,7 +2148,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); tmp2 = (pLayerCfg->Alpha0 << 24U); - LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); + LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | + LTDC_LxDCCR_DCALPHA); LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); /* Specifies the constant alpha value */ @@ -2134,7 +2186,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay /* Configure the color frame buffer pitch in byte */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); - LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U)); + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \ + (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U)); /* Configure the frame buffer line number */ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); @@ -2160,4 +2213,3 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c index 8c39194a66..2ee7795bf3 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -76,7 +75,8 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */ /* Note 1 : Code in line w/ Current LTDC specification */ - hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \ + DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL; hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL; @@ -88,8 +88,10 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc /* Retrieve vertical timing parameters from DSI */ hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U; hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U; - hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U; - hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U; + hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ + VidCfg->VerticalActive - 1U; + hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U; return HAL_OK; } @@ -114,7 +116,8 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ /* Note 1 : Code in line w/ Current LTDC specification */ - hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \ + DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; @@ -146,4 +149,3 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c index 520efe12c4..859c18aada 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + MMC card Control functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -63,7 +74,7 @@ SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). This function provide the following operations: - (#) Initialize the SDMMC peripheral interface with defaullt configuration. + (#) Initialize the SDMMC peripheral interface with default configuration. The initialization process is done at 400KHz. You can change or adapt this frequency by adjusting the "ClockDiv" field. The MMC Card frequency (SDMMC_CK) is computed as follows: @@ -238,17 +249,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -272,7 +272,30 @@ /** @addtogroup MMC_Private_Defines * @{ */ +#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U) +#define MMC_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define MMC_EXT_CSD_PWR_CL_26_INDEX 201 +#define MMC_EXT_CSD_PWR_CL_52_INDEX 200 +#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 238 + +#define MMC_EXT_CSD_PWR_CL_26_POS 8 +#define MMC_EXT_CSD_PWR_CL_52_POS 0 +#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16 +#else +#define MMC_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE + +#define MMC_EXT_CSD_PWR_CL_26_INDEX 203 +#define MMC_EXT_CSD_PWR_CL_52_INDEX 202 +#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 239 + +#define MMC_EXT_CSD_PWR_CL_26_POS 24 +#define MMC_EXT_CSD_PWR_CL_52_POS 16 +#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24 +#endif +/* Frequencies used in the driver for clock divider calculation */ +#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ /** * @} */ @@ -296,6 +319,7 @@ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void MMC_DMAError(DMA_HandleTypeDef *hdma); static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma); static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma); +static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide); /** * @} */ @@ -375,7 +399,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) } /* Initialize the error code */ - hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; /* Initialize the MMC operation */ hmmc->Context = MMC_CONTEXT_NONE; @@ -383,6 +407,15 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) /* Initialize the MMC state */ hmmc->State = HAL_MMC_STATE_READY; + /* Configure bus width */ + if (hmmc->Init.BusWide != SDIO_BUS_WIDE_1B) + { + if (HAL_MMC_ConfigWideBusOperation(hmmc, hmmc->Init.BusWide) != HAL_OK) + { + return HAL_ERROR; + } + } + return HAL_OK; } @@ -427,6 +460,9 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Enable MMC Clock */ __HAL_MMC_ENABLE(hmmc); + /* Required power up waiting time before starting the MMC initialization sequence */ + HAL_Delay(2); + /* Identify card operating voltage */ errorstate = MMC_PowerON(hmmc); if(errorstate != HAL_MMC_ERROR_NONE) @@ -1151,7 +1187,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData if(hmmc->State == HAL_MMC_STATE_READY) { - hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { @@ -2128,6 +2164,122 @@ HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoT return HAL_OK; } +/** + * @brief Returns information the information of the card which are stored on + * the Extended CSD register. + * @param hmmc Pointer to MMC handle + * @param pExtCSD Pointer to a memory area (512 bytes) that contains all + * Extended CSD register parameters + * @param Timeout Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t *tmp_buf; + + if(NULL == pExtCSD) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + /* Initiaize the destination pointer */ + tmp_buf = pExtCSD; + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 512; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hmmc->Instance, &config); + + /* Send ExtCSD Read command to Card */ + errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF)) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + *tmp_buf = SDIO_ReadFIFO(hmmc->Instance); + tmp_buf++; + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS); + hmmc->State = HAL_MMC_STATE_READY; + } + + return HAL_OK; +} + /** * @brief Enables wide bus operation for the requested card if supported by * card. @@ -2141,10 +2293,10 @@ HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoT */ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode) { - __IO uint32_t count = 0U; + uint32_t count; SDIO_InitTypeDef Init; uint32_t errorstate; - uint32_t response = 0U, busy = 0U; + uint32_t response = 0U; /* Check the parameters */ assert_param(IS_SDIO_BUS_WIDE(WideMode)); @@ -2152,115 +2304,83 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 /* Change State */ hmmc->State = HAL_MMC_STATE_BUSY; - /* Update Clock for Bus mode update */ - Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; - Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; - Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; - Init.BusWide = WideMode; - Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; - Init.ClockDiv = SDIO_INIT_CLK_DIV; - /* Initialize SDIO*/ - (void)SDIO_Init(hmmc->Instance, Init); + errorstate = MMC_PwrClassUpdate(hmmc, WideMode); - if(WideMode == SDIO_BUS_WIDE_8B) + if(errorstate == HAL_MMC_ERROR_NONE) { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); - if(errorstate != HAL_MMC_ERROR_NONE) + if(WideMode == SDIO_BUS_WIDE_8B) { - hmmc->ErrorCode |= errorstate; + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); } - } - else if(WideMode == SDIO_BUS_WIDE_4B) - { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); - if(errorstate != HAL_MMC_ERROR_NONE) + else if(WideMode == SDIO_BUS_WIDE_4B) { - hmmc->ErrorCode |= errorstate; + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); } - } - else if(WideMode == SDIO_BUS_WIDE_1B) - { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); - if(errorstate != HAL_MMC_ERROR_NONE) + else if(WideMode == SDIO_BUS_WIDE_1B) { - hmmc->ErrorCode |= errorstate; + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); } - } - else - { - /* WideMode is not a valid argument*/ - hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; - } - - /* Check for switch error and violation of the trial number of sending CMD 13 */ - while(busy == 0U) - { - if(count == SDMMC_MAX_TRIAL) + else { - hmmc->State = HAL_MMC_STATE_READY; - hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; - return HAL_ERROR; + /* WideMode is not a valid argument*/ + errorstate = HAL_MMC_ERROR_PARAM; } - count++; - /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + /* Check for switch error and violation of the trial number of sending CMD 13 */ + if(errorstate == HAL_MMC_ERROR_NONE) { - hmmc->ErrorCode |= errorstate; - } - - /* Get command response */ - response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); - - /* Get operating voltage*/ - busy = (((response >> 7U) == 1U) ? 0U : 1U); - } + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + break; + } - /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - count = SDMMC_DATATIMEOUT; - while((response & 0x00000100U) == 0U) - { - if(count == 0U) - { - hmmc->State = HAL_MMC_STATE_READY; - hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; - return HAL_ERROR; - } - count--; + /* Get command response */ + response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + count--; + }while(((response & 0x100U) == 0U) && (count != 0U)); - /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) - { - hmmc->ErrorCode |= errorstate; + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + else + { + /* Configure the SDIO peripheral */ + Init = hmmc->Init; + Init.BusWide = WideMode; + (void)SDIO_Init(hmmc->Instance, Init); + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } } - - /* Get command response */ - response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); } - if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); - hmmc->State = HAL_MMC_STATE_READY; + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; return HAL_ERROR; } - else - { - /* Configure the SDIO peripheral */ - Init.ClockEdge = hmmc->Init.ClockEdge; - Init.ClockBypass = hmmc->Init.ClockBypass; - Init.ClockPowerSave = hmmc->Init.ClockPowerSave; - Init.BusWide = WideMode; - Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl; - Init.ClockDiv = hmmc->Init.ClockDiv; - (void)SDIO_Init(hmmc->Instance, Init); - } - - /* Change State */ - hmmc->State = HAL_MMC_STATE_READY; return HAL_OK; } @@ -2622,7 +2742,8 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) { HAL_MMC_CardCSDTypeDef CSD; uint32_t errorstate; - uint16_t mmc_rca = 1U; + uint16_t mmc_rca = 2U; + MMC_InitTypeDef Init; /* Check the power State */ if(SDIO_GetPowerState(hmmc->Instance) == 0U) @@ -2646,9 +2767,9 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) hmmc->CID[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4); } - /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */ /* MMC Card publishes its RCA. */ - errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca); + errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca); if(errorstate != HAL_MMC_ERROR_NONE) { return errorstate; @@ -2675,21 +2796,43 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Get the Card Class */ hmmc->MmcCard.Class = (SDIO_GetResponse(hmmc->Instance, SDIO_RESP2) >> 20U); + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + /* Get CSD parameters */ if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK) { return hmmc->ErrorCode; } - /* Select the Card */ - errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); if(errorstate != HAL_MMC_ERROR_NONE) { - return errorstate; + hmmc->ErrorCode |= errorstate; + } + + /* Get Extended CSD parameters */ + if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK) + { + return hmmc->ErrorCode; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; } - /* Configure SDIO peripheral interface */ - (void)SDIO_Init(hmmc->Instance, hmmc->Init); + /* Configure the SDIO peripheral */ + Init = hmmc->Init; + Init.BusWide = SDIO_BUS_WIDE_1B; + (void)SDIO_Init(hmmc->Instance, Init); /* All cards are initialized */ return HAL_MMC_ERROR_NONE; @@ -2722,8 +2865,8 @@ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) return HAL_MMC_ERROR_INVALID_VOLTRANGE; } - /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */ - errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE); + /* SEND CMD1 APP_CMD with voltage range as argument */ + errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE); if(errorstate != HAL_MMC_ERROR_NONE) { return HAL_MMC_ERROR_UNSUPPORTED_FEATURE; @@ -2954,6 +3097,93 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) } } +/** + * @brief Update the power class of the device. + * @param hmmc MMC handle + * @param Wide Wide of MMC bus + * @param Speed Speed of the MMC bus + * @retval MMC Card error state + */ +static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide) +{ + uint32_t count; + uint32_t response = 0U; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t power_class, supported_pwr_class; + + if((Wide == SDIO_BUS_WIDE_8B) || (Wide == SDIO_BUS_WIDE_4B)) + { + power_class = 0U; /* Default value after power-on or software reset */ + + /* Read the PowerClass field of the Extended CSD register */ + if(MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */ + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + else + { + power_class = ((power_class >> 24U) & 0x000000FFU); + } + + /* Get the supported PowerClass field of the Extended CSD register */ + /* Field PWR_CL_26_xxx [201 or 203] */ + supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_26_POS) & 0x000000FFU); + + if(errorstate == HAL_MMC_ERROR_NONE) + { + if(Wide == SDIO_BUS_WIDE_8B) + { + /* Bit [7:4] : power class for 8-bits bus configuration - Bit [3:0] : power class for 4-bits bus configuration */ + supported_pwr_class = (supported_pwr_class >> 4U); + } + + if ((power_class & 0x0FU) != (supported_pwr_class & 0x0FU)) + { + /* Need to change current power class */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U))); + + if(errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + count--; + }while(((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + } + } + + return errorstate; +} + /** * @} */ @@ -2969,5 +3199,3 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_msp_template.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_msp_template.c index 003ea4cc77..b496b628e2 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_msp_template.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_msp_template.c @@ -8,13 +8,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -98,4 +97,3 @@ void HAL_PPP_MspDeInit(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c index 8421f65490..a0b89e621c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c @@ -6,6 +6,17 @@ * This file provides a generic firmware to drive NAND memories mounted * as external device. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -28,7 +39,7 @@ HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b() to read/write page(s)/spare area(s). These functions use specific device - information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef + information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef structure. The read/write address information is contained by the Nand_Address_Typedef structure passed as parameter. @@ -58,25 +69,25 @@ The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback, + Use Functions HAL_NAND_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : NAND MspInit. (+) MspDeInitCallback : NAND MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default + Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : NAND MspInit. (+) MspDeInitCallback : NAND MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET + By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init - and @ref HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit + reset to the legacy weak (surcharged) functions in the HAL_NAND_Init + and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -84,8 +95,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit - or @ref HAL_NAND_Init function. + using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit + or HAL_NAND_Init function. When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -93,59 +104,31 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ - #ifdef HAL_NAND_MODULE_ENABLED -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - /** @defgroup NAND NAND * @brief NAND HAL module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup NAND_Private_Constants NAND Private Constants - * @{ - */ - -/** - * @} - */ - +/* Private Constants ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ -/** @defgroup NAND_Private_Macros NAND Private Macros - * @{ - */ - -/** - * @} - */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + /** @defgroup NAND_Exported_Functions NAND Exported Functions * @{ */ @@ -173,21 +156,22 @@ * @param AttSpace_Timing pointer to Attribute space timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, + FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) { /* Check the NAND handle state */ - if(hnand == NULL) + if (hnand == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - if(hnand->State == HAL_NAND_STATE_RESET) + if (hnand->State == HAL_NAND_STATE_RESET) { /* Allocate lock resource and initialize it */ hnand->Lock = HAL_UNLOCKED; #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - if(hnand->MspInitCallback == NULL) + if (hnand->MspInitCallback == NULL) { hnand->MspInitCallback = HAL_NAND_MspInit; } @@ -198,20 +182,24 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT #else /* Initialize the low level hardware (MSP) */ HAL_NAND_MspInit(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ } /* Initialize NAND control Interface */ - FMC_NAND_Init(hnand->Instance, &(hnand->Init)); + (void)FMC_NAND_Init(hnand->Instance, &(hnand->Init)); /* Initialize NAND common space timing Interface */ - FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank); + (void)FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank); /* Initialize NAND attribute space timing Interface */ - FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank); + (void)FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank); /* Enable the NAND device */ +#if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank); +#else + __FMC_NAND_ENABLE(hnand->Instance); +#endif /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -228,7 +216,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) { #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - if(hnand->MspDeInitCallback == NULL) + if (hnand->MspDeInitCallback == NULL) { hnand->MspDeInitCallback = HAL_NAND_MspDeInit; } @@ -238,10 +226,10 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) #else /* Initialize the low level hardware (MSP) */ HAL_NAND_MspDeInit(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Configure the NAND registers with their reset values */ - FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank); + (void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank); /* Reset the NAND controller state */ hnand->State = HAL_NAND_STATE_RESET; @@ -262,6 +250,7 @@ __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) { /* Prevent unused argument(s) compilation warning */ UNUSED(hnand); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NAND_MspInit could be implemented in the user file */ @@ -277,6 +266,7 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) { /* Prevent unused argument(s) compilation warning */ UNUSED(hnand); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NAND_MspDeInit could be implemented in the user file */ @@ -288,64 +278,81 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status -*/ + */ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) { /* Check NAND interrupt Rising edge flag */ - if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE)) + if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE)) { /* NAND interrupt callback*/ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Rising edge pending bit */ +#if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE); +#else + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE); +#endif /* FMC_Bank2_3 || FSMC_Bank2_3 */ } /* Check NAND interrupt Level flag */ - if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL)) + if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL)) { /* NAND interrupt callback*/ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Level pending bit */ +#if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL); +#else + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL); +#endif /* FMC_Bank2_3 || FSMC_Bank2_3 */ } /* Check NAND interrupt Falling edge flag */ - if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE)) + if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE)) { /* NAND interrupt callback*/ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Falling edge pending bit */ +#if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE); +#else + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE); +#endif /* FMC_Bank2_3 || FSMC_Bank2_3 */ } /* Check NAND interrupt FIFO empty flag */ - if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT)) + if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT)) { /* NAND interrupt callback*/ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt FIFO empty pending bit */ +#if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT); +#else + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT); +#endif /* FMC_Bank2_3 || FSMC_Bank2_3 */ } + } /** @@ -358,6 +365,7 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) { /* Prevent unused argument(s) compilation warning */ UNUSED(hnand); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NAND_ITCallback could be implemented in the user file */ @@ -391,69 +399,81 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) */ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) { - __IO uint32_t data = 0U; - __IO uint32_t data1 = 0U; - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + __IO uint32_t data = 0; + __IO uint32_t data1 = 0; + uint32_t deviceaddress; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) + if (hnand->State == HAL_NAND_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) - { - deviceaddress = NAND_DEVICE1; - } - else + else if (hnand->State == HAL_NAND_STATE_READY) { - deviceaddress = NAND_DEVICE2; - } + /* Process Locked */ + __HAL_LOCK(hnand); - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif - /* Send Read ID command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + /* Send Read ID command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + __DSB(); - /* Read the electronic signature from NAND flash */ + /* Read the electronic signature from NAND flash */ #ifdef FSMC_PCR2_PWID - if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) + if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) #else /* FMC_PCR2_PWID is defined */ - if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) + if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) #endif - { - data = *(__IO uint32_t *)deviceaddress; + { + data = *(__IO uint32_t *)deviceaddress; + + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); + pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); + } + else + { + data = *(__IO uint32_t *)deviceaddress; + data1 = *((__IO uint32_t *)deviceaddress + 4); + + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1); + pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1); + } - /* Return the data read */ - pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); - pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); - pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); - pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); } else { - data = *(__IO uint32_t *)deviceaddress; - data1 = *((__IO uint32_t *)deviceaddress + 4U); - - /* Return the data read */ - pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); - pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data); - pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1); - pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1); + return HAL_ERROR; } - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - return HAL_OK; } @@ -465,39 +485,48 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN */ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + uint32_t deviceaddress; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE1; + return HAL_BUSY; } - else + else if (hnand->State == HAL_NAND_STATE_READY) { - deviceaddress = NAND_DEVICE2; - } + /* Process Locked */ + __HAL_LOCK(hnand); - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* Send NAND reset command */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif + /* Send NAND reset command */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hnand); + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } return HAL_OK; @@ -532,125 +561,162 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToRead) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numpagesread = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) - { - deviceaddress = NAND_DEVICE1; - } - else + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE2; + return HAL_BUSY; } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) read loop */ - while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + else if (hnand->State == HAL_NAND_STATE_READY) { - /* update the buffer size */ - size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead); + /* Process Locked */ + __HAL_LOCK(hnand); - /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } + deviceaddress = NAND_DEVICE1; } - else /* (hnand->Config.PageSize) > 512 */ + else { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } + deviceaddress = NAND_DEVICE2; } +#else + deviceaddress = NAND_DEVICE; +#endif - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); - /* Check if an extra command is needed for reading pages */ - if(hnand->Config.ExtraCommandEnable == ENABLE) + /* Page(s) read loop */ + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - /* Get tick */ - tickstart = HAL_GetTick(); + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - return HAL_TIMEOUT; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); } } - /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); - } - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; - } - /* Increment read pages number */ - numPagesRead++; + if (hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); - /* Decrement pages to read */ - NumPageToRead--; + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } + /* Process unlocked */ + __HAL_UNLOCK(hnand); - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; + return HAL_TIMEOUT; + } + } - /* Process unlocked */ - __HAL_UNLOCK(hnand); + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + __DSB(); + } + + /* Get Data into Buffer */ + for (index = 0U; index < hnand->Config.PageSize; index++) + { + *buff = *(uint8_t *)deviceaddress; + buff++; + } + + /* Increment read pages number */ + numpagesread++; + + /* Decrement pages to read */ + nbpages--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -664,139 +730,176 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToRead) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numpagesread = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) - { - deviceaddress = NAND_DEVICE1; - } - else + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE2; + return HAL_BUSY; } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) read loop */ - while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + else if (hnand->State == HAL_NAND_STATE_READY) { - /* update the buffer size */ - size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead); + /* Process Locked */ + __HAL_LOCK(hnand); - /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } + deviceaddress = NAND_DEVICE1; } - else /* (hnand->Config.PageSize) > 512 */ + else { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } + deviceaddress = NAND_DEVICE2; } +#else + deviceaddress = NAND_DEVICE; +#endif - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); - if(hnand->Config.ExtraCommandEnable == ENABLE) + /* Page(s) read loop */ + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - /* Get tick */ - tickstart = HAL_GetTick(); + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - return HAL_TIMEOUT; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); } } - /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); - } + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); - /* Calculate PageSize */ -#ifdef FSMC_PCR2_PWID + if (hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + __DSB(); + } + + /* Calculate PageSize */ +#if defined(FSMC_PCR2_PWID) if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) -#else /* FMC_PCR2_PWID is defined */ +#else if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) -#endif - { - size = size / 2U; - } - else - { - /* Do nothing */ - /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ - } +#endif /* FSMC_PCR2_PWID */ + { + hnand->Config.PageSize = hnand->Config.PageSize / 2U; + } + else + { + /* Do nothing */ + /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ + } - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress; - } + /* Get Data into Buffer */ + for (index = 0U; index < hnand->Config.PageSize; index++) + { + *buff = *(uint16_t *)deviceaddress; + buff++; + } - /* Increment read pages number */ - numPagesRead++; + /* Increment read pages number */ + numpagesread++; - /* Decrement pages to read */ - NumPageToRead--; + /* Decrement pages to read */ + nbpages--; - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hnand); + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -810,122 +913,157 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToWrite) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numpageswritten = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE1; + return HAL_BUSY; } - else + else if (hnand->State == HAL_NAND_STATE_READY) { - deviceaddress = NAND_DEVICE2; - } + /* Process Locked */ + __HAL_LOCK(hnand); - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) write loop */ - while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* update the buffer size */ - size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten); + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif - /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Page(s) write loop */ + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - } - else /* (hnand->Config.PageSize) > 512 */ - { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + + /* Write data to memory */ + for (index = 0U; index < hnand->Config.PageSize; index++) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + *(__IO uint8_t *)deviceaddress = *buff; + buff++; __DSB(); } - } - - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; - } + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + /* Get tick */ + tickstart = HAL_GetTick(); - /* Get tick */ - tickstart = HAL_GetTick(); + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { + /* Process unlocked */ + __HAL_UNLOCK(hnand); - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) - { - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } - } - /* Increment written pages number */ - numPagesWritten++; + /* Increment written pages number */ + numpageswritten++; - /* Decrement pages to write */ - NumPageToWrite--; + /* Decrement pages to write */ + nbpages--; - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hnand); + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -939,271 +1077,348 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToWrite) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numpageswritten = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) + if (hnand->State == HAL_NAND_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) + else if (hnand->State == HAL_NAND_STATE_READY) { - deviceaddress = NAND_DEVICE1; - } - else - { - deviceaddress = NAND_DEVICE2; - } + /* Process Locked */ + __HAL_LOCK(hnand); - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* Page(s) write loop */ - while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* update the buffer size */ - size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten); + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif - /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Page(s) write loop */ + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - } - else /* (hnand->Config.PageSize) > 512 */ - { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + + /* Calculate PageSize */ +#if defined(FSMC_PCR2_PWID) + if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) +#else + if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) +#endif /* FSMC_PCR2_PWID */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + hnand->Config.PageSize = hnand->Config.PageSize / 2U; } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + else { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + /* Do nothing */ + /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ } - } - - /* Calculate PageSize */ -#ifdef FSMC_PCR2_PWID - if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) -#else /* FMC_PCR2_PWID is defined */ - if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) -#endif - { - size = size / 2U; - } - else - { - /* Do nothing */ - /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ - } - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++; - } + /* Write data to memory */ + for (index = 0U; index < hnand->Config.PageSize; index++) + { + *(__IO uint16_t *)deviceaddress = *buff; + buff++; + __DSB(); + } - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - return HAL_TIMEOUT; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } } - } - /* Increment written pages number */ - numPagesWritten++; + /* Increment written pages number */ + numpageswritten++; - /* Decrement pages to write */ - NumPageToWrite--; + /* Decrement pages to write */ + nbpages--; - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hnand); + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } return HAL_OK; } /** - * @brief Read Spare area(s) from NAND memory + * @brief Read Spare area(s) from NAND memory (8-bits addressing) * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress pointer to NAND address structure * @param pBuffer pointer to source buffer to write * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) + */ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumSpareAreaToRead) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numsparearearead = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) + if (hnand->State == HAL_NAND_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) + else if (hnand->State == HAL_NAND_STATE_READY) { - deviceaddress = NAND_DEVICE1; - } - else - { - deviceaddress = NAND_DEVICE2; - } + /* Process Locked */ + __HAL_LOCK(hnand); - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif - /* Column in page address */ - columnaddress = COLUMN_ADDRESS(hnand); + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); - /* Spare area(s) read loop */ - while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* update the buffer size */ - size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead); + /* Column in page address */ + columnaddress = COLUMN_ADDRESS(hnand); - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Spare area(s) read loop */ + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } - } - else /* (hnand->Config.PageSize) > 512 */ - { - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } - } + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } - if(hnand->Config.ExtraCommandEnable == ENABLE) - { - /* Get tick */ - tickstart = HAL_GetTick(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) + if (hnand->Config.ExtraCommandEnable == ENABLE) { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - return HAL_TIMEOUT; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } } - } - /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); - } + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + __DSB(); + } - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; - } + /* Get Data into Buffer */ + for (index = 0U; index < hnand->Config.SpareAreaSize; index++) + { + *buff = *(uint8_t *)deviceaddress; + buff++; + } - /* Increment read spare areas number */ - numSpareAreaRead++; + /* Increment read spare areas number */ + numsparearearead++; - /* Decrement spare areas to read */ - NumSpareAreaToRead--; + /* Decrement spare areas to read */ + nbspare--; - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hnand); + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -1216,136 +1431,176 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) + */ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaToRead) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numsparearearead = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE1; + return HAL_BUSY; } - else + else if (hnand->State == HAL_NAND_STATE_READY) { - deviceaddress = NAND_DEVICE2; - } + /* Process Locked */ + __HAL_LOCK(hnand); - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif - /* Column in page address */ - columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); - /* Spare area(s) read loop */ - while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* update the buffer size */ - size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead); + /* Column in page address */ + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Spare area(s) read loop */ + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } - } - else /* (hnand->Config.PageSize) > 512 */ - { - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } - } + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } - if(hnand->Config.ExtraCommandEnable == ENABLE) - { - /* Get tick */ - tickstart = HAL_GetTick(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) + if (hnand->Config.ExtraCommandEnable == ENABLE) { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - return HAL_TIMEOUT; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } } - } - /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); - } + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + __DSB(); + } - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress; - } + /* Get Data into Buffer */ + for (index = 0U; index < hnand->Config.SpareAreaSize; index++) + { + *buff = *(uint16_t *)deviceaddress; + buff++; + } - /* Increment read spare areas number */ - numSpareAreaRead++; + /* Increment read spare areas number */ + numsparearearead++; - /* Decrement spare areas to read */ - NumSpareAreaToRead--; + /* Decrement spare areas to read */ + nbspare--; - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hnand); + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } return HAL_OK; } /** - * @brief Write Spare area(s) to NAND memory + * @brief Write Spare area(s) to NAND memory (8-bits addressing) * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress pointer to NAND address structure @@ -1353,125 +1608,167 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; + uint8_t *buff = pBuffer; - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) - { - deviceaddress = NAND_DEVICE1; - } - else + /* Check the NAND controller state */ + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE2; + return HAL_BUSY; } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnand); - /* Update the FMC_NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* Page address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif - /* Column in page address */ - columnaddress = COLUMN_ADDRESS(hnand); + /* Page address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); - /* Spare area(s) write loop */ - while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* update the buffer size */ - size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten); + /* Column in page address */ + columnaddress = COLUMN_ADDRESS(hnand); - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Spare area(s) write loop */ + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } - } - else /* (hnand->Config.PageSize) > 512 */ - { - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + + /* Write data to memory */ + for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + *(__IO uint8_t *)deviceaddress = *buff; + buff++; + __DSB(); } - } - - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; - } - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - return HAL_TIMEOUT; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } } - } - /* Increment written spare areas number */ - numSpareAreaWritten++; + /* Increment written spare areas number */ + numspareareawritten++; - /* Decrement spare areas to write */ - NumSpareAreaTowrite--; + /* Decrement spare areas to write */ + nbspare--; - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hnand); + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -1485,125 +1782,167 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE1; + return HAL_BUSY; } - else + else if (hnand->State == HAL_NAND_STATE_READY) { - deviceaddress = NAND_DEVICE2; - } + /* Process Locked */ + __HAL_LOCK(hnand); - /* Update the FMC_NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif - /* Column in page address */ - columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); - /* Spare area(s) write loop */ - while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* update the buffer size */ - size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten); + /* Column in page address */ + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Spare area(s) write loop */ + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } - } - else /* (hnand->Config.PageSize) > 512 */ - { - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + + /* Write data to memory */ + for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + *(__IO uint16_t *)deviceaddress = *buff; + buff++; + __DSB(); } - } - - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++; - } - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - return HAL_TIMEOUT; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } } - } - /* Increment written spare areas number */ - numSpareAreaWritten++; + /* Increment written spare areas number */ + numspareareawritten++; - /* Decrement spare areas to write */ - NumSpareAreaTowrite--; + /* Decrement spare areas to write */ + nbspare--; - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hnand); + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -1617,102 +1956,60 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A */ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { - uint32_t deviceaddress = 0U; - uint32_t tickstart = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + uint32_t deviceaddress; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE1; + return HAL_BUSY; } - else + else if (hnand->State == HAL_NAND_STATE_READY) { - deviceaddress = NAND_DEVICE2; - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Send Erase block command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; - - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; + /* Process Locked */ + __HAL_LOCK(hnand); - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) { - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_TIMEOUT; + deviceaddress = NAND_DEVICE1; } - } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif - /* Process unlocked */ - __HAL_UNLOCK(hnand); + /* Send Erase block command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); - return HAL_OK; -} + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; + __DSB(); -/** - * @brief NAND memory read status - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval NAND status - */ -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) -{ - uint32_t data = 0U; - uint32_t deviceaddress = 0U; + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) - { - deviceaddress = NAND_DEVICE1; + /* Process unlocked */ + __HAL_UNLOCK(hnand); } else { - deviceaddress = NAND_DEVICE2; - } - - /* Send Read status operation command */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; - - /* Read status register data */ - data = *(__IO uint8_t *)deviceaddress; - - /* Return the status */ - if((data & NAND_ERROR) == NAND_ERROR) - { - return NAND_ERROR; - } - else if((data & NAND_READY) == NAND_READY) - { - return NAND_READY; + return HAL_ERROR; } - return NAND_BUSY; + return HAL_OK; } /** @@ -1732,17 +2029,17 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA pAddress->Page++; /* Check NAND address is valid */ - if(pAddress->Page == hnand->Config.BlockSize) + if (pAddress->Page == hnand->Config.BlockSize) { - pAddress->Page = 0U; + pAddress->Page = 0; pAddress->Block++; - if(pAddress->Block == hnand->Config.PlaneSize) + if (pAddress->Block == hnand->Config.PlaneSize) { - pAddress->Block = 0U; + pAddress->Block = 0; pAddress->Plane++; - if(pAddress->Plane == (hnand->Config.PlaneNbr)) + if (pAddress->Plane == (hnand->Config.PlaneNbr)) { status = NAND_INVALID_ADDRESS; } @@ -1765,11 +2062,12 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, + pNAND_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -1777,39 +2075,39 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND /* Process locked */ __HAL_LOCK(hnand); - if(hnand->State == HAL_NAND_STATE_READY) + if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = pCallback; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = pCallback; - break; - case HAL_NAND_IT_CB_ID : - hnand->ItCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = pCallback; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = pCallback; + break; + case HAL_NAND_IT_CB_ID : + hnand->ItCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hnand->State == HAL_NAND_STATE_RESET) + else if (hnand->State == HAL_NAND_STATE_RESET) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = pCallback; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = pCallback; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1834,46 +2132,46 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID * @retval status */ -HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hnand); - if(hnand->State == HAL_NAND_STATE_READY) + if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = HAL_NAND_MspInit; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = HAL_NAND_MspDeInit; - break; - case HAL_NAND_IT_CB_ID : - hnand->ItCallback = HAL_NAND_ITCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = HAL_NAND_MspInit; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = HAL_NAND_MspDeInit; + break; + case HAL_NAND_IT_CB_ID : + hnand->ItCallback = HAL_NAND_ITCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hnand->State == HAL_NAND_STATE_RESET) + else if (hnand->State == HAL_NAND_STATE_RESET) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = HAL_NAND_MspInit; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = HAL_NAND_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = HAL_NAND_MspInit; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = HAL_NAND_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1886,15 +2184,15 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NA __HAL_UNLOCK(hnand); return status; } -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### NAND Control functions ##### @@ -1917,19 +2215,25 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NA HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) { /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) + if (hnand->State == HAL_NAND_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Enable ECC feature */ - FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank); + /* Enable ECC feature */ + (void)FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank); - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_READY; + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_READY; + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -1943,19 +2247,25 @@ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) { /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) + if (hnand->State == HAL_NAND_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Disable ECC feature */ - FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank); + /* Disable ECC feature */ + (void)FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank); - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_READY; + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_READY; + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -1970,22 +2280,28 @@ HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) */ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) + if (hnand->State == HAL_NAND_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Get NAND ECC value */ - status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout); + /* Get NAND ECC value */ + status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout); - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_READY; + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_READY; + } + else + { + return HAL_ERROR; + } return status; } @@ -1996,8 +2312,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### NAND State functions ##### @@ -2021,6 +2337,53 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) return hnand->State; } +/** + * @brief NAND memory read status + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @retval NAND status + */ +uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) +{ + uint32_t data; + uint32_t deviceaddress; + UNUSED(hnand); + + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif + + /* Send Read status operation command */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; + + /* Read status register data */ + data = *(__IO uint8_t *)deviceaddress; + + /* Return the status */ + if ((data & NAND_ERROR) == NAND_ERROR) + { + return NAND_ERROR; + } + else if ((data & NAND_READY) == NAND_READY) + { + return NAND_READY; + } + else + { + return NAND_BUSY; + } +} + /** * @} */ @@ -2033,13 +2396,10 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ - STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ - STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_NAND_MODULE_ENABLED */ /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3 */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c index 3d423f915a..0a82044866 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c @@ -6,6 +6,17 @@ * This file provides a generic firmware to drive NOR memories mounted * as external device. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -55,25 +66,25 @@ The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback, + Use Functions HAL_NOR_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : NOR MspInit. (+) MspDeInitCallback : NOR MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default + Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : NOR MspInit. (+) MspDeInitCallback : NOR MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET + By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init - and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit + reset to the legacy weak (surcharged) functions in the HAL_NOR_Init + and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -81,8 +92,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit - or @ref HAL_NOR_Init function. + using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit + or HAL_NOR_Init function. When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -90,35 +101,24 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" +#if defined(FMC_Bank1) || defined(FSMC_Bank1) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ +#ifdef HAL_NOR_MODULE_ENABLED + /** @defgroup NOR NOR * @brief NOR driver modules * @{ */ -#ifdef HAL_NOR_MODULE_ENABLED -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -151,9 +151,35 @@ #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 +#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF +#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040 +#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8 +#define NOR_CMD_CONFIRM (uint16_t)0x00D0 +#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020 +#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060 +#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070 +#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050 + /* Mask on NOR STATUS REGISTER */ +#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 +#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080 + +/* Address of the primary command set */ +#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013 + +/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */ +#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */ +#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */ +#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */ +#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */ +#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */ +#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */ +#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */ +#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */ +#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */ +#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */ /** * @} @@ -200,21 +226,25 @@ static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; * @param ExtTiming pointer to NOR extended mode timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming) { + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; + /* Check the NOR handle parameter */ - if(hnor == NULL) + if (hnor == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - if(hnor->State == HAL_NOR_STATE_RESET) + if (hnor->State == HAL_NOR_STATE_RESET) { /* Allocate lock resource and initialize it */ hnor->Lock = HAL_UNLOCKED; #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - if(hnor->MspInitCallback == NULL) + if (hnor->MspInitCallback == NULL) { hnor->MspInitCallback = HAL_NOR_MspInit; } @@ -228,13 +258,13 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe } /* Initialize NOR control Interface */ - FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); + (void)FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); /* Initialize NOR timing Interface */ - FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); + (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); /* Initialize NOR extended mode timing Interface */ - FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); + (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); @@ -249,10 +279,44 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe uwNORMemoryDataWidth = NOR_MEMORY_16B; } - /* Check the NOR controller state */ + /* Initialize the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - return HAL_OK; + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE) + { + (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_PROTECTED; + } + else + { + /* Get the value of the command set */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + + status = HAL_NOR_ReturnToReadMode(hnor); + } + + return status; } /** @@ -264,7 +328,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) { #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - if(hnor->MspDeInitCallback == NULL) + if (hnor->MspDeInitCallback == NULL) { hnor->MspDeInitCallback = HAL_NOR_MspDeInit; } @@ -277,9 +341,9 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ /* Configure the NOR registers with their reset values */ - FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); + (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); - /* Update the NOR controller state */ + /* Reset the NOR controller state */ hnor->State = HAL_NOR_STATE_RESET; /* Release Lock */ @@ -298,6 +362,7 @@ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) { /* Prevent unused argument(s) compilation warning */ UNUSED(hnor); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NOR_MspInit could be implemented in the user file */ @@ -313,6 +378,7 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) { /* Prevent unused argument(s) compilation warning */ UNUSED(hnor); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NOR_MspDeInit could be implemented in the user file */ @@ -363,56 +429,87 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) */ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); + uint32_t deviceaddress; + HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) { - deviceaddress = NOR_MEMORY_ADRESS2; + return HAL_BUSY; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + else if (state == HAL_NOR_STATE_PROTECTED) { - deviceaddress = NOR_MEMORY_ADRESS3; + return HAL_ERROR; } - else /* FMC_NORSRAM_BANK4 */ + else if (state == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS4; - } + /* Process Locked */ + __HAL_LOCK(hnor); - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; - /* Send read ID command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } - /* Read the NOR IDs */ - pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); - pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); - pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); - pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); + /* Send read ID command */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; + if (status != HAL_ERROR) + { + /* Read the NOR IDs */ + pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); + pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE1_ADDR); + pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE2_ADDR); + pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE3_ADDR); + } - /* Process unlocked */ - __HAL_UNLOCK(hnor); + /* Check the NOR controller state */ + hnor->State = state; - return HAL_OK; + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; } /** @@ -423,44 +520,72 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I */ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); + uint32_t deviceaddress; + HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) { - deviceaddress = NOR_MEMORY_ADRESS2; + return HAL_BUSY; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + else if (state == HAL_NOR_STATE_PROTECTED) { - deviceaddress = NOR_MEMORY_ADRESS3; + return HAL_ERROR; } - else /* FMC_NORSRAM_BANK4 */ + else if (state == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS4; - } + /* Process Locked */ + __HAL_LOCK(hnor); - NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } - /* Process unlocked */ - __HAL_UNLOCK(hnor); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - return HAL_OK; + /* Check the NOR controller state */ + hnor->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; } /** @@ -473,53 +598,81 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) */ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); + uint32_t deviceaddress; + HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) { - deviceaddress = NOR_MEMORY_ADRESS2; + return HAL_BUSY; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + else if (state == HAL_NOR_STATE_PROTECTED) { - deviceaddress = NOR_MEMORY_ADRESS3; + return HAL_ERROR; } - else /* FMC_NORSRAM_BANK4 */ + else if (state == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS4; - } + /* Process Locked */ + __HAL_LOCK(hnor); - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; - /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } - /* Read the data */ - *pData = *(__IO uint32_t *)(uint32_t)pAddress; + /* Send read data command */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; + if (status != HAL_ERROR) + { + /* Read the data */ + *pData = (uint16_t)(*(__IO uint32_t *)pAddress); + } - /* Process unlocked */ - __HAL_UNLOCK(hnor); + /* Check the NOR controller state */ + hnor->State = state; - return HAL_OK; + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; } /** @@ -532,53 +685,75 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint */ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + if (hnor->State == HAL_NOR_STATE_BUSY) { - deviceaddress = NOR_MEMORY_ADRESS3; + return HAL_BUSY; } - else /* FMC_NORSRAM_BANK4 */ + else if (hnor->State == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS4; - } + /* Process Locked */ + __HAL_LOCK(hnor); - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } - /* Send program data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + /* Send program data command */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Write the data */ - NOR_WRITE(pAddress, *pData); + if (status != HAL_ERROR) + { + /* Write the data */ + NOR_WRITE(pAddress, *pData); + } - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hnor); + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } - return HAL_OK; + return status; } /** @@ -590,60 +765,93 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u * @param uwBufferSize number of Half word to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); + uint32_t deviceaddress; + uint32_t size = uwBufferSize; + uint32_t address = uwAddress; + uint16_t *data = pData; + HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) { - deviceaddress = NOR_MEMORY_ADRESS1; + return HAL_BUSY; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + else if (state == HAL_NOR_STATE_PROTECTED) { - deviceaddress = NOR_MEMORY_ADRESS2; + return HAL_ERROR; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + else if (state == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } + /* Process Locked */ + __HAL_LOCK(hnor); - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; - /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } - /* Read buffer */ - while( uwBufferSize > 0U) - { - *pData++ = *(__IO uint16_t *)uwAddress; - uwAddress += 2U; - uwBufferSize--; - } + /* Send read data command */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; + if (status != HAL_ERROR) + { + /* Read buffer */ + while (size > 0U) + { + *data = *(__IO uint16_t *)address; + data++; + address += 2U; + size--; + } + } - /* Process unlocked */ - __HAL_UNLOCK(hnor); + /* Check the NOR controller state */ + hnor->State = state; - return HAL_OK; + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; } /** @@ -655,75 +863,105 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress * @param uwBufferSize Size of the buffer to write * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize) { - uint16_t * p_currentaddress = (uint16_t *)NULL; - uint16_t * p_endaddress = (uint16_t *)NULL; - uint32_t lastloadedaddress = 0U, deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); + uint16_t *p_currentaddress; + const uint16_t *p_endaddress; + uint16_t *data = pData; + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) + if (hnor->State == HAL_NOR_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + else if (hnor->State == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } + /* Process Locked */ + __HAL_LOCK(hnor); - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; - /* Initialize variables */ - p_currentaddress = (uint16_t*)((uint32_t)(uwAddress)); - p_endaddress = p_currentaddress + (uwBufferSize-1U); - lastloadedaddress = (uint32_t)(uwAddress); + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + /* Initialize variables */ + p_currentaddress = (uint16_t *)(deviceaddress + uwAddress); + p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U))); - /* Write Buffer Load Command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1U)); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - /* Load Data into NOR Buffer */ - while(p_currentaddress <= p_endaddress) - { - /* Store last loaded address & data value (for polling) */ - lastloadedaddress = (uint32_t)p_currentaddress; + /* Write Buffer Load Command */ + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); + NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + /* Write Buffer Load Command */ + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM); + NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - NOR_WRITE(p_currentaddress, *pData++); + if (status != HAL_ERROR) + { + /* Load Data into NOR Buffer */ + while (p_currentaddress <= p_endaddress) + { + NOR_WRITE(p_currentaddress, *data); - p_currentaddress ++; - } + data++; + p_currentaddress ++; + } - NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); + } + else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */ + { + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM); + } + } - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hnor); + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } - return HAL_OK; + return status; } @@ -737,53 +975,78 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr */ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + if (hnor->State == HAL_NOR_STATE_BUSY) { - deviceaddress = NOR_MEMORY_ADRESS1; + return HAL_BUSY; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + else if (hnor->State == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } + /* Process Locked */ + __HAL_LOCK(hnor); - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; - /* Send block erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } - /* Check the NOR memory status and update the controller state */ - hnor->State = HAL_NOR_STATE_READY; + /* Send block erase command sequence */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK); + NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); + NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE); + NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Process unlocked */ - __HAL_UNLOCK(hnor); + /* Check the NOR memory status and update the controller state */ + hnor->State = HAL_NOR_STATE_READY; - return HAL_OK; + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; } @@ -796,56 +1059,72 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd */ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { - uint32_t deviceaddress = 0U; - - /* Prevent unused argument(s) compilation warning */ + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; UNUSED(Address); - /* Process Locked */ - __HAL_LOCK(hnor); - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + if (hnor->State == HAL_NOR_STATE_BUSY) { - deviceaddress = NOR_MEMORY_ADRESS3; + return HAL_BUSY; } - else /* FMC_NORSRAM_BANK4 */ + else if (hnor->State == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS4; - } + /* Process Locked */ + __HAL_LOCK(hnor); - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; - /* Send NOR chip erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } - /* Check the NOR memory status and update the controller state */ - hnor->State = HAL_NOR_STATE_READY; + /* Send NOR chip erase command sequence */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Process unlocked */ - __HAL_UNLOCK(hnor); + /* Check the NOR memory status and update the controller state */ + hnor->State = HAL_NOR_STATE_READY; - return HAL_OK; + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return status; } /** @@ -857,52 +1136,64 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) */ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); + uint32_t deviceaddress; + HAL_NOR_StateTypeDef state; /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) { - deviceaddress = NOR_MEMORY_ADRESS2; + return HAL_BUSY; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + else if (state == HAL_NOR_STATE_PROTECTED) { - deviceaddress = NOR_MEMORY_ADRESS3; + return HAL_ERROR; } - else /* FMC_NORSRAM_BANK4 */ + else if (state == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS4; - } + /* Process Locked */ + __HAL_LOCK(hnor); - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; - /* Send read CFI query command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } - /* read the NOR CFI information */ - pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); - pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); - pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); - pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); + /* Send read CFI query command */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; + /* read the NOR CFI information */ + pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); + pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); + pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); + pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); - /* Process unlocked */ - __HAL_UNLOCK(hnor); + /* Check the NOR controller state */ + hnor->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -919,12 +1210,13 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, + pNOR_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -933,20 +1225,20 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal __HAL_LOCK(hnor); state = hnor->State; - if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) + if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_NOR_MSP_INIT_CB_ID : - hnor->MspInitCallback = pCallback; - break; - case HAL_NOR_MSP_DEINIT_CB_ID : - hnor->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NOR_MSP_INIT_CB_ID : + hnor->MspInitCallback = pCallback; + break; + case HAL_NOR_MSP_DEINIT_CB_ID : + hnor->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -970,7 +1262,7 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID * @retval status */ -HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; @@ -979,20 +1271,20 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C __HAL_LOCK(hnor); state = hnor->State; - if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) + if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_NOR_MSP_INIT_CB_ID : - hnor->MspInitCallback = HAL_NOR_MspInit; - break; - case HAL_NOR_MSP_DEINIT_CB_ID : - hnor->MspDeInitCallback = HAL_NOR_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NOR_MSP_INIT_CB_ID : + hnor->MspInitCallback = HAL_NOR_MspInit; + break; + case HAL_NOR_MSP_DEINIT_CB_ID : + hnor->MspDeInitCallback = HAL_NOR_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1006,13 +1298,14 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C return status; } #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ + /** * @} */ /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### NOR Control functions ##### @@ -1033,17 +1326,28 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C */ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) { - /* Process Locked */ - __HAL_LOCK(hnor); + /* Check the NOR controller state */ + if (hnor->State == HAL_NOR_STATE_PROTECTED) + { + /* Process Locked */ + __HAL_LOCK(hnor); - /* Enable write operation */ - FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; + /* Enable write operation */ + (void)FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); - /* Process unlocked */ - __HAL_UNLOCK(hnor); + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -1056,20 +1360,28 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) */ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) { - /* Process Locked */ - __HAL_LOCK(hnor); + /* Check the NOR controller state */ + if (hnor->State == HAL_NOR_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnor); - /* Update the SRAM controller state */ - hnor->State = HAL_NOR_STATE_BUSY; + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; - /* Disable write operation */ - FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); + /* Disable write operation */ + (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_PROTECTED; + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_PROTECTED; - /* Process unlocked */ - __HAL_UNLOCK(hnor); + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -1079,8 +1391,8 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) */ /** @defgroup NOR_Exported_Functions_Group4 NOR State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### NOR State functions ##### @@ -1110,14 +1422,15 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) * the configuration information for NOR module. * @param Address Device address * @param Timeout NOR programming Timeout - * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR + * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR * or HAL_NOR_STATUS_TIMEOUT */ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) { HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; - uint16_t tmpSR1 = 0, tmpSR2 = 0; - uint32_t tickstart = 0U; + uint16_t tmpsr1; + uint16_t tmpsr2; + uint32_t tickstart; /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ HAL_NOR_MspWait(hnor, Timeout); @@ -1126,45 +1439,84 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /* Get tick */ tickstart = HAL_GetTick(); - while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT)) + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) { - status = HAL_NOR_STATUS_TIMEOUT; + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + status = HAL_NOR_STATUS_TIMEOUT; + } } - } - /* Read NOR status register (DQ6 and DQ5) */ - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; + /* Read NOR status register (DQ6 and DQ5) */ + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) - { - return HAL_NOR_STATUS_SUCCESS ; - } + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) + { + return HAL_NOR_STATUS_SUCCESS ; + } - if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) - { - status = HAL_NOR_STATUS_ONGOING; + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + { + status = HAL_NOR_STATUS_ONGOING; + } + + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) + { + return HAL_NOR_STATUS_SUCCESS; + } + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + { + return HAL_NOR_STATUS_ERROR; + } } + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + do + { + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + tmpsr2 = *(__IO uint16_t *)(Address); - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_NOR_STATUS_TIMEOUT; + } + } + } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U); - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + tmpsr1 = *(__IO uint16_t *)(Address); + if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U) { - return HAL_NOR_STATUS_SUCCESS; + /* Clear the Status Register */ + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + status = HAL_NOR_STATUS_ERROR; } - if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + else { - return HAL_NOR_STATUS_ERROR; + status = HAL_NOR_STATUS_SUCCESS; } } + else + { + /* Primary command set not supported by the driver */ + status = HAL_NOR_STATUS_ERROR; + } /* Return the operation status */ return status; @@ -1177,17 +1529,15 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ - STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ - STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx ||\ - STM32F423xx */ -#endif /* HAL_NOR_MODULE_ENABLED */ + /** * @} */ +#endif /* HAL_NOR_MODULE_ENABLED */ + /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* FMC_Bank1 || FSMC_Bank1 */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c index 205776002d..14deb478fd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c @@ -6,13 +6,24 @@ * This file provides a generic firmware to drive PCCARD memories mounted * as external device. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] This driver is a generic layered driver which contains a set of APIs used to - control PCCARD/compact flash memories. It uses the FMC/FSMC layer functions + control PCCARD/compact flash memories. It uses the FMC/FSMC layer functions to interface with PCCARD devices. This driver is used for: (+) PCCARD/Compact Flash memory configuration sequence using the function @@ -50,25 +61,25 @@ The compilation define USE_HAL_PCCARD_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_PCCARD_RegisterCallback() to register a user callback, + Use Functions HAL_PCCARD_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : PCCARD MspInit. (+) MspDeInitCallback : PCCARD MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_PCCARD_UnRegisterCallback() to reset a callback to the default + Use function HAL_PCCARD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : PCCARD MspInit. (+) MspDeInitCallback : PCCARD MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_PCCARD_Init and if the state is HAL_PCCARD_STATE_RESET + By default, after the HAL_PCCARD_Init and if the state is HAL_PCCARD_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_PCCARD_Init - and @ref HAL_PCCARD_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_PCCARD_Init and @ref HAL_PCCARD_DeInit + reset to the legacy weak (surcharged) functions in the HAL_PCCARD_Init + and HAL_PCCARD_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_PCCARD_Init and HAL_PCCARD_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -76,8 +87,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_PCCARD_RegisterCallback before calling @ref HAL_PCCARD_DeInit - or @ref HAL_PCCARD_Init function. + using HAL_PCCARD_RegisterCallback before calling HAL_PCCARD_DeInit + or HAL_PCCARD_Init function. When The compilation define USE_HAL_PCCARD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -85,29 +96,19 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" +#if defined(FMC_Bank4) || defined(FSMC_Bank4) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ #ifdef HAL_PCCARD_MODULE_ENABLED -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /** @defgroup PCCARD PCCARD * @brief PCCARD HAL module driver * @{ @@ -161,20 +162,21 @@ * @param IOSpaceTiming IO space timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming) +HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, + FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming) { /* Check the PCCARD controller state */ - if(hpccard == NULL) + if (hpccard == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - if(hpccard->State == HAL_PCCARD_STATE_RESET) + if (hpccard->State == HAL_PCCARD_STATE_RESET) { /* Allocate lock resource and initialize it */ hpccard->Lock = HAL_UNLOCKED; #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) - if(hpccard->MspInitCallback == NULL) + if (hpccard->MspInitCallback == NULL) { hpccard->MspInitCallback = HAL_PCCARD_MspInit; } @@ -222,7 +224,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard) { #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) - if(hpccard->MspDeInitCallback == NULL) + if (hpccard->MspDeInitCallback == NULL) { hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; } @@ -312,9 +314,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp __HAL_LOCK(hpccard); /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Update the PCCARD controller state */ @@ -324,25 +326,25 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp *pStatus = PCCARD_READY; /* Send the Identify Command */ - *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECEC; + *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xECEC; /* Read PCCARD IDs and timeout treatment */ do { - /* Read the PCCARD status */ - status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); + /* Read the PCCARD status */ + status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); - timeout--; - }while((status != PCCARD_STATUS_OK) && timeout); + timeout--; + } while ((status != PCCARD_STATUS_OK) && timeout); - if(timeout == 0U) + if (timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } else { - /* Read PCCARD ID bytes */ - for(index = 0U; index < 16U; index++) + /* Read PCCARD ID bytes */ + for (index = 0U; index < 16U; index++) { CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA); } @@ -366,7 +368,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp * @param pStatus pointer to PCCARD status * @retval HAL status */ -HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) +HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus) { uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U; uint8_t status = 0; @@ -375,9 +378,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t __HAL_LOCK(hpccard); /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Update the PCCARD controller state */ @@ -387,7 +390,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pStatus = PCCARD_READY; /* Set the parameters to write a sector */ - *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00; + *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x0000; *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress); *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0; @@ -396,9 +399,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t /* wait till the Status = 0x80 */ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - }while((status == 0x80) && timeout); + } while ((status == 0x80U) && timeout); - if(timeout == 0U) + if (timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } @@ -410,15 +413,15 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t /* wait till the Status = PCCARD_STATUS_OK */ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - }while((status != PCCARD_STATUS_OK) && timeout); + } while ((status != PCCARD_STATUS_OK) && timeout); - if(timeout == 0U) + if (timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } /* Read bytes */ - for(; index < PCCARD_SECTOR_SIZE; index++) + for (; index < PCCARD_SECTOR_SIZE; index++) { *(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR); } @@ -442,7 +445,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t * @param pStatus pointer to PCCARD status * @retval HAL status */ -HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) +HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus) { uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U; uint8_t status = 0; @@ -451,9 +455,9 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ __HAL_LOCK(hpccard); /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Update the PCCARD controller state */ @@ -463,7 +467,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ *pStatus = PCCARD_READY; /* Set the parameters to write a sector */ - *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00; + *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x0000; *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress); *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0; @@ -472,15 +476,15 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ /* Wait till the Status = PCCARD_STATUS_OK */ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - }while((status != PCCARD_STATUS_OK) && timeout); + } while ((status != PCCARD_STATUS_OK) && timeout); - if(timeout == 0U) + if (timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } /* Write bytes */ - for(; index < PCCARD_SECTOR_SIZE; index++) + for (; index < PCCARD_SECTOR_SIZE; index++) { *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++; } @@ -490,9 +494,9 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ /* Wait till the Status = PCCARD_STATUS_WRITE_OK */ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - }while((status != PCCARD_STATUS_WRITE_OK) && timeout); + } while ((status != PCCARD_STATUS_WRITE_OK) && timeout); - if(timeout == 0U) + if (timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } @@ -524,9 +528,9 @@ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16 __HAL_LOCK(hpccard); /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Update the PCCARD controller state */ @@ -546,13 +550,13 @@ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16 /* wait till the PCCARD is ready */ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); - while((status != PCCARD_STATUS_WRITE_OK) && timeout) + while ((status != PCCARD_STATUS_WRITE_OK) && timeout) { status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; } - if(timeout == 0U) + if (timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } @@ -578,9 +582,9 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard) __HAL_LOCK(hpccard); /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Provide a SW reset and Read and verify the: @@ -593,7 +597,7 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard) /* Check the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_BUSY; - *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION ) = 0x01; + *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION) = 0x01; /* Check the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_READY; @@ -609,11 +613,11 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard) * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @retval HAL status -*/ + */ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) { /* Check PCCARD interrupt Rising edge flag */ - if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE)) + if (__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE)) { /* PCCARD interrupt callback*/ #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) @@ -627,7 +631,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) } /* Check PCCARD interrupt Level flag */ - if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL)) + if (__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL)) { /* PCCARD interrupt callback*/ #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) @@ -641,7 +645,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) } /* Check PCCARD interrupt Falling edge flag */ - if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE)) + if (__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE)) { /* PCCARD interrupt callback*/ #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) @@ -655,7 +659,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) } /* Check PCCARD interrupt FIFO empty flag */ - if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT)) + if (__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT)) { /* PCCARD interrupt callback*/ #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) @@ -697,11 +701,12 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard) * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, + pPCCARD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -709,39 +714,39 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HA /* Process locked */ __HAL_LOCK(hpccard); - if(hpccard->State == HAL_PCCARD_STATE_READY) + if (hpccard->State == HAL_PCCARD_STATE_READY) { switch (CallbackId) { - case HAL_PCCARD_MSP_INIT_CB_ID : - hpccard->MspInitCallback = pCallback; - break; - case HAL_PCCARD_MSP_DEINIT_CB_ID : - hpccard->MspDeInitCallback = pCallback; - break; - case HAL_PCCARD_IT_CB_ID : - hpccard->ItCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_PCCARD_MSP_INIT_CB_ID : + hpccard->MspInitCallback = pCallback; + break; + case HAL_PCCARD_MSP_DEINIT_CB_ID : + hpccard->MspDeInitCallback = pCallback; + break; + case HAL_PCCARD_IT_CB_ID : + hpccard->ItCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hpccard->State == HAL_PCCARD_STATE_RESET) + else if (hpccard->State == HAL_PCCARD_STATE_RESET) { switch (CallbackId) { - case HAL_PCCARD_MSP_INIT_CB_ID : - hpccard->MspInitCallback = pCallback; - break; - case HAL_PCCARD_MSP_DEINIT_CB_ID : - hpccard->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_PCCARD_MSP_INIT_CB_ID : + hpccard->MspInitCallback = pCallback; + break; + case HAL_PCCARD_MSP_DEINIT_CB_ID : + hpccard->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -766,46 +771,46 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HA * @arg @ref HAL_PCCARD_IT_CB_ID PCCARD IT callback ID * @retval status */ -HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hpccard); - if(hpccard->State == HAL_PCCARD_STATE_READY) + if (hpccard->State == HAL_PCCARD_STATE_READY) { switch (CallbackId) { - case HAL_PCCARD_MSP_INIT_CB_ID : - hpccard->MspInitCallback = HAL_PCCARD_MspInit; - break; - case HAL_PCCARD_MSP_DEINIT_CB_ID : - hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; - break; - case HAL_PCCARD_IT_CB_ID : - hpccard->ItCallback = HAL_PCCARD_ITCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_PCCARD_MSP_INIT_CB_ID : + hpccard->MspInitCallback = HAL_PCCARD_MspInit; + break; + case HAL_PCCARD_MSP_DEINIT_CB_ID : + hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; + break; + case HAL_PCCARD_IT_CB_ID : + hpccard->ItCallback = HAL_PCCARD_ITCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hpccard->State == HAL_PCCARD_STATE_RESET) + else if (hpccard->State == HAL_PCCARD_STATE_RESET) { switch (CallbackId) { - case HAL_PCCARD_MSP_INIT_CB_ID : - hpccard->MspInitCallback = HAL_PCCARD_MspInit; - break; - case HAL_PCCARD_MSP_DEINIT_CB_ID : - hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_PCCARD_MSP_INIT_CB_ID : + hpccard->MspInitCallback = HAL_PCCARD_MspInit; + break; + case HAL_PCCARD_MSP_DEINIT_CB_ID : + hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -825,8 +830,8 @@ HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback (PCCARD_HandleTypeDef *hpccard, */ /** @defgroup PCCARD_Exported_Functions_Group3 State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### PCCARD State functions ##### @@ -864,20 +869,20 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard) uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0U; /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_PCCARD_STATUS_ONGOING; + return HAL_PCCARD_STATUS_ONGOING; } status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); - while((status_pccard == PCCARD_BUSY) && timeout) + while ((status_pccard == PCCARD_BUSY) && timeout) { status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; } - if(timeout == 0U) + if (timeout == 0U) { status_pccard = PCCARD_TIMEOUT_ERROR; } @@ -900,19 +905,19 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard) uint8_t data = 0U, status_pccard = PCCARD_BUSY; /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_PCCARD_STATUS_ONGOING; + return HAL_PCCARD_STATUS_ONGOING; } /* Read status operation */ data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); - if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR) + if ((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR) { status_pccard = PCCARD_TIMEOUT_ERROR; } - else if((data & PCCARD_READY) == PCCARD_READY) + else if ((data & PCCARD_READY) == PCCARD_READY) { status_pccard = PCCARD_READY; } @@ -927,16 +932,15 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard) /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ - STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#endif /* HAL_PCCARD_MODULE_ENABLED */ /** * @} */ +#endif /* HAL_PCCARD_MODULE_ENABLED */ + /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* FMC_Bank4 || FSMC_Bank4 */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c index aa9702eed3..7e46592b31 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -41,17 +52,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -422,7 +422,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, /** * @brief Unregister an USB PCD Callback - * USB PCD callabck is redirected to the weak predefined callback + * USB PCD callback is redirected to the weak predefined callback * @param hpcd USB PCD handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1061,7 +1061,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) uint32_t epint; uint32_t epnum; uint32_t fifoemptymsk; - uint32_t temp; + uint32_t RegVal; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) @@ -1072,6 +1072,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) return; } + /* store current frame number */ + hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) { /* incorrect mode, acknowledge the interrupt */ @@ -1083,30 +1086,31 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - temp = USBx->GRXSTSP; + RegVal = USBx->GRXSTSP; - ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; + ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; - if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) { - if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) + if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) { (void)USB_ReadPacket(USBx, ep->xfer_buff, - (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); + (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); - ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; } } - else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; } else { /* ... */ } + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); } @@ -1141,6 +1145,30 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); } + /* Clear OUT Endpoint disable interrupt */ + if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) + { + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; + } + + ep = &hpcd->OUT_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); + } + /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) { @@ -1210,6 +1238,21 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) { + (void)USB_FlushTxFifo(USBx, epnum); + + ep = &hpcd->IN_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) @@ -1300,7 +1343,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USBx_INEP(i)->DIEPINT = 0xFB7FU; USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; USBx_OUTEP(i)->DOEPINT = 0xFB7FU; USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; @@ -1372,18 +1414,37 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); } + /* Handle Global OUT NAK effective Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) + { + USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; + + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) + { + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); + } + } + } + /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) { - /* Keep application checking the corresponding Iso IN endpoint - causing the incomplete Interrupt */ - epnum = 0U; + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_INEP(epnum)->DIEPCTL; -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) + { + hpcd->IN_ep[epnum].is_iso_incomplete = 1U; + + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); + } + } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); } @@ -1391,15 +1452,25 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { - /* Keep application checking the corresponding Iso OUT endpoint - causing the incomplete Interrupt */ - epnum = 0U; + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_OUTEP(epnum)->DOEPCTL; -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && + ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + { + hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; + + USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; + + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; + break; + } + } + } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } @@ -1419,9 +1490,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) { - temp = hpcd->Instance->GOTGINT; + RegVal = hpcd->Instance->GOTGINT; - if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); @@ -1429,7 +1500,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) HAL_PCD_DisconnectCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - hpcd->Instance->GOTGINT |= temp; + hpcd->Instance->GOTGINT |= RegVal; } } } @@ -1954,6 +2025,32 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) return HAL_OK; } +/** + * @brief Abort an USB EP transaction. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + HAL_StatusTypeDef ret; + PCD_EPTypeDef *ep; + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + } + + /* Stop Xfer */ + ret = USB_EPStopXfer(hpcd->Instance, ep); + + return ret; +} + /** * @brief Flush an endpoint * @param hpcd PCD handle @@ -2027,6 +2124,33 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) return hpcd->State; } +/** + * @brief Set the USB Device high speed test mode. + * @param hpcd PCD handle + * @param testmode USB Device high speed test mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + + switch (testmode) + { + case TEST_J: + case TEST_K: + case TEST_SE0_NAK: + case TEST_PACKET: + case TEST_FORCE_EN: + USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; + break; + + default: + break; + } + + return HAL_OK; +} /** * @} */ @@ -2108,6 +2232,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { + USB_OTG_EPTypeDef *ep; USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); @@ -2138,18 +2263,24 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint } else { - /* out data packet received over EP0 */ - hpcd->OUT_ep[epnum].xfer_count = - hpcd->OUT_ep[epnum].maxpacket - - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + ep = &hpcd->OUT_ep[epnum]; - hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; + /* out data packet received over EP */ + ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + if (epnum == 0U) { - /* this is ZLP, so prepare EP0 for next setup */ - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + if (ep->xfer_len == 0U) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + else + { + ep->xfer_buff += ep->xfer_count; + } } + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else @@ -2254,5 +2385,3 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c index 7c7697c676..292faf13bc 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c @@ -10,13 +10,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -164,26 +163,10 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /* Enable DCD : Data Contact Detect */ USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; - /* Wait Detect flag or a timeout is happen */ - while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > 1000U) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - return; - } - } - - /* Right response got */ - HAL_Delay(200U); + /* Wait for Min DCD Timeout */ + HAL_Delay(300U); - /* Check Detect flag*/ + /* Check Detect flag */ if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET) { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) @@ -193,7 +176,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - /*Primary detection: checks if connected to Standard Downstream Port + /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN; HAL_Delay(50U); @@ -229,7 +212,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } else { - /* case Charging Downstream Port */ + /* case Charging Downstream Port */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); #else @@ -241,11 +224,23 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /* Battery Charging capability discovery finished */ (void)HAL_PCDEx_DeActivateBCD(hpcd); + /* Check for the Timeout, else start USB Device */ + if ((HAL_GetTick() - tickstart) > 1000U) + { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); #else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } } /** @@ -344,5 +339,3 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c index 1e2171a4e6..b9f7cc20cb 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c @@ -11,14 +11,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -571,5 +569,3 @@ void HAL_PWR_DisableSEVOnPend(void) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c index a94f9e11cf..f18f4bf90c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c @@ -10,14 +10,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -600,5 +598,3 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c index 688ce00b50..74ffe1647c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c @@ -14,6 +14,17 @@ * + Errors management and abort functionality * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -111,7 +122,7 @@ ================================================= [..] (#) HAL_QSPI_GetError() function gives the error raised during the last operation. - (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and + (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and flushes the fifo : (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. @@ -194,17 +205,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -286,7 +286,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /** * @brief Initialize the QSPI mode according to the specified parameters * in the QSPI_InitTypeDef and initialize the associated handle. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) @@ -387,7 +387,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /** * @brief De-Initialize the QSPI peripheral. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -428,7 +428,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Initialize the QSPI MSP. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) @@ -443,7 +443,7 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) /** * @brief DeInitialize the QSPI MSP. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) @@ -482,7 +482,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Handle QSPI interrupt request. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) @@ -772,9 +772,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /** * @brief Set the command configuration. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @param cmd : structure that contains the command configuration information - * @param Timeout : Timeout duration + * @param Timeout Timeout duration * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -862,15 +862,14 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /** * @brief Set the command configuration in interrupt mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) { HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); @@ -961,11 +960,10 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration * @note This function is used only in Indirect Write Mode - * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) @@ -1047,9 +1045,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1135,8 +1133,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /** * @brief Send an amount of data in non-blocking mode with interrupt. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1195,8 +1193,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1259,8 +1257,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) /** * @brief Send an amount of data in non-blocking mode with DMA. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1426,8 +1424,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer. + * @param hqspi QSPI handle + * @param pData pointer to data buffer. * @note This function is used only in Indirect Read Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1634,10 +1632,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the polling configuration information. - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. + * @param Timeout Timeout duration * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1735,9 +1733,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the polling configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1838,9 +1836,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the memory mapped configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ @@ -1927,7 +1925,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT /** * @brief Transfer Error callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1942,7 +1940,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Abort completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1957,7 +1955,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1972,7 +1970,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1987,7 +1985,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -2002,7 +2000,7 @@ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Half Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -2017,7 +2015,7 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Half Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -2032,7 +2030,7 @@ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief FIFO Threshold callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -2047,7 +2045,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Status Match callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -2062,7 +2060,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Timeout callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -2078,8 +2076,8 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Register a User QSPI Callback * To be used instead of the weak (surcharged) predefined callback - * @param hqspi : QSPI handle - * @param CallbackId : ID of the callback to be registered + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -2093,7 +2091,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID - * @param pCallback : pointer to the Callback function + * @param pCallback pointer to the Callback function * @retval status */ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback) @@ -2192,8 +2190,8 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI /** * @brief Unregister a User QSPI Callback * QSPI Callback is redirected to the weak (surcharged) predefined callback - * @param hqspi : QSPI handle - * @param CallbackId : ID of the callback to be unregistered + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -2320,7 +2318,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS /** * @brief Return the QSPI handle state. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) @@ -2331,7 +2329,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI error code. -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval QSPI Error Code */ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) @@ -2341,7 +2339,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission. -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -2368,25 +2366,33 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) } } - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) + { + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - /* Wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); + /* Wait until TC flag is set to go back in idle state */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - if (status == HAL_OK) - { - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + if (status == HAL_OK) + { + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - /* Wait until BUSY flag is reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - } + /* Wait until BUSY flag is reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + } - if (status == HAL_OK) - { - /* Reset functional mode configuration to indirect write mode by default */ - CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + if (status == HAL_OK) + { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + /* Update state */ + hqspi->State = HAL_QSPI_STATE_READY; + } + } + else + { /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -2397,7 +2403,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -2438,22 +2444,30 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) } else { - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) + { + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - /* Enable the QSPI Transfer Complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); + /* Enable the QSPI Transfer Complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + } + else + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + } } } return status; } /** @brief Set QSPI timeout. - * @param hqspi : QSPI handle. - * @param Timeout : Timeout for the QSPI memory access. + * @param hqspi QSPI handle. + * @param Timeout Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -2462,8 +2476,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi : QSPI handle. - * @param Threshold : Threshold of the Fifo (value between 1 and 16). + * @param hqspi QSPI handle. + * @param Threshold Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2495,7 +2509,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi : QSPI handle. + * @param hqspi QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) @@ -2504,8 +2518,8 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) } /** @brief Set FlashID. - * @param hqspi : QSPI handle. - * @param FlashID : Index of the flash memory to be accessed. + * @param hqspi QSPI handle. + * @param FlashID Index of the flash memory to be accessed. * This parameter can be a value of @ref QSPI_Flash_Select. * @note The FlashID is ignored when dual flash mode is enabled. * @retval HAL status @@ -2554,7 +2568,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashI /** * @brief DMA QSPI receive process complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -2568,7 +2582,7 @@ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) @@ -2582,7 +2596,7 @@ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI receive process half complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -2598,7 +2612,7 @@ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process half complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -2614,7 +2628,7 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI communication error callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) @@ -2639,7 +2653,7 @@ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI abort complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) @@ -2678,11 +2692,11 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) /** * @brief Wait for a flag state until timeout. - * @param hqspi : QSPI handle - * @param Flag : Flag checked - * @param State : Value of the flag expected - * @param Tickstart : Tick start value - * @param Timeout : Duration of the timeout + * @param hqspi QSPI handle + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Tickstart Tick start value + * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, @@ -2733,9 +2747,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleType /** * @brief Configure the communication registers. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information - * @param FunctionalMode : functional mode to configured + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information + * @param FunctionalMode functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode @@ -2899,5 +2913,3 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin */ #endif /* defined(QUADSPI) */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c index 552ef18ed8..f187348743 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c @@ -54,14 +54,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -1122,4 +1120,3 @@ __weak void HAL_RCC_CSSCallback(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c index b7db34fabc..114e09e058 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c @@ -10,14 +10,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -3784,4 +3782,3 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c index a9b233837d..bd50438df1 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c @@ -9,6 +9,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -79,17 +90,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -369,7 +369,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call /** * @brief Unregister an RNG Callback - * RNG callabck is redirected to the weak predefined callback + * RNG callback is redirected to the weak predefined callback * @param hrng RNG handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -865,4 +865,3 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c index 00f9e4b03e..2d2be66ddc 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c @@ -4,21 +4,32 @@ * @author MCD Application Team * @brief RTC HAL module driver. * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) peripheral: + * functionalities of the Real-Time Clock (RTC) peripheral: * + Initialization and de-initialization functions - * + RTC Time and Date functions - * + RTC Alarm functions + * + RTC Calendar (Time and Date) configuration functions + * + RTC Alarms (Alarm A and Alarm B) configuration functions * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== - ##### Backup Domain Operating Condition ##### + ##### RTC and Backup Domain Operating Condition ##### ============================================================================== [..] The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the VBAT voltage when the main VDD supply is powered off. - To retain the content of the RTC backup registers, backup SRAM, and supply + To retain the content of the RTC backup registers, BKP SRAM, and supply the RTC when VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source. @@ -26,7 +37,7 @@ off, the VBAT pin powers the following blocks: (#) The RTC (#) The LSE oscillator - (#) The backup SRAM when the low power backup regulator is enabled + (#) The BKP SRAM when the low power backup regulator is enabled (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) [..] When the backup domain is supplied by VDD (analog switch connected to VDD), @@ -44,9 +55,10 @@ ##### Backup Domain Reset ##### ================================================================== [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. The BKPSRAM is not affected by this reset. The only - way to reset the BKPSRAM is through the Flash interface by requesting - a protection level change from 1 to 0. + to their reset values. + The BKP SRAM is not affected by this reset. The only way to reset the BKP + SRAM is through the Flash interface by requesting a protection level + change from 1 to 0. [..] A backup domain reset is generated when one of the following events occurs: (#) Software reset, triggered by setting the BDRST bit in the RCC Backup domain control register (RCC_BDCR). @@ -54,19 +66,18 @@ ##### Backup Domain Access ##### ================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. + [..] After reset, the backup domain (RTC registers, RTC backup data registers + and BKP SRAM) is protected against possible unwanted write accesses. [..] To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the - __HAL_RCC_PWR_CLK_ENABLE() function. + __HAL_RCC_PWR_CLK_ENABLE() macro. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. - (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. - + (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() macro. + (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro. - ##### How to use this driver ##### - ================================================================== + ============================================================================== + ##### How to use this driver ##### + ============================================================================== [..] (+) Enable the RTC domain access (see description in the section above). (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour @@ -77,13 +88,21 @@ [..] (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() and HAL_RTC_SetDate() functions. - (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() + functions. + (+) To manage the RTC summer or winter time change, use the following + functions: + (++) HAL_RTC_DST_Add1Hour() or HAL_RTC_DST_Sub1Hour to add or subtract + 1 hour from the calendar time. + (++) HAL_RTC_DST_SetStoreOperation() or HAL_RTC_DST_ClearStoreOperation + to memorize whether the time change has been performed or not. *** Alarm configuration *** =========================== [..] (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. - You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. + You can also configure the RTC Alarm with interrupt mode using the + HAL_RTC_SetAlarm_IT() function. (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. ##### RTC and low power modes ##### @@ -91,30 +110,28 @@ [..] The MCU can be woken up from a low power mode by an RTC alternate function. [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - RTC wake-up, RTC tamper event detection and RTC time stamp event detection. + RTC wakeup, RTC tamper event detection and RTC timestamp event detection. These RTC alternate functions can wake up the system from the Stop and Standby low power modes. [..] The system can also wake up from low power modes without depending - on an external interrupt (Auto-wake-up mode), by using the RTC alarm - or the RTC wake-up events. + on an external interrupt (Auto-wakeup mode), by using the RTC alarm + or the RTC wakeup events. [..] The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals. - Wake-up from STOP and STANDBY modes is possible only when the RTC clock source - is LSE or LSI. + Wakeup from STOP and STANDBY modes is possible only when the RTC clock + source is LSE or LSI. *** Callback registration *** ============================================= - [..] The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Function HAL_RTC_RegisterCallback() to register an interrupt callback. - [..] Function HAL_RTC_RegisterCallback() allows to register following callbacks: (+) AlarmAEventCallback : RTC Alarm A Event callback. (+) AlarmBEventCallback : RTC Alarm B Event callback. - (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) TimeStampEventCallback : RTC Timestamp Event callback. (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. (+) Tamper1EventCallback : RTC Tamper 1 Event callback. (+) Tamper2EventCallback : RTC Tamper 2 Event callback. @@ -123,7 +140,6 @@ [..] This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - [..] Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default weak function. @@ -132,49 +148,36 @@ This function allows to reset following callbacks: (+) AlarmAEventCallback : RTC Alarm A Event callback. (+) AlarmBEventCallback : RTC Alarm B Event callback. - (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) TimeStampEventCallback : RTC Timestamp Event callback. (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. (+) Tamper1EventCallback : RTC Tamper 1 Event callback. (+) Tamper2EventCallback : RTC Tamper 2 Event callback. (+) MspInitCallback : RTC MspInit callback. (+) MspDeInitCallback : RTC MspDeInit callback. - [..] By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, - all callbacks are set to the corresponding weak functions : + all callbacks are set to the corresponding weak functions: examples AlarmAEventCallback(), WakeUpTimerEventCallback(). - Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function - in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null - (not registered beforehand). - If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - + Exception done for MspInit() and MspDeInit() callbacks that are reset to the + legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only + when these callbacks are null (not registered beforehand). + If not, MspInit() or MspDeInit() are not null, HAL_RTC_Init()/HAL_RTC_DeInit() + keep and use the user MspInit()/MspDeInit() callbacks (registered beforehand). [..] Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks + Exception done MspInit()/MspDeInit() that can be registered/unregistered + in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state. + Thus registered (user) MspInit()/MspDeInit() callbacks can be used during the + Init/DeInit. + In that case first register the MspInit()/MspDeInit() user callbacks using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() - or HAL_RTC_Init() function. - + or HAL_RTC_Init() functions. [..] When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - @endverbatim + not defined, the callback registration feature is not available and all + callbacks are set to the corresponding weak functions. - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * + @endverbatim ****************************************************************************** */ @@ -186,7 +189,7 @@ */ /** @defgroup RTC RTC - * @brief RTC HAL module driver + * @brief RTC HAL module driver * @{ */ @@ -204,8 +207,8 @@ */ /** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -216,7 +219,7 @@ RTC registers synchronization check and reference clock detection enable. (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. + (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler. (++) When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize power consumption. (#) All RTC registers are Write protected. Writing to the RTC registers @@ -226,11 +229,11 @@ and its value can be updated. When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles. (#) To read the calendar through the shadow registers after Calendar - initialization, calendar update or after wake-up from low power modes + initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the - RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function + RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function implements the above software sequence (RSF clear and RSF check). @endverbatim @@ -245,22 +248,25 @@ */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { - /* Check the RTC peripheral state */ - if(hrtc == NULL) + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check RTC handler validity */ + if (hrtc == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); - assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut)); - assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); + assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); + assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - if(hrtc->State == HAL_RTC_STATE_RESET) + if (hrtc->State == HAL_RTC_STATE_RESET) { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; @@ -270,22 +276,24 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ +#if defined(RTC_TAMPER2_SUPPORT) hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ +#endif /* RTC_TAMPER2_SUPPORT */ - if(hrtc->MspInitCallback == NULL) + if (hrtc->MspInitCallback == NULL) { hrtc->MspInitCallback = HAL_RTC_MspInit; } /* Init the low level hardware */ hrtc->MspInitCallback(hrtc); - if(hrtc->MspDeInitCallback == NULL) + if (hrtc->MspDeInitCallback == NULL) { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } -#else - if(hrtc->State == HAL_RTC_STATE_RESET) +#else /* USE_HAL_RTC_REGISTER_CALLBACKS */ + if (hrtc->State == HAL_RTC_STATE_RESET) { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; @@ -293,7 +301,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); } -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; @@ -301,18 +309,10 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - return HAL_ERROR; - } - else + if (status == HAL_OK) { /* Clear RTC_CR FMT, OSEL and POL Bits */ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); @@ -321,48 +321,39 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Configure the RTC PRER */ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U); + hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - } + status = RTC_ExitInitMode(hrtc); + } - hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE; + if (status == HAL_OK) + { + hrtc->Instance->TAFCR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL; hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + return status; } /** * @brief DeInitializes the RTC peripheral * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @note This function doesn't reset the RTC Backup Data registers. + * @note This function does not reset the RTC Backup Data registers. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart = 0U; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; @@ -370,116 +361,76 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - return HAL_ERROR; - } - else + if (status == HAL_OK) { - /* Reset TR, DR and CR registers */ + /* Reset RTC registers */ hrtc->Instance->TR = 0x00000000U; - hrtc->Instance->DR = 0x00002101U; - /* Reset All CR bits except CR[2:0] */ - hrtc->Instance->CR &= 0x00000007U; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till WUTWF flag is set and if Time out is reached exit */ - while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Reset all RTC CR register bits */ - hrtc->Instance->CR &= 0x00000000U; - hrtc->Instance->WUTR = 0x0000FFFFU; - hrtc->Instance->PRER = 0x007F00FFU; + hrtc->Instance->DR = (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0); + hrtc->Instance->CR &= 0x00000000U; + hrtc->Instance->WUTR = RTC_WUTR_WUT; + hrtc->Instance->PRER = (uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU); hrtc->Instance->CALIBR = 0x00000000U; - hrtc->Instance->ALRMAR = 0x00000000U; - hrtc->Instance->ALRMBR = 0x00000000U; - hrtc->Instance->SHIFTR = 0x00000000U; - hrtc->Instance->CALR = 0x00000000U; + hrtc->Instance->ALRMAR = 0x00000000U; + hrtc->Instance->ALRMBR = 0x00000000U; + hrtc->Instance->CALR = 0x00000000U; + hrtc->Instance->SHIFTR = 0x00000000U; hrtc->Instance->ALRMASSR = 0x00000000U; hrtc->Instance->ALRMBSSR = 0x00000000U; - /* Reset ISR register and exit initialization mode */ - hrtc->Instance->ISR = 0x00000000U; - - /* Reset Tamper and alternate functions configuration register */ - hrtc->Instance->TAFCR = 0x00000000U; - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - } + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - if(hrtc->MspDeInitCallback == NULL) + if (status == HAL_OK) { - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - } + /* Reset Tamper and alternate functions configuration register */ + hrtc->Instance->TAFCR = 0x00000000U; - /* DeInit the low level hardware: CLOCK, NVIC.*/ - hrtc->MspDeInitCallback(hrtc); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } -#else - /* De-Initialize RTC MSP */ - HAL_RTC_MspDeInit(hrtc); -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hrtc->MspDeInitCallback(hrtc); +#else /* USE_HAL_RTC_REGISTER_CALLBACKS */ + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - hrtc->State = HAL_RTC_STATE_RESET; + hrtc->State = HAL_RTC_STATE_RESET; + } /* Release Lock */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) /** - * @brief Register a User RTC Callback + * @brief Registers a User RTC Callback * To be used instead of the weak predefined callback - * @param hrtc RTC handle + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID - * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID - * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wake-Up Timer Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @note HAL_RTC_TAMPER2_EVENT_CB_ID is not applicable to all devices. * @param pCallback pointer to the Callback function * @retval HAL status */ @@ -487,7 +438,7 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -495,64 +446,66 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call /* Process locked */ __HAL_LOCK(hrtc); - if(HAL_RTC_STATE_READY == hrtc->State) + if (HAL_RTC_STATE_READY == hrtc->State) { switch (CallbackID) { - case HAL_RTC_ALARM_A_EVENT_CB_ID : - hrtc->AlarmAEventCallback = pCallback; - break; - - case HAL_RTC_ALARM_B_EVENT_CB_ID : - hrtc->AlarmBEventCallback = pCallback; - break; - - case HAL_RTC_TIMESTAMP_EVENT_CB_ID : - hrtc->TimeStampEventCallback = pCallback; - break; - - case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : - hrtc->WakeUpTimerEventCallback = pCallback; - break; - - case HAL_RTC_TAMPER1_EVENT_CB_ID : - hrtc->Tamper1EventCallback = pCallback; - break; - - case HAL_RTC_TAMPER2_EVENT_CB_ID : - hrtc->Tamper2EventCallback = pCallback; - break; - - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = pCallback; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = pCallback; + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = pCallback; + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = pCallback; + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = pCallback; + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = pCallback; + break; + +#if defined(RTC_TAMPER2_SUPPORT) + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = pCallback; + break; +#endif /* RTC_TAMPER2_SUPPORT */ + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(HAL_RTC_STATE_RESET == hrtc->State) + else if (HAL_RTC_STATE_RESET == hrtc->State) { switch (CallbackID) { - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = pCallback; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -568,19 +521,21 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call } /** - * @brief Unregister an RTC Callback + * @brief Unregisters an RTC Callback * RTC callabck is redirected to the weak predefined callback - * @param hrtc RTC handle + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID - * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID - * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wake-Up Timer Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @note HAL_RTC_TAMPER2_EVENT_CB_ID is not applicable to all devices. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) @@ -590,64 +545,66 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca /* Process locked */ __HAL_LOCK(hrtc); - if(HAL_RTC_STATE_READY == hrtc->State) + if (HAL_RTC_STATE_READY == hrtc->State) { switch (CallbackID) { - case HAL_RTC_ALARM_A_EVENT_CB_ID : - hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ - break; - - case HAL_RTC_ALARM_B_EVENT_CB_ID : - hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ - break; - - case HAL_RTC_TIMESTAMP_EVENT_CB_ID : - hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ - break; - - case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : - hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ - break; - - case HAL_RTC_TAMPER1_EVENT_CB_ID : - hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ - break; - - case HAL_RTC_TAMPER2_EVENT_CB_ID : - hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ - break; - - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = HAL_RTC_MspInit; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + break; + +#if defined(RTC_TAMPER2_SUPPORT) + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ + break; +#endif /* RTC_TAMPER2_SUPPORT */ + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(HAL_RTC_STATE_RESET == hrtc->State) + else if (HAL_RTC_STATE_RESET == hrtc->State) { switch (CallbackID) { - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = HAL_RTC_MspInit; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -669,12 +626,13 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca * the configuration information for RTC. * @retval None */ -__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_MspInit could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTC_MspInit could be implemented in the user file */ } @@ -684,12 +642,13 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) * the configuration information for RTC. * @retval None */ -__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_MspDeInit could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTC_MspDeInit could be implemented in the user file */ } @@ -698,8 +657,8 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) */ /** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions - * @brief RTC Time and Date functions - * + * @brief RTC Time and Date functions + * @verbatim =============================================================================== ##### RTC Time and Date functions ##### @@ -716,6 +675,8 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param sTime Pointer to Time structure + * @note DayLightSaving and StoreOperation interfaces are deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions. * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format @@ -725,8 +686,9 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { uint32_t tmpreg = 0U; + HAL_StatusTypeDef status; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); @@ -736,9 +698,9 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(sTime->Hours)); assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); @@ -751,14 +713,14 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim assert_param(IS_RTC_MINUTES(sTime->Minutes)); assert_param(IS_RTC_SECONDS(sTime->Seconds)); - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - (((uint32_t)sTime->TimeFormat) << 16U)); + tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + ( (uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ( (uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ + (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); } else { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); @@ -770,69 +732,45 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ - ((uint32_t)(sTime->Minutes) << 8U) | \ - ((uint32_t)sTime->Seconds) | \ - ((uint32_t)(sTime->TimeFormat) << 16U)); + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t) sTime->Seconds) | \ + ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + if (status == HAL_OK) { /* Set the RTC_TR register */ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK; + /* Clear the bits to be configured (Deprecated. Use HAL_RTC_DST_xxx functions instead) */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP; - /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ + /* Configure the RTC_CR register (Deprecated. Use HAL_RTC_DST_xxx functions instead) */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } + status = RTC_ExitInitMode(hrtc); + } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } - hrtc->State = HAL_RTC_STATE_READY; + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_OK; - } + return status; } /** @@ -844,13 +782,19 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format - * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds - * value in second fraction ratio with time unit following generic formula: - * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit - * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers to ensure consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers until current date is read. + * @note You can use SubSeconds and SecondFraction (sTime structure fields + * returned) to convert SubSeconds value in second fraction ratio with + * time unit following generic formula: + * Second fraction ratio * time_unit = + * [(SecondFraction - SubSeconds) / (SecondFraction + 1)] * time_unit + * This conversion can be performed only if no shift operation is pending + * (ie. SHFP=0) when PREDIV_S >= SS + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the + * values in the higher-order calendar shadow registers to ensure + * consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers + * until current date is read to ensure consistency between the time and + * date values. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) @@ -860,7 +804,7 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - /* Get subseconds structure field from the corresponding register */ + /* Get subseconds value from the corresponding register */ sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); /* Get SecondFraction structure field from the corresponding register field*/ @@ -870,13 +814,13 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U); - sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U); - sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U); + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); + sTime->Seconds = (uint8_t)( tmpreg & (RTC_TR_ST | RTC_TR_SU)); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos); /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { /* Convert the time structure parameters to Binary format */ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); @@ -901,32 +845,33 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { uint32_t datetmpreg = 0U; + HAL_StatusTypeDef status; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - /* Process Locked */ - __HAL_LOCK(hrtc); + /* Process Locked */ + __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; - if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) { sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); } assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { assert_param(IS_RTC_YEAR(sDate->Year)); assert_param(IS_RTC_MONTH(sDate->Month)); assert_param(IS_RTC_DATE(sDate->Date)); - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - ((uint32_t)sDate->WeekDay << 13U)); + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); } else { @@ -934,64 +879,39 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); - datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ - (((uint32_t)sDate->Month) << 8U) | \ - ((uint32_t)sDate->Date) | \ - (((uint32_t)sDate->WeekDay) << 13U)); + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + ((uint32_t) sDate->Date) | \ + (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - return HAL_ERROR; - } - else + if (status == HAL_OK) { /* Set the RTC_DR register */ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } + status = RTC_ExitInitMode(hrtc); + } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } - hrtc->State = HAL_RTC_STATE_READY ; + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_OK; - } + return status; } /** @@ -1003,9 +923,12 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers to ensure consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers until Current date is read. + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the + * values in the higher-order calendar shadow registers to ensure + * consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers + * until current date is read to ensure consistency between the time and + * date values. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) @@ -1019,18 +942,18 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U); - sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U); - sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U); + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos); + sDate->Date = (uint8_t) (datetmpreg & (RTC_DR_DT | RTC_DR_DU)); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos); /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { /* Convert the date structure parameters to Binary format */ - sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); + sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); - sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); + sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); } return HAL_OK; } @@ -1040,8 +963,8 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ /** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions - * @brief RTC Alarm functions - * + * @brief RTC Alarm functions + * @verbatim =============================================================================== ##### RTC Alarm functions ##### @@ -1061,12 +984,16 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the HAL_RTC_DeactivateAlarm()). + * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { uint32_t tickstart = 0U; - uint32_t tmpreg = 0U, subsecondtmpreg = 0U; + uint32_t tmpreg = 0U; + uint32_t subsecondtmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -1079,11 +1006,14 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state to BUSY */ hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == RTC_FORMAT_BIN) + /* Check the data format (binary or BCD) and store the Alarm time and date + configuration accordingly */ + if (Format == RTC_FORMAT_BIN) { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); @@ -1096,7 +1026,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); } @@ -1105,17 +1035,17 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } else { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); @@ -1129,7 +1059,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } @@ -1138,37 +1068,41 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t) sAlarm->AlarmMask)); } - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + /* Store the Alarm subseconds configuration */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | \ + (uint32_t)(sAlarm->AlarmSubSecondMask)); /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) + if (sAlarm->Alarm == RTC_ALARM_A) { - /* Disable the Alarm A interrupt */ + /* Disable the Alarm A */ __HAL_RTC_ALARMA_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ + /* In case interrupt mode is used, the interrupt source must be disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); + /* Clear the Alarm flag */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1183,26 +1117,29 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Sub Second register */ + /* Configure the Alarm A Subseconds register */ hrtc->Instance->ALRMASSR = subsecondtmpreg; /* Configure the Alarm state: Enable Alarm */ __HAL_RTC_ALARMA_ENABLE(hrtc); } else { - /* Disable the Alarm B interrupt */ + /* Disable the Alarm B */ __HAL_RTC_ALARMB_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ + /* In case interrupt mode is used, the interrupt source must be disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); + /* Clear the Alarm flag */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1217,7 +1154,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Sub Second register */ + /* Configure the Alarm B Subseconds register */ hrtc->Instance->ALRMBSSR = subsecondtmpreg; /* Configure the Alarm state: Enable Alarm */ __HAL_RTC_ALARMB_ENABLE(hrtc); @@ -1226,7 +1163,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ + /* Change RTC state back to READY */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1236,7 +1173,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } /** - * @brief Sets the specified RTC Alarm with Interrupt + * @brief Sets the specified RTC Alarm with Interrupt. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param sAlarm Pointer to Alarm structure @@ -1244,12 +1181,16 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the HAL_RTC_DeactivateAlarm()). + * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t tmpreg = 0U, subsecondtmpreg = 0U; - __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U) ; + __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + uint32_t tmpreg = 0U; + uint32_t subsecondtmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -1262,11 +1203,14 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state to BUSY */ hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == RTC_FORMAT_BIN) + /* Check the data format (binary or BCD) and store the Alarm time and date + configuration accordingly */ + if (Format == RTC_FORMAT_BIN) { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); @@ -1279,7 +1223,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); } @@ -1287,17 +1231,18 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } else { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); @@ -1311,7 +1256,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } @@ -1319,30 +1264,33 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); + + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t) sAlarm->AlarmMask)); } - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + + /* Store the Alarm subseconds configuration */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | \ + (uint32_t)(sAlarm->AlarmSubSecondMask)); /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) + if (sAlarm->Alarm == RTC_ALARM_A) { - /* Disable the Alarm A interrupt */ + /* Disable the Alarm A */ __HAL_RTC_ALARMA_DISABLE(hrtc); - /* Clear flag alarm A */ + /* Clear the Alarm flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ do { if (count-- == 0U) @@ -1357,26 +1305,28 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef return HAL_TIMEOUT; } - } - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET); + } while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U); hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Sub Second register */ + /* Configure the Alarm A Subseconds register */ hrtc->Instance->ALRMASSR = subsecondtmpreg; /* Configure the Alarm state: Enable Alarm */ __HAL_RTC_ALARMA_ENABLE(hrtc); /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); + __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA); } else { - /* Disable the Alarm B interrupt */ + /* Disable the Alarm B */ __HAL_RTC_ALARMB_DISABLE(hrtc); - /* Clear flag alarm B */ + /* Clear the Alarm flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + /* Reload the counter */ + count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + + /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */ do { if (count-- == 0U) @@ -1391,11 +1341,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef return HAL_TIMEOUT; } - } - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET); + } while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U); hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Sub Second register */ + /* Configure the Alarm B Subseconds register */ hrtc->Instance->ALRMBSSR = subsecondtmpreg; /* Configure the Alarm state: Enable Alarm */ __HAL_RTC_ALARMB_ENABLE(hrtc); @@ -1405,12 +1354,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* RTC Alarm Interrupt Configuration: EXTI configuration */ __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - - EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT; + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state back to READY */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1420,13 +1369,13 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } /** - * @brief Deactivate the specified RTC Alarm + * @brief Deactivates the specified RTC Alarm. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB + * @arg RTC_ALARM_A: Alarm A + * @arg RTC_ALARM_B: Alarm B * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) @@ -1444,21 +1393,21 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - if(Alarm == RTC_ALARM_A) + if (Alarm == RTC_ALARM_A) { - /* AlarmA */ + /* Disable Alarm A */ __HAL_RTC_ALARMA_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ + /* In case interrupt mode is used, the interrupt source must be disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1474,19 +1423,19 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar } else { - /* AlarmB */ + /* Disable Alarm B */ __HAL_RTC_ALARMB_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB); + /* In case interrupt mode is used, the interrupt source must be disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1500,6 +1449,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar } } } + /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1518,8 +1468,8 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar * @param sAlarm Pointer to Date structure * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB + * @arg RTC_ALARM_A: Alarm A + * @arg RTC_ALARM_B: Alarm B * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format @@ -1528,19 +1478,19 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar */ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) { - uint32_t tmpreg = 0U, subsecondtmpreg = 0U; + uint32_t tmpreg = 0U; + uint32_t subsecondtmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); assert_param(IS_RTC_ALARM(Alarm)); - if(Alarm == RTC_ALARM_A) + if (Alarm == RTC_ALARM_A) { - /* AlarmA */ sAlarm->Alarm = RTC_ALARM_A; tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); + subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS); } else { @@ -1551,67 +1501,67 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } /* Fill the structure with the read parameters */ - sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U); - sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U); - sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U); + sAlarm->AlarmTime.Hours = (uint8_t) ((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t) ((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t) ( tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); + sAlarm->AlarmTime.TimeFormat = (uint8_t) ((tmpreg & RTC_ALRMAR_PM) >> RTC_TR_PM_Pos); sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; - sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U); - sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + sAlarm->AlarmDateWeekDay = (uint8_t) ((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t) (tmpreg & RTC_ALRMAR_WDSEL); + sAlarm->AlarmMask = (uint32_t) (tmpreg & RTC_ALARMMASK_ALL); - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { - sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); - sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); } return HAL_OK; } /** - * @brief This function handles Alarm interrupt request. + * @brief Handles Alarm interrupt request. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) { - /* Get the AlarmA interrupt source enable status */ - if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != (uint32_t)RESET) + /* Get the Alarm A interrupt source enable status */ + if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U) { - /* Get the pending status of the AlarmA Interrupt */ - if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET) + /* Get the pending status of the Alarm A Interrupt */ + if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U) { - /* AlarmA callback */ - #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Alarm A callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->AlarmAEventCallback(hrtc); - #else +#else HAL_RTC_AlarmAEventCallback(hrtc); - #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* Clear the AlarmA interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF); + /* Clear the Alarm A interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); } } - /* Get the AlarmB interrupt source enable status */ - if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != (uint32_t)RESET) + /* Get the Alarm B interrupt source enable status */ + if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U) { - /* Get the pending status of the AlarmB Interrupt */ - if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != (uint32_t)RESET) + /* Get the pending status of the Alarm B Interrupt */ + if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U) { - /* AlarmB callback */ - #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Alarm B callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->AlarmBEventCallback(hrtc); - #else +#else HAL_RTCEx_AlarmBEventCallback(hrtc); - #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* Clear the AlarmB interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF); + /* Clear the Alarm B interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); } } @@ -1632,13 +1582,14 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTC_AlarmAEventCallback could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTC_AlarmAEventCallback could be implemented in the user file */ } /** - * @brief This function handles AlarmA Polling request. + * @brief Handles Alarm A Polling request. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Timeout Timeout duration @@ -1648,14 +1599,15 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T { uint32_t tickstart = 0U; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) + /* Wait till RTC ALRAF flag is set and if timeout is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1663,7 +1615,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T } } - /* Clear the Alarm interrupt pending bit */ + /* Clear the Alarm flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); /* Change RTC state */ @@ -1677,8 +1629,8 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T */ /** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions - * @brief Peripheral Control functions - * + * @brief Peripheral Control functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -1686,6 +1638,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T [..] This subsection provides functions allowing to (+) Wait for RTC Time and Date Synchronization + (+) Manage RTC Summer or Winter time change @endverbatim * @{ @@ -1697,7 +1650,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * @note The RTC Resynchronization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wake-up from low power modes + * initialization, calendar update or after wakeup from low power modes * the software must first clear the RSF flag. * The software must then wait until it is set again before reading * the calendar, which means that the calendar registers have been @@ -1706,20 +1659,20 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * the configuration information for RTC. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { uint32_t tickstart = 0U; /* Clear RSF flag */ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait the registers to be synchronised */ - while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) + while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -1729,38 +1682,10 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) } /** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Get RTC state - -@endverbatim - * @{ - */ -/** - * @brief Returns the RTC state. + * @brief Daylight Saving Time, adds one hour to the calendar in one + * single operation without going through the initialization procedure. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @retval HAL state - */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) -{ - return hrtc->State; -} - -/** - * @brief Daylight Saving Time, Add one hour to the calendar in one single operation - * without going through the initialization procedure. - * @param hrtc RTC handle * @retval None */ void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) @@ -1771,9 +1696,10 @@ void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) } /** - * @brief Daylight Saving Time, Substract one hour from the calendar in one + * @brief Daylight Saving Time, subtracts one hour from the calendar in one * single operation without going through the initialization procedure. - * @param hrtc RTC handle + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) @@ -1784,9 +1710,10 @@ void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) } /** - * @brief Daylight Saving Time, Set the store operation bit. + * @brief Daylight Saving Time, sets the store operation bit. * @note It can be used by the software in order to memorize the DST status. - * @param hrtc RTC handle + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) @@ -1797,8 +1724,9 @@ void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) } /** - * @brief Daylight Saving Time, Clear the store operation bit. - * @param hrtc RTC handle + * @brief Daylight Saving Time, clears the store operation bit. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) @@ -1809,7 +1737,7 @@ void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) } /** - * @brief Daylight Saving Time, Read the store operation bit. + * @brief Daylight Saving Time, reads the store operation bit. * @param hrtc RTC handle * @retval operation see RTC_StoreOperation_Definitions */ @@ -1822,6 +1750,44 @@ uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) * @} */ +/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Get RTC state + +@endverbatim + * @{ + */ +/** + * @brief Returns the RTC state. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL state + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) +{ + return hrtc->State; +} + +/** + * @} + */ + + +/** + * @} + */ + +/** @addtogroup RTC_Private_Functions + * @{ + */ + /** * @brief Enters the RTC Initialization mode. * @note The RTC Initialization mode is write protected, use the @@ -1830,61 +1796,90 @@ uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) * the configuration information for RTC. * @retval HAL status */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { uint32_t tickstart = 0U; + HAL_StatusTypeDef status = HAL_OK; - /* Check if the Initialization mode is set */ - if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + /* Check that Initialization mode is not already set */ + if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) { - /* Set the Initialization mode */ - hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; + /* Set INIT bit to enter Initialization mode */ + SET_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC is in INIT state and if Time out is reached exit */ - while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + /* Wait till RTC is in INIT state and if timeout is reached exit */ + while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR)) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + status = HAL_ERROR; } } } - return HAL_OK; + return status; } +/** + * @brief Exits the RTC Initialization mode. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Clear INIT bit to exit Initialization mode */ + CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + status = HAL_ERROR; + } + } + + return status; +} /** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value Byte to be converted + * @brief Converts a 2-digit number from decimal to BCD format. + * @param number decimal-formatted number (from 0 to 99) to be converted * @retval Converted byte */ -uint8_t RTC_ByteToBcd2(uint8_t Value) +uint8_t RTC_ByteToBcd2(uint8_t number) { - uint32_t bcdhigh = 0U; + uint8_t bcdhigh = 0U; - while(Value >= 10U) + while (number >= 10U) { bcdhigh++; - Value -= 10U; + number -= 10U; } - return ((uint8_t)(bcdhigh << 4U) | Value); + return ((uint8_t)(bcdhigh << 4U) | number); } /** - * @brief Converts from 2 digit BCD to Binary. - * @param Value BCD value to be converted + * @brief Converts a 2-digit number from BCD to decimal format. + * @param number BCD-formatted number (from 00 to 99) to be converted * @retval Converted word */ -uint8_t RTC_Bcd2ToByte(uint8_t Value) +uint8_t RTC_Bcd2ToByte(uint8_t number) { - uint32_t tmp = 0U; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); + uint8_t tmp = 0U; + tmp = ((uint8_t)(number & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (number & (uint8_t)0x0F)); } /** @@ -1899,5 +1894,3 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c index 8e07b4e22e..eb5708fa0d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c @@ -2,58 +2,76 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc_ex.c * @author MCD Application Team - * @brief RTC HAL module driver. + * @brief Extended RTC HAL module driver. * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) Extension peripheral: - * + RTC Time Stamp functions + * functionalities of the Real-Time Clock (RTC) Extended peripheral: + * + RTC Timestamp functions * + RTC Tamper functions - * + RTC Wake-up functions - * + Extension Control functions - * + Extension RTC features functions + * + RTC Wakeup functions + * + Extended Control functions + * + Extended RTC features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== - ##### How to use this driver ##### + ##### How to use this driver ##### ============================================================================== [..] (+) Enable the RTC domain access. (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour format using the HAL_RTC_Init() function. - *** RTC Wake-up configuration *** + *** RTC Wakeup configuration *** ================================ [..] - (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() - function. You can also configure the RTC Wake-up timer in interrupt mode - using the HAL_RTCEx_SetWakeUpTimer_IT() function. - (+) To read the RTC Wake-up Counter register, use the HAL_RTCEx_GetWakeUpTimer() + (+) To configure the RTC Wakeup Clock source and Counter use the + HAL_RTCEx_SetWakeUpTimer() function. + You can also configure the RTC Wakeup timer in interrupt mode using the + HAL_RTCEx_SetWakeUpTimer_IT() function. + (+) To read the RTC Wakeup Counter register, use the HAL_RTCEx_GetWakeUpTimer() function. - *** TimeStamp configuration *** + *** Timestamp configuration *** =============================== [..] - (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the - HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with - interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function. - (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() - function. - (+) The TIMESTAMP alternate function can be mapped either to RTC_AF1 (PC13) - or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TSINSEL bit in - RTC_TAFCR register. The corresponding pin is also selected by HAL_RTCEx_SetTimeStamp() - or HAL_RTCEx_SetTimeStamp_IT() function. + (+) To configure the RTC Timestamp use the HAL_RTCEx_SetTimeStamp() function. + You can also configure the RTC Timestamp with interrupt mode using the + HAL_RTCEx_SetTimeStamp_IT() function. + (+) To read the RTC Timestamp Time and Date register, use the + HAL_RTCEx_GetTimeStamp() function. + (+) The Timestamp alternate function can be mapped either to RTC_AF1 (PC13) + or RTC_AF2 (PI8) depending on the value of TSINSEL bit in RTC_TAFCR + register. + For STM32F446xx devices RTC_AF2 corresponds to pin PA0 and not to pin PI8. + The corresponding pin is also selected by HAL_RTCEx_SetTimeStamp() + or HAL_RTCEx_SetTimeStamp_IT() functions. *** Tamper configuration *** ============================ [..] - (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge - or Level according to the Tamper filter (if equal to 0 Edge else Level) - value, sampling frequency, precharge or discharge and Pull-UP using the - HAL_RTCEx_SetTamper() function. You can configure RTC Tamper in interrupt - mode using HAL_RTCEx_SetTamper_IT() function. + (+) To Enable the RTC Tamper and configure the Tamper filter count, trigger + Edge or Level according to the Tamper filter value (if equal to 0 Edge + else Level), sampling frequency, precharge or discharge and Pull-UP use + the HAL_RTCEx_SetTamper() function. + You can configure RTC Tamper in interrupt mode using HAL_RTCEx_SetTamper_IT() + function. (+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13) - or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TAMP1INSEL bit in - RTC_TAFCR register. The corresponding pin is also selected by HAL_RTCEx_SetTamper() - or HAL_RTCEx_SetTamper_IT() function. + or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in RTC_TAFCR + register. + The corresponding pin is also selected by HAL_RTCEx_SetTamper() + or HAL_RTCEx_SetTamper_IT() functions. + (+) The TAMPER2 alternate function is mapped to RTC_AF2 (PI8). + For STM32F446xx devices RTC_AF2 corresponds to pin PA0 and not to pin PI8. *** Backup Data Registers configuration *** =========================================== @@ -63,18 +81,44 @@ (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() function. - @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * + *** Coarse Digital Calibration configuration *** + ================================================ + [..] + (+) The Coarse Digital Calibration can be used to compensate crystal inaccuracy + by setting the DCS bit in RTC_CALIBR register. + (+) When positive calibration is enabled (DCS = ‘0’), 2 asynchronous prescaler + clock cycles are added every minute during 2xDC minutes. + This causes the calendar to be updated sooner, thereby adjusting the + effective RTC frequency to be a bit higher. + (+) When negative calibration is enabled (DCS = ‘1’), 1 asynchronous prescaler + clock cycle is removed every minute during 2xDC minutes. + This causes the calendar to be updated later, thereby adjusting the + effective RTC frequency to be a bit lower. + (+) DC is configured through bits DC[4:0] of RTC_CALIBR register. This number + ranges from 0 to 31 corresponding to a time interval (2xDC) ranging from + 0 to 62. + (+) In order to measure the clock deviation, a 512 Hz clock is output for + calibration. + (+) The RTC Coarse Digital Calibration value and sign can be calibrated using + the HAL_RTCEx_SetCoarseCalib() function. + + *** Smooth Digital Calibration configuration *** + ================================================ + [..] + (+) RTC frequency can be digitally calibrated with a resolution of about + 0.954 ppm with a range from -487.1 ppm to +488.5 ppm. + The correction of the frequency is performed using a series of small + adjustments (adding and/or subtracting individual RTCCLK pulses). + (+) The smooth digital calibration is performed during a cycle of about 2^20 + RTCCLK pulses (or 32 seconds) when the input frequency is 32,768 Hz. + This cycle is maintained by a 20-bit counter clocked by RTCCLK. + (+) The smooth calibration register (RTC_CALR) specifies the number of RTCCLK + clock cycles to be masked during the 32-second cycle. + (+) The RTC Smooth Digital Calibration value and the corresponding calibration + cycle period (32s, 16s, or 8s) can be calibrated using the + HAL_RTCEx_SetSmoothCalib() function. + + @endverbatim ****************************************************************************** */ @@ -86,7 +130,7 @@ */ /** @defgroup RTCEx RTCEx - * @brief RTC HAL module driver + * @brief RTC Extended HAL module driver * @{ */ @@ -97,80 +141,90 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions * @{ */ -/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions - * @brief RTC TimeStamp and Tamper functions - * +/** @defgroup RTCEx_Exported_Functions_Group1 RTC Timestamp and Tamper functions + * @brief RTC Timestamp and Tamper functions + * @verbatim =============================================================================== - ##### RTC TimeStamp and Tamper functions ##### + ##### RTC Timestamp and Tamper functions ##### =============================================================================== - [..] This section provides functions allowing to configure TimeStamp feature + [..] This section provides functions allowing to configure Timestamp feature @endverbatim * @{ */ /** - * @brief Sets TimeStamp. - * @note This API must be called before enabling the TimeStamp feature. + * @brief Sets Timestamp. + * @note This API must be called before enabling the Timestamp feature. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * @param RTC_TimeStampEdge Specifies the pin edge on which the Timestamp is * activated. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin. + * @arg RTC_TIMESTAMPEDGE_RISING: the Timestamp event occurs on + * the rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Timestamp event occurs on + * the falling edge of the related pin. + * @param RTC_TimeStampPin Specifies the RTC Timestamp Pin. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. - * @arg RTC_TIMESTAMPPIN_POS1: PI8/PA0 is selected as RTC TimeStamp Pin. - * (not applicable in the case of STM32F412xx, STM32F413xx and STM32F423xx devices) - * (PI8 for all STM32 devices except for STM32F446xx devices the PA0 is used) - * @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC Timestamp Pin. + * @arg RTC_TIMESTAMPPIN_POS1: PI8 is selected as RTC Timestamp Pin. + * @note RTC_TIMESTAMPPIN_POS1 corresponds to pin PA0 in the case of + * STM32F446xx devices. + * @note RTC_TIMESTAMPPIN_POS1 is not applicable to the following list of devices: + * STM32F412xx, STM32F413xx and STM32F423xx. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin) { uint32_t tmpreg = 0U; /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + assert_param(IS_TIMESTAMP_EDGE(RTC_TimeStampEdge)); assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state to BUSY */ hrtc->State = HAL_RTC_STATE_BUSY; + hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL; + hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); + /* Get the RTC_CR register and clear the bits to be configured */ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - tmpreg|= TimeStampEdge; + /* Configure the Timestamp TSEDGE bit */ + tmpreg |= RTC_TimeStampEdge; /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL; - hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); - - /* Configure the Time Stamp TSEDGE and Enable bits */ + /* Copy the desired configuration into the CR register */ hrtc->Instance->CR = (uint32_t)tmpreg; + /* Clear RTC Timestamp flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); + + /* Clear RTC Timestamp overrun Flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); + + /* Enable the Timestamp saving */ __HAL_RTC_TIMESTAMP_ENABLE(hrtc); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ + /* Change RTC state back to READY */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -180,67 +234,76 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS } /** - * @brief Sets TimeStamp with Interrupt. + * @brief Sets Timestamp with Interrupt. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @note This API must be called before enabling the TimeStamp feature. - * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * @note This API must be called before enabling the Timestamp feature. + * @param RTC_TimeStampEdge Specifies the pin edge on which the Timestamp is * activated. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin. + * @arg RTC_TIMESTAMPEDGE_RISING: the Timestamp event occurs on + * the rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Timestamp event occurs on + * the falling edge of the related pin. + * @param RTC_TimeStampPin Specifies the RTC Timestamp Pin. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. - * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx, STM32F412xx, STM32F413xx and STM32F423xx devices) - * @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC Timestamp Pin. + * @arg RTC_TIMESTAMPPIN_POS1: PI8 is selected as RTC Timestamp Pin. + * @note RTC_TIMESTAMPPIN_POS1 corresponds to pin PA0 in the case of + * STM32F446xx devices. + * @note RTC_TIMESTAMPPIN_POS1 is not applicable to the following list of devices: + * STM32F412xx, STM32F413xx and STM32F423xx. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin) { uint32_t tmpreg = 0U; /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + assert_param(IS_TIMESTAMP_EDGE(RTC_TimeStampEdge)); assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state to BUSY */ hrtc->State = HAL_RTC_STATE_BUSY; + hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL; + hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); + /* Get the RTC_CR register and clear the bits to be configured */ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - tmpreg |= TimeStampEdge; + /* Configure the Timestamp TSEDGE bit */ + tmpreg |= RTC_TimeStampEdge; /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the Time Stamp TSEDGE and Enable bits */ + /* Copy the desired configuration into the CR register */ hrtc->Instance->CR = (uint32_t)tmpreg; - hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL; - hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); - /* Clear RTC Timestamp flag */ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable IT timestamp */ - __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); + /* Clear RTC Timestamp overrun Flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - /* RTC timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + /* Enable the Timestamp saving */ + __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + /* Enable IT Timestamp */ + __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* RTC Timestamp Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); + + /* Change RTC state back to READY */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -250,7 +313,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti } /** - * @brief Deactivates TimeStamp. + * @brief Deactivates Timestamp. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status @@ -273,7 +336,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) /* Get the RTC_CR register and clear the bits to be configured */ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - /* Configure the Time Stamp TSEDGE and Enable bits */ + /* Configure the Timestamp TSEDGE and Enable bits */ hrtc->Instance->CR = (uint32_t)tmpreg; /* Enable the write protection for RTC registers */ @@ -288,70 +351,71 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) } /** - * @brief Gets the RTC TimeStamp value. + * @brief Gets the RTC Timestamp value. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param sTimeStamp Pointer to Time structure * @param sTimeStampDate Pointer to Date structure * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: - * RTC_FORMAT_BIN: Binary data format - * RTC_FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format) { - uint32_t tmptime = 0U, tmpdate = 0U; + uint32_t tmptime = 0U; + uint32_t tmpdate = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - /* Get the TimeStamp time and date registers values */ + /* Get the Timestamp time and date registers values */ tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK); tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U); - sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U); + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos); + sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos); sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; /* Fill the Date structure fields with the read parameters */ - sTimeStampDate->Year = 0U; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U); - sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U); + sTimeStampDate->Year = 0U; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos); + sTimeStampDate->Date = (uint8_t)((tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)) >> RTC_TSDR_DU_Pos); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos); /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { - /* Convert the TimeStamp structure parameters to Binary format */ - sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); + /* Convert the Timestamp structure parameters to Binary format */ + sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); /* Convert the DateTimeStamp structure parameters to Binary format */ - sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); - sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); + sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); + sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); } - /* Clear the TIMESTAMP Flag */ + /* Clear the Timestamp Flag */ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); return HAL_OK; } /** - * @brief Sets Tamper - * @note By calling this API we disable the tamper interrupt for all tampers. + * @brief Sets Tamper. + * @note By calling this API the tamper global interrupt will be disabled. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) { uint32_t tmpreg = 0U; @@ -360,6 +424,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection)); assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger)); assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); @@ -370,20 +435,46 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef hrtc->State = HAL_RTC_STATE_BUSY; - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + /* Copy control register into temporary variable */ + tmpreg = hrtc->Instance->TAFCR; + + /* Enable selected tamper */ + tmpreg |= (sTamper->Tamper); + + /* Configure the tamper trigger bit (this bit is just on the right of the + tamper enable bit, hence the one-time right shift before updating it) */ + if (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE) { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); + /* Set the tamper trigger bit (case of falling edge or high level) */ + tmpreg |= (uint32_t)(sTamper->Tamper << 1U); } + else + { + /* Clear the tamper trigger bit (case of rising edge or low level) */ + tmpreg &= (uint32_t)~(sTamper->Tamper << 1U); + } + + /* Clear remaining fields before setting them */ + tmpreg &= ~(RTC_TAMPERFILTER_MASK | \ + RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \ + RTC_TAMPERPRECHARGEDURATION_MASK | \ + RTC_TAMPER_PULLUP_MASK | \ + RTC_TAFCR_TAMP1INSEL | \ + RTC_TIMESTAMPONTAMPERDETECTION_MASK); - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)sTamper->Trigger |\ - (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\ - (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); + /* Set remaining parameters of desired configuration into temporary variable */ + tmpreg |= ((uint32_t)sTamper->Filter | \ + (uint32_t)sTamper->SamplingFrequency | \ + (uint32_t)sTamper->PrechargeDuration | \ + (uint32_t)sTamper->TamperPullUp | \ + (uint32_t)sTamper->PinSelection | \ + (uint32_t)sTamper->TimeStampOnTamperDetection); - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\ - (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\ - (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPINSEL | (uint32_t)RTC_TAFCR_TAMPIE); + /* Disable tamper global interrupt in case it is enabled */ + tmpreg &= (uint32_t)~RTC_TAFCR_TAMPIE; - hrtc->Instance->TAFCR |= tmpreg; + /* Copy desired configuration into configuration register */ + hrtc->Instance->TAFCR = tmpreg; hrtc->State = HAL_RTC_STATE_READY; @@ -395,13 +486,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef /** * @brief Sets Tamper with interrupt. - * @note By calling this API we force the tamper interrupt for all tampers. + * @note By calling this API the tamper global interrupt will be enabled. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param sTamper Pointer to RTC Tamper. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) { uint32_t tmpreg = 0U; @@ -410,6 +501,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection)); assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger)); assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); @@ -420,40 +512,50 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType hrtc->State = HAL_RTC_STATE_BUSY; - /* Configure the tamper trigger */ - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)sTamper->Trigger |\ - (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\ - (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); + /* Copy control register into temporary variable */ + tmpreg = hrtc->Instance->TAFCR; - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\ - (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\ - (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPINSEL); + /* Enable selected tamper */ + tmpreg |= (sTamper->Tamper); - hrtc->Instance->TAFCR |= tmpreg; - - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE; - - if(sTamper->Tamper == RTC_TAMPER_1) + /* Configure the tamper trigger bit (this bit is just on the right of the + tamper enable bit, hence the one-time right shift before updating it) */ + if (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE) { - /* Clear RTC Tamper 1 flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + /* Set the tamper trigger bit (case of falling edge or high level) */ + tmpreg |= (uint32_t)(sTamper->Tamper << 1U); } else { - /* Clear RTC Tamper 2 flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + /* Clear the tamper trigger bit (case of rising edge or low level) */ + tmpreg &= (uint32_t)~(sTamper->Tamper << 1U); } + /* Clear remaining fields before setting them */ + tmpreg &= ~(RTC_TAMPERFILTER_MASK | \ + RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \ + RTC_TAMPERPRECHARGEDURATION_MASK | \ + RTC_TAMPER_PULLUP_MASK | \ + RTC_TAFCR_TAMP1INSEL | \ + RTC_TIMESTAMPONTAMPERDETECTION_MASK); + + /* Set remaining parameters of desired configuration into temporary variable */ + tmpreg |= ((uint32_t)sTamper->Filter | \ + (uint32_t)sTamper->SamplingFrequency | \ + (uint32_t)sTamper->PrechargeDuration | \ + (uint32_t)sTamper->TamperPullUp | \ + (uint32_t)sTamper->PinSelection | \ + (uint32_t)sTamper->TimeStampOnTamperDetection); + + /* Enable global tamper interrupt */ + tmpreg |= (uint32_t)RTC_TAFCR_TAMPIE; + + /* Copy desired configuration into configuration register */ + hrtc->Instance->TAFCR = tmpreg; + /* RTC Tamper Interrupt Configuration: EXTI configuration */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); hrtc->State = HAL_RTC_STATE_READY; @@ -465,10 +567,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /** * @brief Deactivates Tamper. + * @note The tamper global interrupt bit will remain unchanged. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Tamper Selected tamper pin. - * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_1: Tamper 1 + * @arg RTC_TAMPER_2: Tamper 2 + * @note RTC_TAMPER_2 is not applicable to all devices. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) @@ -492,36 +598,36 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T } /** - * @brief This function handles TimeStamp interrupt request. + * @brief Handles Timestamp and Tamper interrupt request. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) { - /* Get the TimeStamp interrupt source enable status */ - if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != (uint32_t)RESET) + /* Get the Timestamp interrupt source enable status */ + if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U) { - /* Get the pending status of the TIMESTAMP Interrupt */ - if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != (uint32_t)RESET) + /* Get the pending status of the Timestamp Interrupt */ + if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != 0U) { - /* TIMESTAMP callback */ + /* Timestamp callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->TimeStampEventCallback(hrtc); #else HAL_RTCEx_TimeStampEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* Clear the TIMESTAMP interrupt pending bit */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF); + /* Clear the Timestamp interrupt pending bit */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); } } - /* Get the Tamper1 interrupt source enable status */ - if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != (uint32_t)RESET) + /* Get the Tamper 1 interrupt source enable status */ + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U) { - /* Get the pending status of the Tamper1 Interrupt */ - if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET) + /* Get the pending status of the Tamper 1 Interrupt */ + if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U) { /* Tamper callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -531,15 +637,16 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); } } - /* Get the Tamper2 interrupt source enable status */ - if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != (uint32_t)RESET) +#if defined(RTC_TAMPER2_SUPPORT) + /* Get the Tamper 2 interrupt source enable status */ + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U) { - /* Get the pending status of the Tamper2 Interrupt */ - if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != (uint32_t)RESET) + /* Get the pending status of the Tamper 2 Interrupt */ + if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U) { /* Tamper callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -552,8 +659,9 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); } } +#endif /* RTC_TAMPER2_SUPPORT */ - /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ + /* Clear the EXTI's Flag for RTC Timestamp and Tamper */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); /* Change RTC state */ @@ -561,7 +669,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) } /** - * @brief TimeStamp callback. + * @brief Timestamp callback. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None @@ -570,8 +678,9 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_TimeStampEventCallback could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file */ } @@ -585,11 +694,13 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_Tamper1EventCallback could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file */ } +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Tamper 2 callback. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains @@ -600,13 +711,15 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_Tamper2EventCallback could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file */ } +#endif /* RTC_TAMPER2_SUPPORT */ /** - * @brief This function handles TimeStamp polling request. + * @brief Handles Timestamp polling request. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Timeout Timeout duration @@ -619,27 +732,27 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /* Get tick */ tickstart = HAL_GetTick(); - while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) + while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U) { - if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + + if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U) { - /* Clear the TIMESTAMP Overrun Flag */ + /* Clear the Timestamp Overrun Flag */ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - /* Change TIMESTAMP state */ + /* Change Timestamp state */ hrtc->State = HAL_RTC_STATE_ERROR; return HAL_ERROR; } - - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } } /* Change RTC state */ @@ -649,7 +762,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 } /** - * @brief This function handles Tamper1 Polling. + * @brief Handles Tamper 1 Polling. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Timeout Timeout duration @@ -663,11 +776,11 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ tickstart = HAL_GetTick(); /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET) + while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == 0U) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -676,7 +789,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ } /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -684,8 +797,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ return HAL_OK; } +#if defined(RTC_TAMPER2_SUPPORT) /** - * @brief This function handles Tamper2 Polling. + * @brief Handles Tamper 2 Polling. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Timeout Timeout duration @@ -699,11 +813,11 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ tickstart = HAL_GetTick(); /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET) + while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == 0U) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -712,38 +826,39 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ } /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F); + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; return HAL_OK; } +#endif /* RTC_TAMPER2_SUPPORT */ /** * @} */ -/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions - * @brief RTC Wake-up functions - * +/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wakeup functions + * @brief RTC Wakeup functions + * @verbatim =============================================================================== - ##### RTC Wake-up functions ##### + ##### RTC Wakeup functions ##### =============================================================================== - [..] This section provides functions allowing to configure Wake-up feature + [..] This section provides functions allowing to configure Wakeup feature @endverbatim * @{ */ /** - * @brief Sets wake up timer. + * @brief Sets wakeup timer. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param WakeUpCounter Wake up counter - * @param WakeUpClock Wake up clock + * @param WakeUpCounter Wakeup counter + * @param WakeUpClock Wakeup clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) @@ -762,15 +877,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) + /* Check RTC WUTWF flag is reset only when wakeup timer enabled*/ + if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) { tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) + /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */ + while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -785,14 +900,19 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak } } + /* Disable the Wakeup timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + /* Clear the Wakeup flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + + /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ + while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -806,16 +926,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak } } - /* Clear the Wake-up Timer clock source bits in CR register */ + /* Clear the Wakeup Timer clock source bits in CR register */ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; /* Configure the clock source */ hrtc->Instance->CR |= (uint32_t)WakeUpClock; - /* Configure the Wake-up Timer counter */ + /* Configure the Wakeup Timer counter */ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - /* Enable the Wake-up Timer */ + /* Enable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); /* Enable the write protection for RTC registers */ @@ -830,16 +950,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak } /** - * @brief Sets wake up timer with interrupt + * @brief Sets wakeup timer with interrupt. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param WakeUpCounter Wake up counter - * @param WakeUpClock Wake up clock + * @param WakeUpCounter Wakeup counter + * @param WakeUpClock Wakeup clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { - __IO uint32_t count; + __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); @@ -853,14 +973,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Check RTC WUTWF flag is reset only when wake up timer enabled */ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) + /* Check RTC WUTWF flag is reset only when wakeup timer enabled */ + if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) { - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */ do { - if(count-- == 0U) + if (count-- == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -872,17 +991,22 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t return HAL_TIMEOUT; } - } - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET); + } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U); } + /* Disable the Wakeup timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + /* Clear the Wakeup flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + + /* Reload the counter */ + count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + + /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ do { - if(count-- == 0U) + if (count-- == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -894,30 +1018,25 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t return HAL_TIMEOUT; } - } - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET); + } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U); - /* Configure the Wake-up Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Clear the Wake-up Timer clock source bits in CR register */ + /* Clear the Wakeup Timer clock source bits in CR register */ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; /* Configure the clock source */ hrtc->Instance->CR |= (uint32_t)WakeUpClock; - /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - - EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; + /* Configure the Wakeup Timer counter */ + hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - /* Clear RTC Wake Up timer Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + /* RTC wakeup timer Interrupt Configuration: EXTI configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - /* Configure the Interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); + /* Configure the interrupt in the RTC_CR register */ + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT); - /* Enable the Wake-up Timer */ + /* Enable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); /* Enable the write protection for RTC registers */ @@ -932,12 +1051,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t } /** - * @brief Deactivates wake up timer counter. + * @brief Deactivates wakeup timer counter. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) { uint32_t tickstart = 0U; @@ -949,19 +1068,19 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Disable the Wake-up Timer */ + /* Disable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ + while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -987,7 +1106,7 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) } /** - * @brief Gets wake up timer counter. + * @brief Gets wakeup timer counter. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval Counter value @@ -999,8 +1118,8 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) } /** - * @brief This function handles Wake Up Timer interrupt request. - * @note Unlike alarm interrupt line (shared by AlarmA and AlarmB) and tamper + * @brief Handles Wakeup Timer interrupt request. + * @note Unlike alarm interrupt line (shared by Alarms A and B) or tamper * interrupt line (shared by timestamp and tampers) wakeup timer * interrupt line is exclusive to the wakeup timer. * There is no need in this case to check on the interrupt enable @@ -1011,17 +1130,17 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) { - /* Get the pending status of the WAKEUPTIMER Interrupt */ - if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != (uint32_t)RESET) + /* Get the pending status of the Wakeup timer Interrupt */ + if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U) { - /* WAKEUPTIMER callback */ + /* Wakeup timer callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->WakeUpTimerEventCallback(hrtc); #else HAL_RTCEx_WakeUpTimerEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* Clear the WAKEUPTIMER interrupt pending bit */ + /* Clear the Wakeup timer interrupt pending bit */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); } @@ -1033,7 +1152,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) } /** - * @brief Wake Up Timer callback. + * @brief Wakeup Timer callback. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None @@ -1042,13 +1161,14 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file */ } /** - * @brief This function handles Wake Up Timer Polling. + * @brief Handles Wakeup Timer Polling. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Timeout Timeout duration @@ -1061,20 +1181,19 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /* Get tick */ tickstart = HAL_GetTick(); - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) + while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; } } } - /* Clear the WAKEUPTIMER Flag */ + /* Clear the Wakeup timer Flag */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); /* Change RTC state */ @@ -1087,13 +1206,12 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin * @} */ - -/** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions - * @brief Extension Peripheral Control functions - * +/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * @verbatim =============================================================================== - ##### Extension Peripheral Control functions ##### + ##### Extended Peripheral Control functions ##### =============================================================================== [..] This subsection provides functions allowing to @@ -1119,8 +1237,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param BackupRegister RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. + * This parameter can be: RTC_BKP_DRx (where x can be from 0 to 19) + * to specify the register. * @param Data Data to be written in the specified RTC Backup data register. * @retval None */ @@ -1131,7 +1249,7 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); - tmp = (uint32_t)&(hrtc->Instance->BKP0R); + tmp = (uint32_t) & (hrtc->Instance->BKP0R); tmp += (BackupRegister * 4U); /* Write the specified register */ @@ -1143,8 +1261,8 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param BackupRegister RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. + * This parameter can be: RTC_BKP_DRx (where x can be from 0 to 19) + * to specify the register. * @retval Read value */ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) @@ -1154,7 +1272,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); - tmp = (uint32_t)&(hrtc->Instance->BKP0R); + tmp = (uint32_t) & (hrtc->Instance->BKP0R); tmp += (BackupRegister * 4U); /* Read the specified register */ @@ -1166,7 +1284,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param CalibSign Specifies the sign of the coarse calibration value. - * This parameter can be one of the following values : + * This parameter can be one of the following values: * @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive * @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative * @param Value value of coarse calibration expressed in ppm (coded on 5 bits). @@ -1178,8 +1296,10 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) * sign with a 4-ppm step. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t CalibSign, uint32_t Value) +HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value) { + HAL_StatusTypeDef status; + /* Check the parameters */ assert_param(IS_RTC_CALIB_SIGN(CalibSign)); assert_param(IS_RTC_CALIB_VALUE(Value)); @@ -1192,42 +1312,33 @@ HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t Cal /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - return HAL_ERROR; - } - else + if (status == HAL_OK) { /* Enable the Coarse Calibration */ __HAL_RTC_COARSE_CALIB_ENABLE(hrtc); /* Set the coarse calibration value */ - hrtc->Instance->CALIBR = (uint32_t)(CalibSign|Value); + hrtc->Instance->CALIBR = (uint32_t)(CalibSign | Value); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + status = RTC_ExitInitMode(hrtc); + } + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change state */ - hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } /** @@ -1236,8 +1347,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t Cal * the configuration information for RTC. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc) { + HAL_StatusTypeDef status; + /* Process Locked */ __HAL_LOCK(hrtc); @@ -1246,39 +1359,30 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + if (status == HAL_OK) { - /* Enable the Coarse Calibration */ + /* Disable the Coarse Calibration */ __HAL_RTC_COARSE_CALIB_DISABLE(hrtc); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + status = RTC_ExitInitMode(hrtc); + } + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change state */ - hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } /** @@ -1286,7 +1390,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param SmoothCalibPeriod Select the Smooth Calibration Period. - * This parameter can be can be one of the following values : + * This parameter can be can be one of the following values: * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. @@ -1294,21 +1398,21 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) * This parameter can be one of the following values: * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmouthCalibMinusPulsesValue Select the value of CALM[80] bits. + * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits. * This parameter can be one any value from 0 to 0x000001FF. * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field - * SmouthCalibMinusPulsesValue must be equal to 0. + * SmoothCalibMinusPulsesValue must be equal to 0. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) { uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -1319,15 +1423,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* check if a calibration is pending*/ - if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) { - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); /* check if a calibration is pending*/ - while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1344,7 +1448,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo } /* Configure the Smooth calibration settings */ - hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue); + hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | \ + (uint32_t)SmoothCalibPlusPulses | \ + (uint32_t)SmoothCalibMinusPulsesValue); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1364,14 +1470,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param ShiftAdd1S Select to add or not 1 second to the time calendar. - * This parameter can be one of the following values : + * This parameter can be one of the following values: * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. * @arg RTC_SHIFTADD1S_RESET: No effect. * @param ShiftSubFS Select the number of Second Fractions to substitute. * This parameter can be one any value from 0 to 0x7FFF. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) { uint32_t tickstart = 0U; @@ -1390,59 +1496,59 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh /* Get tick */ tickstart = HAL_GetTick(); - /* Wait until the shift is completed*/ - while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) + /* Wait until the shift is completed */ + while ((hrtc->Instance->ISR & RTC_ISR_SHPF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_TIMEOUT; + hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } + } - /* Check if the reference clock detection is disabled */ - if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); + /* Check if the reference clock detection is disabled */ + if ((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U) + { + /* Configure the Shift settings */ + hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_ERROR; + hrtc->State = HAL_RTC_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_ERROR; - } + return HAL_ERROR; } } - else - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + else + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1460,13 +1566,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param CalibOutput Select the Calibration output Selection . + * @param CalibOutput Select the Calibration output Selection. * This parameter can be one of the following values: * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput) { /* Check the parameters */ assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); @@ -1505,7 +1611,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32 * the configuration information for RTC. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc) { /* Process Locked */ __HAL_LOCK(hrtc); @@ -1535,8 +1641,10 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) * the configuration information for RTC. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc) { + HAL_StatusTypeDef status; + /* Process Locked */ __HAL_LOCK(hrtc); @@ -1545,38 +1653,30 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + if (status == HAL_OK) { + /* Enable the reference clock detection */ __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + status = RTC_ExitInitMode(hrtc); + } + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } /** @@ -1585,8 +1685,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) * the configuration information for RTC. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc) { + HAL_StatusTypeDef status; + /* Process Locked */ __HAL_LOCK(hrtc); @@ -1595,38 +1697,30 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - return HAL_ERROR; - } - else + if (status == HAL_OK) { + /* Disable the reference clock detection */ __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + status = RTC_ExitInitMode(hrtc); + } + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } /** @@ -1637,7 +1731,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) * directly from the Calendar counter. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) { /* Process Locked */ __HAL_LOCK(hrtc); @@ -1670,7 +1764,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) * directly from the Calendar counter. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) { /* Process Locked */ __HAL_LOCK(hrtc); @@ -1699,9 +1793,9 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) * @} */ - /** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions - * @brief Extended features functions - * +/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions + * @brief Extended features functions + * @verbatim =============================================================================== ##### Extended features functions ##### @@ -1724,13 +1818,14 @@ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_AlarmBEventCallback could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file */ } /** - * @brief This function handles AlarmB Polling request. + * @brief Handles Alarm B Polling request. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Timeout Timeout duration @@ -1743,11 +1838,12 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /* Get tick */ tickstart = HAL_GetTick(); - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) + /* Wait till RTC ALRBF flag is set and if timeout is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == 0U) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1755,7 +1851,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t } } - /* Clear the Alarm Flag */ + /* Clear the Alarm flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); /* Change RTC state */ @@ -1780,5 +1876,3 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c index 7d157ccbca..19e3748285 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -199,18 +210,6 @@ and weak (surcharged) callbacks are used. @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -2553,4 +2552,3 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c index 120a277747..78a73f8089 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c @@ -7,6 +7,17 @@ * functionalities of SAI extension peripheral: * + Extension features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### SAI peripheral extension features ##### @@ -23,17 +34,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -308,4 +308,3 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c index 994ba0c57f..32e54ea152 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -242,17 +253,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -430,6 +430,9 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /* Enable SDIO Clock */ __HAL_SD_ENABLE(hsd); + /* Required power up waiting time before starting the SD initialization sequence */ + HAL_Delay(2); + /* Identify card operating voltage */ errorstate = SD_PowerON(hsd); if(errorstate != HAL_SD_ERROR_NONE) @@ -3272,5 +3275,3 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd) */ #endif /* SDIO */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c index 2489e7e416..31633a2b4e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c @@ -6,6 +6,17 @@ * This file provides a generic firmware to drive SDRAM memories mounted * as external device. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -18,7 +29,7 @@ with SDRAM memories: (#) Declare a SDRAM_HandleTypeDef handle structure, for example: - SDRAM_HandleTypeDef hdsram + SDRAM_HandleTypeDef hsdram (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed values of the structure member. @@ -63,25 +74,25 @@ The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SDRAM_RegisterCallback() to register a user callback, + Use Functions HAL_SDRAM_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : SDRAM MspInit. (+) MspDeInitCallback : SDRAM MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_SDRAM_UnRegisterCallback() to reset a callback to the default + Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : SDRAM MspInit. (+) MspDeInitCallback : SDRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET + By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SDRAM_Init - and @ref HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SDRAM_Init and @ref HAL_SDRAM_DeInit + reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init + and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -89,8 +100,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SDRAM_RegisterCallback before calling @ref HAL_SDRAM_DeInit - or @ref HAL_SDRAM_Init function. + using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit + or HAL_SDRAM_Init function. When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -98,39 +109,33 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" +#if defined(FMC_Bank5_6) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ +#ifdef HAL_SDRAM_MODULE_ENABLED + /** @defgroup SDRAM SDRAM * @brief SDRAM driver modules * @{ */ -#ifdef HAL_SDRAM_MODULE_ENABLED -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma); +static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma); +static void SDRAM_DMAError(DMA_HandleTypeDef *hdma); + /* Exported functions --------------------------------------------------------*/ /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions * @{ @@ -161,17 +166,17 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) { /* Check the SDRAM handle parameter */ - if(hsdram == NULL) + if (hsdram == NULL) { return HAL_ERROR; } - if(hsdram->State == HAL_SDRAM_STATE_RESET) + if (hsdram->State == HAL_SDRAM_STATE_RESET) { /* Allocate lock resource and initialize it */ hsdram->Lock = HAL_UNLOCKED; #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - if(hsdram->MspInitCallback == NULL) + if (hsdram->MspInitCallback == NULL) { hsdram->MspInitCallback = HAL_SDRAM_MspInit; } @@ -184,18 +189,17 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy #else /* Initialize the low level hardware (MSP) */ HAL_SDRAM_MspInit(hsdram); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } /* Initialize the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_BUSY; /* Initialize SDRAM control Interface */ - FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); + (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); /* Initialize SDRAM timing Interface */ - FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); - + (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); /* Update the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_READY; @@ -211,7 +215,7 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) { #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - if(hsdram->MspDeInitCallback == NULL) + if (hsdram->MspDeInitCallback == NULL) { hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; } @@ -221,10 +225,10 @@ HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) #else /* Initialize the low level hardware (MSP) */ HAL_SDRAM_MspDeInit(hsdram); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /* Configure the SDRAM registers with their reset values */ - FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); + (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); /* Reset the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_RESET; @@ -245,6 +249,7 @@ __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsdram); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_SDRAM_MspInit could be implemented in the user file */ @@ -260,6 +265,7 @@ __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsdram); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_SDRAM_MspDeInit could be implemented in the user file */ @@ -270,18 +276,18 @@ __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval HAL status -*/ + */ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) { /* Check SDRAM interrupt Rising edge flag */ - if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) + if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) { /* SDRAM refresh error interrupt callback */ #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) hsdram->RefreshErrorCallback(hsdram); #else HAL_SDRAM_RefreshErrorCallback(hsdram); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /* Clear SDRAM refresh error interrupt pending bit */ __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); @@ -298,6 +304,7 @@ __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsdram); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file */ @@ -313,6 +320,7 @@ __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file */ @@ -327,10 +335,12 @@ __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file */ } + /** * @} */ @@ -358,34 +368,46 @@ __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize) { + uint32_t size; __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsdram); + uint8_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (state == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { - return HAL_ERROR; - } + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from source */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *(__IO uint8_t *)pSdramAddress; + pdestbuff++; + pSdramAddress++; + } - /* Read data from source */ - for(; BufferSize != 0U; BufferSize--) + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else { - *pDstBuffer = *(__IO uint8_t *)pSdramAddress; - pDstBuffer++; - pSdramAddress++; + return HAL_ERROR; } - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - return HAL_OK; } @@ -398,37 +420,45 @@ HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddr * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize) { + uint32_t size; __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; - uint32_t tmp = 0U; - - /* Process Locked */ - __HAL_LOCK(hsdram); + uint8_t *psrcbuff = pSrcBuffer; /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + else if (hsdram->State == HAL_SDRAM_STATE_READY) { - return HAL_ERROR; - } + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *(__IO uint8_t *)pSdramAddress = *psrcbuff; + psrcbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else { - *(__IO uint8_t *)pSdramAddress = *pSrcBuffer; - pSrcBuffer++; - pSdramAddress++; + return HAL_ERROR; } - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - return HAL_OK; } @@ -441,34 +471,54 @@ HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize) { - __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsdram); + uint32_t size; + __IO uint32_t *pSdramAddress = pAddress; + uint16_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (state == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { - return HAL_ERROR; - } + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from memory */ + for (size = BufferSize; size >= 2U ; size -= 2U) + { + *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); + pdestbuff++; + *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U); + pdestbuff++; + pSdramAddress++; + } + + /* Read last 16-bits if size is not 32-bits multiple */ + if ((BufferSize % 2U) != 0U) + { + *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); + } - /* Read data from source */ - for(; BufferSize != 0U; BufferSize--) + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else { - *pDstBuffer = *(__IO uint16_t *)pSdramAddress; - pDstBuffer++; - pSdramAddress++; + return HAL_ERROR; } - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - return HAL_OK; } @@ -481,37 +531,53 @@ HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize) { - __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; - uint32_t tmp = 0U; - - /* Process Locked */ - __HAL_LOCK(hsdram); + uint32_t size; + __IO uint32_t *psdramaddress = pAddress; + uint16_t *psrcbuff = pSrcBuffer; /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + else if (hsdram->State == HAL_SDRAM_STATE_READY) { - return HAL_ERROR; - } + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size >= 2U ; size -= 2U) + { + *psdramaddress = (uint32_t)(*psrcbuff); + psrcbuff++; + *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U); + psrcbuff++; + psdramaddress++; + } + + /* Write last 16-bits if size is not 32-bits multiple */ + if ((BufferSize % 2U) != 0U) + { + *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U); + } - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else { - *(__IO uint16_t *)pSdramAddress = *pSrcBuffer; - pSrcBuffer++; - pSdramAddress++; + return HAL_ERROR; } - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - return HAL_OK; } @@ -524,34 +590,46 @@ HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { + uint32_t size; __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsdram); + uint32_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (state == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { - return HAL_ERROR; - } + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; - /* Read data from source */ - for(; BufferSize != 0U; BufferSize--) + /* Read data from source */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *(__IO uint32_t *)pSdramAddress; + pdestbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else { - *pDstBuffer = *(__IO uint32_t *)pSdramAddress; - pDstBuffer++; - pSdramAddress++; + return HAL_ERROR; } - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - return HAL_OK; } @@ -564,37 +642,45 @@ HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { - __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; - uint32_t tmp = 0U; - - /* Process Locked */ - __HAL_LOCK(hsdram); + uint32_t size; + __IO uint32_t *pSdramAddress = pAddress; + uint32_t *psrcbuff = pSrcBuffer; /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + else if (hsdram->State == HAL_SDRAM_STATE_READY) { - return HAL_ERROR; - } + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *pSdramAddress = *psrcbuff; + psrcbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else { - *(__IO uint32_t *)pSdramAddress = *pSrcBuffer; - pSrcBuffer++; - pSdramAddress++; + return HAL_ERROR; } - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - return HAL_OK; } @@ -607,36 +693,48 @@ HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { - uint32_t tmp = 0U; - - /* Process Locked */ - __HAL_LOCK(hsdram); + HAL_StatusTypeDef status; + HAL_SDRAM_StateTypeDef state = hsdram->State; /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) + if (state == HAL_SDRAM_STATE_BUSY) { - return HAL_BUSY; + status = HAL_BUSY; } - else if(tmp == HAL_SDRAM_STATE_PRECHARGED) + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { - return HAL_ERROR; - } + /* Process Locked */ + __HAL_LOCK(hsdram); - /* Configure DMA user callbacks */ - hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; - hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); + /* Configure DMA user callbacks */ + if (state == HAL_SDRAM_STATE_READY) + { + hsdram->hdma->XferCpltCallback = SDRAM_DMACplt; + } + else + { + hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt; + } + hsdram->hdma->XferErrorCallback = SDRAM_DMAError; - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); - return HAL_OK; + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + status = HAL_ERROR; + } + + return status; } /** @@ -648,36 +746,40 @@ HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { - uint32_t tmp = 0U; - - /* Process Locked */ - __HAL_LOCK(hsdram); + HAL_StatusTypeDef status; /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { - return HAL_BUSY; + status = HAL_BUSY; } - else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + else if (hsdram->State == HAL_SDRAM_STATE_READY) { - return HAL_ERROR; - } + /* Process Locked */ + __HAL_LOCK(hsdram); - /* Configure DMA user callbacks */ - hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; - hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); + /* Configure DMA user callbacks */ + hsdram->hdma->XferCpltCallback = SDRAM_DMACplt; + hsdram->hdma->XferErrorCallback = SDRAM_DMAError; - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); - return HAL_OK; + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + status = HAL_ERROR; + } + + return status; } #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) @@ -693,12 +795,13 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SDRAM_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -707,39 +810,39 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_S __HAL_LOCK(hsdram); state = hsdram->State; - if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { switch (CallbackId) { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = pCallback; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = pCallback; - break; - case HAL_SDRAM_REFRESH_ERR_CB_ID : - hsdram->RefreshErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hsdram->State == HAL_SDRAM_STATE_RESET) + else if (hsdram->State == HAL_SDRAM_STATE_RESET) { switch (CallbackId) { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = pCallback; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -766,7 +869,7 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_S * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID * @retval status */ -HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; HAL_SDRAM_StateTypeDef state; @@ -775,45 +878,45 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL __HAL_LOCK(hsdram); state = hsdram->State; - if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { switch (CallbackId) { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = HAL_SDRAM_MspInit; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; - break; - case HAL_SDRAM_REFRESH_ERR_CB_ID : - hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; - break; - case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : - hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; - break; - case HAL_SDRAM_DMA_XFER_ERR_CB_ID : - hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; + break; + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hsdram->State == HAL_SDRAM_STATE_RESET) + else if (hsdram->State == HAL_SDRAM_STATE_RESET) { switch (CallbackId) { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = HAL_SDRAM_MspInit; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -838,12 +941,13 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_DmaCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SDRAM_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -852,20 +956,20 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL __HAL_LOCK(hsdram); state = hsdram->State; - if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { switch (CallbackId) { - case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : - hsdram->DmaXferCpltCallback = pCallback; - break; - case HAL_SDRAM_DMA_XFER_ERR_CB_ID : - hsdram->DmaXferErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = pCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -878,15 +982,15 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL __HAL_UNLOCK(hsdram); return status; } -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup SDRAM_Exported_Functions_Group3 Control functions - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### SDRAM Control functions ##### @@ -908,19 +1012,25 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) { /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Enable write protection */ - FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); + /* Enable write protection */ + (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -933,20 +1043,28 @@ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) */ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) { + HAL_SDRAM_StateTypeDef state = hsdram->State; + /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (state == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } + else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Disable write protection */ - FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); + /* Disable write protection */ + (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_READY; + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -959,28 +1077,37 @@ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, + uint32_t Timeout) { + HAL_SDRAM_StateTypeDef state = hsdram->State; + /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (state == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED)) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Send SDRAM command */ - FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); + /* Send SDRAM command */ + (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); - /* Update the SDRAM controller state */ - if(Command->CommandMode == FMC_SDRAM_CMD_PALL) - { - hsdram->State = HAL_SDRAM_STATE_PRECHARGED; + /* Update the SDRAM controller state state */ + if (Command->CommandMode == FMC_SDRAM_CMD_PALL) + { + hsdram->State = HAL_SDRAM_STATE_PRECHARGED; + } + else + { + hsdram->State = HAL_SDRAM_STATE_READY; + } } else { - hsdram->State = HAL_SDRAM_STATE_READY; + return HAL_ERROR; } return HAL_OK; @@ -996,19 +1123,25 @@ HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_C HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) { /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Program the refresh rate */ - FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); + /* Program the refresh rate */ + (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate); - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_READY; + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -1023,19 +1156,25 @@ HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) { /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Set the Auto-Refresh number */ - FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber); + /* Set the Auto-Refresh number */ + (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber); - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_READY; + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -1049,7 +1188,7 @@ HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, ui uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) { /* Return the SDRAM memory current mode */ - return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); + return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); } /** @@ -1057,8 +1196,8 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) */ /** @defgroup SDRAM_Exported_Functions_Group4 State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### SDRAM State functions ##### @@ -1089,14 +1228,81 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ -#endif /* HAL_SDRAM_MODULE_ENABLED */ + +/** + * @brief DMA SDRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma) +{ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferCpltCallback(hdma); +#else + HAL_SDRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma) +{ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferCpltCallback(hdma); +#else + HAL_SDRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SDRAM error callback. + * @param hdma : DMA handle + * @retval None + */ +static void SDRAM_DMAError(DMA_HandleTypeDef *hdma) +{ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_ERROR; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferErrorCallback(hdma); +#else + HAL_SDRAM_DMA_XferErrorCallback(hdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + /** * @} */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ + /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* FMC_Bank5_6 */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c index 6746744c03..e721d80cd6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -159,17 +170,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -756,9 +756,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint8_t *tmp = pData; + const uint8_t *tmp = pData; uint32_t tickstart = 0U; if(hsc->gState == HAL_SMARTCARD_STATE_READY) @@ -876,7 +876,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if(hsc->gState == HAL_SMARTCARD_STATE_READY) @@ -969,9 +969,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size) { - uint32_t *tmp; + const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if(hsc->gState == HAL_SMARTCARD_STATE_READY) @@ -1001,8 +1001,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 hsc->hdmatx->XferAbortCallback = NULL; /* Enable the SMARTCARD transmit DMA stream */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size); + tmp = (const uint32_t*)&pData; + HAL_DMA_Start_IT(hsc->hdmatx, *(const uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size); /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC); @@ -1921,11 +1921,12 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) } /** - * @brief This function handles SMARTCARD Communication Timeout. + * @brief This function handles SMARTCARD Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @param Flag Specifies the SMARTCARD flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status @@ -2360,4 +2361,3 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c index 09df379bc9..25c72fda52 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c @@ -10,6 +10,17 @@ * + IO operation functions * + Peripheral State, Mode and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -152,18 +163,6 @@ are set to the corresponding weak functions. @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -2783,4 +2782,3 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c index 50fac5e027..da7c302189 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c @@ -8,6 +8,18 @@ * + Data transfers functions * + DMA transfers management * + Interrupts and flags management + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -142,18 +154,6 @@ are set to the corresponding weak functions. @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -188,7 +188,8 @@ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma); static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma); static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif); static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif); -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart); +static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, + FlagStatus Status, uint32_t Timeout, uint32_t tickstart); /** * @} */ @@ -238,7 +239,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) uint32_t tmpreg; /* Check the SPDIFRX handle allocation */ - if(hspdif == NULL) + if (hspdif == NULL) { return HAL_ERROR; } @@ -256,7 +257,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask)); #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - if(hspdif->State == HAL_SPDIFRX_STATE_RESET) + if (hspdif->State == HAL_SPDIFRX_STATE_RESET) { /* Allocate lock resource and initialize it */ hspdif->Lock = HAL_UNLOCKED; @@ -267,7 +268,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback; /* Legacy weak CxCpltCallback */ hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback; /* Legacy weak ErrorCallback */ - if(hspdif->MspInitCallback == NULL) + if (hspdif->MspInitCallback == NULL) { hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit */ } @@ -276,7 +277,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) hspdif->MspInitCallback(hspdif); } #else - if(hspdif->State == HAL_SPDIFRX_STATE_RESET) + if (hspdif->State == HAL_SPDIFRX_STATE_RESET) { /* Allocate lock resource and initialize it */ hspdif->Lock = HAL_UNLOCKED; @@ -310,7 +311,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) hspdif->Init.ChannelStatusMask | hspdif->Init.ValidityBitMask | hspdif->Init.ParityErrorMask - ); + ); hspdif->Instance->CR = tmpreg; @@ -331,7 +332,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) { /* Check the SPDIFRX handle allocation */ - if(hspdif == NULL) + if (hspdif == NULL) { return HAL_ERROR; } @@ -345,7 +346,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) __HAL_SPDIFRX_IDLE(hspdif); #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - if(hspdif->MspDeInitCallback == NULL) + if (hspdif->MspDeInitCallback == NULL) { hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspDeInit */ } @@ -415,11 +416,12 @@ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, + pSPDIFRX_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; @@ -428,7 +430,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA /* Process locked */ __HAL_LOCK(hspdif); - if(HAL_SPDIFRX_STATE_READY == hspdif->State) + if (HAL_SPDIFRX_STATE_READY == hspdif->State) { switch (CallbackID) { @@ -468,7 +470,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA break; } } - else if(HAL_SPDIFRX_STATE_RESET == hspdif->State) + else if (HAL_SPDIFRX_STATE_RESET == hspdif->State) { switch (CallbackID) { @@ -483,7 +485,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA default : /* Update the error code */ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; - /* Return error status */ + /* Return error status */ status = HAL_ERROR; break; } @@ -503,7 +505,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA /** * @brief Unregister a SPDIFRX Callback - * SPDIFRX callabck is redirected to the weak predefined callback + * SPDIFRX callback is redirected to the weak predefined callback * @param hspdif SPDIFRX handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -516,14 +518,15 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA * @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ -HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, + HAL_SPDIFRX_CallbackIDTypeDef CallbackID) { -HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hspdif); - if(HAL_SPDIFRX_STATE_READY == hspdif->State) + if (HAL_SPDIFRX_STATE_READY == hspdif->State) { switch (CallbackID) { @@ -550,12 +553,12 @@ HAL_StatusTypeDef status = HAL_OK; default : /* Update the error code */ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; - /* Return error status */ + /* Return error status */ status = HAL_ERROR; break; } } - else if(HAL_SPDIFRX_STATE_RESET == hspdif->State) + else if (HAL_SPDIFRX_STATE_RESET == hspdif->State) { switch (CallbackID) { @@ -601,7 +604,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF uint32_t tmpreg; /* Check the SPDIFRX handle allocation */ - if(hspdif == NULL) + if (hspdif == NULL) { return HAL_ERROR; } @@ -617,9 +620,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF /* Reset the old SPDIFRX CR configuration */ tmpreg = hspdif->Instance->CR; - if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) && - (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) || - ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) + if (((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) && + (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) || + ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) { return HAL_ERROR; } @@ -683,8 +686,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF (++) HAL_SPDIFRX_CxCpltCallback() @endverbatim -* @{ -*/ + * @{ + */ /** * @brief Receives an amount of data (Data Flow) in blocking mode. @@ -695,18 +698,19 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint16_t sizeCounter = Size; uint32_t *pTmpBuf = pData; - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(hspdif->State == HAL_SPDIFRX_STATE_READY) + if (hspdif->State == HAL_SPDIFRX_STATE_READY) { /* Process Locked */ __HAL_LOCK(hspdif); @@ -720,7 +724,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin tickstart = HAL_GetTick(); /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -729,13 +733,13 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin __HAL_SPDIFRX_RCV(hspdif); /* Receive data flow */ - while(sizeCounter > 0U) + while (sizeCounter > 0U) { /* Get tick */ tickstart = HAL_GetTick(); /* Wait until RXNE flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -768,18 +772,19 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint16_t sizeCounter = Size; uint32_t *pTmpBuf = pData; - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(hspdif->State == HAL_SPDIFRX_STATE_READY) + if (hspdif->State == HAL_SPDIFRX_STATE_READY) { /* Process Locked */ __HAL_LOCK(hspdif); @@ -793,7 +798,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, tickstart = HAL_GetTick(); /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -802,13 +807,13 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, __HAL_SPDIFRX_RCV(hspdif); /* Receive control flow */ - while(sizeCounter > 0U) + while (sizeCounter > 0U) { /* Get tick */ tickstart = HAL_GetTick(); /* Wait until CSRNE flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK) + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -845,9 +850,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -873,7 +878,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, /* Enable the SPDIFRX RXNE interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE); - if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); @@ -892,7 +897,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -930,9 +935,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -958,7 +963,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi /* Enable the SPDIFRX CSRNE interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); @@ -977,7 +982,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -1015,12 +1020,12 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) { /* Process Locked */ __HAL_LOCK(hspdif); @@ -1042,7 +1047,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError; /* Enable the DMA request */ - if(HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK) { /* Set SPDIFRX error */ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; @@ -1059,7 +1064,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/ hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN; - if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); @@ -1078,7 +1083,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -1116,12 +1121,12 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) { hspdif->pCsBuffPtr = pData; hspdif->CsXferSize = Size; @@ -1143,7 +1148,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError; /* Enable the DMA request */ - if(HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK) { /* Set SPDIFRX error */ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; @@ -1160,7 +1165,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/ hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN; - if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); @@ -1179,7 +1184,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -1244,21 +1249,21 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) uint32_t itSource = hspdif->Instance->IMR; /* SPDIFRX in mode Data Flow Reception */ - if(((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource & SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE)) + if (((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource & SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE); SPDIFRX_ReceiveDataFlow_IT(hspdif); } /* SPDIFRX in mode Control Flow Reception */ - if(((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource & SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE)) + if (((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource & SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE); SPDIFRX_ReceiveControlFlow_IT(hspdif); } /* SPDIFRX Overrun error interrupt occurred */ - if(((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource & SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE)) + if (((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource & SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_OVRIE); @@ -1270,7 +1275,7 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) } /* SPDIFRX Parity error interrupt occurred */ - if(((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource & SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE)) + if (((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource & SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_PERRIE); @@ -1381,7 +1386,7 @@ and the data flow. * @param hspdif SPDIFRX handle * @retval HAL state */ -HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif) +HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif) { return hspdif->State; } @@ -1391,7 +1396,7 @@ HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * cons * @param hspdif SPDIFRX handle * @retval SPDIFRX Error Code */ -uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif) +uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif) { return hspdif->ErrorCode; } @@ -1407,10 +1412,10 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif) */ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Rx DMA Request */ - if(hdma->Init.Mode != DMA_CIRCULAR) + if (hdma->Init.Mode != DMA_CIRCULAR) { hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN); hspdif->RxXferCount = 0; @@ -1430,7 +1435,7 @@ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) */ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) hspdif->RxHalfCpltCallback(hspdif); @@ -1447,7 +1452,7 @@ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) */ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Cb DMA Request */ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); @@ -1468,7 +1473,7 @@ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) */ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) hspdif->CxHalfCpltCallback(hspdif); @@ -1484,13 +1489,13 @@ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) */ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Rx and Cb DMA Request */ hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN)); hspdif->RxXferCount = 0; - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Set the error code and execute error callback*/ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA; @@ -1516,7 +1521,7 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) hspdif->pRxBuffPtr++; hspdif->RxXferCount--; - if(hspdif->RxXferCount == 0U) + if (hspdif->RxXferCount == 0U) { /* Disable RXNE/PE and OVR interrupts */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE); @@ -1527,9 +1532,9 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) __HAL_UNLOCK(hspdif); #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - hspdif->RxCpltCallback(hspdif); + hspdif->RxCpltCallback(hspdif); #else - HAL_SPDIFRX_RxCpltCallback(hspdif); + HAL_SPDIFRX_RxCpltCallback(hspdif); #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ } } @@ -1546,7 +1551,7 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) hspdif->pCsBuffPtr++; hspdif->CsXferCount--; - if(hspdif->CsXferCount == 0U) + if (hspdif->CsXferCount == 0U) { /* Disable CSRNE interrupt */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); @@ -1557,9 +1562,9 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) __HAL_UNLOCK(hspdif); #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - hspdif->CxCpltCallback(hspdif); + hspdif->CxCpltCallback(hspdif); #else - HAL_SPDIFRX_CxCpltCallback(hspdif); + HAL_SPDIFRX_CxCpltCallback(hspdif); #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ } } @@ -1573,15 +1578,16 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) * @param tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart) +static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t tickstart) { /* Wait until flag is set */ - while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status) + while (__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); @@ -1592,7 +1598,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -1619,5 +1625,3 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c index 8e53f3f9fd..62d5d65870 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c @@ -9,7 +9,17 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -184,18 +194,6 @@ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -3156,7 +3154,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t * ptmpreg8; + __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Initialize the 8bit temporary pointer */ @@ -3314,7 +3312,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint8_t * ptmpreg8; + __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Initialize the 8bit temporary pointer */ @@ -3526,7 +3524,7 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, return HAL_TIMEOUT; } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ - if(count == 0U) + if (count == 0U) { tmp_timeout = 0U; } @@ -3915,4 +3913,3 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c index 2f38bfe6f3..ef2eaf092e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c @@ -6,6 +6,17 @@ * This file provides a generic firmware to drive SRAM memories * mounted as external device. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -64,25 +75,25 @@ The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback, + Use Functions HAL_SRAM_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : SRAM MspInit. (+) MspDeInitCallback : SRAM MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default + Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : SRAM MspInit. (+) MspDeInitCallback : SRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET + By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init - and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit + reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init + and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -90,8 +101,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit - or @ref HAL_SRAM_Init function. + using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit + or HAL_SRAM_Init function. When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -99,49 +110,41 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" +#if defined(FMC_Bank1) || defined(FSMC_Bank1) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ +#ifdef HAL_SRAM_MODULE_ENABLED + /** @defgroup SRAM SRAM * @brief SRAM driver modules * @{ */ -#ifdef HAL_SRAM_MODULE_ENABLED - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void SRAM_DMACplt(DMA_HandleTypeDef *hdma); +static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma); +static void SRAM_DMAError(DMA_HandleTypeDef *hdma); /* Exported functions --------------------------------------------------------*/ + /** @defgroup SRAM_Exported_Functions SRAM Exported Functions * @{ */ + /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions. * @verbatim ============================================================================== @@ -162,21 +165,22 @@ * @param ExtTiming Pointer to SRAM extended mode timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming) { /* Check the SRAM handle parameter */ - if(hsram == NULL) + if (hsram == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - if(hsram->State == HAL_SRAM_STATE_RESET) + if (hsram->State == HAL_SRAM_STATE_RESET) { /* Allocate lock resource and initialize it */ hsram->Lock = HAL_UNLOCKED; #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - if(hsram->MspInitCallback == NULL) + if (hsram->MspInitCallback == NULL) { hsram->MspInitCallback = HAL_SRAM_MspInit; } @@ -188,21 +192,25 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp #else /* Initialize the low level hardware (MSP) */ HAL_SRAM_MspInit(hsram); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } /* Initialize SRAM control Interface */ - FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); + (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); /* Initialize SRAM timing Interface */ - FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); + (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); /* Initialize SRAM extended mode timing Interface */ - FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); + (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, + hsram->Init.ExtendedMode); /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); + /* Initialize the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + return HAL_OK; } @@ -212,10 +220,10 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp * the configuration information for SRAM module. * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) +HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) { #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - if(hsram->MspDeInitCallback == NULL) + if (hsram->MspDeInitCallback == NULL) { hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; } @@ -225,11 +233,12 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) #else /* De-Initialize the low level hardware (MSP) */ HAL_SRAM_MspDeInit(hsram); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /* Configure the SRAM registers with their reset values */ - FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); + (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); + /* Reset the SRAM controller state */ hsram->State = HAL_SRAM_STATE_RESET; /* Release Lock */ @@ -248,7 +257,8 @@ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsram); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_MspInit could be implemented in the user file */ } @@ -263,6 +273,7 @@ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsram); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_MspDeInit could be implemented in the user file */ @@ -278,6 +289,7 @@ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file */ @@ -293,7 +305,8 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file */ } @@ -302,7 +315,7 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) * @} */ -/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions +/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions * @brief Input Output and memory control functions * @verbatim @@ -325,29 +338,41 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize) { - __IO uint8_t * pSramAddress = (uint8_t *)pAddress; + uint32_t size; + __IO uint8_t *psramaddress = (uint8_t *)pAddress; + uint8_t *pdestbuff = pDstBuffer; + HAL_SRAM_StateTypeDef state = hsram->State; - /* Process Locked */ - __HAL_LOCK(hsram); + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; - /* Read data from memory */ - for(; BufferSize != 0U; BufferSize--) - { - *pDstBuffer = *(__IO uint8_t *)pSramAddress; - pDstBuffer++; - pSramAddress++; - } + /* Read data from memory */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *psramaddress; + pdestbuff++; + psramaddress++; + } - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; + /* Update the SRAM controller state */ + hsram->State = state; - /* Process unlocked */ - __HAL_UNLOCK(hsram); + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -361,36 +386,41 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize) { - __IO uint8_t * pSramAddress = (uint8_t *)pAddress; + uint32_t size; + __IO uint8_t *psramaddress = (uint8_t *)pAddress; + uint8_t *psrcbuff = pSrcBuffer; /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) + if (hsram->State == HAL_SRAM_STATE_READY) { - return HAL_ERROR; - } + /* Process Locked */ + __HAL_LOCK(hsram); - /* Process Locked */ - __HAL_LOCK(hsram); + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *psramaddress = *psrcbuff; + psrcbuff++; + psramaddress++; + } - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else { - *(__IO uint8_t *)pSramAddress = *pSrcBuffer; - pSrcBuffer++; - pSramAddress++; + return HAL_ERROR; } - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - return HAL_OK; } @@ -403,29 +433,53 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize) { - __IO uint16_t * pSramAddress = (uint16_t *)pAddress; + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint16_t *pdestbuff = pDstBuffer; + uint8_t limit; + HAL_SRAM_StateTypeDef state = hsram->State; - /* Process Locked */ - __HAL_LOCK(hsram); + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; - /* Read data from memory */ - for(; BufferSize != 0U; BufferSize--) - { - *pDstBuffer = *(__IO uint16_t *)pSramAddress; - pDstBuffer++; - pSramAddress++; - } + /* Check if the size is a 32-bits multiple */ + limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; + /* Read data from memory */ + for (size = BufferSize; size != limit; size -= 2U) + { + *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); + pdestbuff++; + *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U); + pdestbuff++; + psramaddress++; + } - /* Process unlocked */ - __HAL_UNLOCK(hsram); + /* Read last 16-bits if size is not 32-bits multiple */ + if (limit != 0U) + { + *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -439,35 +493,52 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize) { - __IO uint16_t * pSramAddress = (uint16_t *)pAddress; + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint16_t *psrcbuff = pSrcBuffer; + uint8_t limit; /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) + if (hsram->State == HAL_SRAM_STATE_READY) { - return HAL_ERROR; - } + /* Process Locked */ + __HAL_LOCK(hsram); - /* Process Locked */ - __HAL_LOCK(hsram); + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; + /* Check if the size is a 32-bits multiple */ + limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) - { - *(__IO uint16_t *)pSramAddress = *pSrcBuffer; - pSrcBuffer++; - pSramAddress++; - } + /* Write data to memory */ + for (size = BufferSize; size != limit; size -= 2U) + { + *psramaddress = (uint32_t)(*psrcbuff); + psrcbuff++; + *psramaddress |= ((uint32_t)(*psrcbuff) << 16U); + psrcbuff++; + psramaddress++; + } - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; + /* Write last 16-bits if size is not 32-bits multiple */ + if (limit != 0U) + { + *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U); + } - /* Process unlocked */ - __HAL_UNLOCK(hsram); + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -481,27 +552,41 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint32_t *pdestbuff = pDstBuffer; + HAL_SRAM_StateTypeDef state = hsram->State; - /* Read data from memory */ - for(; BufferSize != 0U; BufferSize--) + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { - *pDstBuffer = *(__IO uint32_t *)pAddress; - pDstBuffer++; - pAddress++; - } + /* Process Locked */ + __HAL_LOCK(hsram); - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; - /* Process unlocked */ - __HAL_UNLOCK(hsram); + /* Read data from memory */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *psramaddress; + pdestbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -515,34 +600,41 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint32_t *psrcbuff = pSrcBuffer; + /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) + if (hsram->State == HAL_SRAM_STATE_READY) { - return HAL_ERROR; - } + /* Process Locked */ + __HAL_LOCK(hsram); - /* Process Locked */ - __HAL_LOCK(hsram); + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *psramaddress = *psrcbuff; + psrcbuff++; + psramaddress++; + } - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else { - *(__IO uint32_t *)pAddress = *pSrcBuffer; - pSrcBuffer++; - pAddress++; + return HAL_ERROR; } - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - return HAL_OK; } @@ -555,28 +647,44 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { - /* Process Locked */ - __HAL_LOCK(hsram); + HAL_StatusTypeDef status; + HAL_SRAM_StateTypeDef state = hsram->State; - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); - /* Configure DMA user callbacks */ - hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); + /* Configure DMA user callbacks */ + if (state == HAL_SRAM_STATE_READY) + { + hsram->hdma->XferCpltCallback = SRAM_DMACplt; + } + else + { + hsram->hdma->XferCpltCallback = SRAM_DMACpltProt; + } + hsram->hdma->XferErrorCallback = SRAM_DMAError; - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); - /* Process unlocked */ - __HAL_UNLOCK(hsram); + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + status = HAL_ERROR; + } - return HAL_OK; + return status; } /** @@ -588,34 +696,36 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { + HAL_StatusTypeDef status; + /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) + if (hsram->State == HAL_SRAM_STATE_READY) { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; + /* Process Locked */ + __HAL_LOCK(hsram); - /* Configure DMA user callbacks */ - hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); + /* Configure DMA user callbacks */ + hsram->hdma->XferCpltCallback = SRAM_DMACplt; + hsram->hdma->XferErrorCallback = SRAM_DMAError; - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); - /* Process unlocked */ - __HAL_UNLOCK(hsram); + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + status = HAL_ERROR; + } - return HAL_OK; + return status; } #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) @@ -630,12 +740,13 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -644,20 +755,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = pCallback; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = pCallback; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -683,7 +794,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID * @retval status */ -HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; @@ -692,42 +803,42 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = HAL_SRAM_MspInit; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; - break; - case HAL_SRAM_DMA_XFER_CPLT_CB_ID : - hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - break; - case HAL_SRAM_DMA_XFER_ERR_CB_ID : - hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(state == HAL_SRAM_STATE_RESET) + else if (state == HAL_SRAM_STATE_RESET) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = HAL_SRAM_MspInit; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -752,12 +863,13 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -766,20 +878,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_DMA_XFER_CPLT_CB_ID : - hsram->DmaXferCpltCallback = pCallback; - break; - case HAL_SRAM_DMA_XFER_ERR_CB_ID : - hsram->DmaXferErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = pCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -792,14 +904,15 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR __HAL_UNLOCK(hsram); return status; } -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + /** * @} */ /** @defgroup SRAM_Exported_Functions_Group3 Control functions - * @brief management functions - * + * @brief Control functions + * @verbatim ============================================================================== ##### SRAM Control functions ##### @@ -820,17 +933,28 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR */ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) { - /* Process Locked */ - __HAL_LOCK(hsram); + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_PROTECTED) + { + /* Process Locked */ + __HAL_LOCK(hsram); - /* Enable write operation */ - FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; + /* Enable write operation */ + (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); - /* Process unlocked */ - __HAL_UNLOCK(hsram); + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -843,20 +967,28 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) */ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) { - /* Process Locked */ - __HAL_LOCK(hsram); + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; - /* Disable write operation */ - FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); + /* Disable write operation */ + (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_PROTECTED; + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_PROTECTED; - /* Process unlocked */ - __HAL_UNLOCK(hsram); + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } return HAL_OK; } @@ -865,9 +997,9 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) * @} */ -/** @defgroup SRAM_Exported_Functions_Group4 State functions - * @brief Peripheral State functions - * +/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### SRAM State functions ##### @@ -890,6 +1022,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) { return hsram->State; } + /** * @} */ @@ -897,16 +1030,81 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ -#endif /* HAL_SRAM_MODULE_ENABLED */ + +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferCpltCallback(hdma); +#else + HAL_SRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_PROTECTED; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferCpltCallback(hdma); +#else + HAL_SRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SRAM error callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMAError(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_ERROR; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferErrorCallback(hdma); +#else + HAL_SRAM_DMA_XferErrorCallback(hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} + /** * @} */ +#endif /* HAL_SRAM_MODULE_ENABLED */ + /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* FMC_Bank1 || FSMC_Bank1 */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c index f3d46cdd34..1ca1781e9f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c @@ -29,6 +29,17 @@ * + Commutation Event configuration with Interruption and DMA * + TIM OCRef clear configuration * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### TIMER Generic features ##### @@ -169,17 +180,6 @@ all interrupt callbacks are set to the corresponding weak functions: @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -4470,13 +4470,11 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); - if (status == HAL_OK) - { - status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); - } return status; @@ -4809,13 +4807,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); - if (status == HAL_OK) - { - status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); - } return status; } @@ -7623,4 +7619,3 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim) /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c index bba44f15c6..092175f562 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c @@ -10,6 +10,17 @@ * + Time Complementary signal break and dead time configuration * + Time Master and Slave synchronization configuration * + Timer remapping capabilities configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### TIMER Extended features ##### @@ -64,17 +75,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -2098,11 +2098,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { - __HAL_LOCK(htim); /* Check parameters */ assert_param(IS_TIM_REMAP(htim->Instance, Remap)); + __HAL_LOCK(htim); + #if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP) if ((Remap & LPTIM_REMAP_MASK) == LPTIM_REMAP_MASK) { @@ -2249,7 +2250,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ @@ -2425,5 +2426,3 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_alarm_template.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_alarm_template.c index 969c8cf2a1..e7f0ace40a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_alarm_template.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_alarm_template.c @@ -10,6 +10,18 @@ * + The alarm is configured to assert an interrupt when the RTC reaches 1ms * + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00 * + HSE (default), LSE or LSI can be selected as RTC clock source + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -30,17 +42,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -314,4 +315,3 @@ void RTC_Alarm_IRQHandler(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_wakeup_template.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_wakeup_template.c index ec1a91d3fa..a9cff87d24 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_wakeup_template.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_rtc_wakeup_template.c @@ -11,6 +11,18 @@ * + The wakeup feature is configured to assert an interrupt each 1ms * + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback * + HSE (default), LSE or LSI can be selected as RTC clock source + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -31,17 +43,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -289,4 +290,3 @@ void RTC_WKUP_IRQHandler(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_tim_template.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_tim_template.c index 5fd548353b..8e18d9744c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_timebase_tim_template.c @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -175,4 +174,4 @@ void TIM6_DAC_IRQHandler(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c index 5e53813c86..36b7317a61 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c @@ -9,6 +9,18 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -240,17 +252,6 @@ | 1 | 1 | | SB | 8 bit data | PB | STB | | +-------------------------------------------------------------+ ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1132,10 +1133,10 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint8_t *pdata8bits; - uint16_t *pdata16bits; + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; uint32_t tickstart = 0U; /* Check that a Tx process is not already ongoing */ @@ -1162,7 +1163,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; + pdata16bits = (const uint16_t *) pData; } else { @@ -1311,7 +1312,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) @@ -1391,9 +1392,9 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { - uint32_t *tmp; + const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) @@ -1426,8 +1427,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat huart->hdmatx->XferAbortCallback = NULL; /* Enable the UART transmit DMA stream */ - tmp = (uint32_t *)&pData; - HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); + tmp = (const uint32_t *)&pData; + HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); @@ -1543,7 +1544,10 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) __HAL_UART_CLEAR_OREFLAG(huart); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the UART DMA Rx request */ @@ -3157,11 +3161,12 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) } /** - * @brief This function handles UART Communication Timeout. + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @param Flag specifies the UART flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status @@ -3217,8 +3222,11 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat /* Process Unlocked */ __HAL_UNLOCK(huart); - /* Enable the UART Parity Error Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); @@ -3272,8 +3280,11 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa /* Process Unlocked */ __HAL_UNLOCK(huart); - /* Enable the UART Parity Error Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3500,14 +3511,14 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { - uint16_t *tmp; + const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { - tmp = (uint16_t *) huart->pTxBuffPtr; + tmp = (const uint16_t *) huart->pTxBuffPtr; huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); huart->pTxBuffPtr += 2U; } @@ -3518,7 +3529,7 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) if (--huart->TxXferCount == 0U) { - /* Disable the UART Transmit Complete Interrupt */ + /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); /* Enable the UART Transmit Complete Interrupt */ @@ -3738,4 +3749,3 @@ static void UART_SetConfig(UART_HandleTypeDef *huart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c index aa6f021425..945a646959 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c @@ -9,6 +9,18 @@ * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -182,17 +194,6 @@ | 1 | 1 | | SB | 8 bit data | PB | STB | | +-------------------------------------------------------------+ ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -746,10 +747,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout) { - uint8_t *ptxdata8bits; - uint16_t *ptxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; uint32_t tickstart; if (husart->State == HAL_USART_STATE_READY) @@ -775,7 +776,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { ptxdata8bits = NULL; - ptxdata16bits = (uint16_t *) pTxData; + ptxdata16bits = (const uint16_t *) pTxData; } else { @@ -936,13 +937,13 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { uint8_t *prxdata8bits; uint16_t *prxdata16bits; - uint8_t *ptxdata8bits; - uint16_t *ptxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; uint16_t rxdatacount; uint32_t tickstart; @@ -982,7 +983,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { prxdata8bits = NULL; ptxdata8bits = NULL; - ptxdata16bits = (uint16_t *) pTxData; + ptxdata16bits = (const uint16_t *) pTxData; prxdata16bits = (uint16_t *) pRxData; } else @@ -1076,7 +1077,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t * @retval HAL status * @note The USART errors are not managed to avoid the overrun error. */ -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) { if (husart->State == HAL_USART_STATE_READY) { @@ -1150,8 +1151,16 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error and Data Register not empty Interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error and Data Register not empty Interrupts */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + } + else + { + /* Enable the USART Data Register not empty Interrupts */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1179,7 +1188,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx * @param Size Amount of data elements (u8 or u16) to be sent (same amount to be received). * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { if (husart->State == HAL_USART_STATE_READY) @@ -1207,8 +1216,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /* Enable the USART Data Register not empty Interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1235,9 +1247,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) { - uint32_t *tmp; + const uint32_t *tmp; if (husart->State == HAL_USART_STATE_READY) { @@ -1268,8 +1280,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p husart->hdmatx->XferAbortCallback = NULL; /* Enable the USART transmit DMA stream */ - tmp = (uint32_t *)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size); + tmp = (const uint32_t *)&pTxData; + HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size); /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC); @@ -1362,8 +1374,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1397,10 +1412,10 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - uint32_t *tmp; + const uint32_t *tmp; if (husart->State == HAL_USART_STATE_READY) { @@ -1442,11 +1457,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Enable the USART receive DMA stream */ tmp = (uint32_t *)&pRxData; - HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t *)tmp, Size); + HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(const uint32_t *)tmp, Size); /* Enable the USART transmit DMA stream */ - tmp = (uint32_t *)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size); + tmp = (const uint32_t *)&pTxData; + HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size); /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC); @@ -1457,8 +1472,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -2291,11 +2309,12 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) } /** - * @brief This function handles USART Communication Timeout. + * @brief This function handles USART Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param husart Pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @param Flag specifies the USART flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Tickstart Tick start value. * @param Timeout Timeout duration. * @retval HAL status @@ -2480,13 +2499,13 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) { - uint16_t *tmp; + const uint16_t *tmp; if (husart->State == HAL_USART_STATE_BUSY_TX) { if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - tmp = (uint16_t *) husart->pTxBuffPtr; + tmp = (const uint16_t *) husart->pTxBuffPtr; husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); husart->pTxBuffPtr += 2U; } @@ -2622,8 +2641,8 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) */ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { - uint8_t *pdata8bits; - uint16_t *pdata16bits; + const uint16_t *pdatatx16bits; + uint16_t *pdatarx16bits; if (husart->State == HAL_USART_STATE_BUSY_TX_RX) { @@ -2633,9 +2652,8 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - pdata8bits = NULL; - pdata16bits = (uint16_t *) husart->pTxBuffPtr; - husart->Instance->DR = (uint16_t)(*pdata16bits & (uint16_t)0x01FF); + pdatatx16bits = (const uint16_t *) husart->pTxBuffPtr; + husart->Instance->DR = (uint16_t)(*pdatatx16bits & (uint16_t)0x01FF); husart->pTxBuffPtr += 2U; } else @@ -2659,22 +2677,19 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - pdata8bits = NULL; - pdata16bits = (uint16_t *) husart->pRxBuffPtr; - *pdata16bits = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); + pdatarx16bits = (uint16_t *) husart->pRxBuffPtr; + *pdatarx16bits = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); husart->pRxBuffPtr += 2U; } else { - pdata8bits = (uint8_t *) husart->pRxBuffPtr; - pdata16bits = NULL; if ((husart->Init.WordLength == USART_WORDLENGTH_9B) || ((husart->Init.WordLength == USART_WORDLENGTH_8B) && (husart->Init.Parity == USART_PARITY_NONE))) { - *pdata8bits = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF); + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF); } else { - *pdata8bits = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F); + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F); } husart->pRxBuffPtr += 1U; } @@ -2821,4 +2836,3 @@ static void USART_SetConfig(USART_HandleTypeDef *husart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c index 0cb9591d62..216ea2b92c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c @@ -7,6 +7,17 @@ * functionalities of the Window Watchdog (WWDG) peripheral: * + Initialization and Configuration functions * + IO operation functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### WWDG Specific features ##### @@ -40,7 +51,7 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) at 42MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 97.52�s + max timeout before reset: approximately 97.52us (++) Counter max (T[5;0] = 0x3F) at 42MHz (PCLK1) with prescaler dividing by 8: max timeout before reset: approximately 49.93ms @@ -112,17 +123,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -418,5 +418,3 @@ __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c index e180e439ec..2d6e082864 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -921,4 +920,3 @@ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c index 372e2f2723..113879301f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -26,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif/* USE_FULL_ASSERT */ +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F4xx_LL_Driver * @{ @@ -102,6 +101,3 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c index a84445a62f..4514d9186f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dac.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -279,4 +278,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c index a662b6fd37..74029e2ffc 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -422,4 +421,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma2d.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma2d.c index 92941c4fb6..9f6c8f51c8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma2d.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma2d.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -593,6 +592,3 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c index 31d70ac681..ce2f7b054b 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS.Clause * ****************************************************************************** */ @@ -211,4 +210,3 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c index b26565e6d3..1bdf9dea7a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c @@ -10,11 +10,22 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### FMC peripheral features ##### ============================================================================== - [..] The Flexible memory controller (FMC) includes three memory controllers: + [..] The Flexible memory controller (FMC) includes following memory controllers: (+) The NOR/PSRAM memory controller (+) The NAND/PC Card memory controller (+) The Synchronous DRAM (SDRAM) controller @@ -42,17 +53,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -61,27 +61,133 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || (defined(HAL_NAND_MODULE_ENABLED)) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules * @{ */ -#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + +/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants + * @{ + */ + +/* ----------------------- FMC registers bit mask --------------------------- */ + +#if defined(FMC_Bank1) +/* --- BCR Register ---*/ +/* BCR register clear mask */ + +/* --- BTR Register ---*/ +/* BTR register clear mask */ +#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD |\ + FMC_BTR1_DATAST | FMC_BTR1_BUSTURN |\ + FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT |\ + FMC_BTR1_ACCMOD)) + +/* --- BWTR Register ---*/ +/* BWTR register clear mask */ +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD |\ + FMC_BWTR1_DATAST | FMC_BWTR1_BUSTURN |\ + FMC_BWTR1_ACCMOD)) +#endif /* FMC_Bank1 */ +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) + +#if defined (FMC_PCR_PWAITEN) +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \ + FMC_PCR_PTYP | FMC_PCR_PWID | \ + FMC_PCR_ECCEN | FMC_PCR_TCLR | \ + FMC_PCR_TAR | FMC_PCR_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 |\ + FMC_PMEM_MEMHOLD2 | FMC_PMEM_MEMHIZ2)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 |\ + FMC_PATT_ATTHOLD2 | FMC_PATT_ATTHIZ2)) +#else +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | \ + FMC_PCR2_PTYP | FMC_PCR2_PWID | \ + FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \ + FMC_PCR2_TAR | FMC_PCR2_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 |\ + FMC_PMEM2_MEMHOLD2 | FMC_PMEM2_MEMHIZ2)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 |\ + FMC_PATT2_ATTHOLD2 | FMC_PATT2_ATTHIZ2)) + +#endif /* FMC_PCR_PWAITEN */ +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ +#if defined(FMC_Bank4) +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR4_CLEAR_MASK ((uint32_t)(FMC_PCR4_PWAITEN | FMC_PCR4_PBKEN | \ + FMC_PCR4_PTYP | FMC_PCR4_PWID | \ + FMC_PCR4_ECCEN | FMC_PCR4_TCLR | \ + FMC_PCR4_TAR | FMC_PCR4_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM4_CLEAR_MASK ((uint32_t)(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 |\ + FMC_PMEM4_MEMHOLD4 | FMC_PMEM4_MEMHIZ4)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT4_CLEAR_MASK ((uint32_t)(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 |\ + FMC_PATT4_ATTHOLD4 | FMC_PATT4_ATTHIZ4)) + +/* --- PIO4 Register ---*/ +/* PIO4 register clear mask */ +#define PIO4_CLEAR_MASK ((uint32_t)(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | \ + FMC_PIO4_IOHOLD4 | FMC_PIO4_IOHIZ4)) + +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) + +/* --- SDCR Register ---*/ +/* SDCR register clear mask */ +#define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCR1_NC | FMC_SDCR1_NR | \ + FMC_SDCR1_MWID | FMC_SDCR1_NB | \ + FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | \ + FMC_SDCR1_RPIPE)) + +/* --- SDTR Register ---*/ +/* SDTR register clear mask */ +#define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | \ + FMC_SDTR1_TRAS | FMC_SDTR1_TRC | \ + FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)) +#endif /* FMC_Bank5_6 */ + +/** + * @} + */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup FMC_LL_Private_Functions +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions * @{ */ -/** @addtogroup FMC_LL_NORSRAM +#if defined(FMC_Bank1) + +/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions * @brief NORSRAM Controller functions * @verbatim @@ -101,12 +207,11 @@ (+) FMC NORSRAM bank enable/disable write operation using the functions FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() - @endverbatim * @{ */ -/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1 +/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -130,9 +235,12 @@ * @param Init Pointer to NORSRAM Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_InitTypeDef *Init) { - uint32_t tmpr = 0U; + uint32_t flashaccess; + uint32_t btcr_reg; + uint32_t mask; /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); @@ -142,95 +250,102 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(FMC_BCR1_WRAPMOD) assert_param(IS_FMC_WRAP_MODE(Init->WrapMode)); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* FMC_BCR1_WRAPMOD */ assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); +#if defined(FMC_BCR1_CCLKEN) assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); - assert_param(IS_FMC_PAGESIZE(Init->PageSize)); -#if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#endif +#if defined(FMC_BCR1_WFDIS) assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); -#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ - - /* Get the BTCR register value */ - tmpr = Device->BTCR[Init->NSBank]; - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT, CPSIZE, CBURSTRW and CCLKEN bits */ - tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ - FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ - FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \ - FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ - FMC_BCR1_ASYNCWAIT | FMC_BCR1_CPSIZE | FMC_BCR1_CBURSTRW | \ - FMC_BCR1_CCLKEN)); +#endif /* FMC_BCR1_WFDIS */ + assert_param(IS_FMC_PAGESIZE(Init->PageSize)); - /* Set NORSRAM device control parameters */ - tmpr |= (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WrapMode |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->PageSize |\ - Init->WriteBurst |\ - Init->ContinuousClock); -#else /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */ - tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ - FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ - FMC_BCR1_WAITPOL | FMC_BCR1_WAITCFG | FMC_BCR1_CPSIZE | \ - FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ - FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | \ - FMC_BCR1_WFDIS)); + /* Disable NORSRAM Device */ + __FMC_NORSRAM_DISABLE(Device, Init->NSBank); /* Set NORSRAM device control parameters */ - tmpr |= (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->WriteBurst |\ - Init->ContinuousClock |\ - Init->PageSize |\ - Init->WriteFifo); -#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ - - if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) + if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) { - tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; + flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE; + } + else + { + flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; } - Device->BTCR[Init->NSBank] = tmpr; - + btcr_reg = (flashaccess | \ + Init->DataAddressMux | \ + Init->MemoryType | \ + Init->MemoryDataWidth | \ + Init->BurstAccessMode | \ + Init->WaitSignalPolarity | \ + Init->WaitSignalActive | \ + Init->WriteOperation | \ + Init->WaitSignal | \ + Init->ExtendedMode | \ + Init->AsynchronousWait | \ + Init->WriteBurst); + +#if defined(FMC_BCR1_WRAPMOD) + btcr_reg |= Init->WrapMode; +#endif /* FMC_BCR1_WRAPMOD */ +#if defined(FMC_BCR1_CCLKEN) + btcr_reg |= Init->ContinuousClock; +#endif /* FMC_BCR1_CCLKEN */ +#if defined(FMC_BCR1_WFDIS) + btcr_reg |= Init->WriteFifo; +#endif /* FMC_BCR1_WFDIS */ + btcr_reg |= Init->PageSize; + + mask = (FMC_BCR1_MBKEN | + FMC_BCR1_MUXEN | + FMC_BCR1_MTYP | + FMC_BCR1_MWID | + FMC_BCR1_FACCEN | + FMC_BCR1_BURSTEN | + FMC_BCR1_WAITPOL | + FMC_BCR1_WAITCFG | + FMC_BCR1_WREN | + FMC_BCR1_WAITEN | + FMC_BCR1_EXTMOD | + FMC_BCR1_ASYNCWAIT | + FMC_BCR1_CBURSTRW); + +#if defined(FMC_BCR1_WRAPMOD) + mask |= FMC_BCR1_WRAPMOD; +#endif /* FMC_BCR1_WRAPMOD */ +#if defined(FMC_BCR1_CCLKEN) + mask |= FMC_BCR1_CCLKEN; +#endif +#if defined(FMC_BCR1_WFDIS) + mask |= FMC_BCR1_WFDIS; +#endif /* FMC_BCR1_WFDIS */ + mask |= FMC_BCR1_CPSIZE; + + MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); + +#if defined(FMC_BCR1_CCLKEN) /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ - if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) + if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) { - Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock); + MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); } +#endif +#if defined(FMC_BCR1_WFDIS) -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - if(Init->NSBank != FMC_NORSRAM_BANK1) + if (Init->NSBank != FMC_NORSRAM_BANK1) { - Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); + /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */ + SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); } -#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ +#endif /* FMC_BCR1_WFDIS */ return HAL_OK; } @@ -242,7 +357,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); @@ -254,7 +370,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EX /* De-initialize the FMC_NORSRAM device */ /* FMC_NORSRAM_BANK1 */ - if(Bank == FMC_NORSRAM_BANK1) + if (Bank == FMC_NORSRAM_BANK1) { Device->BTCR[Bank] = 0x000030DBU; } @@ -265,7 +381,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EX } Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; - ExDevice->BWTR[Bank] = 0x0FFFFFFFU; + ExDevice->BWTR[Bank] = 0x0FFFFFFFU; return HAL_OK; } @@ -278,9 +394,12 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EX * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr = 0U; +#if defined(FMC_BCR1_CCLKEN) + uint32_t tmpr; +#endif /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); @@ -293,33 +412,25 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); - /* Get the BTCR register value */ - tmpr = Device->BTCR[Bank + 1U]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ - tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \ - FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \ - FMC_BTR1_ACCMOD)); - /* Set FMC_NORSRAM device timing parameters */ - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4U) |\ - ((Timing->DataSetupTime) << 8U) |\ - ((Timing->BusTurnAroundDuration) << 16U) |\ - (((Timing->CLKDivision) - 1U) << 20U) |\ - (((Timing->DataLatency) - 2U) << 24U) |\ - (Timing->AccessMode)); - - Device->BTCR[Bank + 1U] = tmpr; - + MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BTR1_DATAST_Pos) | + ((Timing->BusTurnAroundDuration) << FMC_BTR1_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos) | + (((Timing->DataLatency) - 2U) << FMC_BTR1_DATLAT_Pos) | + (Timing->AccessMode))); + +#if defined(FMC_BCR1_CCLKEN) /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ - if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) + if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U)); - tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << 20U); - Device->BTCR[FMC_NORSRAM_BANK1 + 1U] = tmpr; + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos)); + tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos); + MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); } +#endif return HAL_OK; } @@ -329,17 +440,21 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR * @param Device Pointer to NORSRAM device instance * @param Timing Pointer to NORSRAM Timing structure * @param Bank NORSRAM bank number + * @param ExtendedMode FMC Extended Mode + * This parameter can be one of the following values: + * @arg FMC_EXTENDED_MODE_DISABLE + * @arg FMC_EXTENDED_MODE_ENABLE * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) { - uint32_t tmpr = 0U; - /* Check the parameters */ assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) + if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE) { /* Check the parameters */ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); @@ -350,20 +465,12 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); - /* Get the BWTR register value */ - tmpr = Device->BWTR[Bank]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */ - tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ - FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD)); - - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4U) |\ - ((Timing->DataSetupTime) << 8U) |\ - ((Timing->BusTurnAroundDuration) << 16U) |\ - (Timing->AccessMode)); - - Device->BWTR[Bank] = tmpr; + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) | + Timing->AccessMode | + ((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos))); } else { @@ -377,8 +484,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef */ /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### FMC_NORSRAM Control functions ##### @@ -390,6 +497,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef @endverbatim * @{ */ + /** * @brief Enables dynamically FMC_NORSRAM write operation. * @param Device Pointer to NORSRAM device instance @@ -403,7 +511,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Enable write operation */ - Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; + SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); return HAL_OK; } @@ -421,7 +529,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device assert_param(IS_FMC_NORSRAM_BANK(Bank)); /* Disable write operation */ - Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; + CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); return HAL_OK; } @@ -433,8 +541,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device /** * @} */ +#endif /* FMC_Bank1 */ + +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) -/** @addtogroup FMC_LL_NAND +/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions * @brief NAND Controller functions * @verbatim @@ -459,10 +570,9 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @{ */ -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * +/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @verbatim ============================================================================== ##### Initialization and de_initialization functions ##### @@ -486,8 +596,6 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device */ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) { - uint32_t tmpr = 0U; - /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); assert_param(IS_FMC_NAND_BANK(Init->NandBank)); @@ -498,311 +606,42 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); - /* Get the NAND bank register value */ - tmpr = Device->PCR; - - /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ - tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \ - FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \ - FMC_PCR_TAR | FMC_PCR_ECCPS)); - +#if defined(FMC_Bank2_3) /* Set NAND device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FMC_PCR_MEMORY_TYPE_NAND |\ - Init->MemoryDataWidth |\ - Init->EccComputation |\ - Init->ECCPageSize |\ - ((Init->TCLRSetupTime) << 9U) |\ - ((Init->TARSetupTime) << 13U)); - - /* NAND bank registers configuration */ - Device->PCR = tmpr; - - return HAL_OK; -} - -/** - * @brief Initializes the FMC_NAND Common space Timing according to the specified - * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device Pointer to NAND device instance - * @param Timing Pointer to NAND timing structure - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get the NAND bank 2 register value */ - tmpr = Device->PMEM; - - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 | FMC_PMEM_MEMHOLD2 | \ - FMC_PMEM_MEMHIZ2)); - - /* Set FMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U) - ); - - /* NAND bank registers configuration */ - Device->PMEM = tmpr; - - return HAL_OK; -} - -/** - * @brief Initializes the FMC_NAND Attribute space Timing according to the specified - * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device Pointer to NAND device instance - * @param Timing Pointer to NAND timing structure - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get the NAND bank register value */ - tmpr = Device->PATT; - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 | FMC_PATT_ATTHOLD2 | \ - FMC_PATT_ATTHIZ2)); - - /* Set FMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - /* NAND bank registers configuration */ - Device->PATT = tmpr; - - return HAL_OK; -} - - -/** - * @brief DeInitializes the FMC_NAND device - * @param Device Pointer to NAND device instance - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Disable the NAND Bank */ - __FMC_NAND_DISABLE(Device, Bank); - - /* De-initialize the NAND Bank */ - /* Set the FMC_NAND_BANK registers to their reset values */ - Device->PCR = 0x00000018U; - Device->SR = 0x00000040U; - Device->PMEM = 0xFCFCFCFCU; - Device->PATT = 0xFCFCFCFCU; - - return HAL_OK; -} - -/** - * @} - */ - - -/** @defgroup HAL_FMC_NAND_Group2 Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### FMC_NAND Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FMC NAND interface. - -@endverbatim - * @{ - */ - - -/** - * @brief Enables dynamically FMC_NAND ECC feature. - * @param Device Pointer to NAND device instance - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Enable ECC feature */ - Device->PCR |= FMC_PCR_ECCEN; - - return HAL_OK; -} - - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device Pointer to NAND device instance - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Disable ECC feature */ - Device->PCR &= ~FMC_PCR_ECCEN; - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device Pointer to NAND device instance - * @param ECCval Pointer to ECC value - * @param Bank NAND bank number - * @param Timeout Timeout wait value - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until FIFO is empty */ - while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - /* Get the ECCR register value */ - *ECCval = (uint32_t)Device->ECCR; - - return HAL_OK; -} - -/** - * @} - */ - -#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ -/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FMC NAND interface - (+) De-initialize the FMC NAND interface - (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ -/** - * @brief Initializes the FMC_NAND device according to the specified - * control parameters in the FMC_NAND_HandleTypeDef - * @param Device Pointer to NAND device instance - * @param Init Pointer to NAND Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Init->NandBank)); - assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); - assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); - assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); - assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); - assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); - - if(Init->NandBank == FMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PCR2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PCR3; - } - - /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ - tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \ - FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \ - FMC_PCR2_TAR | FMC_PCR2_ECCPS)); - - /* Set NAND device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FMC_PCR_MEMORY_TYPE_NAND |\ - Init->MemoryDataWidth |\ - Init->EccComputation |\ - Init->ECCPageSize |\ - ((Init->TCLRSetupTime) << 9U) |\ - ((Init->TARSetupTime) << 13U)); - - if(Init->NandBank == FMC_NAND_BANK2) + if (Init->NandBank == FMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - Device->PCR2 = tmpr; + MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) | + ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos))); } else { /* NAND bank 3 registers configuration */ - Device->PCR3 = tmpr; + MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) | + ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos))); } +#else + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | + ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); +#endif return HAL_OK; - } /** @@ -813,10 +652,9 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr = 0U; - /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); @@ -825,38 +663,34 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); assert_param(IS_FMC_NAND_BANK(Bank)); - if(Bank == FMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PMEM2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PMEM3; - } - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \ - FMC_PMEM2_MEMHIZ2)); - +#if defined(FMC_Bank2_3) /* Set FMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U) - ); - - if(Bank == FMC_NAND_BANK2) + if (Bank == FMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - Device->PMEM2 = tmpr; + MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos))); } else { /* NAND bank 3 registers configuration */ - Device->PMEM3 = tmpr; + MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos))); } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ2_Pos))); +#endif return HAL_OK; } @@ -869,10 +703,9 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr = 0U; - /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); @@ -881,37 +714,34 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); assert_param(IS_FMC_NAND_BANK(Bank)); - if(Bank == FMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PATT2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PATT3; - } - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \ - FMC_PATT2_ATTHIZ2)); - +#if defined(FMC_Bank2_3) /* Set FMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - if(Bank == FMC_NAND_BANK2) + if (Bank == FMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - Device->PATT2 = tmpr; + MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos))); } else { /* NAND bank 3 registers configuration */ - Device->PATT3 = tmpr; + MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos))); } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ2_Pos))); +#endif return HAL_OK; } @@ -932,23 +762,34 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) __FMC_NAND_DISABLE(Device, Bank); /* De-initialize the NAND Bank */ - if(Bank == FMC_NAND_BANK2) +#if defined(FMC_Bank2_3) + if (Bank == FMC_NAND_BANK2) { /* Set the FMC_NAND_BANK2 registers to their reset values */ - Device->PCR2 = 0x00000018U; - Device->SR2 = 0x00000040U; - Device->PMEM2 = 0xFCFCFCFCU; - Device->PATT2 = 0xFCFCFCFCU; + WRITE_REG(Device->PCR2, 0x00000018U); + WRITE_REG(Device->SR2, 0x00000040U); + WRITE_REG(Device->PMEM2, 0xFCFCFCFCU); + WRITE_REG(Device->PATT2, 0xFCFCFCFCU); } /* FMC_Bank3_NAND */ else { /* Set the FMC_NAND_BANK3 registers to their reset values */ - Device->PCR3 = 0x00000018U; - Device->SR3 = 0x00000040U; - Device->PMEM3 = 0xFCFCFCFCU; - Device->PATT3 = 0xFCFCFCFCU; + WRITE_REG(Device->PCR3, 0x00000018U); + WRITE_REG(Device->SR3, 0x00000040U); + WRITE_REG(Device->PMEM3, 0xFCFCFCFCU); + WRITE_REG(Device->PATT3, 0xFCFCFCFCU); } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* Set the FMC_NAND_BANK3 registers to their reset values */ + WRITE_REG(Device->PCR, 0x00000018U); + WRITE_REG(Device->SR, 0x00000040U); + WRITE_REG(Device->PMEM, 0xFCFCFCFCU); + WRITE_REG(Device->PATT, 0xFCFCFCFCU); +#endif return HAL_OK; } @@ -957,7 +798,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) * @} */ -/** @addtogroup FMC_LL_NAND_Private_Functions_Group2 +/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions * @brief management functions * @verbatim @@ -971,6 +812,8 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) @endverbatim * @{ */ + + /** * @brief Enables dynamically FMC_NAND ECC feature. * @param Device Pointer to NAND device instance @@ -984,18 +827,26 @@ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) assert_param(IS_FMC_NAND_BANK(Bank)); /* Enable ECC feature */ - if(Bank == FMC_NAND_BANK2) +#if defined(FMC_Bank2_3) + if (Bank == FMC_NAND_BANK2) { - Device->PCR2 |= FMC_PCR2_ECCEN; + SET_BIT(Device->PCR2, FMC_PCR2_ECCEN); } else { - Device->PCR3 |= FMC_PCR3_ECCEN; + SET_BIT(Device->PCR3, FMC_PCR2_ECCEN); } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + SET_BIT(Device->PCR, FMC_PCR_ECCEN); +#endif return HAL_OK; } + /** * @brief Disables dynamically FMC_NAND ECC feature. * @param Device Pointer to NAND device instance @@ -1009,14 +860,21 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) assert_param(IS_FMC_NAND_BANK(Bank)); /* Disable ECC feature */ - if(Bank == FMC_NAND_BANK2) +#if defined(FMC_Bank2_3) + if (Bank == FMC_NAND_BANK2) { - Device->PCR2 &= ~FMC_PCR2_ECCEN; + CLEAR_BIT(Device->PCR2, FMC_PCR2_ECCEN); } else { - Device->PCR3 &= ~FMC_PCR3_ECCEN; + CLEAR_BIT(Device->PCR3, FMC_PCR2_ECCEN); } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); +#endif return HAL_OK; } @@ -1029,9 +887,10 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -1041,19 +900,20 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui tickstart = HAL_GetTick(); /* Wait until FIFO is empty */ - while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) + while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { return HAL_TIMEOUT; } } } - if(Bank == FMC_NAND_BANK2) +#if defined(FMC_Bank2_3) + if (Bank == FMC_NAND_BANK2) { /* Get the ECCR2 register value */ *ECCval = (uint32_t)Device->ECCR2; @@ -1063,6 +923,13 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui /* Get the ECCR3 register value */ *ECCval = (uint32_t)Device->ECCR3; } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* Get the ECCR register value */ + *ECCval = (uint32_t)Device->ECCR; +#endif return HAL_OK; } @@ -1070,13 +937,10 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui /** * @} */ +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ -/** - * @} - */ +#if defined(FMC_Bank4) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /** @addtogroup FMC_LL_PCCARD * @brief PCCARD Controller functions * @@ -1126,28 +990,26 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui */ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init) { - uint32_t tmpr = 0U; - /* Check the parameters */ assert_param(IS_FMC_PCCARD_DEVICE(Device)); +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); - - /* Get PCCARD control register value */ - tmpr = Device->PCR4; - - /* Clear TAR, TCLR, PWAITEN and PWID bits */ - tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \ - FMC_PCR4_PWID | FMC_PCR4_PTYP)); +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ /* Set FMC_PCCARD device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ - (Init->TCLRSetupTime << 9U) |\ - (Init->TARSetupTime << 13U)); - - Device->PCR4 = tmpr; + MODIFY_REG(Device->PCR4, + (FMC_PCR4_PTYP | + FMC_PCR4_PWAITEN | + FMC_PCR4_PWID | + FMC_PCR4_TCLR | + FMC_PCR4_TAR), + (FMC_PCR_MEMORY_TYPE_PCCARD | + Init->Waitfeature | + FMC_NAND_PCC_MEM_BUS_WIDTH_16 | + (Init->TCLRSetupTime << FMC_PCR4_TCLR_Pos) | + (Init->TARSetupTime << FMC_PCR4_TAR_Pos))); return HAL_OK; } @@ -1159,30 +1021,24 @@ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTyp * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing) { - uint32_t tmpr = 0U; - /* Check the parameters */ assert_param(IS_FMC_PCCARD_DEVICE(Device)); +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ - /* Get PCCARD common space timing register value */ - tmpr = Device->PMEM4; - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \ - FMC_PMEM4_MEMHIZ4)); /* Set PCCARD timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - Device->PMEM4 = tmpr; + MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK, + (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM4_MEMWAIT4_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM4_MEMHOLD4_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM4_MEMHIZ4_Pos))); return HAL_OK; } @@ -1194,30 +1050,24 @@ HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing) { - uint32_t tmpr = 0U; - /* Check the parameters */ assert_param(IS_FMC_PCCARD_DEVICE(Device)); +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - - /* Get PCCARD timing parameters */ - tmpr = Device->PATT4; - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \ - FMC_PATT4_ATTHIZ4)); +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ /* Set PCCARD timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - Device->PATT4 = tmpr; + MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK, + (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT4_ATTWAIT4_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT4_ATTHOLD4_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT4_ATTHIZ4_Pos))); return HAL_OK; } @@ -1229,31 +1079,24 @@ HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Devi * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing) { - uint32_t tmpr = 0; - /* Check the parameters */ assert_param(IS_FMC_PCCARD_DEVICE(Device)); +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - - /* Get FMC_PCCARD device timing parameters */ - tmpr = Device->PIO4; - - /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ - tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \ - FMC_PIO4_IOHIZ4)); +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ /* Set FMC_PCCARD device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - Device->PIO4 = tmpr; + MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, + (Timing->SetupTime | + (Timing->WaitSetupTime << FMC_PIO4_IOWAIT4_Pos) | + (Timing->HoldSetupTime << FMC_PIO4_IOHOLD4_Pos) | + (Timing->HiZSetupTime << FMC_PIO4_IOHIZ4_Pos))); return HAL_OK; } @@ -1273,7 +1116,7 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) /* De-initialize the FMC_PCCARD device */ Device->PCR4 = 0x00000018U; - Device->SR4 = 0x00000000U; + Device->SR4 = 0x00000040U; Device->PMEM4 = 0xFCFCFCFCU; Device->PATT4 = 0xFCFCFCFCU; Device->PIO4 = 0xFCFCFCFCU; @@ -1284,10 +1127,11 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) -/** @addtogroup FMC_LL_SDRAM +/** @defgroup FMC_LL_SDRAM * @brief SDRAM Controller functions * @verbatim @@ -1335,9 +1179,6 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) */ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) { - uint32_t tmpr1 = 0U; - uint32_t tmpr2 = 0U; - /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); @@ -1352,60 +1193,44 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); /* Set SDRAM bank configuration parameters */ - if (Init->SDBank != FMC_SDRAM_BANK2) + if (Init->SDBank == FMC_SDRAM_BANK1) { - tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; - - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - - tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ - Init->RowBitsNumber |\ - Init->MemoryDataWidth |\ - Init->InternalBankNumber |\ - Init->CASLatency |\ - Init->WriteProtection |\ - Init->SDClockPeriod |\ - Init->ReadBurst |\ - Init->ReadPipeDelay - ); - Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], + SDCR_CLEAR_MASK, + (Init->ColumnBitsNumber | + Init->RowBitsNumber | + Init->MemoryDataWidth | + Init->InternalBankNumber | + Init->CASLatency | + Init->WriteProtection | + Init->SDClockPeriod | + Init->ReadBurst | + Init->ReadPipeDelay)); } else /* FMC_Bank2_SDRAM */ { - tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; - - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ - Init->ReadBurst |\ - Init->ReadPipeDelay); - - tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; - - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ - Init->RowBitsNumber |\ - Init->MemoryDataWidth |\ - Init->InternalBankNumber |\ - Init->CASLatency |\ - Init->WriteProtection); - - Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; - Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], + FMC_SDCR1_SDCLK | + FMC_SDCR1_RBURST | + FMC_SDCR1_RPIPE, + (Init->SDClockPeriod | + Init->ReadBurst | + Init->ReadPipeDelay)); + + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], + SDCR_CLEAR_MASK, + (Init->ColumnBitsNumber | + Init->RowBitsNumber | + Init->MemoryDataWidth | + Init->InternalBankNumber | + Init->CASLatency | + Init->WriteProtection)); } return HAL_OK; } + /** * @brief Initializes the FMC_SDRAM device timing according to the specified * parameters in the FMC_SDRAM_TimingTypeDef @@ -1414,11 +1239,9 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe * @param Bank SDRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr1 = 0U; - uint32_t tmpr2 = 0U; - /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); @@ -1431,50 +1254,35 @@ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Tim assert_param(IS_FMC_SDRAM_BANK(Bank)); /* Set SDRAM device timing parameters */ - if (Bank != FMC_SDRAM_BANK2) + if (Bank == FMC_SDRAM_BANK1) { - tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; - - /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); - - tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U) |\ - (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\ - (((Timing->SelfRefreshTime)-1U) << 8U) |\ - (((Timing->RowCycleDelay)-1U) << 12U) |\ - (((Timing->WriteRecoveryTime)-1U) <<16U) |\ - (((Timing->RPDelay)-1U) << 20U) |\ - (((Timing->RCDDelay)-1U) << 24U)); - Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], + SDTR_CLEAR_MASK, + (((Timing->LoadToActiveDelay) - 1U) | + (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | + (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | + (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | + (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | + (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); } - else /* FMC_Bank2_SDRAM */ + else /* FMC_Bank2_SDRAM */ { - tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; - - /* Clear TRC and TRP bits */ - tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP)); - - tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1U) << 12U) |\ - (((Timing->RPDelay)-1U) << 20U)); - - tmpr2 = Device->SDTR[FMC_SDRAM_BANK2]; - - /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); - - tmpr2 |= (uint32_t)((((Timing->LoadToActiveDelay)-1U) |\ - (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\ - (((Timing->SelfRefreshTime)-1U) << 8U) |\ - (((Timing->WriteRecoveryTime)-1U) <<16U) |\ - (((Timing->RCDDelay)-1U) << 24U))); - - Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; - Device->SDTR[FMC_SDRAM_BANK2] = tmpr2; + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], + FMC_SDTR1_TRC | + FMC_SDTR1_TRP, + (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | + (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos)); + + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], + SDTR_CLEAR_MASK, + (((Timing->LoadToActiveDelay) - 1U) | + (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | + (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | + (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); } + return HAL_OK; } @@ -1517,6 +1325,7 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) @endverbatim * @{ */ + /** * @brief Enables dynamically FMC_SDRAM write protection. * @param Device Pointer to SDRAM device instance @@ -1530,7 +1339,7 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, ui assert_param(IS_FMC_SDRAM_BANK(Bank)); /* Enable write protection */ - Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE; + SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); return HAL_OK; } @@ -1547,7 +1356,7 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, u assert_param(IS_FMC_SDRAM_BANK(Bank)); /* Disable write protection */ - Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE; + CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); return HAL_OK; } @@ -1560,11 +1369,10 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, u * @param Timeout Timeout wait value * @retval HAL state */ -HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) { - __IO uint32_t tmpr = 0U; uint32_t tickstart = 0U; - /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); @@ -1573,30 +1381,25 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Com assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); /* Set command register */ - tmpr = (uint32_t)((Command->CommandMode) |\ - (Command->CommandTarget) |\ - (((Command->AutoRefreshNumber)-1U) << 5U) |\ - ((Command->ModeRegisterDefinition) << 9U) - ); - - Device->SDCMR = tmpr; - + MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD), + ((Command->CommandMode) | (Command->CommandTarget) | + (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) | + ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos))); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait until command is send */ - while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) + /* wait until command is send */ + while (HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { return HAL_TIMEOUT; } } } - return HAL_OK; } @@ -1613,7 +1416,7 @@ HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32 assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); /* Set the refresh rate in command register */ - Device->SDRTR |= (RefreshRate<<1U); + MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos)); return HAL_OK; } @@ -1624,14 +1427,15 @@ HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32 * @param AutoRefreshNumber Specifies the auto Refresh number. * @retval None */ -HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, + uint32_t AutoRefreshNumber) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); /* Set the Auto-refresh number in command register */ - Device->SDCMR |= (AutoRefreshNumber << 5U); + MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); return HAL_OK; } @@ -1647,14 +1451,14 @@ HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint */ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) { - uint32_t tmpreg = 0U; + uint32_t tmpreg; /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_SDRAM_BANK(Bank)); /* Get the corresponding bank mode */ - if(Bank == FMC_SDRAM_BANK1) + if (Bank == FMC_SDRAM_BANK1) { tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); } @@ -1675,18 +1479,20 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) * @} */ +#endif /* FMC_Bank5_6 */ + /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ -#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */ /** * @} */ +#endif /* HAL_NOR_MODULE_ENABLED */ +/** + * @} + */ /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c index 8fcb2a1580..04966ea018 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -216,5 +215,3 @@ void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct) #endif /* FMPI2C_CR1_PE */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c index e71224c03e..8172871fa6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c @@ -5,52 +5,52 @@ * @brief FSMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following - * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories: + * functionalities of the Flexible Memory Controller (FSMC) peripheral memories: * + Initialization/de-initialization functions * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### FSMC peripheral features ##### ============================================================================== - [..] The Flexible static memory controller (FSMC) includes two memory controllers: - (+) The NOR/PSRAM memory controller - (+) The NAND/PC Card memory controller - - [..] The FSMC functional block makes the interface with synchronous and asynchronous static - memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: - (+) to translate AHB transactions into the appropriate external device protocol. - (+) to meet the access time requirements of the external memory devices. - - [..] All external memories share the addresses, data and control signals with the controller. - Each external device is accessed by means of a unique Chip Select. The FSMC performs - only one access at a time to an external device. - The main features of the FSMC controller are the following: - (+) Interface with static-memory mapped devices including: - (++) Static random access memory (SRAM). - (++) Read-only memory (ROM). - (++) NOR Flash memory/OneNAND Flash memory. - (++) PSRAM (4 memory banks). - (++) 16-bit PC Card compatible devices. - (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of - data. - (+) Independent Chip Select control for each memory bank. - (+) Independent configuration for each memory bank. + [..] The Flexible memory controller (FSMC) includes following memory controllers: + (+) The NOR/PSRAM memory controller + (+) The NAND/PC Card memory controller + + [..] The FSMC functional block makes the interface with synchronous and asynchronous static + memories and 16-bit PC memory cards. Its main purposes are: + (+) to translate AHB transactions into the appropriate external device protocol + (+) to meet the access time requirements of the external memory devices + + [..] All external memories share the addresses, data and control signals with the controller. + Each external device is accessed by means of a unique Chip Select. The FSMC performs + only one access at a time to an external device. + The main features of the FSMC controller are the following: + (+) Interface with static-memory mapped devices including: + (++) Static random access memory (SRAM) + (++) Read-only memory (ROM) + (++) NOR Flash memory/OneNAND Flash memory + (++) PSRAM (4 memory banks) + (++) 16-bit PC Card compatible devices + (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of + data + (+) Independent Chip Select control for each memory bank + (+) Independent configuration for each memory bank @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -59,27 +59,117 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) /** @defgroup FSMC_LL FSMC Low Layer * @brief FSMC driver modules * @{ */ -#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + +/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants + * @{ + */ + +/* ----------------------- FSMC registers bit mask --------------------------- */ + +#if defined(FSMC_Bank1) +/* --- BCR Register ---*/ +/* BCR register clear mask */ + +/* --- BTR Register ---*/ +/* BTR register clear mask */ +#define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD |\ + FSMC_BTR1_DATAST | FSMC_BTR1_BUSTURN |\ + FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT |\ + FSMC_BTR1_ACCMOD)) + +/* --- BWTR Register ---*/ +/* BWTR register clear mask */ +#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD |\ + FSMC_BWTR1_DATAST | FSMC_BWTR1_BUSTURN |\ + FSMC_BWTR1_ACCMOD)) +#endif /* FSMC_Bank1 */ +#if defined(FSMC_Bank2_3) + +#if defined (FSMC_PCR_PWAITEN) +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCR_PWAITEN | FSMC_PCR_PBKEN | \ + FSMC_PCR_PTYP | FSMC_PCR_PWID | \ + FSMC_PCR_ECCEN | FSMC_PCR_TCLR | \ + FSMC_PCR_TAR | FSMC_PCR_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEM_MEMSET2 | FSMC_PMEM_MEMWAIT2 |\ + FSMC_PMEM_MEMHOLD2 | FSMC_PMEM_MEMHIZ2)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATT_ATTSET2 | FSMC_PATT_ATTWAIT2 |\ + FSMC_PATT_ATTHOLD2 | FSMC_PATT_ATTHIZ2)) +#else +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | \ + FSMC_PCR2_PTYP | FSMC_PCR2_PWID | \ + FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \ + FSMC_PCR2_TAR | FSMC_PCR2_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 |\ + FSMC_PMEM2_MEMHOLD2 | FSMC_PMEM2_MEMHIZ2)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 |\ + FSMC_PATT2_ATTHOLD2 | FSMC_PATT2_ATTHIZ2)) + +#endif /* FSMC_PCR_PWAITEN */ +#endif /* FSMC_Bank2_3 */ +#if defined(FSMC_Bank4) +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR4_CLEAR_MASK ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN | \ + FSMC_PCR4_PTYP | FSMC_PCR4_PWID | \ + FSMC_PCR4_ECCEN | FSMC_PCR4_TCLR | \ + FSMC_PCR4_TAR | FSMC_PCR4_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM4_CLEAR_MASK ((uint32_t)(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 |\ + FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT4_CLEAR_MASK ((uint32_t)(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 |\ + FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4)) + +/* --- PIO4 Register ---*/ +/* PIO4 register clear mask */ +#define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \ + FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4)) + +#endif /* FSMC_Bank4 */ + +/** + * @} + */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup FSMC_LL_Private_Functions +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions * @{ */ -/** @addtogroup FSMC_LL_NORSRAM - * @brief NORSRAM Controller functions +#if defined(FSMC_Bank1) + +/** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions + * @brief NORSRAM Controller functions * @verbatim ============================================================================== @@ -102,7 +192,7 @@ * @{ */ -/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1 +/** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -126,9 +216,12 @@ * @param Init Pointer to NORSRAM Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init) +HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_InitTypeDef *Init) { - uint32_t tmpr = 0U; + uint32_t flashaccess; + uint32_t btcr_reg; + uint32_t mask; /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); @@ -138,92 +231,102 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_ assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#if defined(FSMC_BCR1_WRAPMOD) assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#endif /* FSMC_BCR1_WRAPMOD */ assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal)); assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode)); assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); - assert_param(IS_FSMC_PAGESIZE(Init->PageSize)); -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) - assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo)); +#if defined(FSMC_BCR1_CCLKEN) assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock)); -#endif /* STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */ - - /* Get the BTCR register value */ - tmpr = Device->BTCR[Init->NSBank]; - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT, CPSIZE and CBURSTRW bits */ - tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ - FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \ - FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \ - FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \ - FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW)); - /* Set NORSRAM device control parameters */ - tmpr |= (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WrapMode |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->PageSize |\ - Init->WriteBurst - ); -#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT,CPSIZE, CBURSTRW, CCLKEN and WFDIS bits */ - tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ - FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \ - FSMC_BCR1_WAITPOL | FSMC_BCR1_WAITCFG | FSMC_BCR1_WREN | \ - FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | FSMC_BCR1_ASYNCWAIT | \ - FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW | FSMC_BCR1_CCLKEN | \ - FSMC_BCR1_WFDIS)); +#endif +#if defined(FSMC_BCR1_WFDIS) + assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo)); +#endif /* FSMC_BCR1_WFDIS */ + assert_param(IS_FSMC_PAGESIZE(Init->PageSize)); + + /* Disable NORSRAM Device */ + __FSMC_NORSRAM_DISABLE(Device, Init->NSBank); + /* Set NORSRAM device control parameters */ - tmpr |= (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->WriteBurst |\ - Init->ContinuousClock |\ - Init->PageSize |\ - Init->WriteFifo); -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - - if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR) + if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR) { - tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE; + flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE; + } + else + { + flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE; } - Device->BTCR[Init->NSBank] = tmpr; - -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) + btcr_reg = (flashaccess | \ + Init->DataAddressMux | \ + Init->MemoryType | \ + Init->MemoryDataWidth | \ + Init->BurstAccessMode | \ + Init->WaitSignalPolarity | \ + Init->WaitSignalActive | \ + Init->WriteOperation | \ + Init->WaitSignal | \ + Init->ExtendedMode | \ + Init->AsynchronousWait | \ + Init->WriteBurst); + +#if defined(FSMC_BCR1_WRAPMOD) + btcr_reg |= Init->WrapMode; +#endif /* FSMC_BCR1_WRAPMOD */ +#if defined(FSMC_BCR1_CCLKEN) + btcr_reg |= Init->ContinuousClock; +#endif /* FSMC_BCR1_CCLKEN */ +#if defined(FSMC_BCR1_WFDIS) + btcr_reg |= Init->WriteFifo; +#endif /* FSMC_BCR1_WFDIS */ + btcr_reg |= Init->PageSize; + + mask = (FSMC_BCR1_MBKEN | + FSMC_BCR1_MUXEN | + FSMC_BCR1_MTYP | + FSMC_BCR1_MWID | + FSMC_BCR1_FACCEN | + FSMC_BCR1_BURSTEN | + FSMC_BCR1_WAITPOL | + FSMC_BCR1_WAITCFG | + FSMC_BCR1_WREN | + FSMC_BCR1_WAITEN | + FSMC_BCR1_EXTMOD | + FSMC_BCR1_ASYNCWAIT | + FSMC_BCR1_CBURSTRW); + +#if defined(FSMC_BCR1_WRAPMOD) + mask |= FSMC_BCR1_WRAPMOD; +#endif /* FSMC_BCR1_WRAPMOD */ +#if defined(FSMC_BCR1_CCLKEN) + mask |= FSMC_BCR1_CCLKEN; +#endif +#if defined(FSMC_BCR1_WFDIS) + mask |= FSMC_BCR1_WFDIS; +#endif /* FSMC_BCR1_WFDIS */ + mask |= FSMC_BCR1_CPSIZE; + + MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); + +#if defined(FSMC_BCR1_CCLKEN) /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ - if((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1)) + if ((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1)) { - Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock); + MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN, Init->ContinuousClock); } +#endif +#if defined(FSMC_BCR1_WFDIS) - if(Init->NSBank != FSMC_NORSRAM_BANK1) + if (Init->NSBank != FSMC_NORSRAM_BANK1) { - Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); + /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */ + SET_BIT(Device->BTCR[FSMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); } -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#endif /* FSMC_BCR1_WFDIS */ return HAL_OK; } @@ -235,7 +338,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_ * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); @@ -247,7 +351,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM /* De-initialize the FSMC_NORSRAM device */ /* FSMC_NORSRAM_BANK1 */ - if(Bank == FSMC_NORSRAM_BANK1) + if (Bank == FSMC_NORSRAM_BANK1) { Device->BTCR[Bank] = 0x000030DBU; } @@ -258,12 +362,11 @@ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM } Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; - ExDevice->BWTR[Bank] = 0x0FFFFFFFU; + ExDevice->BWTR[Bank] = 0x0FFFFFFFU; return HAL_OK; } - /** * @brief Initialize the FSMC_NORSRAM Timing according to the specified * parameters in the FSMC_NORSRAM_TimingTypeDef @@ -272,9 +375,12 @@ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr = 0U; +#if defined(FSMC_BCR1_CCLKEN) + uint32_t tmpr; +#endif /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); @@ -287,35 +393,25 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FSMC_NORSRAM_BANK(Bank)); - /* Get the BTCR register value */ - tmpr = Device->BTCR[Bank + 1U]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ - tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \ - FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \ - FSMC_BTR1_ACCMOD)); - /* Set FSMC_NORSRAM device timing parameters */ - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4U) |\ - ((Timing->DataSetupTime) << 8U) |\ - ((Timing->BusTurnAroundDuration) << 16U) |\ - (((Timing->CLKDivision)-1U) << 20U) |\ - (((Timing->DataLatency)-2U) << 24U) |\ - (Timing->AccessMode)); - - Device->BTCR[Bank + 1] = tmpr; - -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) + MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FSMC_BTR1_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FSMC_BTR1_DATAST_Pos) | + ((Timing->BusTurnAroundDuration) << FSMC_BTR1_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos) | + (((Timing->DataLatency) - 2U) << FSMC_BTR1_DATLAT_Pos) | + (Timing->AccessMode))); + +#if defined(FSMC_BCR1_CCLKEN) /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ - if(HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN)) + if (HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN)) { - tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U)); - tmpr |= (uint32_t)(((Timing->CLKDivision)-1U) << 20U); - Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] = tmpr; + tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FSMC_BTR1_CLKDIV_Pos)); + tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos); + MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U], FSMC_BTR1_CLKDIV, tmpr); } -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#endif return HAL_OK; } @@ -325,17 +421,21 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO * @param Device Pointer to NORSRAM device instance * @param Timing Pointer to NORSRAM Timing structure * @param Bank NORSRAM bank number + * @param ExtendedMode FSMC Extended Mode + * This parameter can be one of the following values: + * @arg FSMC_EXTENDED_MODE_DISABLE + * @arg FSMC_EXTENDED_MODE_ENABLE * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) +HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) { - uint32_t tmpr = 0U; - /* Check the parameters */ assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) + if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) { /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device)); @@ -346,20 +446,12 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeD assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FSMC_NORSRAM_BANK(Bank)); - /* Get the BWTR register value */ - tmpr = Device->BWTR[Bank]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */ - tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \ - FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD)); - - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4U) |\ - ((Timing->DataSetupTime) << 8U) |\ - ((Timing->BusTurnAroundDuration) << 16U) |\ - (Timing->AccessMode)); - - Device->BWTR[Bank] = tmpr; + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FSMC_BWTR1_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FSMC_BWTR1_DATAST_Pos) | + Timing->AccessMode | + ((Timing->BusTurnAroundDuration) << FSMC_BWTR1_BUSTURN_Pos))); } else { @@ -400,7 +492,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Devic assert_param(IS_FSMC_NORSRAM_BANK(Bank)); /* Enable write operation */ - Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE; + SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); return HAL_OK; } @@ -418,10 +510,11 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi assert_param(IS_FSMC_NORSRAM_BANK(Bank)); /* Disable write operation */ - Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE; + CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); return HAL_OK; } + /** * @} */ @@ -429,9 +522,11 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi /** * @} */ +#endif /* FSMC_Bank1 */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -/** @addtogroup FSMC_LL_NAND +#if defined(FSMC_Bank2_3) + +/** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions * @brief NAND Controller functions * @verbatim @@ -456,7 +551,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi * @{ */ -/** @addtogroup FSMC_LL_NAND_Private_Functions_Group1 +/** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -482,9 +577,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi */ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) { - uint32_t tmpr = 0U; - /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); assert_param(IS_FSMC_NAND_BANK(Init->NandBank)); assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); @@ -493,40 +587,28 @@ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDe assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); - if(Init->NandBank == FSMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PCR2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PCR3; - } - - /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ - tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \ - FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \ - FSMC_PCR2_TAR | FSMC_PCR2_ECCPS)); - /* Set NAND device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FSMC_PCR_MEMORY_TYPE_NAND |\ - Init->MemoryDataWidth |\ - Init->EccComputation |\ - Init->ECCPageSize |\ - ((Init->TCLRSetupTime) << 9U) |\ - ((Init->TARSetupTime) << 13U)); - - if(Init->NandBank == FSMC_NAND_BANK2) + if (Init->NandBank == FSMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - Device->PCR2 = tmpr; + MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | + FSMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FSMC_PCR2_TCLR_Pos) | + ((Init->TARSetupTime) << FSMC_PCR2_TAR_Pos))); } else { /* NAND bank 3 registers configuration */ - Device->PCR3 = tmpr; + MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | + FSMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FSMC_PCR2_TCLR_Pos) | + ((Init->TARSetupTime) << FSMC_PCR2_TAR_Pos))); } return HAL_OK; @@ -540,47 +622,33 @@ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDe * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr = 0U; - /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); - - if(Bank == FSMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PMEM2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PMEM3; - } - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \ - FSMC_PMEM2_MEMHIZ2)); + assert_param(IS_FSMC_NAND_BANK(Bank)); /* Set FSMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U) - ); - - if(Bank == FSMC_NAND_BANK2) + if (Bank == FSMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - Device->PMEM2 = tmpr; + MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FSMC_PMEM2_MEMHIZ2_Pos))); } else { /* NAND bank 3 registers configuration */ - Device->PMEM3 = tmpr; + MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FSMC_PMEM2_MEMHIZ2_Pos))); } return HAL_OK; @@ -594,47 +662,33 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, F * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr = 0U; - /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); - - if(Bank == FSMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PATT2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PATT3; - } - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \ - FSMC_PATT2_ATTHIZ2)); + assert_param(IS_FSMC_NAND_BANK(Bank)); /* Set FSMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U) - ); - - if(Bank == FSMC_NAND_BANK2) + if (Bank == FSMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - Device->PATT2 = tmpr; + MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FSMC_PATT2_ATTHIZ2_Pos))); } else { /* NAND bank 3 registers configuration */ - Device->PATT3 = tmpr; + MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FSMC_PATT2_ATTHIZ2_Pos))); } return HAL_OK; @@ -648,35 +702,40 @@ HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device */ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) { + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); + assert_param(IS_FSMC_NAND_BANK(Bank)); + /* Disable the NAND Bank */ __FSMC_NAND_DISABLE(Device, Bank); /* De-initialize the NAND Bank */ - if(Bank == FSMC_NAND_BANK2) + if (Bank == FSMC_NAND_BANK2) { /* Set the FSMC_NAND_BANK2 registers to their reset values */ - Device->PCR2 = 0x00000018U; - Device->SR2 = 0x00000040U; - Device->PMEM2 = 0xFCFCFCFCU; - Device->PATT2 = 0xFCFCFCFCU; + WRITE_REG(Device->PCR2, 0x00000018U); + WRITE_REG(Device->SR2, 0x00000040U); + WRITE_REG(Device->PMEM2, 0xFCFCFCFCU); + WRITE_REG(Device->PATT2, 0xFCFCFCFCU); } /* FSMC_Bank3_NAND */ else { /* Set the FSMC_NAND_BANK3 registers to their reset values */ - Device->PCR3 = 0x00000018U; - Device->SR3 = 0x00000040U; - Device->PMEM3 = 0xFCFCFCFCU; - Device->PATT3 = 0xFCFCFCFCU; + WRITE_REG(Device->PCR3, 0x00000018U); + WRITE_REG(Device->SR3, 0x00000040U); + WRITE_REG(Device->PMEM3, 0xFCFCFCFCU); + WRITE_REG(Device->PATT3, 0xFCFCFCFCU); } return HAL_OK; } + /** * @} */ -/** @addtogroup FSMC_LL_NAND_Private_Functions_Group2 +/** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions * @brief management functions * @verbatim @@ -691,27 +750,33 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) * @{ */ + /** * @brief Enables dynamically FSMC_NAND ECC feature. * @param Device Pointer to NAND device instance * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) +HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) { + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); + assert_param(IS_FSMC_NAND_BANK(Bank)); + /* Enable ECC feature */ - if(Bank == FSMC_NAND_BANK2) + if (Bank == FSMC_NAND_BANK2) { - Device->PCR2 |= FSMC_PCR2_ECCEN; + SET_BIT(Device->PCR2, FSMC_PCR2_ECCEN); } else { - Device->PCR3 |= FSMC_PCR3_ECCEN; + SET_BIT(Device->PCR3, FSMC_PCR2_ECCEN); } return HAL_OK; } + /** * @brief Disables dynamically FSMC_NAND ECC feature. * @param Device Pointer to NAND device instance @@ -720,14 +785,18 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank */ HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank) { + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); + assert_param(IS_FSMC_NAND_BANK(Bank)); + /* Disable ECC feature */ - if(Bank == FSMC_NAND_BANK2) + if (Bank == FSMC_NAND_BANK2) { - Device->PCR2 &= ~FSMC_PCR2_ECCEN; + CLEAR_BIT(Device->PCR2, FSMC_PCR2_ECCEN); } else { - Device->PCR3 &= ~FSMC_PCR3_ECCEN; + CLEAR_BIT(Device->PCR3, FSMC_PCR2_ECCEN); } return HAL_OK; @@ -741,9 +810,10 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) +HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; /* Check the parameters */ assert_param(IS_FSMC_NAND_DEVICE(Device)); @@ -753,19 +823,19 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, tickstart = HAL_GetTick(); /* Wait until FIFO is empty */ - while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET) + while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { return HAL_TIMEOUT; } } } - if(Bank == FSMC_NAND_BANK2) + if (Bank == FSMC_NAND_BANK2) { /* Get the ECCR2 register value */ *ECCval = (uint32_t)Device->ECCR2; @@ -782,10 +852,9 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, /** * @} */ +#endif /* FSMC_Bank2_3 */ -/** - * @} - */ +#if defined(FSMC_Bank4) /** @addtogroup FSMC_LL_PCCARD * @brief PCCARD Controller functions @@ -806,13 +875,12 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, FSMC_PCCARD_AttributeSpace_Timing_Init() (+) FSMC PCCARD bank IO space timing configuration using the function FSMC_PCCARD_IOSpace_Timing_Init() - @endverbatim * @{ */ /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1 - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * @verbatim ============================================================================== @@ -837,27 +905,26 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, */ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) { - uint32_t tmpr = 0U; - /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); +#if defined(FSMC_Bank2_3) assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); - - /* Get PCCARD control register value */ - tmpr = Device->PCR4; - - /* Clear TAR, TCLR, PWAITEN and PWID bits */ - tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \ - FSMC_PCR4_PWID | FSMC_PCR4_PTYP)); +#endif /* FSMC_Bank2_3 */ /* Set FSMC_PCCARD device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ - (Init->TCLRSetupTime << 9U) |\ - (Init->TARSetupTime << 13U)); - - Device->PCR4 = tmpr; + MODIFY_REG(Device->PCR4, + (FSMC_PCR4_PTYP | + FSMC_PCR4_PWAITEN | + FSMC_PCR4_PWID | + FSMC_PCR4_TCLR | + FSMC_PCR4_TAR), + (FSMC_PCR_MEMORY_TYPE_PCCARD | + Init->Waitfeature | + FSMC_NAND_PCC_MEM_BUS_WIDTH_16 | + (Init->TCLRSetupTime << FSMC_PCR4_TCLR_Pos) | + (Init->TARSetupTime << FSMC_PCR4_TAR_Pos))); return HAL_OK; } @@ -869,29 +936,24 @@ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_Init * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing) { - uint32_t tmpr = 0U; - /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); +#if defined(FSMC_Bank2_3) assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FSMC_Bank2_3 */ - /* Get PCCARD common space timing register value */ - tmpr = Device->PMEM4; - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \ - FSMC_PMEM4_MEMHIZ4)); /* Set PCCARD timing parameters */ - tmpr |= (uint32_t)((Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - (Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - Device->PMEM4 = tmpr; + MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK, + (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PMEM4_MEMWAIT4_Pos) | + ((Timing->HoldSetupTime) << FSMC_PMEM4_MEMHOLD4_Pos) | + ((Timing->HiZSetupTime) << FSMC_PMEM4_MEMHIZ4_Pos))); return HAL_OK; } @@ -903,29 +965,24 @@ HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Devic * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing) { - uint32_t tmpr = 0U; - /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); +#if defined(FSMC_Bank2_3) assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); - - /* Get PCCARD timing parameters */ - tmpr = Device->PATT4; - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \ - FSMC_PATT4_ATTHIZ4)); +#endif /* FSMC_Bank2_3 */ /* Set PCCARD timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - Device->PATT4 = tmpr; + MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK, + (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PATT4_ATTWAIT4_Pos) | + ((Timing->HoldSetupTime) << FSMC_PATT4_ATTHOLD4_Pos) | + ((Timing->HiZSetupTime) << FSMC_PATT4_ATTHIZ4_Pos))); return HAL_OK; } @@ -937,30 +994,24 @@ HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *De * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing) { - uint32_t tmpr = 0U; - /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); +#if defined(FSMC_Bank2_3) assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); - - /* Get FSMC_PCCARD device timing parameters */ - tmpr = Device->PIO4; - - /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ - tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \ - FSMC_PIO4_IOHIZ4)); +#endif /* FSMC_Bank2_3 */ /* Set FSMC_PCCARD device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - Device->PIO4 = tmpr; + MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, + (Timing->SetupTime | + (Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) | + (Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) | + (Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos))); return HAL_OK; } @@ -972,38 +1023,40 @@ HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, F */ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) { + /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); + /* Disable the FSMC_PCCARD device */ __FSMC_PCCARD_DISABLE(Device); /* De-initialize the FSMC_PCCARD device */ Device->PCR4 = 0x00000018U; - Device->SR4 = 0x00000000U; + Device->SR4 = 0x00000040U; Device->PMEM4 = 0xFCFCFCFCU; Device->PATT4 = 0xFCFCFCFCU; Device->PIO4 = 0xFCFCFCFCU; return HAL_OK; } + /** * @} */ +#endif /* FSMC_Bank4 */ + /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */ -#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */ +#endif /* HAL_NOR_MODULE_ENABLED */ /** * @} */ - /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c index 88f64d8084..8902c4ff31 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -302,4 +301,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_i2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_i2c.c index 125fb2ca13..d25e590130 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_i2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_i2c.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -250,4 +249,3 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c index 780961d58c..9336b5ca82 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -189,12 +188,15 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) uint32_t tmpCFGR; uint32_t tmpCMP; uint32_t tmpARR; + uint32_t primask_bit; uint32_t tmpOR; /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - __disable_irq(); + /* Enter critical section */ + primask_bit = __get_PRIMASK(); + __set_PRIMASK(1) ; /********** Save LPTIM Config *********/ /* Save LPTIM source clock */ @@ -274,7 +276,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) LPTIMx->CFGR = tmpCFGR; LPTIMx->OR = tmpOR; - __enable_irq(); + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); } /** @@ -296,5 +299,3 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_pwr.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_pwr.c index fe04bc44c9..0c6f61e3db 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_pwr.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_pwr.c @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) @@ -81,5 +79,3 @@ ErrorStatus LL_PWR_DeInit(void) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c index 9ef64a2629..f45504b4e7 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) @@ -1660,4 +1658,3 @@ uint32_t RCC_PLLI2S_GetFreqDomain_48M(void) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c index 1b202c9606..333d63ca45 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -62,22 +61,32 @@ */ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) { + ErrorStatus status = SUCCESS; + /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); + if (RNGx == RNG) + { #if !defined(RCC_AHB2_SUPPORT) - /* Enable RNG reset state */ - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG); + /* Enable RNG reset state */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG); - /* Release RNG from reset state */ - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RNG); + /* Release RNG from reset state */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RNG); #else - /* Enable RNG reset state */ - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); + /* Enable RNG reset state */ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); /* Release RNG from reset state */ - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); #endif /* !RCC_AHB2_SUPPORT */ - return (SUCCESS); + } + else + { + status = ERROR; + } + + return status; } /** @@ -100,5 +109,3 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c index 14c3cfa5ca..f3ee3ce016 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -85,11 +84,11 @@ || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \ || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY)) -#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U)) +#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U)) #define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U)) -#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) +#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) #define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \ || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \ @@ -105,14 +104,12 @@ || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \ || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL)) - #define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \ ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY)) #define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \ ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY)) - /** * @} */ @@ -128,7 +125,7 @@ /** * @brief De-Initializes the RTC registers to their default reset values. - * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * @note This function does not reset the RTC Clock source and RTC Backup Data * registers. * @param RTCx RTC Instance * @retval An ErrorStatus enumeration value: @@ -150,21 +147,17 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) { /* Reset TR, DR and CR registers */ LL_RTC_WriteReg(RTCx, TR, 0x00000000U); -#if defined(RTC_WAKEUP_SUPPORT) LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT); -#endif /* RTC_WAKEUP_SUPPORT */ - LL_RTC_WriteReg(RTCx, DR , (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + /* Reset All CR bits except CR[2:0] */ -#if defined(RTC_WAKEUP_SUPPORT) LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL)); -#else - LL_RTC_WriteReg(RTCx, CR, 0x00000000U); -#endif /* RTC_WAKEUP_SUPPORT */ - LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); + + LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U); LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U); - LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U); LL_RTC_WriteReg(RTCx, CALR, 0x00000000U); + LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U); LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U); LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U); @@ -368,7 +361,7 @@ ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Date if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U)) { - RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU; + RTC_DateStruct->Month = (uint8_t)(RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU; } if (RTC_Format == LL_RTC_FORMAT_BIN) { @@ -783,7 +776,7 @@ ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx) * synchronized with RTC APB clock. * @note The RTC Resynchronization mode is write protected, use the * @ref LL_RTC_DisableWriteProtection before calling this function. - * @note To read the calendar through the shadow registers after Calendar + * @note To read the calendar through the shadow registers after calendar * initialization, calendar update or after wakeup from low power modes * the software must first clear the RSF flag. * The software must then wait until it is set again before reading @@ -808,7 +801,7 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) /* Wait the registers to be synchronised */ tmp = LL_RTC_IsActiveFlag_RS(RTCx); - while ((timeout != 0U) && (tmp != 0U)) + while ((timeout != 0U) && (tmp != 1U)) { if (LL_SYSTICK_IsActiveCounterFlag() == 1U) { @@ -821,24 +814,6 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) } } - if (status != ERROR) - { - timeout = RTC_SYNCHRO_TIMEOUT; - tmp = LL_RTC_IsActiveFlag_RS(RTCx); - while ((timeout != 0U) && (tmp != 1U)) - { - if (LL_SYSTICK_IsActiveCounterFlag() == 1U) - { - timeout--; - } - tmp = LL_RTC_IsActiveFlag_RS(RTCx); - if (timeout == 0U) - { - status = ERROR; - } - } - } - return (status); } @@ -861,5 +836,3 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c index e54bab6ef6..fec8ba207d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c @@ -11,6 +11,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### SDMMC peripheral features ##### @@ -142,17 +153,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -177,11 +177,6 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx); -static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout); -static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx); -static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx); -static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx); -static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA); /* Exported functions --------------------------------------------------------*/ @@ -311,10 +306,6 @@ HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) /* Set power state to ON */ SDIOx->POWER = SDIO_POWER_PWRCTRL; - /* 1ms: required power up waiting time before starting the SD initialization - sequence */ - HAL_Delay(2); - return HAL_OK; } @@ -1026,6 +1017,31 @@ uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA) return errorstate; } +/** + * @brief Send the Set Relative Address command to MMC card (not SD card). + * @param SDIOx Pointer to SDIO register base + * @param RCA Card RCA + * @retval HAL status + */ +uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD3 SD_CMD_SET_REL_ADDR */ + sdmmc_cmdinit.Argument = ((uint32_t)RCA << 16U); + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_REL_ADDR, SDIO_CMDTIMEOUT); + + return errorstate; +} + /** * @brief Send the Status command and check the response. * @param SDIOx: Pointer to SDIO register base @@ -1125,47 +1141,54 @@ uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument) } /** - * @} - */ - -/* Private function ----------------------------------------------------------*/ -/** @addtogroup SD_Private_Functions - * @{ - */ - -/** - * @brief Checks for error conditions for CMD0. - * @param hsd: SD handle - * @retval SD Card error state + * @brief Send the Send EXT_CSD command and check the response. + * @param SDIOx Pointer to SDMMC register base + * @param Argument Command Argument + * @retval HAL status */ -static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx) +uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) { - /* 8 is the number of required instructions cycles for the below loop statement. - The SDIO_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); - - do - { - if (count-- == 0U) - { - return SDMMC_ERROR_TIMEOUT; - } + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; - }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT)); + /* Send CMD9 SEND_CSD */ + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); - /* Clear all the static flags */ - __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SEND_EXT_CSD,SDIO_CMDTIMEOUT); - return SDMMC_ERROR_NONE; + return errorstate; } +/** + * @} + */ + +/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions + * @brief Responses functions + * +@verbatim + =============================================================================== + ##### Responses management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed responses. + +@endverbatim + * @{ + */ /** * @brief Checks for error conditions for R1 response. - * @param hsd: SD handle + * @param SDIOx Pointer to SDMMC register base * @param SD_CMD: The sent command index * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout) +uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout) { uint32_t response_r1; uint32_t sta_reg; @@ -1297,10 +1320,10 @@ static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t /** * @brief Checks for error conditions for R2 (CID or CSD) response. - * @param hsd: SD handle + * @param SDIOx Pointer to SDMMC register base * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) +uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) { uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. @@ -1341,10 +1364,10 @@ static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) /** * @brief Checks for error conditions for R3 (OCR) response. - * @param hsd: SD handle + * @param SDIOx Pointer to SDMMC register base * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) +uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) { uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. @@ -1378,13 +1401,13 @@ static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) /** * @brief Checks for error conditions for R6 (RCA) response. - * @param hsd: SD handle + * @param SDIOx Pointer to SDMMC register base * @param SD_CMD: The sent command index * @param pRCA: Pointer to the variable that will contain the SD card relative * address RCA * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA) +uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA) { uint32_t response_r1; uint32_t sta_reg; @@ -1454,10 +1477,10 @@ static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t /** * @brief Checks for error conditions for R7 response. - * @param hsd: SD handle + * @param SDIOx Pointer to SDMMC register base * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) +uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) { uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. @@ -1504,28 +1527,38 @@ static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) } /** - * @brief Send the Send EXT_CSD command and check the response. - * @param SDIOx: Pointer to SDMMC register base - * @param Argument: Command Argument - * @retval HAL status + * @} */ -uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief Checks for error conditions for CMD0. + * @param SDIOx Pointer to SDMMC register base + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx) { - SDIO_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; + /* 8 is the number of required instructions cycles for the below loop statement. + The SDIO_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); - /* Send CMD9 SEND_CSD */ - sdmmc_cmdinit.Argument = Argument; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; - sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; - sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; - (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SEND_EXT_CSD,SDIO_CMDTIMEOUT); + }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT)); - return errorstate; + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); + + return SDMMC_ERROR_NONE; } @@ -1543,5 +1576,3 @@ uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) */ #endif /* SDIO */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_spi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_spi.c index 2fde18057e..02a074068e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_spi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_spi.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -623,4 +622,3 @@ ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c index 089c5adebb..b272b62d95 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1188,4 +1187,3 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c index 150d8bbf62..3cf68e363c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -498,5 +497,4 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c index cdd837da2d..1df5fcf1b6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c @@ -11,6 +11,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -23,17 +34,7 @@ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. @endverbatim - ****************************************************************************** - * @attention - * - *

    © Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

    - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * + ****************************************************************************** */ @@ -82,7 +83,6 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { HAL_StatusTypeDef ret; - if (cfg.phy_itface == USB_OTG_ULPI_PHY) { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); @@ -462,7 +462,7 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf } /** - * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO + * @brief USB_FlushTxFifo Flush a Tx FIFO * @param USBx Selected device * @param num FIFO number * This parameter can be a value from 1 to 15 @@ -473,11 +473,26 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { __IO uint32_t count = 0U; + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush TX Fifo */ + count = 0U; USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -487,7 +502,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) } /** - * @brief USB_FlushRxFifo : Flush Rx FIFO + * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ @@ -495,11 +510,26 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { __IO uint32_t count = 0U; + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush RX Fifo */ + count = 0U; USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -834,8 +864,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; } if (dma == 1U) @@ -943,8 +975,11 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe ep->xfer_len = ep->maxpacket; } + /* Store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); if (dma == 1U) { @@ -961,6 +996,64 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe return HAL_OK; } + +/** + * @brief USB_EPStoptXfer Stop transfer on an EP + * @param USBx usb device instance + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* EP enable, IN data in FIFO */ + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); + } + } + else /* OUT endpoint */ + { + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + } + } + + return ret; +} + + /** * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel @@ -1370,7 +1463,9 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) /* Wait for AHB master IDLE state. */ do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -1382,7 +1477,9 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -1401,6 +1498,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { + HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t i; @@ -1444,8 +1542,15 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c } /* Make sure the FIFOs are flushed. */ - (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ - (void)USB_FlushRxFifo(USBx); + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } /* Clear all pending HC Interrupts */ for (i = 0U; i < cfg.Host_channels; i++) @@ -1486,7 +1591,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - return HAL_OK; + return ret; } /** @@ -1703,6 +1808,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, break; } + /* Enable host channel Halt interrupt */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; + /* Enable the top level host channel interrupt. */ USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); @@ -1736,9 +1844,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; - if (ep_type == EP_TYPE_INTR) + if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) { - USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; } return ret; @@ -1911,7 +2019,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t hcnum = (uint32_t)hc_num; - uint32_t count = 0U; + __IO uint32_t count = 0U; uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; @@ -1932,10 +2040,11 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; do { - if (++count > 1000U) + count++; + + if (count > 1000U) { break; } @@ -1955,10 +2064,11 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; do { - if (++count > 1000U) + count++; + + if (count > 1000U) { break; } @@ -2006,16 +2116,24 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) */ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) { + HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t count = 0U; + __IO uint32_t count = 0U; uint32_t value; uint32_t i; (void)USB_DisableGlobalInt(USBx); - /* Flush FIFO */ - (void)USB_FlushTxFifo(USBx, 0x10U); - (void)USB_FlushRxFifo(USBx); + /* Flush USB FIFO */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } /* Flush out any leftover queued requests. */ for (i = 0U; i <= 15U; i++) @@ -2038,7 +2156,9 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) do { - if (++count > 1000U) + count++; + + if (count > 1000U) { break; } @@ -2051,7 +2171,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) (void)USB_EnableGlobalInt(USBx); - return HAL_OK; + return ret; } /** @@ -2102,5 +2222,3 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c index 96686e1f59..f364a81efe 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -748,5 +747,3 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 9a7ac8de06..4c22d8a0f3 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -4,7 +4,7 @@ * STM32F1: 1.1.8 * STM32F2: 1.2.7 * STM32F3: 1.5.6 - * STM32F4: 1.7.13 + * STM32F4: 1.8.0 * STM32F7: 1.2.10 * STM32G0: 1.4.2 * STM32G4: 1.2.2 From c879a72b3a62973d99645ef1e6de92474c2fa453 Mon Sep 17 00:00:00 2001 From: Alexandre Bourdiol Date: Fri, 8 Apr 2022 14:33:36 +0200 Subject: [PATCH 2/2] system(F4): update STM32F4xx CMSIS Drivers to v2.6.8 Included in STM32CubeF4 FW v1.27.0 Signed-off-by: Alexandre Bourdiol --- .../Device/ST/STM32F4xx/Include/stm32f401xc.h | 17 +- .../Device/ST/STM32F4xx/Include/stm32f401xe.h | 17 +- .../Device/ST/STM32F4xx/Include/stm32f405xx.h | 17 +- .../Device/ST/STM32F4xx/Include/stm32f407xx.h | 77 +- .../Device/ST/STM32F4xx/Include/stm32f410cx.h | 17 +- .../Device/ST/STM32F4xx/Include/stm32f410rx.h | 17 +- .../Device/ST/STM32F4xx/Include/stm32f410tx.h | 17 +- .../Device/ST/STM32F4xx/Include/stm32f411xe.h | 17 +- .../Device/ST/STM32F4xx/Include/stm32f412cx.h | 17 +- .../Device/ST/STM32F4xx/Include/stm32f412rx.h | 19 +- .../Device/ST/STM32F4xx/Include/stm32f412vx.h | 19 +- .../Device/ST/STM32F4xx/Include/stm32f412zx.h | 19 +- .../Device/ST/STM32F4xx/Include/stm32f413xx.h | 19 +- .../Device/ST/STM32F4xx/Include/stm32f415xx.h | 17 +- .../Device/ST/STM32F4xx/Include/stm32f417xx.h | 77 +- .../Device/ST/STM32F4xx/Include/stm32f423xx.h | 19 +- .../Device/ST/STM32F4xx/Include/stm32f427xx.h | 81 +- .../Device/ST/STM32F4xx/Include/stm32f429xx.h | 85 +- .../Device/ST/STM32F4xx/Include/stm32f437xx.h | 81 +- .../Device/ST/STM32F4xx/Include/stm32f439xx.h | 85 +- .../Device/ST/STM32F4xx/Include/stm32f446xx.h | 21 +- .../Device/ST/STM32F4xx/Include/stm32f469xx.h | 89 +- .../Device/ST/STM32F4xx/Include/stm32f479xx.h | 89 +- .../Device/ST/STM32F4xx/Include/stm32f4xx.h | 24 +- .../ST/STM32F4xx/Include/system_stm32f4xx.h | 28 +- .../CMSIS/Device/ST/STM32F4xx/README.md | 23 +- .../Device/ST/STM32F4xx/Release_Notes.html | 3938 +++-------------- .../Templates/gcc/startup_stm32f401xc.s | 16 +- .../Templates/gcc/startup_stm32f401xe.s | 16 +- .../Templates/gcc/startup_stm32f405xx.s | 16 +- .../Templates/gcc/startup_stm32f407xx.s | 15 +- .../Templates/gcc/startup_stm32f410cx.s | 14 +- .../Templates/gcc/startup_stm32f410rx.s | 14 +- .../Templates/gcc/startup_stm32f410tx.s | 14 +- .../Templates/gcc/startup_stm32f411xe.s | 16 +- .../Templates/gcc/startup_stm32f412cx.s | 14 +- .../Templates/gcc/startup_stm32f412rx.s | 14 +- .../Templates/gcc/startup_stm32f412vx.s | 14 +- .../Templates/gcc/startup_stm32f412zx.s | 14 +- .../Templates/gcc/startup_stm32f413xx.s | 14 +- .../Templates/gcc/startup_stm32f415xx.s | 17 +- .../Templates/gcc/startup_stm32f417xx.s | 18 +- .../Templates/gcc/startup_stm32f423xx.s | 14 +- .../Templates/gcc/startup_stm32f427xx.s | 15 +- .../Templates/gcc/startup_stm32f429xx.s | 15 +- .../Templates/gcc/startup_stm32f437xx.s | 16 +- .../Templates/gcc/startup_stm32f439xx.s | 17 +- .../Templates/gcc/startup_stm32f446xx.s | 15 +- .../Templates/gcc/startup_stm32f469xx.s | 17 +- .../Templates/gcc/startup_stm32f479xx.s | 17 +- .../Source/Templates/system_stm32f4xx.c | 12 +- .../Device/ST/STM32F4xx/_htmresc/mini-st.css | 2 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 53 files changed, 1304 insertions(+), 4010 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h index bff24a1bc9..f37c761409 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -8408,7 +8407,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -8640,7 +8639,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F401xC_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h index c22bec9d03..fdb6a532cb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -8408,7 +8407,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -8640,7 +8639,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F401xE_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h index 27fc4685e6..febecd7ca9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -14004,7 +14003,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -14309,7 +14308,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F405xx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h index aca5fb395b..56a7125567 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -13247,7 +13246,7 @@ typedef struct /* Ethernet MMC Registers bits definition */ /******************************************************************************/ -/* Bit definition for Ethernet MMC Contol Register */ +/* Bit definition for Ethernet MMC Control Register */ #define ETH_MMCCR_MCFHP_Pos (5U) #define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */ #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */ @@ -13331,7 +13330,7 @@ typedef struct #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */ -/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ +/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */ #define ETH_MMCRFAECR_RFAEC_Pos (0U) #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */ @@ -13345,34 +13344,37 @@ typedef struct /* Ethernet PTP Registers bits definition */ /******************************************************************************/ -/* Bit definition for Ethernet PTP Time Stamp Contol Register */ +/* Bit definition for Ethernet PTP Time Stamp Control Register */ +#define ETH_PTPTSCR_TSPFFMAE_Pos (18U) +#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */ +#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */ #define ETH_PTPTSCR_TSCNT_Pos (16U) #define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */ #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */ -#define ETH_PTPTSSR_TSSMRME_Pos (15U) -#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */ -#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */ -#define ETH_PTPTSSR_TSSEME_Pos (14U) -#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */ -#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */ -#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U) -#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */ -#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */ -#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U) -#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */ -#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */ -#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U) -#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */ -#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */ -#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U) -#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */ -#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */ -#define ETH_PTPTSSR_TSSSR_Pos (9U) -#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */ -#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */ -#define ETH_PTPTSSR_TSSARFE_Pos (8U) -#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */ -#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */ +#define ETH_PTPTSCR_TSSMRME_Pos (15U) +#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */ +#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */ +#define ETH_PTPTSCR_TSSEME_Pos (14U) +#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */ +#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */ +#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U) +#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */ +#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U) +#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */ +#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U) +#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */ +#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U) +#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */ +#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */ +#define ETH_PTPTSCR_TSSSR_Pos (9U) +#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */ +#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */ +#define ETH_PTPTSCR_TSSARFE_Pos (8U) +#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */ +#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */ #define ETH_PTPTSCR_TSARU_Pos (5U) #define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */ @@ -13452,6 +13454,9 @@ typedef struct /******************************************************************************/ /* Bit definition for Ethernet DMA Bus Mode Register */ +#define ETH_DMABMR_MB_Pos (26U) +#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */ +#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */ #define ETH_DMABMR_AAB_Pos (25U) #define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */ #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */ @@ -15295,7 +15300,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -15600,7 +15605,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F407xx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410cx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410cx.h index 3822e7e93c..dac143a399 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410cx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410cx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -7183,7 +7182,7 @@ typedef struct /********************** TIM Instances : 32 bit Counter ************************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)((INSTANCE) == TIM5) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM5)) @@ -7356,7 +7355,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F410Cx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410rx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410rx.h index 78e26a2eb7..491ddf9acf 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410rx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410rx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -7187,7 +7186,7 @@ typedef struct /********************** TIM Instances : 32 bit Counter ************************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)((INSTANCE) == TIM5) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM5)) @@ -7360,7 +7359,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F410Rx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410tx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410tx.h index 73942356dd..4d9c9fc096 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410tx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410tx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -7137,7 +7136,7 @@ typedef struct /********************** TIM Instances : 32 bit Counter ************************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)((INSTANCE) == TIM5) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM5)) @@ -7305,7 +7304,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F410Tx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h index 6c536b9cb8..6d8efbd248 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -8443,7 +8442,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -8679,7 +8678,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F411xE_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412cx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412cx.h index ce8a5cab17..39ba59d4e6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412cx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412cx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -13221,7 +13220,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -13506,7 +13505,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F412Cx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412rx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412rx.h index 1da909089b..15ab5a3459 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412rx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412rx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -6719,7 +6718,7 @@ typedef struct #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!
    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -6721,7 +6720,7 @@ typedef struct #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!
    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -6725,7 +6724,7 @@ typedef struct #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!
    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -7045,7 +7044,7 @@ typedef struct #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!
    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -14289,7 +14288,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -14594,7 +14593,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F415xx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f417xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f417xx.h index 8ae531ee3a..bc5d0407f6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f417xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f417xx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -13527,7 +13526,7 @@ typedef struct /* Ethernet MMC Registers bits definition */ /******************************************************************************/ -/* Bit definition for Ethernet MMC Contol Register */ +/* Bit definition for Ethernet MMC Control Register */ #define ETH_MMCCR_MCFHP_Pos (5U) #define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */ #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */ @@ -13611,7 +13610,7 @@ typedef struct #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */ -/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ +/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */ #define ETH_MMCRFAECR_RFAEC_Pos (0U) #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */ @@ -13625,34 +13624,37 @@ typedef struct /* Ethernet PTP Registers bits definition */ /******************************************************************************/ -/* Bit definition for Ethernet PTP Time Stamp Contol Register */ +/* Bit definition for Ethernet PTP Time Stamp Control Register */ +#define ETH_PTPTSCR_TSPFFMAE_Pos (18U) +#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */ +#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */ #define ETH_PTPTSCR_TSCNT_Pos (16U) #define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */ #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */ -#define ETH_PTPTSSR_TSSMRME_Pos (15U) -#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */ -#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */ -#define ETH_PTPTSSR_TSSEME_Pos (14U) -#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */ -#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */ -#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U) -#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */ -#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */ -#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U) -#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */ -#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */ -#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U) -#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */ -#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */ -#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U) -#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */ -#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */ -#define ETH_PTPTSSR_TSSSR_Pos (9U) -#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */ -#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */ -#define ETH_PTPTSSR_TSSARFE_Pos (8U) -#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */ -#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */ +#define ETH_PTPTSCR_TSSMRME_Pos (15U) +#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */ +#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */ +#define ETH_PTPTSCR_TSSEME_Pos (14U) +#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */ +#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */ +#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U) +#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */ +#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U) +#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */ +#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U) +#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */ +#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U) +#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */ +#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */ +#define ETH_PTPTSCR_TSSSR_Pos (9U) +#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */ +#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */ +#define ETH_PTPTSCR_TSSARFE_Pos (8U) +#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */ +#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */ #define ETH_PTPTSCR_TSARU_Pos (5U) #define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */ @@ -13732,6 +13734,9 @@ typedef struct /******************************************************************************/ /* Bit definition for Ethernet DMA Bus Mode Register */ +#define ETH_DMABMR_MB_Pos (26U) +#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */ +#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */ #define ETH_DMABMR_AAB_Pos (25U) #define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */ #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */ @@ -15575,7 +15580,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -15880,7 +15885,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F417xx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f423xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f423xx.h index 4dda16fac8..3f06b13afc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f423xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f423xx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -7081,7 +7080,7 @@ typedef struct #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!
    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -7300,7 +7299,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -7359,7 +7358,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -7492,7 +7491,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -7546,7 +7545,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -7093,7 +7092,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -459,7 +458,7 @@ typedef struct uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ - __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ @@ -6826,7 +6825,7 @@ typedef struct #define DSI_LCOLCR_LPE_Pos (8U) #define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */ -#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */ +#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosely Packet Enable */ /******************* Bit definition for DSI_LPCR register ***************/ #define DSI_LPCR_DEP_Pos (0U) @@ -10533,7 +10532,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -460,7 +459,7 @@ typedef struct uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ - __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ @@ -7016,7 +7015,7 @@ typedef struct #define DSI_LCOLCR_LPE_Pos (8U) #define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */ -#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */ +#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosely Packet Enable */ /******************* Bit definition for DSI_LPCR register ***************/ #define DSI_LPCR_DEP_Pos (0U) @@ -10723,7 +10722,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -106,11 +105,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS version number V2.6.7 + * @brief CMSIS version number V2.6.8 */ #define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\ @@ -300,8 +299,3 @@ typedef enum /** * @} */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h index 727a06a0cb..142420a22c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h @@ -6,29 +6,12 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -119,4 +102,3 @@ extern void SystemCoreClockUpdate(void); /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/README.md b/system/Drivers/CMSIS/Device/ST/STM32F4xx/README.md index 6a700c82d3..9270214c43 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/README.md +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/README.md @@ -1,19 +1,21 @@ # STM32CubeF4 CMSIS Device MCU Component +![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_f4.svg?color=brightgreen) + ## Overview **STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. -**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series. - * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product - * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio - * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series - * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ... - * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. + * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. + * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series. + * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library... + * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series. -Two models of publication are proposed for the STM32Cube embedded software : - * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series) - * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions. +Two models of publication are proposed for the STM32Cube embedded software: + * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). + * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. ## Description @@ -34,10 +36,11 @@ Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.1 Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.2 Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.0 Tag v2.6.7 | Tag v5.4.0_cm4 | Tag v1.26.2 +Tag v2.6.8 | Tag v5.4.0_cm4 | Tag v1.27.0 The full **STM32CubeF4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF4). ## Troubleshooting If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_f4/issues/new). -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file +For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/topic/0TO0X000000BSqSWAW/stm32-mcus). \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Release_Notes.html index 0d3164f31b..baa4e1fd9f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Release_Notes.html @@ -1,16 +1,15 @@ - - + + + + - - - Release Notes for STM32F4xx CMSIS - + Release Notes for STM32F4xx CMSIS + + + - - - +


    - +
    - +
    -
    Back + Back to Release page
    -

    Release - Notes for STM32F4xx CMSIS

    -

    Copyright - 2017 STMicroelectronics

    -

    +

    Release + Notes for STM32F4xx CMSIS

    +

    Copyright + 2017 STMicroelectronics

    +

    -

     

    - +

     

    +
    - @@ -4534,5 +1995,4 @@

     

    - - + \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s index bf7305ecdf..7368496c05 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -430,6 +429,3 @@ g_pfnVectors: .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s index 0540671820..6272f36289 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -430,6 +429,3 @@ g_pfnVectors: .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s index 86848cd6aa..e463fb3ffd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -497,6 +496,3 @@ g_pfnVectors: .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s index a3e093260e..714d3c4faa 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -504,5 +503,3 @@ g_pfnVectors: .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s index 5d8a93e166..fdcab8fef2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -431,4 +430,3 @@ g_pfnVectors: .weak LPTIM1_IRQHandler .thumb_set LPTIM1_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s index 6c0f02d5c5..0d86852a3a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -431,4 +430,3 @@ g_pfnVectors: .weak LPTIM1_IRQHandler .thumb_set LPTIM1_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s index 8555cf0edc..bb60d6b52c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -422,4 +421,3 @@ g_pfnVectors: .weak LPTIM1_IRQHandler .thumb_set LPTIM1_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s index 360ff11a88..1b86625e56 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -434,6 +433,3 @@ g_pfnVectors: .weak SPI5_IRQHandler .thumb_set SPI5_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s index 36055237e3..d20795efb6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -505,4 +504,3 @@ g_pfnVectors: .weak FMPI2C1_ER_IRQHandler .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s index 89c9f530d8..1f34976a14 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -508,4 +507,3 @@ g_pfnVectors: .weak FMPI2C1_ER_IRQHandler .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s index c758b95342..45cbf1797e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -508,4 +507,3 @@ g_pfnVectors: .weak FMPI2C1_ER_IRQHandler .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s index 585eee990f..c11f39a943 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -508,4 +507,3 @@ g_pfnVectors: .weak FMPI2C1_ER_IRQHandler .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s index 7bbfb8d943..eeac1ed141 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -564,4 +563,3 @@ g_pfnVectors: .weak DFSDM2_FLT3_IRQHandler .thumb_set DFSDM2_FLT3_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s index 4150581411..871c499a85 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -498,7 +497,3 @@ g_pfnVectors: .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s index 58869ef8c8..2bbdc4e869 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -507,8 +506,3 @@ g_pfnVectors: .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s index cb4a760f00..e15f80752b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -567,4 +566,3 @@ g_pfnVectors: .weak DFSDM2_FLT3_IRQHandler .thumb_set DFSDM2_FLT3_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s index 6362461f11..4024d88346 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -533,5 +532,3 @@ g_pfnVectors: .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s index 359646237b..245231d818 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -539,5 +538,3 @@ g_pfnVectors: .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s index 9df97093a2..ac5dccd55f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -536,6 +535,3 @@ g_pfnVectors: .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s index b30110a6e6..36ed7ac4af 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -544,7 +543,3 @@ Infinite_Loop: .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s index 71077a0982..41fb9f4557 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -534,5 +533,3 @@ g_pfnVectors: .weak FMPI2C1_ER_IRQHandler .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s index ddedd0cafe..d5470fa41f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -548,7 +547,3 @@ Infinite_Loop: .weak DSI_IRQHandler .thumb_set DSI_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s index 27a8ab2c0f..9878def15f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -92,7 +91,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -551,7 +550,3 @@ Infinite_Loop: .weak DSI_IRQHandler .thumb_set DSI_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c index 75660b32a3..d26d96f4c3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c @@ -22,13 +22,12 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -746,4 +745,3 @@ void SystemInit_ExtMemCtl(void) /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/mini-st.css b/system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/mini-st.css index 71fbc14fc2..eb41d56c4d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/mini-st.css +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/_htmresc/mini-st.css @@ -1463,7 +1463,7 @@ mark.tag { /* Definitions for progress elements and spinners. */ -/* Progess module CSS variable definitions */ +/* Progress module CSS variable definitions */ :root { --progress-back-color: #ddd; --progress-fore-color: #555; } diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 883cc31089..364eac3b15 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -4,7 +4,7 @@ * STM32F1: 4.3.3 * STM32F2: 2.2.5 * STM32F3: 2.3.6 - * STM32F4: 2.6.7 + * STM32F4: 2.6.8 * STM32F7: 1.2.7 * STM32G0: 1.4.1 * STM32G4: 1.2.2
    -

    Update History

    -

    V2.6.7 / 16-July-2021

    -     -   Main +     		+

    Update History

    + +

    V2.6.8 / 11-February-2022

    + +     +   Main Changes
    -     + + + +
      + +
    • All source files: update disclaimer to add reference to the new license agreement.
      • + +
    • Correct ETH bits definitions to be in line with naming used in the STM32F4 reference manual documents.
      • +
    +

    V2.6.7 / 16-July-2021

    + +     +   Main + + + Changes
    +
      -
    • Add missing definition +
    • Add missing definition FLASH_CR_ERRIE to the CMSIS header file.
      • -
    • Remove unsupported �GPIOF_BASE� +
    • Remove unsupported �GPIOF_BASE� and �GPIOG_BASE� defines from STM32F412Vx device.
      • -
    • Add new atomic register access +
    • Add new atomic register access macros in stm32f4xx.h file.
      • -
    • Add LSI maximum startup time +
    • Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.
      • -
    • Fix a typo in CMSIS STM32F4xx +
    • Fix a typo in CMSIS STM32F4xx version macro (__STM32F4xx_CMSIS_VERSION).
    -

    V2.6.6 / 12-February-2021

    -     -   Main +

    V2.6.6 / 12-February-2021

    +     +   Main Changes
    -     +
      -
    • system_stm32f4xx.c:
      • +
    • system_stm32f4xx.c:
        • -
      • Protect +
      • Protect Vector @@ -225,10 +158,7 @@ FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS
        • -
      • Update +
      • Update SystemInit_ExtMemCtl() API to initialize @@ -236,181 +166,87 @@ loop condition.
      -
    • Add License.md and +
    • Add License.md and Readme.md files required for GitHub publication
      • -
    • Improve GCC startup +
    • Improve GCC startup files robustness.
      • -
    • Fix wrong value for +
    • Fix wrong value for GPIO_MODER_MODE8_Msk and GPIO_MODER_MODE2_Pos.
      • -
    • Update max number of +
    • Update max number of host channels in FS for STM32F446:
        • -
      • Update +
      • Update USB_OTG_FS_HOST_MAX_CHANNEL_NBR value from 8 to 12.
      -
    • Add SMBDEN and SMBHEN +
    • Add SMBDEN and SMBHEN bit definition for STM32F410Tx device.
    -

    V2.6.5 / 10-February-2020

    -     -   Main +

    V2.6.5 / 10-February-2020

    +     +   Main Changes
    -     +
      -
    • All header files
      • +
    • All header files
        • -
      • Update +
      • Update to use new BSD License format
      -
    • MDK-ARM startup files
      • +
    • MDK-ARM startup files
        • -
      • Update +
      • Update to fix invalid config wizard annotations
    -

    V2.6.4 / 06-December-2019

    -     -   Main +

    V2.6.4 / 06-December-2019

    +     +   Main Changes
    -     +
      -
    • stm32f446xx.h file
      • +
    • stm32f446xx.h file
        • -
      • Update +
      • Update to support HW flow control on UART4 and UART5 instances
      -
    • stm32f412xx.h, stm32f413xx.h and stm32f423xx.h files
      • +
    • stm32f412xx.h, stm32f413xx.h and stm32f423xx.h files
        • -
      • Remove +
      • Remove - unused IS_USB_ALL_INSTANCE() assert macro
        • + unused IS_USB_ALL_INSTANCE() assert macro
      -
    • All header files
      • +
    • All header files
        • -
      • Remove +
      • Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro
      -
    • system_stm32f4xx.c file
      • +
    • system_stm32f4xx.c file
        • -
      • Update +
      • Update SystemInit() API to don't reset RCC @@ -418,150 +254,75 @@
    -

    V2.6.3 / 08-February-2019

    -     -   Main +

    V2.6.3 / 08-February-2019

    +     +   Main Changes
    -     +
      -
    • CRYP:
      • +
    • CRYP:
        • -
      • Update CMSIS +
      • Update CMSIS devices with correct CRYP data input register name: DIN instead of DR
        • -
      • Add Bits +
      • Add Bits definition for CRYP CR ALGOMODE AES GCM/CCM
      -
    • HASH:
      • +
    • HASH:
        • -
      • Update +
      • Update HASH_DIGEST_TypeDef structure: resize the HR register
        • -
      • Remove MDMAT Bits +
      • Remove MDMAT Bits definition
      -
    • TIM:
      • +
    • TIM:
        • -
      • Add requires TIM +
      • Add requires TIM assert macros:
          • -
        • IS_TIM_SYNCHRO_INSTANCE()
          • -
        • IS_TIM_CLOCKSOURCE_TIX_INSTANCE()
          • -
        • IS_TIM_CLOCKSOURCE_ITRX_INSTANCE()
          • +
        • IS_TIM_SYNCHRO_INSTANCE()
          • +
        • IS_TIM_CLOCKSOURCE_TIX_INSTANCE()
          • +
        • IS_TIM_CLOCKSOURCE_ITRX_INSTANCE()
      -
    • RCC
      • +
    • RCC
        • -
      • Add +
      • Add RCC_CSR_BORRSTF bits definition
      -
    • GPIO
      +
    • GPIO
        • -
      • Fix +
      • Fix - GPIO BRR bits definition
        • -
      • Adjust + GPIO BRR bits definition
        • +
      • Adjust the GPIO present on STM32F412 devices
      -
    • SAI
      • +
    • SAI
        • -
      • Fix +
      • Fix - frame length in SAI_xFRCR_FSALL & SAI_xFRCR_FRL bits + frame length in SAI_xFRCR_FSALL & SAI_xFRCR_FRL bits description
      -
    • USB:
      • +
    • USB:
        • -
      • Add +
      • Add missing Bits Definitions in @@ -569,33 +330,15 @@
          -
        • USB_OTG_DOEPMSK_AHBERRM
          • -
        • USB_OTG_DOEPMSK_OTEPSPRM
          • -
        • USB_OTG_DOEPMSK_BERRM
          • -
        • USB_OTG_DOEPMSK_NAKM
          • -
        • USB_OTG_DOEPMSK_NYETM
          • +
        • USB_OTG_DOEPMSK_AHBERRM
          • +
        • USB_OTG_DOEPMSK_OTEPSPRM
          • +
        • USB_OTG_DOEPMSK_BERRM
          • +
        • USB_OTG_DOEPMSK_NAKM
          • +
        • USB_OTG_DOEPMSK_NYETM
        -
      • Add +
      • Add missing Bits Definitions in @@ -603,1616 +346,637 @@
          -
        • USB_OTG_DIEPINT_INEPNM
          • -
        • USB_OTG_DIEPINT_AHBERR
          • -
        • USB_OTG_DOEPINT_OUTPKTERR
          • -
        •  USB_OTG_DOEPINT_NAK
          • -
        • USB_OTG_DOEPINT_STPKTRX
          • +
        • USB_OTG_DIEPINT_INEPNM
          • +
        • USB_OTG_DIEPINT_AHBERR
          • +
        • USB_OTG_DOEPINT_OUTPKTERR
          • +
        •  USB_OTG_DOEPINT_NAK
          • +
        • USB_OTG_DOEPINT_STPKTRX
        -
      • Add +
      • Add missing Bits Definitions in USB_OTG_DCFG register
          • -
        • USB_OTG_DCFG_XCVRDLY
          • -
        • USB_OTG_DCFG_ERRATIM
          • +
        • USB_OTG_DCFG_XCVRDLY
          • +
        • USB_OTG_DCFG_ERRATIM
        -
      • Update +
      • Update USB OTG max number of endpoints (6 FS and 9 HS instead of 5 and 8)
      -
    • I2C/FMPI2C
      • +
    • I2C/FMPI2C
        • -
      • Align +
      • Align - Bit naming for FMPI2C_CR1 register: + Bit naming for FMPI2C_CR1 register: FMPI2C_CR1_DFN--> FMPI2C_CR1_DNF
        • -
      • Add +
      • Add - IS_SMBUS_ALL_INSTANCE() + IS_SMBUS_ALL_INSTANCE() define
      -
    • DFSDM
      • +
    • DFSDM
        • -
      • Align - - - Bit naming for DFSDM_FLTICR register: +
      • Align + + + Bit naming for DFSDM_FLTICR register: DFSDM_FLTICR_CLRSCSDF--> DFSDM_FLTICR_CLRSCDF
      -
    • PWR
      • +
    • PWR
        • -
      • Remove PWR_CSR_WUPP +
      • Remove PWR_CSR_WUPP define: feature not available on STM32F469xx/479xx devices
    -

    V2.6.2 / 06-October-2017

    -     -   Main +

    V2.6.2 / 06-October-2017

    +     +   Main Changes
    -     +
        -
      • Remove Date and - Version from all header files
        • -
      • USB_OTG +
      • Remove Date and + Version from all header files
        • +
      • USB_OTG register clean up: remove duplicated bits definitions
        • -
      • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
        • +
      • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
          • -
        • Remove +
        • Remove BKPSRAM_BASE define: feature not available
        -
      • stm32f405xx.h, stm32f407xx.h files
        • +
      • stm32f405xx.h, stm32f407xx.h files
          • -
        • Rename +
        • Rename HASH_RNG_IRQn to RNG_IRQn: HASH instance not available 
        -
      • stm32f410xx.h, stm32f412xx.h, stm32f413xx.h,  stm32f423xx.h files
        • +
      • stm32f410xx.h, stm32f412xx.h, stm32f413xx.h,  stm32f423xx.h files
          • -
        • Add +
        • Add missing wake-up pins defines
        -
      • stm32f412cx.h files
        • +
      • stm32f412cx.h files
          • -
        •  Add - support of USART3 instance
          • +
        •  Add + support of USART3 instance
    -

    V2.6.1 / 14-February-2017

    -     -   Main +

    V2.6.1 / 14-February-2017

    +     +   Main Changes
    -     +
      -
    • General updates in - header files to support LL drivers
      • +
    • General updates in + header files to support LL drivers
        • -
      • Align +
      • Align Bit naming for RCC_CSR register (ex: RCC_CSR_PADRSTF --> RCC_CSR_PINRSTF)
        • -
      • Add +
      • Add new defines for RCC features support:
          • -
        • RCC +
        • RCC PLLI2S and RCC PLLSAI support
          • -
        • RCC +
        • RCC PLLR I2S clock source and RCC PLLR system clock support
          • -
        • RCC +
        • RCC SAI1A PLL source and RCC SAI1B PLL source support
          • -
        • RCC +
        • RCC AHB2 support
        -
      • Add +
      • Add RCC_DCKCFGR_PLLI2SDIVQ_X and  RCC_DCKCFGR_PLLSAIDIVQ_X bits definition
        • -
      • Add new defines for +
      • Add new defines for RCC_PLLI2SCFGR_RST_VALUE, RCC_PLLSAICFGR_RST_VALUE and - RCC_PLLCFGR_RST_VALUE
        • -
      • Add + RCC_PLLCFGR_RST_VALUE
        • +
      • Add new defines for RTC features support:
          • -
        • RTC +
        • RTC Tamper 2 support
          • -
        • RTC +
        • RTC AF2 mapping support
        -
      • Align +
      • Align Bit naming for RTC_CR and RTC_TAFCR - registers (ex: RTC_CR_BCK --> RTC_CR_BKP)
        • -
      • Add + registers (ex: RTC_CR_BCK --> RTC_CR_BKP)
        • +
      • Add new define to manage RTC backup register number: RTC_BKP_NUMBER
        • -
      • Rename +
      • Rename IS_UART_INSTANCE() macro to IS_UART_HALFDUPLEX_INSTANCE()
        • -
      • Add new defines to check - LIN instance: IS_UART_LIN_INSTANCE
        • -
      • Remove +
      • Add new defines to check + LIN instance: IS_UART_LIN_INSTANCE
        • +
      • Remove USART6 instance from STM32F410Tx header file
        • -
      • Rename +
      • Rename IS_I2S_ALL_INSTANCE_EXT() macro to IS_I2S_EXT_ALL_INSTANCEE()
        • -
      • Add +
      • Add IS_I2S_APB1_INSTANCE() macro to check if I2S instance mapping: API1 or APB2
        • -
      • Remove +
      • Remove SPI_I2S_SUPPORT define for SPI I2S features support: I2S feature is available on all STM32F4xx devices
        • -
      • Add +
      • Add SPI_I2S_FULLDUPLEX_SUPPORT define for STM32F413xx/423xx devices
        • -
      • Align +
      • Align SPI_I2SCFGR bit naming: SPI_I2SCFGR_ASTRTEN bit is missing for STM32F412xx devices
        • -
      • Add +
      • Add - new I2S_APB1_APB2_FEATURE + new I2S_APB1_APB2_FEATURE - define + define for STM32F4xx devices where I2S IP's are splited between RCC APB1 and APB2 - interfaces
        + interfaces
        • -
      • Add new FLASH_SR_RDERR define in FLASH_SR register
        • -
      • Add FLASH_OTP_BASE and  FLASH_OTP_END defnes +
      • Add new FLASH_SR_RDERR define in FLASH_SR register
        • +
      • Add FLASH_OTP_BASE and  FLASH_OTP_END defnes to manage FLASH OPT area
        • -
      • Add +
      • Add bit definitions for ETH_MACDBGR register
        • -
      • Add +
      • Add new defines ADC1_COMMON_BASE and ADC123_COMMON_BASE to replace ADC_BASE define
        • -
      • Add +
      • Add new defines ADC1_COMMON and ADC123_COMMON to replace ADC define
        • -
      • Add +
      • Add new ADC macros: IS_ADC_COMMON_INSTANCE() and IS_ADC_MULTIMODE_MASTER_INSTANCE()
        • -
      • Add +
      • Add new defines for ADC multi mode features support
        • -
      • Add +
      • Add new ADC aliases ADC_CDR_RDATA_MST and ADC_CDR_RDATA_SLV for compatibilities with all STM32 Families
        • -
      • Update +
      • Update TIM CNT and ARR register mask on 32-bits
        • -
      • Add new TIM_OR_TI1_RMP define in TIM_OR register
        • -
      • Add +
      • Add new TIM_OR_TI1_RMP define in TIM_OR register
        • +
      • Add new TIM macros to check TIM feature instance support:
          • -
        • IS_TIM_COUNTER_MODE_SELECT_INSTANCE()
          • -
        • IS_TIM_CLOCK_DIVISION_INSTANCE()
          • -
        • IS_TIM_COMMUTATION_EVENT_INSTANCE()
          • -
        • IS_TIM_OCXREF_CLEAR_INSTANCE()
          • -
        • IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE()
          • -
        • IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE()
          • -
        • IS_TIM_REPETITION_COUNTER_INSTANCE()
          • -
        • IS_TIM_ENCODER_INTERFACE_INSTANCE()
          • -
        • IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE()
          • -
        • IS_TIM_BREAK_INSTANCE()
          • +
        • IS_TIM_COUNTER_MODE_SELECT_INSTANCE()
          • +
        • IS_TIM_CLOCK_DIVISION_INSTANCE()
          • +
        • IS_TIM_COMMUTATION_EVENT_INSTANCE()
          • +
        • IS_TIM_OCXREF_CLEAR_INSTANCE()
          • +
        • IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE()
          • +
        • IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE()
          • +
        • IS_TIM_REPETITION_COUNTER_INSTANCE()
          • +
        • IS_TIM_ENCODER_INTERFACE_INSTANCE()
          • +
        • IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE()
          • +
        • IS_TIM_BREAK_INSTANCE()
        -
      • CAN_IER +
      • CAN_IER register clean up: remove duplicated bit definitions
        • -
      • USB_OTG +
      • USB_OTG register: fix the wrong defined values for USB_OTG_GAHBCFG bits
    -

    V2.6.0 / 04-November-2016

    -     -   Main +

    V2.6.0 / 04-November-2016

    +     +   Main Changes
    -     +
      -
    • Add support of STM32F413xx and STM32F423xx devices 
      • +
    • Add support of STM32F413xx and STM32F423xx devices 
        • -
      • Add +
      • Add - "stm32f413xx.h" and "stm32f423xx.h" + "stm32f413xx.h" and "stm32f423xx.h" - files
        • + files
        -
      • -

        Add +

      • +

        Add - startup files  "startup_stm32f413xx.s" + startup files  "startup_stm32f413xx.s" - and "startup_stm32f423xx.s" + and "startup_stm32f423xx.s" for EWARM, MDK-ARM and SW4STM32 toolchains

        • -
      • Add +
      • Add - Linker files "stm32f413xx_flash.icf", + Linker files "stm32f413xx_flash.icf", - "stm32f413xx_sram.icf", + "stm32f413xx_sram.icf", - "stm32f423xx_flash.icf" + "stm32f423xx_flash.icf" - and "stm32f423xx_sram.icf" + and "stm32f423xx_sram.icf" - used + used within EWARM Workspaces
      -
    • All header files
      • +
    • All header files
        • -
      • Use +
      • Use _Pos and _Mask macro for all Bit - Definitions
        • -
      • Update + Definitions
        • +
      • Update LPTIM_OR Bit Definition
        • -
      • Update +
      • Update the defined frequencies by scale for USB exported constants
        • -
      • Add +
      • Add UID_BASE, FLASHSIZE_BASE and PACKAGE_BASE defines
        • -
      • Add +
      • Add new define DAC_CHANNEL2_SUPPORT to manage DAC channel2 support
        • -
      • Use +
      • Use new DAC1 naming
        • -
      • Rename +
      • Rename PWR_CSR_UDSWRDY define to PWR_CSR_UDRDY in PWR_CSR register
        • -
      • Align +
      • Align Bit naming for EXTI_IMR and EXTI_EMR registers (ex: EXTI_IMR_MR0 --> EXTI_IMR_IM0)
        • -
      • Add +
      • Add new EXTI_IMR_IM define in EXTI_IMR register
        • -
      • Add +
      • Add missing DMA registers definition
        • -
      • Add +
      • Add macro to check SMBUS instance support
      -
    • stm32f412cx.h, stm32f412zx.h, stm32f412vx.h, stm32f412rx.h files
      • +
    • stm32f412cx.h, stm32f412zx.h, stm32f412vx.h, stm32f412rx.h files
        • -
      • Add missing SYSCFG +
      • Add missing SYSCFG register: CFGR2
      -
    • stm32f405xx.h, stm32f407xx.h, stm32f427xx.h, stm32f429xx.h files
      • +
    • stm32f405xx.h, stm32f407xx.h, stm32f427xx.h, stm32f429xx.h files
        • -
      • Remove +
      • Remove HASH_RNG_IRQn in IRQn_Type enumeration
      -
    • stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files
      • +
    • stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files
        • -
      • Remove +
      • Remove I2C FLTR register as not supported
      -
    • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
      • +
    • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
        • -
      • Add +
      • Add missing Bit Definition of ETH_MACDBGR register
      -
    • system_stm32f4xx.c file
      • +
    • system_stm32f4xx.c file
        • -
      • Add +
      • Add APBPrescTable declaration
    -

    V2.5.1 / 28-June-2016

    -     -   Main +

    V2.5.1 / 28-June-2016

    +     +   Main Changes
    -     +
      -
    • stm32f412rx.h, - stm32f412vx.h and - - - stm32f412zx.h files:
      • +
    • stm32f412rx.h, + stm32f412vx.h and + + + stm32f412zx.h files:
        • -
      • -

        Add QSPI1_V2_1L +

      • +

        Add QSPI1_V2_1L define to manage the QSPI DMA2 - limitation
        -

        + limitation
        +

    -

    V2.5.0 / 22-April-2016

    -     -   Main +

    V2.5.0 / 22-April-2016

    +     +   Main Changes
    -     +
      -
    • Add support of STM32F412Cx, STM32F412Rx, STM32F412Vx and STM32F412Zx devices
      • +
    • Add support of STM32F412Cx, STM32F412Rx, STM32F412Vx and STM32F412Zx devices
        • -
      • -

        Add - "stm32f412Cx.h", "stm32f412Rx.h", "stm32f412Vx.h" and "stm32f412Zx.h" files

        +
      • +

        Add + "stm32f412Cx.h", "stm32f412Rx.h", "stm32f412Vx.h" and "stm32f412Zx.h" files

        • -
      • -

        Add startup - files  "startup_stm32f412cx.s", "startup_stm32f412rx.s", "startup_stm32f412vx.s" and - - - "startup_stm32f412zx.s" +

      • +

        Add startup + files  "startup_stm32f412cx.s", "startup_stm32f412rx.s", "startup_stm32f412vx.s" and + + + "startup_stm32f412zx.s" for EWARM, MDK-ARM and SW4STM32 toolchains

        • -
      • Add Linker files "stm32f412cx_flash.icf", "stm32f412cx_sram.icf", "stm32f412rx_flash.icf", "stm32f412rx_sram.icf", "stm32f412vx_flash.icf", "stm32f412vx_sram.icf", "stm32f412zx_flash.icf" and "stm32f412zx_sram.icf" used within EWARM +
      • Add Linker files "stm32f412cx_flash.icf", "stm32f412cx_sram.icf", "stm32f412rx_flash.icf", "stm32f412rx_sram.icf", "stm32f412vx_flash.icf", "stm32f412vx_sram.icf", "stm32f412zx_flash.icf" and "stm32f412zx_sram.icf" used within EWARM Workspaces
      -
    • Header files for all +
    • Header files for all STM32 devices
        • -
      • Remove uint32_t cast +
      • Remove uint32_t cast and keep only Misra Cast (U) to avoid - two types cast duplication
        • -
      • Correct some bits + two types cast duplication
        • +
      • Correct some bits definition to be in line with naming used in the Reference Manual
          • -
        • WWDG_CR_Tx changed - - - to WWDG_CR_T_x
          • -
        • WWDG_CFR_Wx changed - - - to WWDG_CFR_W_x
          • -
        • WWDG_CFR_WDGTBx changed - - - to WWDG_CFR_WDGTB_x
          • +
        • WWDG_CR_Tx changed + + + to WWDG_CR_T_x
          • +
        • WWDG_CFR_Wx changed + + + to WWDG_CFR_W_x
          • +
        • WWDG_CFR_WDGTBx changed + + + to WWDG_CFR_WDGTB_x
      -
    • stm32f407xx.h, - stm32f417xx.h, stm32f427xx.h, +
    • stm32f407xx.h, + stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, - stm32f439xx.h, stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files
      • + stm32f439xx.h, stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files
        -
      • Correct some bits +
      • Correct some bits definition to be in line with naming used in the Reference Manual
          -
        • DCMI_RISR_x changed - - - to DCMI_RIS_x
          • -
        • DCMI_RISR_OVF_RIS - - - changed to DCMI_RIS_OVR_RIS
          • -
        • DCMI_IER_OVF_IE - - - changed to DCMI_IER_OVR_IE
          • +
        • DCMI_RISR_x changed + + + to DCMI_RIS_x
          • +
        • DCMI_RISR_OVF_RIS + + + changed to DCMI_RIS_OVR_RIS
          • +
        • DCMI_IER_OVF_IE + + + changed to DCMI_IER_OVR_IE
      -
    • stm32f427xx.h, +
    • stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, - stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files
      • + stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files
        -
      • Correct some bits +
      • Correct some bits definition to be in line with naming used in the Reference Manual
          • -
        • SAI_xFRCR_FSPO changed +
        • SAI_xFRCR_FSPO changed - to SAI_xFRCR_FSPOL
          • + to SAI_xFRCR_FSPOL
        -
      • Rename +
      • Rename IS_SAI_BLOCK_PERIPH to IS_SAI_ALL_INSTANCE
      -
    • stm32f410cx.h, - stm32f410rx.h, stm32f410tx.h files - - - and stm32f446xx.h
      • +
    • stm32f410cx.h, + stm32f410rx.h, stm32f410tx.h files + + + and stm32f446xx.h
        • -
      • Remove +
      • Remove FMPI2C_CR1_SWRST and FMPI2C_CR1_WUPEN Bit definition for I2C_CR1 register
      -
    • stm32f407xx.h, +
    • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, - stm32f437xx.h, stm32f439xx.h, - stm32f469xx.h, stm32f479xx.h files
      • + stm32f437xx.h, stm32f439xx.h, + stm32f469xx.h, stm32f479xx.h files
        -
      • Add missing bits - definitions for DMA2D_CR, +
      • Add missing bits + definitions for DMA2D_CR, DMA2D_FGPFCCR, DMA2D_BGPFCCR, - DMA2D_OPFCCR registers
        • + DMA2D_OPFCCR registers
      -
    • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
      • +
    • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
        • -
      • Add missing RCC_DCKCFGR register +
      • Add missing RCC_DCKCFGR register in RCC_TypeDef structure
        • -
      • Add +
      • Add missing Bit definition for RCC_DCKCFGR register
      -
    • system_stm32f4xx.c
      +
    • system_stm32f4xx.c
        • -
      • Update +
      • Update SystemInit_ExtMemCtl() API to fix delay - optimization problem with GCC compiler: index variable is + optimization problem with GCC compiler: index variable is declared as volatile 
      -
    • stm32f4xx.h
      • +
    • stm32f4xx.h
        • -
      • Rename +
      • Rename __STM32F4xx_CMSIS_DEVICE_VERSION_xx defines to - __STM32F4_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)
        • + __STM32F4_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)
    - -

    V2.4.3 / 29-January-2016

    -     -   Main + +

    V2.4.3 / 29-January-2016

    +     +   Main Changes
      -
    • -

      Header file for all STM32 devices +

    • +

      Header file for all STM32 devices

        • -
      • Rename +
      • Rename ADC @@ -2222,29 +986,17 @@ by ADC_CSR_OVR1, ADC_CSR_OVR2 and ADC_CSR_OVR3 to be aligned with reference manuals
        • -
      • Add +
      • Add missing bits definitions for DAC : DAC_CR_DMAUDRIE1 and DAC_CR_DMAUDRIE2
        • -
      • Update +
      • Update CMSIS driver to be compliant with MISRA C 2004 rule 10.6
        • -
      • Remove +
      • Remove the double definition of @@ -2252,195 +1004,111 @@ new one for  USB_OTG_HS_MAX_OUT_ENDPOINTS
      -
    • stm32f446xx.h, +
    • stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files 
        • -
      • Change +
      • Change the bit definition value of QUADSPI_CR_FTHRES
      -
    • +
    • stm32f446xx.h, stm32f469xx.h, stm32f479xx.h, stm32f429xx.h, stm32f439xx.h files
        • -
      • Rename +
      • Rename the LTDC_GCR_DTEN to LTDC_GCR_DEN in order to be aligned with the reference manual
        • -
      • Rename +
      • Rename DCMI_MISR bit definitions to DCMI_MIS
        • -
      • Rename +
      • Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
        • -
      • Add +
      • Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers
      -
    • +
    • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f437xx.h files
        • -
      • Rename +
      • Rename DCMI_MISR bit definitions to DCMI_MIS
        • -
      • Rename +
      • Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
        • -
      • Add +
      • Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers
      -
    • +
    • stm32f410cx.h, stm32f410rx.h, stm32f410tx.h files
        • -
      • Update +
      • Update - the + the LPTIM SNGSTRT defined value
      -
    • stm32f427xx.h, +
    • stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, - stm32f439xx.h, stm32f469xx.h, stm32f479xx.h + stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
        • -
      • Rename +
      • Rename the DMA2D_IFSR bit definitions to DMA2D_IFCR
      -
    • stm32f427xx.h, +
    • stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, - stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h + stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files 
        • -
      • Correct +
      • Correct a wrong value of SAI_xCR2_CPL definition bit 
        -
        • +
    -

    V2.4.2 / 13-November-2015

    -

    Main Changes

    +

    V2.4.2 / 13-November-2015

    +

    Main Changes

      -
    • -

      system_stm32f4xx.c file +

    • +

      system_stm32f4xx.c file

        • -
      • update +
      • update SystemInit_ExtMemCtl() @@ -2448,117 +1116,69 @@ possibility of simultaneous use of DATA_IN_ExtSRAM and DATA_IN_ExtSDRAM
      -
    • stm32f4xx.h +
    • stm32f4xx.h file
        • -
      • add +
      • add symbols for STM32F411xC devices
      -
    • stm32f405xx.h, +
    • stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files
        • -
      • add +
      • add FSMC_BCRx_CPSIZE bits definitions
        • -
      • remove +
      • remove FSMC_BWTRx_CLKDIV and FSMC_BWTRx_DATLAT bits definitions
      -
    • stm32f429xx.h, +
    • stm32f429xx.h, stm32f427xx.h, stm32f437xx.h files
        • -
      • add +
      • add FMC_BCRx_CPSIZE bits definitions
        • -
      • remove +
      • remove FMC_BWTRx_CLKDIV and FMC_BWTRx_DATLAT bits definitions
      -
    • stm32f446xx.h, +
    • stm32f446xx.h, stm32f469xx.h and stm32f479xx.h
        • -
      • update +
      • update USB_OTG_GlobalTypeDef registers structure to remove ADP control registers
        • -
      • add +
      • add USB_OTG_DOEPMSK_OTEPSPRM and USB_OTG_DOEPINT_OTEPSPR bits definitions
        • -
      • Remove +
      • Remove ADP related bits definitions
        • -
      • add +
      • add IS_PCD_ALL_INSTANCE() and @@ -2566,734 +1186,320 @@
    -

    V2.4.1 / 09-October-2015

    -

    Main Changes

    +

    V2.4.1 / 09-October-2015

    +

    Main Changes

      -
    • "stm32f469xx.h", +
    • "stm32f469xx.h", "stm32f479xx.h"
        -
      • Update bits definition for +
      • Update bits definition for DSI_WPCR and DSI_TCCR registers
    -

    V2.4.0 / 14-August-2015

    -

    Main Changes

    +

    V2.4.0 / 14-August-2015

    +

    Main Changes

      -
    • -

      Add - - - support of STM32F469xx - and STM32F479xx devices
      +

    • +

      Add + + + support of STM32F469xx + and STM32F479xx devices

        • -
      • -

        Add +

      • +

        Add - "stm32f469xx.h" and "stm32f479xx.h" + "stm32f469xx.h" and "stm32f479xx.h" - files

        + files

        -
      • -

        Add +

      • +

        Add - startup files  "startup_stm32f469xx.s" + startup files  "startup_stm32f469xx.s" - and "startup_stm32f479xx.s" + and "startup_stm32f479xx.s" for EWARM, MDK-ARM and SW4STM32 toolchains

        • -
      • Add +
      • Add - Linker files "stm32f469xx_flash.icf", + Linker files "stm32f469xx_flash.icf", - "stm32f469xx_sram.icf", + "stm32f469xx_sram.icf", - "stm32f479xx_flash.icf" + "stm32f479xx_flash.icf" - and "stm32f479xx_sram.icf" + and "stm32f479xx_sram.icf" - used + used within EWARM Workspaces
      -
    • -

      Add +

    • +

      Add - support of STM32F410xx + support of STM32F410xx devices

        • -
      • -

        Add - - - "stm32f410cx.h", "stm32f410tx.h" - and "stm32f410rx.h" - - - files

        +
      • +

        Add + + + "stm32f410cx.h", "stm32f410tx.h" + and "stm32f410rx.h" + + + files

        -
      • -

        Add +

      • +

        Add - startup files  "startup_stm32f410cx.s", + startup files  "startup_stm32f410cx.s", - "startup_stm32f410rx.s" and "startup_stm32f410tx.s" + "startup_stm32f410rx.s" and "startup_stm32f410tx.s" for EWARM, MDK-ARM and SW4STM32 toolchains

        • -
      • Add - - - Linker files "stm32f410cx_flash.icf", - - - "stm32f410cx_sram.icf", - - - "stm32f410rx_flash.icf", "stm32f410tx_sram.icf", - - - "stm32f410tx_flash.icf",  - and "stm32f410rx_sram.icf" - - - used +
      • Add + + + Linker files "stm32f410cx_flash.icf", + + + "stm32f410cx_sram.icf", + + + "stm32f410rx_flash.icf", "stm32f410tx_sram.icf", + + + "stm32f410tx_flash.icf",  + and "stm32f410rx_sram.icf" + + + used within EWARM Workspaces
    -

    V2.3.2 / 26-June-2015

    -

    Main Changes

    +

    V2.3.2 / 26-June-2015

    +

    Main Changes

      -
    • "stm32f405xx.h", +
    • "stm32f405xx.h", "stm32f407xx.h", "stm32f415xx.h" and "stm32f417xx.h"
        -
      • Update FSMC_BTRx_DATAST +
      • Update FSMC_BTRx_DATAST - and FSMC_BWTRx_DATAST (where x can + and FSMC_BWTRx_DATAST (where x can be 1, 2, 3 and 4) mask on 8bits instead of 4bits
      • -
    • "stm32f427xx.h", +
    • "stm32f427xx.h", "stm32f437xx.h", "stm32f429xx.h" and "stm32f439xx.h"
        -
      • Update the defined mask value - for SAI_xSR_FLVL_2
        • +
      • Update the defined mask value + for SAI_xSR_FLVL_2
      • -
    • "stm32f415xx.h", +
    • "stm32f415xx.h", "stm32f417xx.h", "stm32f437xx.h" and "stm32f439xx.h"
        • -
      • HASH alignement with bits namming +
      • HASH alignement with bits namming used in documentation
            -
          • Rename HASH_IMR_DINIM to +
          • Rename HASH_IMR_DINIM to HASH_IMR_DINIE
            -
          • Rename HASH_IMR_DCIM to +
          • Rename HASH_IMR_DCIM to HASH_IMR_DCIE
            -
          • Rename HASH_STR_NBW to +
          • Rename HASH_STR_NBW to HASH_STR_NBW
        -
        • +
      -
    • system_stm32f4xx.c
      • +
    • system_stm32f4xx.c
        • -
      • Remove __IO on constant table +
      • Remove __IO on constant table declaration
        -
      • Implement workaround to cover +
      • Implement workaround to cover RCC limitation regarding peripheral - enable delay
        • + enable delay
        -
      • SystemInit_ExtMemCtl() +
      • SystemInit_ExtMemCtl() update GPIO configuration when external SDRAM is used 
    - -

    V2.3.1 / 03-April-2015

    - Main Changes + +

    V2.3.1 / 03-April-2015

    + Main Changes
      -
    • -

      Header file for all STM32 devices

      +
    • +

      Header file for all STM32 devices

        -
      • Update SRAM2, SRAM3 and +
      • Update SRAM2, SRAM3 and BKPSRAM Bit-Banding base address defined values
        • -
      • Keep reference to +
      • Keep reference to SRAM3 only for STM32F42xx and STM32F43xx devices
        • -
      • Remove CCMDATARAM_BB_BASE: the +
      • Remove CCMDATARAM_BB_BASE: the CCM Data RAM region is not accessible via Bit-Banding
        • -
      • Update the RTC_PRER_PREDIV_S defined value to 0x00007FFF instead of +
      • Update the RTC_PRER_PREDIV_S defined value to 0x00007FFF instead of 0x00001FFF
    -

    V2.3.0 / 02-March-2015

    -

    Main Changes

    - +

    V2.3.0 / 02-March-2015

    +

    Main Changes

    +
      -
    • -

      Add +

    • +

      Add - support of STM32F446xx + support of STM32F446xx devices

        • -
      • -

        Add +

      • +

        Add "stm32f446xx.h" file

        -
      • -

        Add +

      • +

        Add startup file "startup_stm32f446xx.s" for EWARM, MDK-ARM and TrueSTUDIO toolchains

        • -
      • Add +
      • Add Linker files "stm32f446xx_flash.icf" and "stm32f446xx_sram.icf" used within EWARM Workspaces
      -
    • -

      Header file for all STM32 devices

      +
    • +

      Header file for all STM32 devices

        -
      • Add missing bits +
      • Add missing bits definition in the EXTI IMR, EMR, RTSR, FTSR, SWIER and PR registers
        • -
      • Update +
      • Update RCC_AHB1RSTR_OTGHRST bit definition
        • -
      • Update PWR_CR_VOS - bits definition for STM32F40xx +
      • Update PWR_CR_VOS + bits definition for STM32F40xx - and STM32F41xx + and STM32F41xx devices
        • -
      • -

        update SAI_xCR1_MCKDIV bit +

      • +

        update SAI_xCR1_MCKDIV bit definition

    -

    V2.2.0 / 15-December-2014

    -

    Main Changes

    - +

    V2.2.0 / 15-December-2014

    +

    Main Changes

    +
      -
    • -

      stm32f4xx.h

      +
    • +

      stm32f4xx.h

        -
      • -

        Add new constant definition STM32F4 +

      • +

        Add new constant definition STM32F4

      • -
    • -

      system_stm32f4xx.c
      +

    • +

      system_stm32f4xx.c

        -
      • -

        Fix SDRAM configuration in - SystemInit_ExtMemCtl(): change RowBitsNumber +

      • +

        Fix SDRAM configuration in + SystemInit_ExtMemCtl(): change RowBitsNumber from 11 to 12 (for MT48LC4M32B2 available on STM324x9I_EVAL board)

      • -
    • -

      Header file for all STM32 devices

      +
    • +

      Header file for all STM32 devices

        -
      • -

        Add missing bits definition +

      • +

        Add missing bits definition for CAN, FMC and USB peripherals

        • -
      • -

        GPIO_TypeDef: change the BSRR +

      • +

        GPIO_TypeDef: change the BSRR register definition, the two 16-bits definition BSRRH and BSRRL are merged in a single 32-bits @@ -3302,66 +1508,31 @@

    -

    V2.1.0 / 19-June-2014

    -

    Main Changes

    - - - +

    V2.1.0 / 19-June-2014

    +

    Main Changes

    + + +
      -
    • -

      Add +

    • +

      Add - support of STM32F411xExx + support of STM32F411xExx devices

        • -
      • -

        Add +

      • +

        Add "stm32f411xe.h" file

        -
      • -

        Add +

      • +

        Add startup file "startup_stm32f411xx.s" @@ -3369,48 +1540,26 @@ toolchains

      -
    • -

      All - - - header files

      +
    • +

      All + + + header files

        • -
      • -

        Add +

      • +

        Add missing defines for GPIO LCKR Register

        • -
      • -

        Add defines for - memories base and end addresses: +

      • +

        Add defines for + memories base and end addresses: FLASH, SRAM, BKPSRAM and CCMRAM.

        • -
      • -

        Add +

      • +

        Add the @@ -3421,28 +1570,20 @@

          • -
        • -

          example for STM32F405xx.h

          +
        • +

          example for STM32F405xx.h

    -
    #define +
    #define FMC_IRQn              FSMC_IRQn
    - #define + #define FMC_IRQHandler     @@ -3450,187 +1591,102 @@
          -
        • -

          and for STM32F427xx.h

          +
        • +

          and for STM32F427xx.h

    -
    #define +
    #define FSMC_IRQn            FMC_IRQn
    - #define + #define FSMC_IRQHandler   FMC_IRQHandler
      -
    • "stm32f401xc.h" +
    • "stm32f401xc.h" and "stm32f401xe.h": update to be in line - with latest version of the Reference + with latest version of the Reference - manual
      • + manual
        -
      • Remove +
      • Remove RNG registers structures and the corresponding bit definitions
        • -
      • Remove +
      • Remove any occurrence to RNG (clock enable, clock reset,�)
        • -
      • Add +
      • Add the following bit definition for PWR CR register
          • -
        • #define  PWR_CR_ADCDC1      +
        • #define  PWR_CR_ADCDC1      ((uint32_t)0x00002000)
          -
        • #define  PWR_CR_LPLVDS       +
        • #define  PWR_CR_LPLVDS       - ((uint32_t)0x00000400)     
          • + ((uint32_t)0x00000400)     
          -
        • #define  +
        • #define  PWR_CR_MRLVDS   -    ((uint32_t)0x00000800)     
          • +    ((uint32_t)0x00000800)     
      -
    • "stm32f427xx.h", +
    • "stm32f427xx.h", "stm32f437xx.h", "stm32f429xx.h" and "stm32f439xx.h"
        • -
      • Add +
      • Add a new legacy bit definition for PWR to be in line with latest version of the Reference manual
          • -
        • #define  PWR_CR_LPUDS        PWR_CR_LPLVDS
          • +
        • #define  PWR_CR_LPUDS        PWR_CR_LPLVDS
          -
        • #define  +
        • #define  PWR_CR_MRUDS      PWR_CR_MRLVDS
      -
    • -

      Update startup +

    • +

      Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.10 version

      • -
    • -

      system_stm32f4xx.c

      +
    • +

      system_stm32f4xx.c

        • -
      • Remove +
      • Remove dependency vs. the HAL, to allow using @@ -3638,26 +1694,14 @@ HAL drivers
          • -
        • Include - - - stm32f4xx.h - - - instead of stm32f4xx_hal.h
          • -
        • Add +
        • Include + + + stm32f4xx.h + + + instead of stm32f4xx_hal.h
          • +
        • Add definition @@ -3667,176 +1711,62 @@ stm32f4xx_hal_conf).
        -
      • -

        Use �__IO const� +

      • +

        Use �__IO const� instead of �__I�, to avoid any compilation issue when __cplusplus switch is defined

    -

    V2.0.0 / 18-February-2014

    -

    Main Changes

    - - - +

    V2.0.0 / 18-February-2014

    +

    Main Changes

    + + +
      -
    • Update based on STM32Cube +
    • Update based on STM32Cube specification
      • -
    • This version and later has to be - used only with STM32CubeF4 based development
      • +
    • This version and later has to be + used only with STM32CubeF4 based development
    -

    V1.3.0 / +

    V1.3.0 / 08-November-2013

    -

    Main Changes

    +

    Main Changes

      -
    • -

      Add +

    • +

      Add support - of STM32F401xExx - devices

      + of STM32F401xExx + devices

      • -
    • Update startup files "startup_stm32f401xx.s" for EWARM, MDK-ARM, TrueSTUDIO and +
    • Update startup files "startup_stm32f401xx.s" for EWARM, MDK-ARM, TrueSTUDIO and Ride toolchains: Add SPI4 interrupt handler entry in the vector table
    -

    V1.2.1 / +

    V1.2.1 / 19-September-2013

    -

    Main Changes

    +

    Main Changes

      -
    • -

      system_stm32f4xx.c : Update FMC SDRAM +

    • +

      system_stm32f4xx.c : Update FMC SDRAM configuration (RBURST mode activation)

      • -
    • Update startup files "startup_stm32f427_437xx.s" and "startup_stm32f429_439xx.s"  for +
    • Update startup files "startup_stm32f427_437xx.s" and "startup_stm32f429_439xx.s"  for TrueSTUDIO and Ride toolchains and maintain the old name of startup files for legacy purpose
    -

    V1.2.0 / +

    V1.2.0 / 11-September-2013

    -

    Main Changes

    +

    Main Changes

      -
    • -

      Add +

    • +

      Add support @@ -3844,247 +1774,94 @@ and STM32F401xCxx devices

      • -
    • Update +
    • Update - definition of STM32F427/437xx devices : - extension + definition of STM32F427/437xx devices : + extension of the features to include system clock up to 180MHz, dual bank Flash, reduced STOP Mode current, SAI, PCROP, SDRAM and DMA2D
      • -
    • stm32f4xx.h
      -       +
    • stm32f4xx.h
      +
        -
      • Add the +
      • Add the following device defines :
          • -
        • "#define - STM32F40_41xxx" for all STM32405/415/407/417xx devices
          • -
        • "#define - STM32F427_437xx" for all STM32F427/437xx devices
          • -
        • "#define - STM32F429_439xx" for all STM32F429/439xx devices
          • -
        • "#define - STM32F401xx" for all STM32F401xx devices
          • +
        • "#define + STM32F40_41xxx" for all STM32405/415/407/417xx devices
          • +
        • "#define + STM32F427_437xx" for all STM32F427/437xx devices
          • +
        • "#define + STM32F429_439xx" for all STM32F429/439xx devices
          • +
        • "#define + STM32F401xx" for all STM32F401xx devices
        -
      • Maintain the +
      • Maintain the old device define for legacy purpose
        • -
      • Update IRQ +
      • Update IRQ handler enumeration structure to support all STM32F4xx Family devices.  
      • -
    • Add new startup files "startup_stm32f40_41xxx.s","startup_stm32f427_437xx.s", "startup_stm32f429_439xx.s" and "startup_stm32f401xx.s" for all toolchains and maintain +
    • Add new startup files "startup_stm32f40_41xxx.s","startup_stm32f427_437xx.s", "startup_stm32f429_439xx.s" and "startup_stm32f401xx.s" for all toolchains and maintain the old name for startup files for legacy purpose
      • -
    • system_stm32f4xx.c +
    • system_stm32f4xx.c
        -
      • Update +
      • Update the system configuration to - support all STM32F4xx Family devices. + support all STM32F4xx Family devices.  
    -

    V1.1.0 / +

    V1.1.0 / 11-January-2013

    -

    Main Changes

    +

    Main Changes

      -
    • Official release for STM32F427x/437x +
    • Official release for STM32F427x/437x devices.
      • -
    • stm32f4xx.h
      -       +
    • stm32f4xx.h
      +
        -
      • Update product +
      • Update product define: replace "#define STM32F4XX" by "#define STM32F40XX" for STM32F40x/41x devices
        • -
      •  Add new +
      •  Add new product define: "#define STM32F427X" - for STM32F427x/437x devices.
        • + for STM32F427x/437x devices.
      • -
    • Add new startup files "startup_stm32f427x.s" for all +
    • Add new startup files "startup_stm32f427x.s" for all toolchains
      • -
    • rename startup files "startup_stm32f4xx.s" by "startup_stm32f40xx.s" for all +
    • rename startup files "startup_stm32f4xx.s" by "startup_stm32f40xx.s" for all toolchains
      • -
    • system_stm32f4xx.c +
    • system_stm32f4xx.c
        -
      • Prefetch Buffer +
      • Prefetch Buffer enabled
        • -
      • Add reference +
      • Add reference to STM32F427x/437x devices and STM324x7I_EVAL board
        • -
      • SystemInit_ExtMemCtl() +
      • SystemInit_ExtMemCtl() function
          -
        • Add +
        • Add configuration of missing FSMC address and data lines
          -
        • Change +
        • Change memory type to SRAM instead of PSRAM (PSRAM is available only on STM324xG-EVAL RevA) and update @@ -4095,429 +1872,113 @@
        -

        V1.0.2 / 05-March-2012

        -

        Main Changes

        +

        V1.0.2 / 05-March-2012

        +

        Main Changes

          -
        • All source files: license +
        • All source files: license disclaimer text update and add link to the License file on ST Internet.
        -

        V1.0.1 / 28-December-2011

        -

        Main Changes

        +

        V1.0.1 / 28-December-2011

        +

        Main Changes

          -
        • All source files: update +
        • All source files: update disclaimer to add reference to the new license agreement
          • -
        • stm32f4xx.h
          • +
        • stm32f4xx.h
            • -
          • Correct bit +
          • Correct bit - definition: RCC_AHB2RSTR_HSAHRST changed + definition: RCC_AHB2RSTR_HSAHRST changed - to RCC_AHB2RSTR_HASHRST
            • + to RCC_AHB2RSTR_HASHRST
        -

        V1.0.0 / 30-September-2011

        -

        Main Changes

        +

        V1.0.0 / 30-September-2011

        +

        Main Changes

          -
        • First official release for STM32F40x/41x +
        • First official release for STM32F40x/41x devices
          • -
        • Add startup file for TASKING +
        • Add startup file for TASKING toolchain
          • -
        • system_stm32f4xx.c: +
        • system_stm32f4xx.c: driver's comments update
        -

        V1.0.0RC2 / 26-September-2011

        -

        Main Changes

        +

        V1.0.0RC2 / 26-September-2011

        +

        Main Changes

          -
        • Official version (V1.0.0) - Release Candidate2 for STM32F40x/41x +
        • Official version (V1.0.0) + Release Candidate2 for STM32F40x/41x devices
          • -
        • stm32f4xx.h
          • +
        • stm32f4xx.h
            • -
          • Add define for Cortex-M4 - revision __CM4_REV
            • -
          • Correct RCC_CFGR_PPRE2_DIV16 - bit (in RCC_CFGR register) value +
          • Add define for Cortex-M4 + revision __CM4_REV
            • +
          • Correct RCC_CFGR_PPRE2_DIV16 + bit (in RCC_CFGR register) value to 0x0000E000
            • -
          • Correct some bits +
          • Correct some bits definition to be in line with naming - used in the Reference Manual (RM0090)
            • + used in the Reference Manual (RM0090)
              -
            • GPIO_OTYPER_IDR_x - changed to GPIO_IDR_IDR_x
              • -
            • GPIO_OTYPER_ODR_x - changed to GPIO_ODR_ODR_x
              • -
            • SYSCFG_PMC_MII_RMII - changed to SYSCFG_PMC_MII_RMII_SEL
              • -
            • RCC_APB2RSTR_SPI1 - changed to RCC_APB2RSTR_SPI1RST
              • -
            • DBGMCU_APB1_FZ_DBG_IWDEG_STOP - changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
              • -
            • PWR_CR_PMODE - changed to PWR_CR_VOS
              • -
            • PWR_CSR_REGRDY - changed to PWR_CSR_VOSRDY
              • -
            • Add new define +
            • GPIO_OTYPER_IDR_x + changed to GPIO_IDR_IDR_x
              • +
            • GPIO_OTYPER_ODR_x + changed to GPIO_ODR_ODR_x
              • +
            • SYSCFG_PMC_MII_RMII + changed to SYSCFG_PMC_MII_RMII_SEL
              • +
            • RCC_APB2RSTR_SPI1 + changed to RCC_APB2RSTR_SPI1RST
              • +
            • DBGMCU_APB1_FZ_DBG_IWDEG_STOP + changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
              • +
            • PWR_CR_PMODE + changed to PWR_CR_VOS
              • +
            • PWR_CSR_REGRDY + changed to PWR_CSR_VOSRDY
              • +
            • Add new define RCC_AHB1ENR_CCMDATARAMEN
              • -
            • Add new - defines SRAM2_BASE, CCMDATARAM_BASE - and BKPSRAM_BASE
              • +
            • Add new + defines SRAM2_BASE, CCMDATARAM_BASE + and BKPSRAM_BASE
            -
          • GPIO_TypeDef structure: in the +
          • GPIO_TypeDef structure: in the comment change AFR[2] address - mapping to 0x20-0x24 - instead of 0x24-0x28
            • + mapping to 0x20-0x24 + instead of 0x24-0x28
          -
        • system_stm32f4xx.c
          • +
        • system_stm32f4xx.c
            • -
          • SystemInit(): add code +
          • SystemInit(): add code to enable the FPU
            • -
          • SetSysClock(): change +
          • SetSysClock(): change PWR_CR_PMODE - by PWR_CR_VOS
            • -
          • SystemInit_ExtMemCtl(): + by PWR_CR_VOS
            • +
          • SystemInit_ExtMemCtl(): remove commented values
          -
        • startup (for all compilers)
          • +
        • startup (for all compilers)
            • -
          • Delete code used to enable the +
          • Delete code used to enable the FPU (moved to system_stm32f4xx.c file)
            • -
          • File�s header updated
            • +
          • File�s header updated
        -

        V1.0.0RC1 / 25-August-2011

        -

        Main Changes

        +

        V1.0.0RC1 / 25-August-2011

        +

        Main Changes

          -
        • Official version (V1.0.0) - Release Candidate1 for STM32F4xx devices
          • +
        • Official version (V1.0.0) + Release Candidate1 for STM32F4xx devices
        - +
          -
        -

        License

        -
        - Redistribution and use in source and - binary forms, with or without - modification, are permitted provided that - the following conditions are met:
        -         -
          -
        1. Redistributions - - - of source code must retain the above - copyright notice, this list of - conditions and the following - disclaimer.
          2. -
        2. Redistributions -in - - - binary form must reproduce the above - copyright notice, this list of - conditions and the following - disclaimer in the - - - documentation and/or other materials - provided with the distribution.
          3. -
        3. Neither - - - the name of STMicroelectronics nor the - names of its contributors may be used - to endorse or promote products derived -
          -
          4. -
        -        - - - from this software without specific prior - written permission.
        -
        - THIS - - - SOFTWARE IS PROVIDED BY THE COPYRIGHT - HOLDERS AND CONTRIBUTORS "AS IS" AND ANY - EXPRESS OR IMPLIED - WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - THE IMPLIED WARRANTIES OF MERCHANTABILITY - AND FITNESS FOR A PARTICULAR - - - PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, - - - INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, - OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - NOT LIMITED TO, PROCUREMENT - - - OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF LIABILITY, - WHETHER IN CONTRACT, STRICT LIABILITY, OR - TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - - - ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE.         -
        - -
        -
        -

        For - complete documentation on STM32 - Microcontrollers visit www.st.com/STM32

        +
      +
      +
      +

      For + complete documentation on STM32 + Microcontrollers visit www.st.com/STM32