diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c
index bba8f76e5e..4f20c0c778 100644
--- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c
+++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c
@@ -6,6 +6,8 @@
#include "stm32g0xx_hal_smbus_ex.c"
#elif STM32G4xx
#include "stm32g4xx_hal_smbus_ex.c"
+#elif STM32H7xx
+ #include "stm32h7xx_hal_smbus_ex.c"
#elif STM32L0xx
#include "stm32l0xx_hal_smbus_ex.c"
#elif STM32L4xx
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h
index 12e10e68f6..65529a4d38 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h
@@ -2757,6 +2757,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -20348,9 +20351,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -20364,6 +20364,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
+
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h
index cad69ba9ae..3fbdf5fb6c 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h
@@ -2758,6 +2758,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -20360,9 +20363,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -20376,6 +20376,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
+
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h
index 76807b38d2..1fd058d514 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h
@@ -2892,6 +2892,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -20835,9 +20838,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -20851,6 +20851,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
+
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h
index 1022f7ad36..222189a02b 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h
@@ -2893,6 +2893,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -20847,9 +20850,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -20863,6 +20863,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
+
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h
index a83664a43e..0fc670418c 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h
@@ -2892,6 +2892,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -20835,9 +20838,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -20851,6 +20851,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
+
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h735xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h735xx.h
index 700a8135d6..d6db2f3cf4 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h735xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h735xx.h
@@ -2893,6 +2893,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -20847,9 +20850,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -20863,6 +20863,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
+
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h742xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h742xx.h
index 08cc803bf8..ae61fe53f9 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h742xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h742xx.h
@@ -2675,6 +2675,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
index 2608fa63d2..cf2c2d3344 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2017 STMicroelectronics.
+ * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -2770,6 +2770,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xg.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xg.h
index 06c625274e..1acef94563 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xg.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xg.h
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -2864,6 +2864,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xx.h
index 569a033419..daa5331c14 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xx.h
@@ -2864,6 +2864,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xg.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xg.h
index 527b2880fc..1ffe2276bd 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xg.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xg.h
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2021 STMicroelectronics.
+ * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -2947,6 +2947,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h
index d4da9235b5..248396add4 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h
@@ -2947,6 +2947,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h
index 1b0c353e2c..f7d5a6a513 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2018 STMicroelectronics.
+ * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -2846,6 +2846,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h
index 747f2c5148..ffd93852d4 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2017 STMicroelectronics.
+ * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -2846,6 +2846,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h755xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h755xx.h
index 05cefe8617..a771cce799 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h755xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h755xx.h
@@ -2940,6 +2940,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h757xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h757xx.h
index 5d3cbef8eb..20031074f4 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h757xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h757xx.h
@@ -3023,6 +3023,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h
index 2eee9a6854..63c4fd399a 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h
@@ -2653,6 +2653,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -18677,9 +18680,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -18693,6 +18693,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
+
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xxq.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xxq.h
index 5fe69d7381..a54a5b0f46 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xxq.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xxq.h
@@ -2654,6 +2654,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -18689,9 +18692,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -18705,6 +18705,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
+
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xx.h
index 71e6293ea9..2085bf37c7 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xx.h
@@ -2788,6 +2788,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -19157,9 +19160,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -19173,6 +19173,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
+
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xxq.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xxq.h
index 15f7011f5e..a020cbea59 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xxq.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xxq.h
@@ -2789,6 +2789,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -19169,9 +19172,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -19185,6 +19185,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
+
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xx.h
index ede38618f3..c99101f784 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xx.h
@@ -2788,6 +2788,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -19164,9 +19167,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -19180,6 +19180,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
+
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xxq.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xxq.h
index b70617161e..e0be69cf9e 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xxq.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xxq.h
@@ -2789,6 +2789,9 @@ typedef struct
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos (12U)
+#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */
+#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
@@ -19176,9 +19179,6 @@ typedef struct
#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
#define OCTOSPI_DCR1_CSHT_Pos (8U)
#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
@@ -19192,6 +19192,11 @@ typedef struct
#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
+
/**************** Bit definition for OCTOSPI_DCR2 register ******************/
#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
index 20151da61e..c3774c66a3 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
@@ -102,11 +102,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.10.1
+ * @brief CMSIS Device version number V1.10.2
*/
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/License.md b/system/Drivers/CMSIS/Device/ST/STM32H7xx/License.md
index 008472d5ab..479c4f6826 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/License.md
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/License.md
@@ -1 +1,27 @@
-License.md file kept for legacy purpose
\ No newline at end of file
+Copyright 2017 STMicroelectronics.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors
+may be used to endorse or promote products derived from this software without
+specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Release_Notes.html
index 8f90e81079..91fad24350 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Release_Notes.html
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Release_Notes.html
@@ -5,39 +5,49 @@
<meta name="generator" content="pandoc" />
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
<title>Release Notes for STM32H7xx CMSIS</title>
- <style>
- code{white-space: pre-wrap;}
- span.smallcaps{font-variant: small-caps;}
- span.underline{text-decoration: underline;}
- div.column{display: inline-block; vertical-align: top; width: 50%;}
- div.hanging-indent{margin-left: 1.5em; text-indent: -1.5em;}
- ul.task-list{list-style: none;}
- .display.math{display: block; text-align: center; margin: 0.5rem auto;}
+ <style type="text/css">
+ code{white-space: pre-wrap;}
+ span.smallcaps{font-variant: small-caps;}
+ span.underline{text-decoration: underline;}
+ div.column{display: inline-block; vertical-align: top; width: 50%;}
</style>
- <link rel="stylesheet" href="_htmresc/mini-st.css" />
+ <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
<!--[if lt IE 9]>
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
<![endif]-->
+ <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
</head>
<body>
<div class="row">
<div class="col-sm-12 col-lg-4">
-<div class="card fluid">
-<div class="sectione dark">
<center>
-<h1 id="release-notes-for-stm32h7xx-cmsis"><strong>Release Notes for STM32H7xx CMSIS</strong></h1>
+<h1 id="release-notes-for-stm32h7xx-cmsis">Release Notes for <mark> STM32H7xx CMSIS </mark></h1>
<p>Copyright © 2017 STMicroelectronics<br />
</p>
-<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
</center>
</div>
+<div class="col-sm-12 col-lg-8">
+<h1 id="update-history"><strong>Update History</strong></h1>
+<div class="collapse">
+<input type="checkbox" id="collapse-section14" checked aria-hidden="true"> <label for="collapse-section14" aria-hidden="true"><strong>V1.10.2 / 12-February-2022</strong></label>
+<div>
+<h2 id="main-changes">Main Changes</h2>
+<ul>
+<li>General updates to fix known defects and implementation enhancements</li>
+<li>Add support for ADC LDO output voltage ready bit.</li>
+<li>Remove useless OCTOSPI_DCR1_CKCSHT definition: alignment with the reference manual</li>
+<li>All system_stm32h7xx.c template files
+<ul>
+<li>Update VTOR configuration to be modified by user</li>
+</ul></li>
+</ul>
</div>
</div>
-<section id="update-history" class="col-sm-12 col-lg-8">
-<h1><strong>Update History</strong></h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section13" checked aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.10.1 / 06-December-2021</strong></label>
-<h2 id="main-changes">Main Changes</h2>
+<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.10.1 / 06-December-2021</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>All source files: update disclaimer to add reference to the new license agreement.</li>
@@ -59,9 +69,11 @@ <h2 id="main-changes">Main Changes</h2>
</ul></li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.10.0 / 12-February-2021</strong></label>
-<h2 id="main-changes-1">Main Changes</h2>
+<div>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>Fix minor issues related to English typo in comments of registers and fields description</li>
<li>Update STM32H7 devices header files to add GPV registers definition, base address and instance</li>
@@ -75,33 +87,35 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Update MDK-ARM template scatter files for dual core devices to fix a typo within the IRAM1 section</li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label>
-<h2 id="main-changes-2">Main Changes</h2>
+<div>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
-<li><p>Add support of stm32h723xx, stm32h725xx, stm32h733xx, stm32h735xx, stm32h730xx and stm32h730xxQ devices:</p>
+<li>Add support of stm32h723xx, stm32h725xx, stm32h733xx, stm32h735xx, stm32h730xx and stm32h730xxQ devices:
<ul>
<li>Add “stm32h723xx.h” , “stm32h725xx.h”, “stm32h733xx.h”, “stm32h735xx.h”, “stm32h730xx.h” and “stm32h730xxq.h” files</li>
<li>Add startup files “startup_stm32h723xx.s”, “startup_stm32h725xx.s”, “startup_stm32h733xx.s”, “startup_stm32h735xx.s”, “startup_stm32h730xx.s” and “startup_stm32h730xxq.s” for EWARM , MDK-ARM and GCC toolchains</li>
<li>Add part numbers list to stm32h7xx.h header file:
<ul>
-<li><p>STM32H723xx: STM32H723VGH6, STM32H723VGT6, STM32H723ZGI6, STM32H723ZGT6, STM32H723VET6, STM32H723VEH6, STM32H723ZET6, STM32H723ZEI6 Devices</p></li>
-<li><p>STM32H725xx: STM32H725AGI6, STM32H725IGK6, STM32H725IGT6, STM32H725RGV6, STM32H725VGT6, STM32H725VGY6, STM32H725ZGT6, STM32H725REV6, SM32H725VET6, STM32H725ZET6, STM32H725AEI6, STM32H725IET6, STM32H725IEK6 Devices</p></li>
-<li><p>STM32H733xx: STM32H733VGH6, STM32H733VGT6, STM32H733ZGI6, STM32H733ZGT6, Devices</p></li>
-<li><p>STM32H735xx: STM32H735AGI6, STM32H735IGK6, STM32H735RGV6, STM32H735VGT6, STM32H735VGY6, STM32H735ZGT6 Devices</p></li>
-<li><p>STM32H730xx: STM32H730VBH6, STM32H730VBT6, STM32H730ZBT6, STM32H730ZBI6 Devices</p></li>
+<li>STM32H723xx: STM32H723VGH6, STM32H723VGT6, STM32H723ZGI6, STM32H723ZGT6, STM32H723VET6, STM32H723VEH6, STM32H723ZET6, STM32H723ZEI6 Devices</li>
+<li>STM32H725xx: STM32H725AGI6, STM32H725IGK6, STM32H725IGT6, STM32H725RGV6, STM32H725VGT6, STM32H725VGY6, STM32H725ZGT6, STM32H725REV6, SM32H725VET6, STM32H725ZET6, STM32H725AEI6, STM32H725IET6, STM32H725IEK6 Devices</li>
+<li>STM32H733xx: STM32H733VGH6, STM32H733VGT6, STM32H733ZGI6, STM32H733ZGT6, Devices</li>
+<li>STM32H735xx: STM32H735AGI6, STM32H735IGK6, STM32H735RGV6, STM32H735VGT6, STM32H735VGY6, STM32H735ZGT6 Devices</li>
+<li>STM32H730xx: STM32H730VBH6, STM32H730VBT6, STM32H730ZBT6, STM32H730ZBI6 Devices</li>
<li><p>STM32H730xxQ: STM32H730IBT6Q, STM32H730ABI6Q, STM32H730IBK6Q Devices</p></li>
-<li><p>Add EWARM STM32H723xx, STM32H725xx, STM32H733xx, STM32H735xx, STM32H730xx and STM32H730xxQ devices linker files (1MB flash) for EWARM toolchain</p></li>
+<li>Add EWARM STM32H723xx, STM32H725xx, STM32H733xx, STM32H735xx, STM32H730xx and STM32H730xxQ devices linker files (1MB flash) for EWARM toolchain</li>
<li><p>Add EWARM STM32H723xE and STM32H725xE devices linker files (<strong>Subset 512KB flash</strong>) for EWARM toolchain</p></li>
</ul></li>
<li>Note : <strong>stm32h730xx</strong> and <strong>stm32h730xxQ</strong> are <strong>Value line</strong> devices with 128KB flash:</li>
</ul></li>
-<li><p>Update STM32H7 devices header files:</p>
+<li>Update STM32H7 devices header files:
<ul>
<li>Fix FDCAN_ECR_TEC_Msk definition (8 bits bit field instead of 4)</li>
<li>Fix IS_SMBUS_INSTANCE macro definition with the right instances list for each STM32H7 line</li>
</ul></li>
-<li><p>Update system_stm32h7xx.c, system_stm32h7xx_dualcore_boot_cm4_cm7.c, system_stm32h7xx_dualcore_bootcm4_cm7gated.c, system_stm32h7xx_dualcore_bootcm7_cm4gated.c and system_stm32h7xx_singlecore.c files to:</p>
+<li>Update system_stm32h7xx.c, system_stm32h7xx_dualcore_boot_cm4_cm7.c, system_stm32h7xx_dualcore_bootcm4_cm7gated.c, system_stm32h7xx_dualcore_bootcm7_cm4gated.c and system_stm32h7xx_singlecore.c files to:
<ul>
<li>Add Flash latency settings depending of the previous CPU frequency (Increasing or decreasing the CPU frequency)<br />
</li>
@@ -112,28 +126,30 @@ <h2 id="main-changes-2">Main Changes</h2>
</li>
</ul></li>
</ul></li>
-<li><p>Update system_stm32h7xx.c, system_stm32h7xx_dualcore_boot_cm4_cm7.c, system_stm32h7xx_dualcore_bootcm4_cm7gated.c and system_stm32h7xx_dualcore_bootcm7_cm4gated.c to:</p>
+<li>Update system_stm32h7xx.c, system_stm32h7xx_dualcore_boot_cm4_cm7.c, system_stm32h7xx_dualcore_bootcm4_cm7gated.c and system_stm32h7xx_dualcore_bootcm7_cm4gated.c to:
<ul>
<li>Use D2_AXISRAM_BASE for Coretx-M4 VTOR when executing from RAM instead of D2_AHBSRAM_BASE
<ul>
<li>Note: both addresses are aliases to the same D2 domain physical RAM. D2_AXISRAM_BASE (<span class="citation" data-cites="0x10000000">@0x10000000</span>) gives access to the RAM with access using Instruction bus (I), where D2_AHBSRAM_BASE(<span class="citation" data-cites="0x30000000">@0x30000000</span>) gives access to the RAM with access using Data bus. thus when executing from this D2 RAM it is recommended to use D2_AXISRAM_BASE alias so the execution scheme respects the Harvard architecture (One bus for data and one bus for instructions).</li>
</ul></li>
</ul></li>
-<li><p>Update system_stm32h7xx.c and system_stm32h7xx_dualcore_boot_cm4_cm7.c to:</p>
+<li>Update system_stm32h7xx.c and system_stm32h7xx_dualcore_boot_cm4_cm7.c to:
<ul>
<li>Fix usage of SCB->SCR register: SEVONPEND enabled so that an interrupt generated by the other CPU triggers an event and wakes up the current CPU after a WFI/WFE instruction even if the interrupt is disabled</li>
</ul></li>
-<li><p>Add EWARM, linker files for STM32H742xG and STM32H743xG devices coming with 1MB flash: 512KB for each bank</p></li>
+<li>Add EWARM, linker files for STM32H742xG and STM32H743xG devices coming with 1MB flash: 512KB for each bank</li>
<li><p>Add EWARM, MDK-ARM and GCC linker files for STM32H745xG and STM32H747xG devices coming with 1MB flash: 512KB for each bank</p></li>
-<li><p>Update GCC startup files for all devices to align sequence to EWARM/MDK-ARM by calling “SystemInit” prior to any memory access</p>
+<li>Update GCC startup files for all devices to align sequence to EWARM/MDK-ARM by calling “SystemInit” prior to any memory access
<ul>
<li>Allowing to avoid issues when using external memories</li>
</ul></li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label>
-<h2 id="main-changes-3">Main Changes</h2>
+<div>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>General updates to align Bits and registers definitions with the STM32H7 reference manual</li>
<li>Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero</li>
@@ -150,12 +166,14 @@ <h2 id="main-changes-3">Main Changes</h2>
</ul></li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
-<h2 id="main-changes-4">Main Changes</h2>
+<div>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li><p>General updates to align Bit and registers definition with the STM32H7 reference manual</p></li>
-<li><p>Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices:</p>
+<li>Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices:
<ul>
<li>Add “stm32h7a3xx.h”, “stm32h7a3xxq.h”, “stm32h7b3xx.h”, “stm32h7b3xxq.h”, “stm32h7b0xx.h” and “stm32h7b0xxq.h” files</li>
<li>Add startup files “startup_stm32h7a3xx.s”, “startup_stm32h7a3xxq.s”, “startup_stm32h7b3xx.s”, “startup_stm32h7b3xxq.s”, “startup_stm32h7b0xx.s” and “startup_stm32h7b0xxq.s” for EWARM , MDK-ARM and STM32CubeIDE toolchains</li>
@@ -168,19 +186,21 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>STM32H7B0xx : STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ</li>
</ul></li>
</ul></li>
-<li><p>Update DMA2D bits definitions: Update to support Line offset mode and swap bytes features</p>
+<li>Update DMA2D bits definitions: Update to support Line offset mode and swap bytes features
<ul>
<li>Add CR_LOM (Line Ofset Mode) bit definition, Add OPFCCR_SB (Swap Bytes) bit definition</li>
<li>Update CR_MODE, FGOR_LO, BGOR_LO and OOR_LO bit definition</li>
</ul></li>
-<li><p>Update USB_OTG_GAHBCFG bit definition: to be aligned with LL_USB usage</p></li>
+<li>Update USB_OTG_GAHBCFG bit definition: to be aligned with LL_USB usage</li>
<li><p>Add USB_OTG_DOEPMSK_AHBERRM, USB_OTG_DOEPMSK_BERRM, USB_OTG_DOEPMSK_NAKM, USB_OTG_DOEPMSK_NYETM, USB_OTG_DIEPINT_AHBERR, USB_OTG_DIEPINT_INEPNM, USB_OTG_DOEPINT_AHBERR, USB_OTG_DOEPINT_OUTPKTERR, USB_OTG_DOEPINT_BERR, USB_OTG_DOEPINT_NAK and USB_OTG_DOEPINT_STPKTRX bit definitions</p></li>
<li><p>Update IS_TIM_REMAP_INSTANCE and IS_TIM_SYNCHRO_INSTANCE macro implementation</p></li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
-<h2 id="main-changes-5">Main Changes</h2>
+<div>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices</li>
<li>Add definition of “ART” instance: pointer to “ART_TypeDef” structure</li>
@@ -191,9 +211,11 @@ <h2 id="main-changes-5">Main Changes</h2>
<li>Remove useless definition of “SDMMC” instance (keep only definitions of “SDMMC1” and “SDMMC2”)</li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
-<h2 id="main-changes-6">Main Changes</h2>
+<div>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
<li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li>
@@ -203,22 +225,22 @@ <h2 id="main-changes-6">Main Changes</h2>
<li>Add startup files “startup_stm32h745xx.s”, “startup_stm32h747xx.s”, “startup_stm32h755xx.s”, “startup_stm32h757xx.s” and “startup_stm32h742xx.s” for EWARM , MDK-ARM and SW4STM32 toolchains</li>
<li>Add part numbers list to stm32h7xx.h header file:
<ul>
-<li><p>STM32H742xx: STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI</p></li>
-<li><p>STM32H743xx: STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI</p></li>
-<li><p>STM32H753xx: STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI</p></li>
-<li><p>STM32H750xx: STM32H750V, STM32H750I, STM32H750X</p></li>
-<li><p>STM32H747xx: STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI</p></li>
-<li><p>STM32H757xx: STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI</p></li>
-<li><p>STM32H745xx: STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI</p></li>
+<li>STM32H742xx: STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI</li>
+<li>STM32H743xx: STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI</li>
+<li>STM32H753xx: STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI</li>
+<li>STM32H750xx: STM32H750V, STM32H750I, STM32H750X</li>
+<li>STM32H747xx: STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI</li>
+<li>STM32H757xx: STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI</li>
+<li>STM32H745xx: STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI</li>
<li><p>STM32H755xx: STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI</p></li>
-<li><p>Add system_stm32h7xx_singlecore.c : system initialization template source file for single core lines (STM32H743xx, STM32H753xx, STM32H750xx and STM32H742xx)</p></li>
-<li><p>Add system initialization template source file for dual core lines:</p>
+<li>Add system_stm32h7xx_singlecore.c : system initialization template source file for single core lines (STM32H743xx, STM32H753xx, STM32H750xx and STM32H742xx)</li>
+<li>Add system initialization template source file for dual core lines:
<ul>
<li>system_stm32h7xx_dualcore_boot_cm4_cm7.c: template for the boot case where Cortex-M7 and Cortex-M4 are boot at once</li>
<li>system_stm32h7xx_dualcore_bootcm7_cm4gated.c: template for the boot case where Cortex-M7 is booting and Cortex-M4 is gated using FLASH Option Bytes</li>
<li>system_stm32h7xx_dualcore_bootcm4_cm7gated.c: template for the boot case where Cortex-M4 is booting and Cortex-M7 is gated using FLASH Option Bytes</li>
</ul></li>
-<li><p>Add EWARM, MDK-ARM and SW4STM32 <strong>Dual Core</strong> devices linker files</p></li>
+<li>Add EWARM, MDK-ARM and SW4STM32 <strong>Dual Core</strong> devices linker files</li>
<li><p>Add EWARM STM32H742xx devices linker files</p></li>
</ul></li>
</ul></li>
@@ -253,9 +275,11 @@ <h2 id="main-changes-6">Main Changes</h2>
</ul></li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label>
-<h2 id="main-changes-7">Main Changes</h2>
+<div>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li><strong>Patch Release on top of V1.3.0</strong></li>
<li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files:
@@ -264,9 +288,11 @@ <h2 id="main-changes-7">Main Changes</h2>
</ul></li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
-<h2 id="main-changes-8">Main Changes</h2>
+<div>
+<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li>STM32H7xx include files:
<ul>
@@ -307,9 +333,11 @@ <h2 id="main-changes-8">Main Changes</h2>
</ul></li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
-<h2 id="main-changes-9">Main Changes</h2>
+<div>
+<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li>Add support for stm32h750xx value line devices:
<ul>
@@ -318,30 +346,37 @@ <h2 id="main-changes-9">Main Changes</h2>
</ul></li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
-<h2 id="main-changes-10">Main Changes</h2>
+<div>
+<h2 id="main-changes-11">Main Changes</h2>
<ul>
<li>Update FDCAN bit definition</li>
<li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
-<h2 id="main-changes-11">Main Changes</h2>
+<div>
+<h2 id="main-changes-12">Main Changes</h2>
<ul>
<li>Update USB OTG bit definition</li>
<li>Adjust PLL fractional computation</li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
-<h2 id="main-changes-12">Main Changes</h2>
+<div>
+<h2 id="main-changes-13">Main Changes</h2>
<ul>
<li>First official release for <strong>STM32H743xx/753xx</strong> devices</li>
</ul>
</div>
-</section>
+</div>
+</div>
</div>
<footer class="sticky">
For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span>
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c
index 44b7c2316b..c99a7b1dbf 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c
@@ -46,6 +46,7 @@
#include "stm32h7xx.h"
#include <math.h>
+
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
@@ -93,14 +94,14 @@
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
- This value must be a multiple of 0x200. */
+ This value must be a multiple of 0x300. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
+ This value must be a multiple of 0x300. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
- This value must be a multiple of 0x200. */
+ This value must be a multiple of 0x300. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
+ This value must be a multiple of 0x300. */
#endif /* VECT_TAB_SRAM */
#else
/*!< Uncomment the following line if you need to relocate your vector Table
@@ -108,14 +109,14 @@
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
- This value must be a multiple of 0x200. */
+ This value must be a multiple of 0x300. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
+ This value must be a multiple of 0x300. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
- This value must be a multiple of 0x200. */
+ This value must be a multiple of 0x300. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
+ This value must be a multiple of 0x300. */
#endif /* VECT_TAB_SRAM */
#endif /* DUAL_CORE && CORE_CM4 */
#endif /* USER_VECT_TAB_ADDRESS */
@@ -187,7 +188,7 @@ void SystemInit (void)
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
/* Set HSION bit */
@@ -203,7 +204,7 @@ void SystemInit (void)
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
#if defined(D3_SRAM_BASE)
@@ -261,10 +262,10 @@ void SystemInit (void)
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U;
}
-#endif
+#endif /* STM32H7_DEV_ID */
-#if defined (DATA_IN_D2_SRAM)
- /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
+#if defined(DATA_IN_D2_SRAM)
+ /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
#if defined(RCC_AHB2ENR_D2SRAM3EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
#elif defined(RCC_AHB2ENR_D2SRAM2EN)
@@ -284,7 +285,6 @@ void SystemInit (void)
#endif /* USER_VECT_TAB_ADDRESS */
#else
-
/*
* Disable the FMC bank1 (enabled after reset).
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
@@ -298,7 +298,6 @@ void SystemInit (void)
#endif /* USER_VECT_TAB_ADDRESS */
#endif /*DUAL_CORE && CORE_CM4*/
-
}
/**
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c
index 04b114a554..4af82c9e68 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c
@@ -80,11 +80,48 @@
*/
/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if defined(CORE_CM4)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
- This value must be a multiple of 0x300. */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x300. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x300. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x300. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x300. */
+#endif /* VECT_TAB_SRAM */
+#elif defined(CORE_CM7)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x300. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x300. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x300. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x300. */
+#endif /* VECT_TAB_SRAM */
+#else
+#error Please #define CORE_CM4 or CORE_CM7
+#endif /* CORE_CM4 */
+#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
@@ -148,13 +185,13 @@ void SystemInit (void)
detectable by the CPU after a WFI/WFE instruction.*/
SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
-#ifdef CORE_CM7
+#if defined(CORE_CM7)
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Increasing the CPU frequency */
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
/* Set HSION bit */
@@ -163,14 +200,14 @@ void SystemInit (void)
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
- /* Reset HSEON, HSECSSON, CSION, RC48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
+ /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= 0xEAF6ED7FU;
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
/* Reset D1CFGR register */
@@ -213,7 +250,6 @@ void SystemInit (void)
/* Enable CortexM7 HSEM EXTI line (line 78)*/
EXTI_D2->EMR3 |= 0x4000UL;
-
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{
/* if stm32h7 revY*/
@@ -223,18 +259,13 @@ void SystemInit (void)
#endif /* CORE_CM7*/
-#ifdef CORE_CM4
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-#else
-#ifdef CORE_CM7
+#if defined(CORE_CM4)
+ /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+#elif defined(CORE_CM7)
/*
* Disable the FMC bank1 (enabled after reset).
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
@@ -242,18 +273,14 @@ void SystemInit (void)
*/
FMC_Bank1_R->BTCR[0] = 0x000030D2;
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */
-#else
- SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
#else
#error Please #define CORE_CM4 or CORE_CM7
-#endif
-#endif
-
+#endif /* CORE_CM4 */
}
/**
@@ -372,11 +399,11 @@ void SystemCoreClockUpdate (void)
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
-#if defined(DUAL_CORE) && defined(CORE_CM4)
+#if defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
-#endif /* DUAL_CORE && CORE_CM4 */
+#endif /* CORE_CM4 */
}
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c
index 0f17fdd58d..bf6bfcd310 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c
@@ -83,11 +83,48 @@
*/
/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if defined(CORE_CM4)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
- This value must be a multiple of 0x300. */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x300. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x300. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x300. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x300. */
+#endif /* VECT_TAB_SRAM */
+#elif defined(CORE_CM7)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x300. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x300. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x300. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x300. */
+#endif /* VECT_TAB_SRAM */
+#else
+#error Please #define CORE_CM4 or CORE_CM7
+#endif /* CORE_CM4 */
+#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
@@ -147,13 +184,13 @@ void SystemInit (void)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
#endif
-#ifdef CORE_CM4
+#if defined(CORE_CM4)
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Increasing the CPU frequency */
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
/* Set HSION bit */
@@ -169,7 +206,7 @@ void SystemInit (void)
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
/* Reset D1CFGR register */
@@ -209,22 +246,11 @@ void SystemInit (void)
/* Disable all interrupts */
RCC->CIER = 0x00000000;
-
-
-#endif /* CORE_CM4*/
-
-#ifdef CORE_CM4
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-#else
-#ifdef CORE_CM7
-
+ /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+#elif defined(CORE_CM7)
/* dual core CM7 or single core line */
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{
@@ -240,18 +266,13 @@ void SystemInit (void)
*/
FMC_Bank1_R->BTCR[0] = 0x000030D2;
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
#else
#error Please #define CORE_CM4 or CORE_CM7
-#endif
-#endif
-
+#endif /* CORE_CM4 */
}
/**
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c
index 65310b6a39..c6c1c8e45f 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c
@@ -83,11 +83,48 @@
*/
/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if defined(CORE_CM4)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
- This value must be a multiple of 0x300. */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x300. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x300. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x300. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x300. */
+#endif /* VECT_TAB_SRAM */
+#elif defined(CORE_CM7)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x300. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x300. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x300. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x300. */
+#endif /* VECT_TAB_SRAM */
+#else
+#error Please #define CORE_CM4 or CORE_CM7
+#endif /* CORE_CM4 */
+#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
@@ -147,13 +184,13 @@ void SystemInit (void)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
#endif
-#ifdef CORE_CM7
+#if defined(CORE_CM7)
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Increasing the CPU frequency */
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
/* Set HSION bit */
@@ -169,7 +206,7 @@ void SystemInit (void)
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
/* Reset D1CFGR register */
@@ -217,20 +254,16 @@ void SystemInit (void)
*((__IO uint32_t*)0x51008108) = 0x000000001U;
}
-#endif /* CORE_CM7*/
+#endif /* CORE_CM7 */
-#ifdef CORE_CM4
+#if defined(CORE_CM4)
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-#else
-#ifdef CORE_CM7
+ /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+#elif defined(CORE_CM7)
/*
* Disable the FMC bank1 (enabled after reset).
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
@@ -238,18 +271,14 @@ void SystemInit (void)
*/
FMC_Bank1_R->BTCR[0] = 0x000030D2;
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
#else
#error Please #define CORE_CM4 or CORE_CM7
-#endif
-#endif
-
+#endif /* CORE_CM4 */
}
/**
@@ -368,11 +397,11 @@ void SystemCoreClockUpdate (void)
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
-#if defined(DUAL_CORE) && defined(CORE_CM4)
+#if defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
-#endif /* DUAL_CORE && CORE_CM4 */
+#endif /* CORE_CM4 */
}
/**
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c
index bfb5849c34..de86fc3765 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c
@@ -82,11 +82,29 @@
/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
/* #define DATA_IN_D2_SRAM */
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
- This value must be a multiple of 0x300. */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
@@ -155,7 +173,7 @@ void SystemInit (void)
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
/* Set HSION bit */
@@ -171,7 +189,7 @@ void SystemInit (void)
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
}
#if defined(D3_SRAM_BASE)
@@ -240,6 +258,7 @@ void SystemInit (void)
#else
RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
#endif /* RCC_AHB2ENR_D2SRAM3EN */
+
tmpreg = RCC->AHB2ENR;
(void) tmpreg;
#endif /* DATA_IN_D2_SRAM */
@@ -252,13 +271,9 @@ void SystemInit (void)
FMC_Bank1_R->BTCR[0] = 0x000030D2;
/* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
-#else
- SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
}
/**
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/_htmresc/favicon.png b/system/Drivers/CMSIS/Device/ST/STM32H7xx/_htmresc/favicon.png
new file mode 100644
index 0000000000..06713eec49
Binary files /dev/null and b/system/Drivers/CMSIS/Device/ST/STM32H7xx/_htmresc/favicon.png differ
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/_htmresc/mini-st_2020.css b/system/Drivers/CMSIS/Device/ST/STM32H7xx/_htmresc/mini-st_2020.css
new file mode 100644
index 0000000000..db8b406aa4
--- /dev/null
+++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/_htmresc/mini-st_2020.css
@@ -0,0 +1,1711 @@
+@charset "UTF-8";
+/*
+ Flavor name: Custom (mini-custom)
+ Generated online - https://minicss.org/flavors
+ mini.css version: v3.0.1
+*/
+/*
+ Browsers resets and base typography.
+*/
+/* Core module CSS variable definitions */
+:root {
+ --fore-color: #03234b;
+ --secondary-fore-color: #03234b;
+ --back-color: #ffffff;
+ --secondary-back-color: #ffffff;
+ --blockquote-color: #e6007e;
+ --pre-color: #e6007e;
+ --border-color: #3cb4e6;
+ --secondary-border-color: #3cb4e6;
+ --heading-ratio: 1.2;
+ --universal-margin: 0.5rem;
+ --universal-padding: 0.25rem;
+ --universal-border-radius: 0.075rem;
+ --background-margin: 1.5%;
+ --a-link-color: #3cb4e6;
+ --a-visited-color: #8c0078; }
+
+html {
+ font-size: 13.5px; }
+
+a, b, del, em, i, ins, q, span, strong, u {
+ font-size: 1em; }
+
+html, * {
+ font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif;
+ line-height: 1.25;
+ -webkit-text-size-adjust: 100%; }
+
+* {
+ font-size: 1rem; }
+
+body {
+ margin: 0;
+ color: var(--fore-color);
+ @background: var(--back-color);
+ background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top;
+ background-size: var(--background-margin);
+ }
+
+details {
+ display: block; }
+
+summary {
+ display: list-item; }
+
+abbr[title] {
+ border-bottom: none;
+ text-decoration: underline dotted; }
+
+input {
+ overflow: visible; }
+
+img {
+ max-width: 100%;
+ height: auto; }
+
+h1, h2, h3, h4, h5, h6 {
+ line-height: 1.25;
+ margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ font-weight: 400; }
+ h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
+ color: var(--secondary-fore-color);
+ display: block;
+ margin-top: -0.25rem; }
+
+h1 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
+
+h2 {
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) );
+ border-style: none none solid none ;
+ border-width: thin;
+ border-color: var(--border-color); }
+h3 {
+ font-size: calc(1rem * var(--heading-ratio) ); }
+
+h4 {
+ font-size: calc(1rem * var(--heading-ratio)); }
+
+h5 {
+ font-size: 1rem; }
+
+h6 {
+ font-size: calc(1rem / var(--heading-ratio)); }
+
+p {
+ margin: var(--universal-margin); }
+
+ol, ul {
+ margin: var(--universal-margin);
+ padding-left: calc(3 * var(--universal-margin)); }
+
+b, strong {
+ font-weight: 700; }
+
+hr {
+ box-sizing: content-box;
+ border: 0;
+ line-height: 1.25em;
+ margin: var(--universal-margin);
+ height: 0.0714285714rem;
+ background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
+
+blockquote {
+ display: block;
+ position: relative;
+ font-style: italic;
+ color: var(--secondary-fore-color);
+ margin: var(--universal-margin);
+ padding: calc(3 * var(--universal-padding));
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.3rem solid var(--blockquote-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+ blockquote:before {
+ position: absolute;
+ top: calc(0rem - var(--universal-padding));
+ left: 0;
+ font-family: sans-serif;
+ font-size: 2rem;
+ font-weight: 800;
+ content: "\201c";
+ color: var(--blockquote-color); }
+ blockquote[cite]:after {
+ font-style: normal;
+ font-size: 0.75em;
+ font-weight: 700;
+ content: "\a— " attr(cite);
+ white-space: pre; }
+
+code, kbd, pre, samp {
+ font-family: Menlo, Consolas, monospace;
+ font-size: 0.85em; }
+
+code {
+ background: var(--secondary-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+kbd {
+ background: var(--fore-color);
+ color: var(--back-color);
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+
+pre {
+ overflow: auto;
+ background: var(--secondary-back-color);
+ padding: calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.2857142857rem solid var(--pre-color);
+ border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
+
+sup, sub, code, kbd {
+ line-height: 0;
+ position: relative;
+ vertical-align: baseline; }
+
+small, sup, sub, figcaption {
+ font-size: 0.75em; }
+
+sup {
+ top: -0.5em; }
+
+sub {
+ bottom: -0.25em; }
+
+figure {
+ margin: var(--universal-margin); }
+
+figcaption {
+ color: var(--secondary-fore-color); }
+
+a {
+ text-decoration: none; }
+ a:link {
+ color: var(--a-link-color); }
+ a:visited {
+ color: var(--a-visited-color); }
+ a:hover, a:focus {
+ text-decoration: underline; }
+
+/*
+ Definitions for the grid system, cards and containers.
+*/
+.container {
+ margin: 0 auto;
+ padding: 0 calc(1.5 * var(--universal-padding)); }
+
+.row {
+ box-sizing: border-box;
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap;
+ margin: 0 0 0 var(--background-margin); }
+
+.col-sm,
+[class^='col-sm-'],
+[class^='col-sm-offset-'],
+.row[class*='cols-sm-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+.col-sm,
+.row.cols-sm > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+.col-sm-1,
+.row.cols-sm-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+.col-sm-offset-0 {
+ margin-left: 0; }
+
+.col-sm-2,
+.row.cols-sm-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+.col-sm-offset-1 {
+ margin-left: 8.3333333333%; }
+
+.col-sm-3,
+.row.cols-sm-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+.col-sm-offset-2 {
+ margin-left: 16.6666666667%; }
+
+.col-sm-4,
+.row.cols-sm-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+.col-sm-offset-3 {
+ margin-left: 25%; }
+
+.col-sm-5,
+.row.cols-sm-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+.col-sm-offset-4 {
+ margin-left: 33.3333333333%; }
+
+.col-sm-6,
+.row.cols-sm-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+.col-sm-offset-5 {
+ margin-left: 41.6666666667%; }
+
+.col-sm-7,
+.row.cols-sm-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+.col-sm-offset-6 {
+ margin-left: 50%; }
+
+.col-sm-8,
+.row.cols-sm-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+.col-sm-offset-7 {
+ margin-left: 58.3333333333%; }
+
+.col-sm-9,
+.row.cols-sm-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+.col-sm-offset-8 {
+ margin-left: 66.6666666667%; }
+
+.col-sm-10,
+.row.cols-sm-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+.col-sm-offset-9 {
+ margin-left: 75%; }
+
+.col-sm-11,
+.row.cols-sm-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+.col-sm-offset-10 {
+ margin-left: 83.3333333333%; }
+
+.col-sm-12,
+.row.cols-sm-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+.col-sm-offset-11 {
+ margin-left: 91.6666666667%; }
+
+.col-sm-normal {
+ order: initial; }
+
+.col-sm-first {
+ order: -999; }
+
+.col-sm-last {
+ order: 999; }
+
+@media screen and (min-width: 500px) {
+ .col-md,
+ [class^='col-md-'],
+ [class^='col-md-offset-'],
+ .row[class*='cols-md-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-md,
+ .row.cols-md > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-md-1,
+ .row.cols-md-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-md-offset-0 {
+ margin-left: 0; }
+
+ .col-md-2,
+ .row.cols-md-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-md-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-md-3,
+ .row.cols-md-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-md-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-md-4,
+ .row.cols-md-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-md-offset-3 {
+ margin-left: 25%; }
+
+ .col-md-5,
+ .row.cols-md-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-md-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-md-6,
+ .row.cols-md-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-md-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-md-7,
+ .row.cols-md-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-md-offset-6 {
+ margin-left: 50%; }
+
+ .col-md-8,
+ .row.cols-md-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-md-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-md-9,
+ .row.cols-md-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-md-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-md-10,
+ .row.cols-md-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-md-offset-9 {
+ margin-left: 75%; }
+
+ .col-md-11,
+ .row.cols-md-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-md-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-md-12,
+ .row.cols-md-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-md-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-md-normal {
+ order: initial; }
+
+ .col-md-first {
+ order: -999; }
+
+ .col-md-last {
+ order: 999; } }
+@media screen and (min-width: 1280px) {
+ .col-lg,
+ [class^='col-lg-'],
+ [class^='col-lg-offset-'],
+ .row[class*='cols-lg-'] > * {
+ box-sizing: border-box;
+ flex: 0 0 auto;
+ padding: 0 calc(var(--universal-padding) / 2); }
+
+ .col-lg,
+ .row.cols-lg > * {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0; }
+
+ .col-lg-1,
+ .row.cols-lg-1 > * {
+ max-width: 8.3333333333%;
+ flex-basis: 8.3333333333%; }
+
+ .col-lg-offset-0 {
+ margin-left: 0; }
+
+ .col-lg-2,
+ .row.cols-lg-2 > * {
+ max-width: 16.6666666667%;
+ flex-basis: 16.6666666667%; }
+
+ .col-lg-offset-1 {
+ margin-left: 8.3333333333%; }
+
+ .col-lg-3,
+ .row.cols-lg-3 > * {
+ max-width: 25%;
+ flex-basis: 25%; }
+
+ .col-lg-offset-2 {
+ margin-left: 16.6666666667%; }
+
+ .col-lg-4,
+ .row.cols-lg-4 > * {
+ max-width: 33.3333333333%;
+ flex-basis: 33.3333333333%; }
+
+ .col-lg-offset-3 {
+ margin-left: 25%; }
+
+ .col-lg-5,
+ .row.cols-lg-5 > * {
+ max-width: 41.6666666667%;
+ flex-basis: 41.6666666667%; }
+
+ .col-lg-offset-4 {
+ margin-left: 33.3333333333%; }
+
+ .col-lg-6,
+ .row.cols-lg-6 > * {
+ max-width: 50%;
+ flex-basis: 50%; }
+
+ .col-lg-offset-5 {
+ margin-left: 41.6666666667%; }
+
+ .col-lg-7,
+ .row.cols-lg-7 > * {
+ max-width: 58.3333333333%;
+ flex-basis: 58.3333333333%; }
+
+ .col-lg-offset-6 {
+ margin-left: 50%; }
+
+ .col-lg-8,
+ .row.cols-lg-8 > * {
+ max-width: 66.6666666667%;
+ flex-basis: 66.6666666667%; }
+
+ .col-lg-offset-7 {
+ margin-left: 58.3333333333%; }
+
+ .col-lg-9,
+ .row.cols-lg-9 > * {
+ max-width: 75%;
+ flex-basis: 75%; }
+
+ .col-lg-offset-8 {
+ margin-left: 66.6666666667%; }
+
+ .col-lg-10,
+ .row.cols-lg-10 > * {
+ max-width: 83.3333333333%;
+ flex-basis: 83.3333333333%; }
+
+ .col-lg-offset-9 {
+ margin-left: 75%; }
+
+ .col-lg-11,
+ .row.cols-lg-11 > * {
+ max-width: 91.6666666667%;
+ flex-basis: 91.6666666667%; }
+
+ .col-lg-offset-10 {
+ margin-left: 83.3333333333%; }
+
+ .col-lg-12,
+ .row.cols-lg-12 > * {
+ max-width: 100%;
+ flex-basis: 100%; }
+
+ .col-lg-offset-11 {
+ margin-left: 91.6666666667%; }
+
+ .col-lg-normal {
+ order: initial; }
+
+ .col-lg-first {
+ order: -999; }
+
+ .col-lg-last {
+ order: 999; } }
+/* Card component CSS variable definitions */
+:root {
+ --card-back-color: #3cb4e6;
+ --card-fore-color: #03234b;
+ --card-border-color: #03234b; }
+
+.card {
+ display: flex;
+ flex-direction: column;
+ justify-content: space-between;
+ align-self: center;
+ position: relative;
+ width: 100%;
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ border: 0.0714285714rem solid var(--card-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ overflow: hidden; }
+ @media screen and (min-width: 320px) {
+ .card {
+ max-width: 320px; } }
+ .card > .sectione {
+ background: var(--card-back-color);
+ color: var(--card-fore-color);
+ box-sizing: border-box;
+ margin: 0;
+ border: 0;
+ border-radius: 0;
+ border-bottom: 0.0714285714rem solid var(--card-border-color);
+ padding: var(--universal-padding);
+ width: 100%; }
+ .card > .sectione.media {
+ height: 200px;
+ padding: 0;
+ -o-object-fit: cover;
+ object-fit: cover; }
+ .card > .sectione:last-child {
+ border-bottom: 0; }
+
+/*
+ Custom elements for card elements.
+*/
+@media screen and (min-width: 240px) {
+ .card.small {
+ max-width: 240px; } }
+@media screen and (min-width: 480px) {
+ .card.large {
+ max-width: 480px; } }
+.card.fluid {
+ max-width: 100%;
+ width: auto; }
+
+.card.warning {
+ --card-back-color: #e5b8b7;
+ --card-fore-color: #3b234b;
+ --card-border-color: #8c0078; }
+
+.card.error {
+ --card-back-color: #464650;
+ --card-fore-color: #ffffff;
+ --card-border-color: #8c0078; }
+
+.card > .sectione.dark {
+ --card-back-color: #3b234b;
+ --card-fore-color: #ffffff; }
+
+.card > .sectione.double-padded {
+ padding: calc(1.5 * var(--universal-padding)); }
+
+/*
+ Definitions for forms and input elements.
+*/
+/* Input_control module CSS variable definitions */
+:root {
+ --form-back-color: #ffe97f;
+ --form-fore-color: #03234b;
+ --form-border-color: #3cb4e6;
+ --input-back-color: #ffffff;
+ --input-fore-color: #03234b;
+ --input-border-color: #3cb4e6;
+ --input-focus-color: #0288d1;
+ --input-invalid-color: #d32f2f;
+ --button-back-color: #e2e2e2;
+ --button-hover-back-color: #dcdcdc;
+ --button-fore-color: #212121;
+ --button-border-color: transparent;
+ --button-hover-border-color: transparent;
+ --button-group-border-color: rgba(124, 124, 124, 0.54); }
+
+form {
+ background: var(--form-back-color);
+ color: var(--form-fore-color);
+ border: 0.0714285714rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
+
+fieldset {
+ border: 0.0714285714rem solid var(--form-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 4);
+ padding: var(--universal-padding); }
+
+legend {
+ box-sizing: border-box;
+ display: table;
+ max-width: 100%;
+ white-space: normal;
+ font-weight: 500;
+ padding: calc(var(--universal-padding) / 2); }
+
+label {
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+.input-group {
+ display: inline-block; }
+ .input-group.fluid {
+ display: flex;
+ align-items: center;
+ justify-content: center; }
+ .input-group.fluid > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+ @media screen and (max-width: 499px) {
+ .input-group.fluid {
+ align-items: stretch;
+ flex-direction: column; } }
+ .input-group.vertical {
+ display: flex;
+ align-items: stretch;
+ flex-direction: column; }
+ .input-group.vertical > input {
+ max-width: 100%;
+ flex-grow: 1;
+ flex-basis: 0px; }
+
+[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {
+ height: auto; }
+
+[type="search"] {
+ -webkit-appearance: textfield;
+ outline-offset: -2px; }
+
+[type="search"]::-webkit-search-cancel-button,
+[type="search"]::-webkit-search-decoration {
+ -webkit-appearance: none; }
+
+input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],
+[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {
+ box-sizing: border-box;
+ background: var(--input-back-color);
+ color: var(--input-fore-color);
+ border: 0.0714285714rem solid var(--input-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: calc(var(--universal-margin) / 2);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {
+ border-color: var(--input-focus-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {
+ border-color: var(--input-invalid-color);
+ box-shadow: none; }
+input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {
+ background: var(--secondary-back-color); }
+
+select {
+ max-width: 100%; }
+
+option {
+ overflow: hidden;
+ text-overflow: ellipsis; }
+
+[type="checkbox"], [type="radio"] {
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ position: relative;
+ height: calc(1rem + var(--universal-padding) / 2);
+ width: calc(1rem + var(--universal-padding) / 2);
+ vertical-align: text-bottom;
+ padding: 0;
+ flex-basis: calc(1rem + var(--universal-padding) / 2) !important;
+ flex-grow: 0 !important; }
+ [type="checkbox"]:checked:before, [type="radio"]:checked:before {
+ position: absolute; }
+
+[type="checkbox"]:checked:before {
+ content: '\2713';
+ font-family: sans-serif;
+ font-size: calc(1rem + var(--universal-padding) / 2);
+ top: calc(0rem - var(--universal-padding));
+ left: calc(var(--universal-padding) / 4); }
+
+[type="radio"] {
+ border-radius: 100%; }
+ [type="radio"]:checked:before {
+ border-radius: 100%;
+ content: '';
+ top: calc(0.0714285714rem + var(--universal-padding) / 2);
+ left: calc(0.0714285714rem + var(--universal-padding) / 2);
+ background: var(--input-fore-color);
+ width: 0.5rem;
+ height: 0.5rem; }
+
+:placeholder-shown {
+ color: var(--input-fore-color); }
+
+::-ms-placeholder {
+ color: var(--input-fore-color);
+ opacity: 0.54; }
+
+button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {
+ border-style: none;
+ padding: 0; }
+
+button, html [type="button"], [type="reset"], [type="submit"] {
+ -webkit-appearance: button; }
+
+button {
+ overflow: visible;
+ text-transform: none; }
+
+button, [type="button"], [type="submit"], [type="reset"],
+a.button, label.button, .button,
+a[role="button"], label[role="button"], [role="button"] {
+ display: inline-block;
+ background: var(--button-back-color);
+ color: var(--button-fore-color);
+ border: 0.0714285714rem solid var(--button-border-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
+ margin: var(--universal-margin);
+ text-decoration: none;
+ cursor: pointer;
+ transition: background 0.3s; }
+ button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,
+ a.button:hover,
+ a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,
+ a[role="button"]:hover,
+ a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {
+ background: var(--button-hover-back-color);
+ border-color: var(--button-hover-border-color); }
+
+input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {
+ cursor: not-allowed;
+ opacity: 0.75; }
+
+.button-group {
+ display: flex;
+ border: 0.0714285714rem solid var(--button-group-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
+ margin: 0;
+ max-width: 100%;
+ flex: 1 1 auto;
+ text-align: center;
+ border: 0;
+ border-radius: 0;
+ box-shadow: none; }
+ .button-group > :not(:first-child) {
+ border-left: 0.0714285714rem solid var(--button-group-border-color); }
+ @media screen and (max-width: 499px) {
+ .button-group {
+ flex-direction: column; }
+ .button-group > :not(:first-child) {
+ border: 0;
+ border-top: 0.0714285714rem solid var(--button-group-border-color); } }
+
+/*
+ Custom elements for forms and input elements.
+*/
+button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {
+ --button-back-color: #1976d2;
+ --button-fore-color: #f8f8f8; }
+ button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {
+ --button-hover-back-color: #1565c0; }
+
+button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {
+ --button-back-color: #d32f2f;
+ --button-fore-color: #f8f8f8; }
+ button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {
+ --button-hover-back-color: #c62828; }
+
+button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {
+ --button-back-color: #308732;
+ --button-fore-color: #f8f8f8; }
+ button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {
+ --button-hover-back-color: #277529; }
+
+button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {
+ --button-back-color: #212121;
+ --button-fore-color: #f8f8f8; }
+ button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {
+ --button-hover-back-color: #111; }
+
+button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {
+ padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {
+ padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));
+ margin: var(--universal-margin); }
+
+/*
+ Definitions for navigation elements.
+*/
+/* Navigation module CSS variable definitions */
+:root {
+ --header-back-color: #03234b;
+ --header-hover-back-color: #ffd200;
+ --header-fore-color: #ffffff;
+ --header-border-color: #3cb4e6;
+ --nav-back-color: #ffffff;
+ --nav-hover-back-color: #ffe97f;
+ --nav-fore-color: #e6007e;
+ --nav-border-color: #3cb4e6;
+ --nav-link-color: #3cb4e6;
+ --footer-fore-color: #ffffff;
+ --footer-back-color: #03234b;
+ --footer-border-color: #3cb4e6;
+ --footer-link-color: #3cb4e6;
+ --drawer-back-color: #ffffff;
+ --drawer-hover-back-color: #ffe97f;
+ --drawer-border-color: #3cb4e6;
+ --drawer-close-color: #e6007e; }
+
+header {
+ height: 2.75rem;
+ background: var(--header-back-color);
+ color: var(--header-fore-color);
+ border-bottom: 0.0714285714rem solid var(--header-border-color);
+ padding: calc(var(--universal-padding) / 4) 0;
+ white-space: nowrap;
+ overflow-x: auto;
+ overflow-y: hidden; }
+ header.row {
+ box-sizing: content-box; }
+ header .logo {
+ color: var(--header-fore-color);
+ font-size: 1.75rem;
+ padding: var(--universal-padding) calc(2 * var(--universal-padding));
+ text-decoration: none; }
+ header button, header [type="button"], header .button, header [role="button"] {
+ box-sizing: border-box;
+ position: relative;
+ top: calc(0rem - var(--universal-padding) / 4);
+ height: calc(3.1875rem + var(--universal-padding) / 2);
+ background: var(--header-back-color);
+ line-height: calc(3.1875rem - var(--universal-padding) * 1.5);
+ text-align: center;
+ color: var(--header-fore-color);
+ border: 0;
+ border-radius: 0;
+ margin: 0;
+ text-transform: uppercase; }
+ header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {
+ background: var(--header-hover-back-color); }
+
+nav {
+ background: var(--nav-back-color);
+ color: var(--nav-fore-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-radius: var(--universal-border-radius);
+ margin: var(--universal-margin); }
+ nav * {
+ padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
+ nav a, nav a:visited {
+ display: block;
+ color: var(--nav-link-color);
+ border-radius: var(--universal-border-radius);
+ transition: background 0.3s; }
+ nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {
+ text-decoration: none;
+ background: var(--nav-hover-back-color); }
+ nav .sublink-1 {
+ position: relative;
+ margin-left: calc(2 * var(--universal-padding)); }
+ nav .sublink-1:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 1 * var(--universal-padding));
+ top: -0.0714285714rem;
+ content: '';
+ height: 100%;
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-left: 0; }
+ nav .sublink-2 {
+ position: relative;
+ margin-left: calc(4 * var(--universal-padding)); }
+ nav .sublink-2:before {
+ position: absolute;
+ left: calc(var(--universal-padding) - 3 * var(--universal-padding));
+ top: -0.0714285714rem;
+ content: '';
+ height: 100%;
+ border: 0.0714285714rem solid var(--nav-border-color);
+ border-left: 0; }
+
+footer {
+ background: var(--footer-back-color);
+ color: var(--footer-fore-color);
+ border-top: 0.0714285714rem solid var(--footer-border-color);
+ padding: calc(2 * var(--universal-padding)) var(--universal-padding);
+ font-size: 0.875rem; }
+ footer a, footer a:visited {
+ color: var(--footer-link-color); }
+
+header.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ top: 0; }
+
+footer.sticky {
+ position: -webkit-sticky;
+ position: sticky;
+ z-index: 1101;
+ bottom: 0; }
+
+.drawer-toggle:before {
+ display: inline-block;
+ position: relative;
+ vertical-align: bottom;
+ content: '\00a0\2261\00a0';
+ font-family: sans-serif;
+ font-size: 1.5em; }
+@media screen and (min-width: 500px) {
+ .drawer-toggle:not(.persistent) {
+ display: none; } }
+
+[type="checkbox"].drawer {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].drawer + * {
+ display: block;
+ box-sizing: border-box;
+ position: fixed;
+ top: 0;
+ width: 320px;
+ height: 100vh;
+ overflow-y: auto;
+ background: var(--drawer-back-color);
+ border: 0.0714285714rem solid var(--drawer-border-color);
+ border-radius: 0;
+ margin: 0;
+ z-index: 1110;
+ right: -320px;
+ transition: right 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close {
+ position: absolute;
+ top: var(--universal-margin);
+ right: var(--universal-margin);
+ z-index: 1111;
+ width: 2rem;
+ height: 2rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].drawer + * .drawer-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--drawer-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 2rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {
+ background: var(--drawer-hover-back-color); }
+ @media screen and (max-width: 320px) {
+ [type="checkbox"].drawer + * {
+ width: 100%; } }
+ [type="checkbox"].drawer:checked + * {
+ right: 0; }
+ @media screen and (min-width: 500px) {
+ [type="checkbox"].drawer:not(.persistent) + * {
+ position: static;
+ height: 100%;
+ z-index: 1100; }
+ [type="checkbox"].drawer:not(.persistent) + * .drawer-close {
+ display: none; } }
+
+/*
+ Definitions for the responsive table component.
+*/
+/* Table module CSS variable definitions. */
+:root {
+ --table-border-color: #03234b;
+ --table-border-separator-color: #03234b;
+ --table-head-back-color: #03234b;
+ --table-head-fore-color: #ffffff;
+ --table-body-back-color: #ffffff;
+ --table-body-fore-color: #03234b;
+ --table-body-alt-back-color: #f4f4f4; }
+
+table {
+ border-collapse: separate;
+ border-spacing: 0;
+ margin: 0;
+ display: flex;
+ flex: 0 1 auto;
+ flex-flow: row wrap;
+ padding: var(--universal-padding);
+ padding-top: 0; }
+ table caption {
+ font-size: 1rem;
+ margin: calc(2 * var(--universal-margin)) 0;
+ max-width: 100%;
+ flex: 0 0 100%; }
+ table thead, table tbody {
+ display: flex;
+ flex-flow: row wrap;
+ border: 0.0714285714rem solid var(--table-border-color); }
+ table thead {
+ z-index: 999;
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
+ border-bottom: 0.0714285714rem solid var(--table-border-separator-color); }
+ table tbody {
+ border-top: 0;
+ margin-top: calc(0 - var(--universal-margin));
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ table tr {
+ display: flex;
+ padding: 0; }
+ table th, table td {
+ padding: calc(0.5 * var(--universal-padding));
+ font-size: 0.9rem; }
+ table th {
+ text-align: left;
+ background: var(--table-head-back-color);
+ color: var(--table-head-fore-color); }
+ table td {
+ background: var(--table-body-back-color);
+ color: var(--table-body-fore-color);
+ border-top: 0.0714285714rem solid var(--table-border-color); }
+
+table:not(.horizontal) {
+ overflow: auto;
+ max-height: 100%; }
+ table:not(.horizontal) thead, table:not(.horizontal) tbody {
+ max-width: 100%;
+ flex: 0 0 100%; }
+ table:not(.horizontal) tr {
+ flex-flow: row wrap;
+ flex: 0 0 100%; }
+ table:not(.horizontal) th, table:not(.horizontal) td {
+ flex: 1 0 0%;
+ overflow: hidden;
+ text-overflow: ellipsis; }
+ table:not(.horizontal) thead {
+ position: sticky;
+ top: 0; }
+ table:not(.horizontal) tbody tr:first-child td {
+ border-top: 0; }
+
+table.horizontal {
+ border: 0; }
+ table.horizontal thead, table.horizontal tbody {
+ border: 0;
+ flex: .2 0 0;
+ flex-flow: row nowrap; }
+ table.horizontal tbody {
+ overflow: auto;
+ justify-content: space-between;
+ flex: .8 0 0;
+ margin-left: 0;
+ padding-bottom: calc(var(--universal-padding) / 4); }
+ table.horizontal tr {
+ flex-direction: column;
+ flex: 1 0 auto; }
+ table.horizontal th, table.horizontal td {
+ width: auto;
+ border: 0;
+ border-bottom: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
+ border-top: 0; }
+ table.horizontal th {
+ text-align: right;
+ border-left: 0.0714285714rem solid var(--table-border-color);
+ border-right: 0.0714285714rem solid var(--table-border-separator-color); }
+ table.horizontal thead tr:first-child {
+ padding-left: 0; }
+ table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td {
+ border-right: 0.0714285714rem solid var(--table-border-color); }
+ table.horizontal tbody tr:last-child td:first-child {
+ border-top-right-radius: 0.25rem; }
+ table.horizontal tbody tr:last-child td:last-child {
+ border-bottom-right-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:first-child {
+ border-top-left-radius: 0.25rem; }
+ table.horizontal thead tr:first-child th:last-child {
+ border-bottom-left-radius: 0.25rem; }
+
+@media screen and (max-width: 499px) {
+ table, table.horizontal {
+ border-collapse: collapse;
+ border: 0;
+ width: 100%;
+ display: table; }
+ table thead, table th, table.horizontal thead, table.horizontal th {
+ border: 0;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ padding: 0;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ table tbody, table.horizontal tbody {
+ border: 0;
+ display: table-row-group; }
+ table tr, table.horizontal tr {
+ display: block;
+ border: 0.0714285714rem solid var(--table-border-color);
+ border-radius: var(--universal-border-radius);
+ background: #ffffff;
+ padding: var(--universal-padding);
+ margin: var(--universal-margin);
+ margin-bottom: calc(1 * var(--universal-margin)); }
+ table th, table td, table.horizontal th, table.horizontal td {
+ width: auto; }
+ table td, table.horizontal td {
+ display: block;
+ border: 0;
+ text-align: right; }
+ table td:before, table.horizontal td:before {
+ content: attr(data-label);
+ float: left;
+ font-weight: 600; }
+ table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {
+ border-top: 0; }
+ table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
+ border-right: 0; } }
+table tr:nth-of-type(2n) > td {
+ background: var(--table-body-alt-back-color); }
+
+@media screen and (max-width: 500px) {
+ table tr:nth-of-type(2n) {
+ background: var(--table-body-alt-back-color); } }
+:root {
+ --table-body-hover-back-color: #90caf9; }
+
+table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); }
+
+@media screen and (max-width: 500px) {
+ table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {
+ background: var(--table-body-hover-back-color); } }
+/*
+ Definitions for contextual background elements, toasts and tooltips.
+*/
+/* Contextual module CSS variable definitions */
+:root {
+ --mark-back-color: #3cb4e6;
+ --mark-fore-color: #ffffff; }
+
+mark {
+ background: var(--mark-back-color);
+ color: var(--mark-fore-color);
+ font-size: 0.95em;
+ line-height: 1em;
+ border-radius: var(--universal-border-radius);
+ padding: calc(var(--universal-padding) / 4) var(--universal-padding); }
+ mark.inline-block {
+ display: inline-block;
+ font-size: 1em;
+ line-height: 1.4;
+ padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
+
+:root {
+ --toast-back-color: #424242;
+ --toast-fore-color: #fafafa; }
+
+.toast {
+ position: fixed;
+ bottom: calc(var(--universal-margin) * 3);
+ left: 50%;
+ transform: translate(-50%, -50%);
+ z-index: 1111;
+ color: var(--toast-fore-color);
+ background: var(--toast-back-color);
+ border-radius: calc(var(--universal-border-radius) * 16);
+ padding: var(--universal-padding) calc(var(--universal-padding) * 3); }
+
+:root {
+ --tooltip-back-color: #212121;
+ --tooltip-fore-color: #fafafa; }
+
+.tooltip {
+ position: relative;
+ display: inline-block; }
+ .tooltip:before, .tooltip:after {
+ position: absolute;
+ opacity: 0;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: all 0.3s;
+ z-index: 1010;
+ left: 50%; }
+ .tooltip:not(.bottom):before, .tooltip:not(.bottom):after {
+ bottom: 75%; }
+ .tooltip.bottom:before, .tooltip.bottom:after {
+ top: 75%; }
+ .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {
+ opacity: 1;
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%); }
+ .tooltip:before {
+ content: '';
+ background: transparent;
+ border: var(--universal-margin) solid transparent;
+ left: calc(50% - var(--universal-margin)); }
+ .tooltip:not(.bottom):before {
+ border-top-color: #212121; }
+ .tooltip.bottom:before {
+ border-bottom-color: #212121; }
+ .tooltip:after {
+ content: attr(aria-label);
+ color: var(--tooltip-fore-color);
+ background: var(--tooltip-back-color);
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ white-space: nowrap;
+ transform: translateX(-50%); }
+ .tooltip:not(.bottom):after {
+ margin-bottom: calc(2 * var(--universal-margin)); }
+ .tooltip.bottom:after {
+ margin-top: calc(2 * var(--universal-margin)); }
+
+:root {
+ --modal-overlay-color: rgba(0, 0, 0, 0.45);
+ --modal-close-color: #e6007e;
+ --modal-close-hover-color: #ffe97f; }
+
+[type="checkbox"].modal {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ [type="checkbox"].modal + div {
+ position: fixed;
+ top: 0;
+ left: 0;
+ display: none;
+ width: 100vw;
+ height: 100vh;
+ background: var(--modal-overlay-color); }
+ [type="checkbox"].modal + div .card {
+ margin: 0 auto;
+ max-height: 50vh;
+ overflow: auto; }
+ [type="checkbox"].modal + div .card .modal-close {
+ position: absolute;
+ top: 0;
+ right: 0;
+ width: 1.75rem;
+ height: 1.75rem;
+ border-radius: var(--universal-border-radius);
+ padding: var(--universal-padding);
+ margin: 0;
+ cursor: pointer;
+ transition: background 0.3s; }
+ [type="checkbox"].modal + div .card .modal-close:before {
+ display: block;
+ content: '\00D7';
+ color: var(--modal-close-color);
+ position: relative;
+ font-family: sans-serif;
+ font-size: 1.75rem;
+ line-height: 1;
+ text-align: center; }
+ [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {
+ background: var(--modal-close-hover-color); }
+ [type="checkbox"].modal:checked + div {
+ display: flex;
+ flex: 0 1 auto;
+ z-index: 1200; }
+ [type="checkbox"].modal:checked + div .card .modal-close {
+ z-index: 1211; }
+
+:root {
+ --collapse-label-back-color: #03234b;
+ --collapse-label-fore-color: #ffffff;
+ --collapse-label-hover-back-color: #3cb4e6;
+ --collapse-selected-label-back-color: #3cb4e6;
+ --collapse-border-color: var(--collapse-label-back-color);
+ --collapse-selected-border-color: #ceecf8;
+ --collapse-content-back-color: #ffffff;
+ --collapse-selected-label-border-color: #3cb4e6; }
+
+.collapse {
+ width: calc(100% - 2 * var(--universal-margin));
+ opacity: 1;
+ display: flex;
+ flex-direction: column;
+ margin: var(--universal-margin);
+ border-radius: var(--universal-border-radius); }
+ .collapse > [type="radio"], .collapse > [type="checkbox"] {
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%); }
+ .collapse > label {
+ flex-grow: 1;
+ display: inline-block;
+ height: 1.25rem;
+ cursor: pointer;
+ transition: background 0.2s;
+ color: var(--collapse-label-fore-color);
+ background: var(--collapse-label-back-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ padding: calc(1.25 * var(--universal-padding)); }
+ .collapse > label:hover, .collapse > label:focus {
+ background: var(--collapse-label-hover-back-color); }
+ .collapse > label + div {
+ flex-basis: auto;
+ height: 1px;
+ width: 1px;
+ margin: -1px;
+ overflow: hidden;
+ position: absolute;
+ clip: rect(0 0 0 0);
+ -webkit-clip-path: inset(100%);
+ clip-path: inset(100%);
+ transition: max-height 0.3s;
+ max-height: 1px; }
+ .collapse > :checked + label {
+ background: var(--collapse-selected-label-back-color);
+ border-color: var(--collapse-selected-label-border-color); }
+ .collapse > :checked + label + div {
+ box-sizing: border-box;
+ position: relative;
+ width: 100%;
+ height: auto;
+ overflow: auto;
+ margin: 0;
+ background: var(--collapse-content-back-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ border-top: 0;
+ padding: var(--universal-padding);
+ clip: auto;
+ -webkit-clip-path: inset(0%);
+ clip-path: inset(0%);
+ max-height: 100%; }
+ .collapse > label:not(:first-of-type) {
+ border-top: 0; }
+ .collapse > label:first-of-type {
+ border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }
+ .collapse > label:last-of-type:not(:first-of-type) {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+ .collapse > label:last-of-type:first-of-type {
+ border-radius: var(--universal-border-radius); }
+ .collapse > :checked:last-of-type:not(:first-of-type) + label {
+ border-radius: 0; }
+ .collapse > :checked:last-of-type + label + div {
+ border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }
+
+/*
+ Custom elements for contextual background elements, toasts and tooltips.
+*/
+mark.tertiary {
+ --mark-back-color: #3cb4e6; }
+
+mark.tag {
+ padding: calc(var(--universal-padding)/2) var(--universal-padding);
+ border-radius: 1em; }
+
+/*
+ Definitions for progress elements and spinners.
+*/
+/* Progress module CSS variable definitions */
+:root {
+ --progress-back-color: #3cb4e6;
+ --progress-fore-color: #555; }
+
+progress {
+ display: block;
+ vertical-align: baseline;
+ -webkit-appearance: none;
+ -moz-appearance: none;
+ appearance: none;
+ height: 0.75rem;
+ width: calc(100% - 2 * var(--universal-margin));
+ margin: var(--universal-margin);
+ border: 0;
+ border-radius: calc(2 * var(--universal-border-radius));
+ background: var(--progress-back-color);
+ color: var(--progress-fore-color); }
+ progress::-webkit-progress-value {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress::-webkit-progress-bar {
+ background: var(--progress-back-color); }
+ progress::-moz-progress-bar {
+ background: var(--progress-fore-color);
+ border-top-left-radius: calc(2 * var(--universal-border-radius));
+ border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-webkit-progress-value {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress[value="1000"]::-moz-progress-bar {
+ border-radius: calc(2 * var(--universal-border-radius)); }
+ progress.inline {
+ display: inline-block;
+ vertical-align: middle;
+ width: 60%; }
+
+:root {
+ --spinner-back-color: #ddd;
+ --spinner-fore-color: #555; }
+
+@keyframes spinner-donut-anim {
+ 0% {
+ transform: rotate(0deg); }
+ 100% {
+ transform: rotate(360deg); } }
+.spinner {
+ display: inline-block;
+ margin: var(--universal-margin);
+ border: 0.25rem solid var(--spinner-back-color);
+ border-left: 0.25rem solid var(--spinner-fore-color);
+ border-radius: 50%;
+ width: 1.25rem;
+ height: 1.25rem;
+ animation: spinner-donut-anim 1.2s linear infinite; }
+
+/*
+ Custom elements for progress bars and spinners.
+*/
+progress.primary {
+ --progress-fore-color: #1976d2; }
+
+progress.secondary {
+ --progress-fore-color: #d32f2f; }
+
+progress.tertiary {
+ --progress-fore-color: #308732; }
+
+.spinner.primary {
+ --spinner-fore-color: #1976d2; }
+
+.spinner.secondary {
+ --spinner-fore-color: #d32f2f; }
+
+.spinner.tertiary {
+ --spinner-fore-color: #308732; }
+
+/*
+ Definitions for icons - powered by Feather (https://feathericons.com/).
+*/
+span[class^='icon-'] {
+ display: inline-block;
+ height: 1em;
+ width: 1em;
+ vertical-align: -0.125em;
+ background-size: contain;
+ margin: 0 calc(var(--universal-margin) / 4); }
+ span[class^='icon-'].secondary {
+ -webkit-filter: invert(25%);
+ filter: invert(25%); }
+ span[class^='icon-'].inverse {
+ -webkit-filter: invert(100%);
+ filter: invert(100%); }
+
+span.icon-alert {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-bookmark {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-calendar {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-credit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-edit {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+span.icon-link {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-help {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-home {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-info {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-lock {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-mail {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+span.icon-location {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-phone {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-rss {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+span.icon-search {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-settings {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-share {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-cart {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+span.icon-upload {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+span.icon-user {
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+
+/*
+ Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26).
+*/
+span.icon-st-update {
+ background-image: url("Update.svg"); }
+span.icon-st-add {
+ background-image: url("Add button.svg"); }
+
+/*
+ Definitions for utilities and helper classes.
+*/
+/* Utility module CSS variable definitions */
+:root {
+ --generic-border-color: rgba(0, 0, 0, 0.3);
+ --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); }
+
+.hidden {
+ display: none !important; }
+
+.visually-hidden {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; }
+
+.bordered {
+ border: 0.0714285714rem solid var(--generic-border-color) !important; }
+
+.rounded {
+ border-radius: var(--universal-border-radius) !important; }
+
+.circular {
+ border-radius: 50% !important; }
+
+.shadowed {
+ box-shadow: var(--generic-box-shadow) !important; }
+
+.responsive-margin {
+ margin: calc(var(--universal-margin) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-margin {
+ margin: calc(var(--universal-margin) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-margin {
+ margin: var(--universal-margin) !important; } }
+
+.responsive-padding {
+ padding: calc(var(--universal-padding) / 4) !important; }
+ @media screen and (min-width: 500px) {
+ .responsive-padding {
+ padding: calc(var(--universal-padding) / 2) !important; } }
+ @media screen and (min-width: 1280px) {
+ .responsive-padding {
+ padding: var(--universal-padding) !important; } }
+
+@media screen and (max-width: 499px) {
+ .hidden-sm {
+ display: none !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .hidden-md {
+ display: none !important; } }
+@media screen and (min-width: 1280px) {
+ .hidden-lg {
+ display: none !important; } }
+@media screen and (max-width: 499px) {
+ .visually-hidden-sm {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 500px) and (max-width: 1279px) {
+ .visually-hidden-md {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+@media screen and (min-width: 1280px) {
+ .visually-hidden-lg {
+ position: absolute !important;
+ width: 1px !important;
+ height: 1px !important;
+ margin: -1px !important;
+ border: 0 !important;
+ padding: 0 !important;
+ clip: rect(0 0 0 0) !important;
+ -webkit-clip-path: inset(100%) !important;
+ clip-path: inset(100%) !important;
+ overflow: hidden !important; } }
+
+/*# sourceMappingURL=mini-custom.css.map */
+
+img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; }
+img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;}
+
+.figure {
+ display: block;
+ margin-left: auto;
+ margin-right: auto;
+ text-align: center;
+}
\ No newline at end of file
diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/_htmresc/st_logo_2020.png b/system/Drivers/CMSIS/Device/ST/STM32H7xx/_htmresc/st_logo_2020.png
new file mode 100644
index 0000000000..d6cebb5ac7
Binary files /dev/null and b/system/Drivers/CMSIS/Device/ST/STM32H7xx/_htmresc/st_logo_2020.png differ
diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
index 883cc31089..aa365e83fb 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
+++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
@@ -8,7 +8,7 @@
* STM32F7: 1.2.7
* STM32G0: 1.4.1
* STM32G4: 1.2.2
- * STM32H7: 1.10.1
+ * STM32H7: 1.10.2
* STM32L0: 1.9.2
* STM32L1: 2.3.2
* STM32L4: 1.7.2
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
index 48aff551fa..844bb943af 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -104,6 +104,12 @@ extern "C" {
#if defined(STM32H7)
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
/**
* @}
*/
@@ -225,8 +231,11 @@ extern "C" {
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
+#if defined(STM32H5) || defined(STM32C0)
+#else
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+#endif
/**
* @}
*/
@@ -268,6 +277,11 @@ extern "C" {
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
#endif
+#if defined(STM32H5)
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
+#endif
+
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
@@ -410,6 +424,10 @@ extern "C" {
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
/**
* @}
*/
@@ -489,7 +507,7 @@ extern "C" {
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
-#if defined(STM32G0)
+#if defined(STM32G0) || defined(STM32C0)
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
#else
@@ -558,6 +576,106 @@ extern "C" {
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
+#if defined(STM32H5)
+#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
+#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
+#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
+#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
+#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
+#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
+
+#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
+#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
+#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
+#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
+
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
+
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
+
+#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
+
+#define SYSCFG_ETH_MII SBS_ETH_MII
+#define SYSCFG_ETH_RMII SBS_ETH_RMII
+#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
+
+#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
+#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
+#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
+
+#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
+
+#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
+#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU SBS_SAU
+#define SYSCFG_MPU_SEC SBS_MPU_SEC
+#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#else
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#endif /* __ARM_FEATURE_CMSE */
+
+#define SYSCFG_CLK SBS_CLK
+#define SYSCFG_CLASSB SBS_CLASSB
+#define SYSCFG_FPU SBS_FPU
+#define SYSCFG_ALL SBS_ALL
+
+#define SYSCFG_SEC SBS_SEC
+#define SYSCFG_NSEC SBS_NSEC
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
+
+#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
+#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
+#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
+
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
+
+#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
+#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
+
+#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
+#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
+#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
+#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
+#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
+#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
+#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
+
+#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
+#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
+#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
+#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
+#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
+#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
+
+#define HAL_SYSCFG_Lock HAL_SBS_Lock
+#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
+#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
+#endif /* __ARM_FEATURE_CMSE */
+
+#endif /* STM32H5 */
+
+
/**
* @}
*/
@@ -1690,6 +1808,79 @@ extern "C" {
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+#if defined (STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
+
+#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
+#endif
+
/**
* @}
*/
@@ -3323,7 +3514,10 @@ extern "C" {
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#if defined(STM32GK)
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_DISABLE
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_DISABLE
+#elif defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) || defined(STM32V7) || defined(STM32N6)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3458,7 +3652,9 @@ extern "C" {
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
#endif
/**
@@ -3477,7 +3673,7 @@ extern "C" {
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32GK) || defined (STM32WB_GEN2) || defined (STM32WBA) || defined (STM32V7) || defined (STM32H5) || defined (STM32C0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3530,6 +3726,10 @@ extern "C" {
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+#if defined (STM32H5)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
+#endif /* STM32H5 */
+
/**
* @}
*/
@@ -3541,7 +3741,7 @@ extern "C" {
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32h7xx_hal_eth_ex_legacy.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32h7xx_hal_eth_ex_legacy.h
new file mode 100644
index 0000000000..966f293553
--- /dev/null
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32h7xx_hal_eth_ex_legacy.h
@@ -0,0 +1,354 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_eth_ex_legacy.h
+ * @author MCD Application Team
+ * @brief Header file of ETH HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_ETH_EX_LEGACY_H
+#define STM32H7xx_HAL_ETH_EX_LEGACY_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(ETH)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ETHEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ETHEx_Exported_Types ETHEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief ETH RX VLAN structure definition
+ */
+typedef struct{
+ FunctionalState InnerVLANTagInStatus; /*!< Enables or disables Inner VLAN Tag in Rx Status */
+
+ uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive
+ This parameter can be a value of @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
+
+ FunctionalState InnerVLANTag; /*!< Enables or disables Inner VLAN Tag */
+
+ FunctionalState DoubleVLANProcessing; /*!< Enable or Disable double VLAN processing */
+
+ FunctionalState VLANTagHashTableMatch; /*!< Enable or Disable VLAN Tag Hash Table Match */
+
+ FunctionalState VLANTagInStatus; /*!< Enable or Disable VLAN Tag in Rx status */
+
+ uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive
+ This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */
+
+ uint32_t VLANTypeCheck; /*!< Enable or Disable VLAN Type Check
+ This parameter can be a value of @ref ETHEx_VLAN_Type_Check */
+
+ FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */
+}ETH_RxVLANConfigTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH TX VLAN structure definition
+ */
+typedef struct{
+ FunctionalState SourceTxDesc; /*!< Enable or Disable VLAN tag source from DMA tx descriptors */
+
+ FunctionalState SVLANType; /*!< Enable or Disable insertion of SVLAN type */
+
+ uint32_t VLANTagControl; /*!< Sets the VLAN tag control in tx packets
+ This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */
+}ETH_TxVLANConfigTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH L3 filter structure definition
+ */
+typedef struct{
+ uint32_t Protocol; /*!< Sets the L3 filter protocol to IPv4 or IPv6
+ This parameter can be a value of @ref ETHEx_L3_Protocol */
+
+ uint32_t SrcAddrFilterMatch; /*!< Sets the L3 filter source address match
+ This parameter can be a value of @ref ETHEx_L3_Source_Match */
+
+ uint32_t DestAddrFilterMatch; /*!< Sets the L3 filter destination address match
+ This parameter can be a value of @ref ETHEx_L3_Destination_Match */
+
+ uint32_t SrcAddrHigherBitsMatch; /*!< Sets the L3 filter source address higher bits match
+ This parameter can be a value from 0 to 31 */
+
+ uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match
+ This parameter can be a value from 0 to 31 */
+
+ uint32_t Ip4SrcAddr; /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used
+ This parameter can be a value from 0x0 to 0xFFFFFFFF */
+
+ uint32_t Ip4DestAddr; /*!< Sets the L3 filter IPv4 destination address if IPv4 protocol is used
+ This parameter can be a value from 0 to 0xFFFFFFFF */
+
+ uint32_t Ip6Addr[4]; /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used
+ This parameter must be a table of 4 words (4* 32 bits) */
+}ETH_L3FilterConfigTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH L4 filter structure definition
+ */
+typedef struct{
+ uint32_t Protocol; /*!< Sets the L4 filter protocol to TCP or UDP
+ This parameter can be a value of @ref ETHEx_L4_Protocol */
+
+ uint32_t SrcPortFilterMatch; /*!< Sets the L4 filter source port match
+ This parameter can be a value of @ref ETHEx_L4_Source_Match */
+
+ uint32_t DestPortFilterMatch; /*!< Sets the L4 filter destination port match
+ This parameter can be a value of @ref ETHEx_L4_Destination_Match */
+
+ uint32_t SourcePort; /*!< Sets the L4 filter source port
+ This parameter must be a value from 0x0 to 0xFFFF */
+
+ uint32_t DestinationPort; /*!< Sets the L4 filter destination port
+ This parameter must be a value from 0x0 to 0xFFFF */
+}ETH_L4FilterConfigTypeDef;
+/**
+ *
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants
+ * @{
+ */
+
+/** @defgroup ETHEx_LPI_Event ETHEx LPI Event
+ * @{
+ */
+#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN
+#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX
+#define ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN
+#define ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX
+/**
+ * @}
+ */
+
+/** @defgroup ETHEx_L3_Filter ETHEx L3 Filter
+ * @{
+ */
+#define ETH_L3_FILTER_0 ((uint32_t)0x00000000)
+#define ETH_L3_FILTER_1 ((uint32_t)0x0000000C)
+/**
+ * @}
+ */
+
+/** @defgroup ETHEx_L4_Filter ETHEx L4 Filter
+ * @{
+ */
+#define ETH_L4_FILTER_0 ((uint32_t)0x00000000)
+#define ETH_L4_FILTER_1 ((uint32_t)0x0000000C)
+/**
+ * @}
+ */
+
+/** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol
+ * @{
+ */
+#define ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN
+#define ETH_L3_IPV4_MATCH ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match
+ * @{
+ */
+#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM
+#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)
+#define ETH_L3_SRC_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match
+ * @{
+ */
+#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM
+#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)
+#define ETH_L3_DEST_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol
+ * @{
+ */
+#define ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN
+#define ETH_L4_TCP_MATCH ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match
+ * @{
+ */
+#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM
+#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
+#define ETH_L4_SRC_PORT_MATCH_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match
+ * @{
+ */
+#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM
+#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)
+#define ETH_L4_DEST_PORT_MATCH_DISABLE ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping
+ * @{
+ */
+#define ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP
+#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS
+#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS
+#define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EIVLS_ALWAYSSTRIP
+/**
+ * @}
+ */
+
+/** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping
+ * @{
+ */
+#define ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP
+#define ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS
+#define ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS
+#define ETH_VLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EVLS_ALWAYSSTRIP
+/**
+ * @}
+ */
+
+/** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check
+ * @{
+ */
+#define ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC
+#define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)
+#define ETH_VLANTYPECHECK_CVLAN ((uint32_t)0x00000000)
+/**
+ * @}
+ */
+
+/** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control
+ * @{
+ */
+#define ETH_VLANTAGCONTROL_NONE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)
+#define ETH_VLANTAGCONTROL_DELETE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)
+#define ETH_VLANTAGCONTROL_INSERT (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)
+#define ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)
+/**
+ * @}
+ */
+
+/** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag
+ * @{
+ */
+#define ETH_INNER_TX_VLANTAG ((uint32_t)0x00000001U)
+#define ETH_OUTER_TX_VLANTAG ((uint32_t)0x00000000U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ETHEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ETHEx_Exported_Functions_Group1
+ * @{
+ */
+/* MAC ARP Offloading APIs ***************************************************/
+void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth);
+void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth);
+void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress);
+
+/* MAC L3 L4 Filtering APIs ***************************************************/
+void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
+void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
+
+/* MAC VLAN Processing APIs ************************************************/
+void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
+void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
+void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
+HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
+void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier);
+
+/* Energy Efficient Ethernet APIs *********************************************/
+void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop);
+void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
+uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ETH */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_ETH_EX_LEGACY_H */
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32h7xx_hal_eth_legacy.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32h7xx_hal_eth_legacy.h
new file mode 100644
index 0000000000..878036dd81
--- /dev/null
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32h7xx_hal_eth_legacy.h
@@ -0,0 +1,1682 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_eth_legacy.h
+ * @author MCD Application Team
+ * @brief Header file of ETH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_ETH_LEGACY_H
+#define STM32H7xx_HAL_ETH_LEGACY_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+#if defined(ETH)
+
+/** @addtogroup STM32H7xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ETH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#ifndef ETH_TX_DESC_CNT
+ #define ETH_TX_DESC_CNT 4U
+#endif
+
+#ifndef ETH_RX_DESC_CNT
+ #define ETH_RX_DESC_CNT 4U
+#endif
+
+/*********************** Descriptors struct def section ************************/
+/** @defgroup ETH_Exported_Types ETH Exported Types
+ * @{
+ */
+
+/**
+ * @brief ETH DMA Descriptor structure definition
+ */
+typedef struct
+{
+ __IO uint32_t DESC0;
+ __IO uint32_t DESC1;
+ __IO uint32_t DESC2;
+ __IO uint32_t DESC3;
+ uint32_t BackupAddr0; /* used to store rx buffer 1 address */
+ uint32_t BackupAddr1; /* used to store rx buffer 2 address */
+}ETH_DMADescTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH Buffers List structure definition
+ */
+typedef struct __ETH_BufferTypeDef
+{
+ uint8_t *buffer; /*<! buffer address */
+
+ uint32_t len; /*<! buffer length */
+
+ struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
+}ETH_BufferTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief DMA Transmit Descriptors Wrapper structure definition
+ */
+typedef struct
+{
+ uint32_t TxDesc[ETH_TX_DESC_CNT]; /*<! Tx DMA descriptors addresses */
+
+ uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */
+
+ uint32_t* PacketAddress[ETH_TX_DESC_CNT]; /*<! Ethernet packet addresses array */
+
+ uint32_t* CurrentPacketAddress; /*<! Current transmit NX_PACKET addresses */
+
+ uint32_t BuffersInUse; /*<! Buffers in Use */
+}ETH_TxDescListTypeDef;
+/**
+ *
+ */
+
+ /**
+ * @brief Transmit Packet Configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Attributes; /*!< Tx packet HW features capabilities.
+ This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
+
+ uint32_t Length; /*!< Total packet length */
+
+ ETH_BufferTypeDef *TxBuffer; /*!< Tx buffers pointers */
+
+ uint32_t SrcAddrCtrl; /*!< Specifies the source address insertion control.
+ This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
+
+ uint32_t CRCPadCtrl; /*!< Specifies the CRC and Pad insertion and replacement control.
+ This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control */
+
+ uint32_t ChecksumCtrl; /*!< Specifies the checksum insertion control.
+ This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control */
+
+ uint32_t MaxSegmentSize; /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
+ This parameter can be a value from 0x0 to 0x3FFF */
+
+ uint32_t PayloadLen; /*!< Sets Total payload length only when TCP segmentation is enabled.
+ This parameter can be a value from 0x0 to 0x3FFFF */
+
+ uint32_t TCPHeaderLen; /*!< Sets TCP header length only when TCP segmentation is enabled.
+ This parameter can be a value from 0x5 to 0xF */
+
+ uint32_t VlanTag; /*!< Sets VLAN Tag only when VLAN is enabled.
+ This parameter can be a value from 0x0 to 0xFFFF*/
+
+ uint32_t VlanCtrl; /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
+ This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
+
+ uint32_t InnerVlanTag; /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
+ This parameter can be a value from 0x0 to 0x3FFFF */
+
+ uint32_t InnerVlanCtrl; /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
+ This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control */
+
+}ETH_TxPacketConfig;
+/**
+ *
+ */
+
+/**
+ * @brief DMA Receive Descriptors Wrapper structure definition
+ */
+typedef struct
+{
+ uint32_t RxDesc[ETH_RX_DESC_CNT]; /*<! Rx DMA descriptors addresses. */
+
+ uint32_t CurRxDesc; /*<! Current Rx descriptor, ready for next reception. */
+
+ uint32_t FirstAppDesc; /*<! First descriptor of last received packet. */
+
+ uint32_t AppDescNbr; /*<! Number of descriptors of last received packet. */
+
+ uint32_t AppContextDesc; /*<! If 1 a context descriptor is present in last received packet.
+ If 0 no context descriptor is present in last received packet. */
+
+ uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt.
+ If 0, DMA will not generate the Rx complete interrupt. */
+}ETH_RxDescListTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief Received Packet Information structure definition
+ */
+typedef struct
+{
+ uint32_t SegmentCnt; /*<! Number of Rx Descriptors */
+
+ uint32_t VlanTag; /*<! Vlan Tag value */
+
+ uint32_t InnerVlanTag; /*<! Inner Vlan Tag value */
+
+ uint32_t Checksum; /*<! Rx Checksum status.
+ This parameter can be a value of @ref ETH_Rx_Checksum_Status */
+
+ uint32_t HeaderType; /*<! IP header type.
+ This parameter can be a value of @ref ETH_Rx_IP_Header_Type */
+
+ uint32_t PayloadType; /*<! Payload type.
+ This parameter can be a value of @ref ETH_Rx_Payload_Type */
+
+ uint32_t MacFilterStatus; /*<! MAC filter status.
+ This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */
+
+ uint32_t L3FilterStatus; /*<! L3 filter status
+ This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */
+
+ uint32_t L4FilterStatus; /*<! L4 filter status
+ This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */
+
+ uint32_t ErrorCode; /*<! Rx error code
+ This parameter can be a combination of @ref ETH_Rx_Error_Code */
+
+} ETH_RxPacketInfo;
+/**
+ *
+ */
+
+/**
+ * @brief ETH MAC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t SourceAddrControl; /*!< Selects the Source Address Insertion or Replacement Control.
+ This parameter can be a value of @ref ETH_Source_Addr_Control */
+
+ FunctionalState ChecksumOffload; /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
+
+ uint32_t InterPacketGapVal; /*!< Sets the minimum IPG between Packet during transmission.
+ This parameter can be a value of @ref ETH_Inter_Packet_Gap */
+
+ FunctionalState GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
+
+ FunctionalState Support2KPacket; /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
+
+ FunctionalState CRCStripTypePacket; /*!< Enables or disables the CRC stripping for Type packets.*/
+
+ FunctionalState AutomaticPadCRCStrip; /*!< Enables or disables the Automatic MAC Pad/CRC Stripping.*/
+
+ FunctionalState Watchdog; /*!< Enables or disables the Watchdog timer on Rx path
+ When enabled, the MAC allows no more then 2048 bytes to be received.
+ When disabled, the MAC can receive up to 16384 bytes. */
+
+ FunctionalState Jabber; /*!< Enables or disables Jabber timer on Tx path
+ When enabled, the MAC allows no more then 2048 bytes to be sent.
+ When disabled, the MAC can send up to 16384 bytes. */
+
+ FunctionalState JumboPacket; /*!< Enables or disables receiving Jumbo Packet
+ When enabled, the MAC allows jumbo packets of 9,018 bytes
+ without reporting a giant packet error */
+
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
+ This parameter can be a value of @ref ETH_Speed */
+
+ uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+ This parameter can be a value of @ref ETH_Duplex_Mode */
+
+ FunctionalState LoopbackMode; /*!< Enables or disables the loopback mode */
+
+ FunctionalState CarrierSenseBeforeTransmit; /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
+
+ FunctionalState ReceiveOwn; /*!< Enables or disables the Receive Own in Half Duplex mode. */
+
+ FunctionalState CarrierSenseDuringTransmit; /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
+
+ FunctionalState RetryTransmission; /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
+
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
+ This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+ FunctionalState DeferralCheck; /*!< Enables or disables the deferral check function in Half Duplex mode. */
+
+ uint32_t PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
+ This parameter can be a value of @ref ETH_Preamble_Length */
+
+ FunctionalState UnicastSlowProtocolPacketDetect; /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
+
+ FunctionalState SlowProtocolDetect; /*!< Enable or disables the Slow Protocol Detection. */
+
+ FunctionalState CRCCheckingRxPackets; /*!< Enable or disables the CRC Checking for Received Packets. */
+
+ uint32_t GiantPacketSizeLimit; /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
+ greater than the value programmed in this field in units of bytes
+ This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/
+
+ FunctionalState ExtendedInterPacketGap; /*!< Enable or disables the extended inter packet gap. */
+
+ uint32_t ExtendedInterPacketGapVal; /*!< Sets the Extended IPG between Packet during transmission.
+ This parameter can be a value from 0x0 to 0xFF */
+
+ FunctionalState ProgrammableWatchdog; /*!< Enable or disables the Programmable Watchdog.*/
+
+ uint32_t WatchdogTimeout; /*!< This field is used as watchdog timeout for a received packet
+ This parameter can be a value of @ref ETH_Watchdog_Timeout */
+
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
+
+ FunctionalState ZeroQuantaPause; /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
+
+ uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+
+ FunctionalState TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
+ or the MAC back pressure operation in Half Duplex mode */
+
+ FunctionalState UnicastPausePacketDetect; /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
+
+ FunctionalState ReceiveFlowControl; /*!< Enables or disables the MAC to decodes the received Pause packet
+ and disables its transmitter for a specified (Pause) time */
+
+ uint32_t TransmitQueueMode; /*!< Specifies the Transmit Queue operating mode.
+ This parameter can be a value of @ref ETH_Transmit_Mode */
+
+ uint32_t ReceiveQueueMode; /*!< Specifies the Receive Queue operating mode.
+ This parameter can be a value of @ref ETH_Receive_Mode */
+
+ FunctionalState DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */
+
+ FunctionalState ForwardRxErrorPacket; /*!< Enables or disables forwarding Error Packets. */
+
+ FunctionalState ForwardRxUndersizedGoodPacket; /*!< Enables or disables forwarding Undersized Good Packets.*/
+} ETH_MACConfigTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH DMA Configuration Structure definition
+ */
+ typedef struct
+ {
+ uint32_t DMAArbitration; /*!< Sets the arbitration scheme between DMA Tx and Rx
+ This parameter can be a value of @ref ETH_DMA_Arbitration */
+
+ FunctionalState AddressAlignedBeats; /*!< Enables or disables the AHB Master interface address aligned
+ burst transfers on Read and Write channels */
+
+ uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers.
+ This parameter can be a value of @ref ETH_Burst_Mode */
+
+ FunctionalState RebuildINCRxBurst; /*!< Enables or disables the AHB Master to rebuild the pending beats
+ of any initiated burst transfer with INCRx and SINGLE transfers. */
+
+ FunctionalState PBLx8Mode; /*!< Enables or disables the PBL multiplication by eight. */
+
+ uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
+
+ FunctionalState SecondPacketOperate; /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
+ Packet of Transmit data even before obtaining the status for the first one. */
+
+ uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
+
+ FunctionalState FlushRxPacket; /*!< Enables or disables the Rx Packet Flush */
+
+ FunctionalState TCPSegmentation; /*!< Enables or disables the TCP Segmentation */
+
+ uint32_t MaximumSegmentSize; /*!< Sets the maximum segment size that should be used while segmenting the packet
+ This parameter can be a value from 0x40 to 0x3FFF */
+} ETH_DMAConfigTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief HAL ETH Media Interfaces enum definition
+ */
+typedef enum
+{
+ HAL_ETH_MII_MODE = 0x00U, /*!< Media Independent Interface */
+ HAL_ETH_RMII_MODE = 0x01U /*!< Reduced Media Independent Interface */
+}ETH_MediaInterfaceTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH Init Structure definition
+ */
+typedef struct
+{
+
+ uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
+
+ ETH_MediaInterfaceTypeDef MediaInterface; /*!< Selects the MII interface or the RMII interface. */
+
+ ETH_DMADescTypeDef *TxDesc; /*!< Provides the address of the first DMA Tx descriptor in the list */
+
+ ETH_DMADescTypeDef *RxDesc; /*!< Provides the address of the first DMA Rx descriptor in the list */
+
+ uint32_t RxBuffLen; /*!< Provides the length of Rx buffers size */
+
+}ETH_InitTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef uint32_t HAL_ETH_StateTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH Handle Structure definition
+ */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+typedef struct __ETH_HandleTypeDef
+#else
+typedef struct
+#endif
+{
+ ETH_TypeDef *Instance; /*!< Register base address */
+
+ ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
+
+ ETH_TxDescListTypeDef TxDescList; /*!< Tx descriptor wrapper: holds all Tx descriptors list
+ addresses and current descriptor index */
+
+ ETH_RxDescListTypeDef RxDescList; /*!< Rx descriptor wrapper: holds all Rx descriptors list
+ addresses and current descriptor index */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_ETH_StateTypeDef */
+
+ __IO HAL_ETH_StateTypeDef RxState; /*!< ETH state information related to Rx operations.
+ This parameter can be a value of @ref HAL_ETH_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine
+ This parameter can be a value of of @ref ETH_Error_Code */
+
+ __IO uint32_t DMAErrorCode; /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
+ This parameter can be a combination of @ref ETH_DMA_Status_Flags */
+
+ __IO uint32_t MACErrorCode; /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
+ This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */
+
+ __IO uint32_t MACWakeUpEvent; /*!< Holds the Wake Up event when the MAC exit the power down mode
+ This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */
+
+ __IO uint32_t MACLPIEvent; /*!< Holds the LPI event when the an LPI status interrupt occurs.
+ This parameter can be a value of @ref ETHEx_LPI_Event */
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+
+ void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */
+ void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */
+ void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH DMA Error Callback */
+ void (* MACErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH MAC Error Callback */
+ void (* PMTCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Power Management Callback */
+ void (* EEECallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH EEE Callback */
+ void (* WakeUpCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Wake UP Callback */
+
+ void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */
+ void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */
+
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+} ETH_HandleTypeDef;
+/**
+ *
+ */
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL ETH Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
+ HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
+
+ HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
+ HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
+ HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */
+ HAL_ETH_MAC_ERROR_CB_ID = 0x05U, /*!< ETH MAC Error Callback ID */
+ HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */
+ HAL_ETH_EEE_CB_ID = 0x07U, /*!< ETH EEE Callback ID */
+ HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */
+
+
+}HAL_ETH_CallbackIDTypeDef;
+
+/**
+ * @brief HAL ETH Callback pointer definition
+ */
+typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */
+
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+ * @brief ETH MAC filter structure definition
+ */
+typedef struct{
+ FunctionalState PromiscuousMode; /*!< Enable or Disable Promiscuous Mode */
+
+ FunctionalState ReceiveAllMode; /*!< Enable or Disable Receive All Mode */
+
+ FunctionalState HachOrPerfectFilter; /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
+
+ FunctionalState HashUnicast; /*!< Enable or Disable Hash filtering on unicast packets */
+
+ FunctionalState HashMulticast; /*!< Enable or Disable Hash filtering on multicast packets */
+
+ FunctionalState PassAllMulticast; /*!< Enable or Disable passing all multicast packets */
+
+ FunctionalState SrcAddrFiltering; /*!< Enable or Disable source address filtering module */
+
+ FunctionalState SrcAddrInverseFiltering; /*!< Enable or Disable source address inverse filtering */
+
+ FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
+
+ FunctionalState BroadcastFilter; /*!< Enable or Disable broadcast filter */
+
+ uint32_t ControlPacketsFilter; /*!< Set the control packets filter
+ This parameter can be a value of @ref ETH_Control_Packets_Filter */
+}ETH_MACFilterConfigTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH Power Down structure definition
+ */
+typedef struct{
+ FunctionalState WakeUpPacket; /*!< Enable or Disable Wake up packet detection in power down mode */
+
+ FunctionalState MagicPacket; /*!< Enable or Disable Magic packet detection in power down mode */
+
+ FunctionalState GlobalUnicast; /*!< Enable or Disable Global unicast packet detection in power down mode */
+
+ FunctionalState WakeUpForward; /*!< Enable or Disable Forwarding Wake up packets */
+
+}ETH_PowerDownConfigTypeDef;
+/**
+ *
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ETH_Exported_Constants ETH Exported Constants
+ * @{
+ */
+
+/** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
+ * @{
+ */
+
+/*
+ DMA Tx Normal Descriptor Read Format
+ -----------------------------------------------------------------------------------------------
+ TDES0 | Buffer1 or Header Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES1 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
+ -----------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of TDES0 RF register
+ */
+#define ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */
+
+/**
+ * @brief Bit definition of TDES1 RF register
+ */
+#define ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */
+
+/**
+ * @brief Bit definition of TDES2 RF register
+ */
+#define ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000U) /*!< Interrupt on Completion */
+#define ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000U) /*!< Transmit Timestamp Enable */
+#define ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000U) /*!< Buffer 2 Length */
+#define ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000U) /*!< VLAN Tag Insertion or Replacement mask */
+#define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add a VLAN tag. */
+#define ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000U) /*!< Remove the VLAN tag from the packets before transmission. */
+#define ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000U) /*!< Insert a VLAN tag. */
+#define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U) /*!< Replace the VLAN tag. */
+#define ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFFU) /*!< Buffer 1 Length */
+#define ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FFU) /*!< Header Length */
+
+/**
+ * @brief Bit definition of TDES3 RF register
+ */
+#define ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */
+#define ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */
+#define ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */
+#define ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000U) /*!< CRC Pad Control mask */
+#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000U) /*!< CRC Pad Control: CRC and Pad Insertion */
+#define ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000U) /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
+#define ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000U) /*!< CRC Pad Control: Disable CRC Insertion */
+#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000U) /*!< CRC Pad Control: CRC Replacement */
+#define ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000U) /*!< SA Insertion Control mask*/
+#define ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000U) /*!< SA Insertion Control: Do not include the source address */
+#define ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000U) /*!< SA Insertion Control: Include or insert the source address */
+#define ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000U) /*!< SA Insertion Control: Replace the source address */
+#define ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000U) /*!< TCP Header Length */
+#define ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000U) /*!< TCP segmentation enable */
+#define ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000U) /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is disabled */
+#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000U) /*!< Only IP header checksum calculation and insertion are enabled. */
+#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000U) /*!< IP header checksum and payload checksum calculation and insertion are
+ enabled, but pseudo header checksum is not calculated in hardware */
+#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000U) /*!< IP Header checksum and payload checksum calculation and insertion are
+ enabled, and pseudo header checksum is calculated in hardware. */
+#define ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFFU) /*!< TCP Payload Length */
+#define ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFFU) /*!< Transmit End of Ring */
+
+/*
+ DMA Tx Normal Descriptor Write Back Format
+ -----------------------------------------------------------------------------------------------
+ TDES0 | Timestamp Low |
+ -----------------------------------------------------------------------------------------------
+ TDES1 | Timestamp High |
+ -----------------------------------------------------------------------------------------------
+ TDES2 | Reserved[31:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES3 | OWN(31) | Status[30:0] |
+ -----------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of TDES0 WBF register
+ */
+#define ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
+
+/**
+ * @brief Bit definition of TDES1 WBF register
+ */
+#define ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */
+
+/**
+ * @brief Bit definition of TDES3 WBF register
+ */
+#define ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */
+#define ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */
+#define ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */
+#define ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000U) /*!< Tx Timestamp Status */
+#define ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000U) /*!< Disable Padding */
+#define ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000U) /*!< Transmit Timestamp Enable */
+#define ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
+#define ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */
+#define ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000U) /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
+#define ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */
+#define ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0U) /*!< Collision Count */
+#define ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008U) /*!< Excessive Deferral */
+#define ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004U) /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002U) /*!< Deferred Bit */
+#define ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004U) /*!< IP Header Error */
+
+
+/*
+ DMA Tx Context Descriptor
+ -----------------------------------------------------------------------------------------------
+ TDES0 | Timestamp Low |
+ -----------------------------------------------------------------------------------------------
+ TDES1 | Timestamp High |
+ -----------------------------------------------------------------------------------------------
+ TDES2 | Inner VLAN Tag[31:16] | Reserved(15) | Maximum Segment Size [14:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES3 | OWN(31) | Status[30:0] |
+ -----------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of Tx context descriptor register 0
+ */
+#define ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */
+
+/**
+ * @brief Bit definition of Tx context descriptor register 1
+ */
+#define ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */
+
+/**
+ * @brief Bit definition of Tx context descriptor register 2
+ */
+#define ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */
+#define ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFFU) /*!< Maximum Segment Size */
+
+/**
+ * @brief Bit definition of Tx context descriptor register 3
+ */
+#define ETH_DMATXCDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Context Type */
+#define ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000U) /*!< One-Step Timestamp Correction Enable */
+#define ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000U) /*!< One-Step Timestamp Correction Input or MSS Valid */
+#define ETH_DMATXCDESC_CDE ((uint32_t)0x00800000U) /*!< Context Descriptor Error */
+#define ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000U) /*!< Inner VLAN Tag Insert or Replace Mask */
+#define ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add the inner VLAN tag. */
+#define ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000U) /*!< Remove the inner VLAN tag from the packets before transmission. */
+#define ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000U) /*!< Insert the inner VLAN tag. */
+#define ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000U) /*!< Replace the inner VLAN tag. */
+#define ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000U) /*!< Inner VLAN Tag Valid */
+#define ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000U) /*!< VLAN Tag Valid */
+#define ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFFU) /*!< VLAN Tag */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
+ * @{
+ */
+
+/*
+ DMA Rx Normal Descriptor read format
+ -----------------------------------------------------------------------------------------------------------
+ RDES0 | Buffer1 or Header Address [31:0] |
+ -----------------------------------------------------------------------------------------------------------
+ RDES1 | Reserved |
+ -----------------------------------------------------------------------------------------------------------
+ RDES2 | Payload or Buffer2 Address[31:0] |
+ -----------------------------------------------------------------------------------------------------------
+ RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) | Reserved [23:0] |
+ -----------------------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of Rx normal descriptor register 0 read format
+ */
+#define ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFFU) /*!< Header or Buffer 1 Address Pointer */
+
+/**
+ * @brief Bit definition of Rx normal descriptor register 2 read format
+ */
+#define ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer 2 Address Pointer */
+
+/**
+ * @brief Bit definition of Rx normal descriptor register 3 read format
+ */
+#define ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000U) /*!< Interrupt Enabled on Completion */
+#define ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000U) /*!< Buffer 2 Address Valid */
+#define ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000U) /*!< Buffer 1 Address Valid */
+
+/*
+ DMA Rx Normal Descriptor write back format
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES0 | Inner VLAN Tag[31:16] | Outer VLAN Tag[15:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES1 | OAM code, or MAC Control Opcode [31:16] | Extended Status |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES2 | MAC Filter Status[31:16] | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES3 | OWN(31) | CTXT(30) | FD(29) | LD(28) | Status[27:16] | ES(15) | Packet Length[14:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of Rx normal descriptor register 0 write back format
+ */
+#define ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */
+#define ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFFU) /*!< Outer VLAN Tag */
+
+/**
+ * @brief Bit definition of Rx normal descriptor register 1 write back format
+ */
+#define ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000U) /*!< OAM Sub-Type Code, or MAC Control Packet opcode */
+#define ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000U) /*!< Timestamp Dropped */
+#define ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000U) /*!< Timestamp Available */
+#define ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000U) /*!< PTP Version */
+#define ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000U) /*!< PTP Packet Type */
+#define ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000U) /*!< PTP Message Type: No PTP message received */
+#define ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100U) /*!< PTP Message Type: SYNC (all clock types) */
+#define ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200U) /*!< PTP Message Type: Follow_Up (all clock types) */
+#define ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300U) /*!< PTP Message Type: Delay_Req (all clock types) */
+#define ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400U) /*!< PTP Message Type: Delay_Resp (all clock types) */
+#define ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500U) /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock) */
+#define ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600U) /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock) */
+#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700U) /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) */
+#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800U) /*!< PTP Message Type: Announce */
+#define ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900U) /*!< PTP Message Type: Management */
+#define ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00U) /*!< PTP Message Type: Signaling */
+#define ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00U) /*!< PTP Message Type: PTP packet with Reserved message type */
+#define ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080U) /*!< IP Payload Error */
+#define ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040U) /*!< IP Checksum Bypassed */
+#define ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020U) /*!< IPv6 header Present */
+#define ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010U) /*!< IPv4 header Present */
+#define ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008U) /*!< IP Header Error */
+#define ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003U) /*!< Payload Type mask */
+#define ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000U) /*!< Payload Type: Unknown type or IP/AV payload not processed */
+#define ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001U) /*!< Payload Type: UDP */
+#define ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002U) /*!< Payload Type: TCP */
+#define ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003U) /*!< Payload Type: ICMP */
+
+/**
+ * @brief Bit definition of Rx normal descriptor register 2 write back format
+ */
+#define ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000U) /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
+#define ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000U) /*!< Layer 4 Filter Match */
+#define ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000U) /*!< Layer 3 Filter Match */
+#define ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000U) /*!< MAC Address Match or Hash Value */
+#define ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000U) /*!< Hash Filter Status */
+#define ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000U) /*!< Destination Address Filter Fail */
+#define ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000U) /*!< SA Address Filter Fail */
+#define ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000U) /*!< VLAN Filter Status */
+#define ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400U) /*!< ARP Reply Not Generated */
+
+
+/**
+ * @brief Bit definition of Rx normal descriptor register 3 write back format
+ */
+#define ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< Own Bit */
+#define ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */
+#define ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */
+#define ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */
+#define ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000U) /*!< Receive Status RDES2 Valid */
+#define ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000U) /*!< Receive Status RDES1 Valid */
+#define ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000U) /*!< Receive Status RDES0 Valid */
+#define ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000U) /*!< CRC Error */
+#define ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000U) /*!< Giant Packet */
+#define ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000U) /*!< Receive Watchdog Timeout */
+#define ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000U) /*!< Overflow Error */
+#define ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000U) /*!< Receive Error */
+#define ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000U) /*!< Dribble Bit Error */
+#define ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000U) /*!< Length/Type Field */
+#define ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000U) /*!< The packet is a length packet */
+#define ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000U) /*!< The packet is a type packet */
+#define ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000U) /*!< The packet is a ARP Request packet type */
+#define ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000U) /*!< The packet is a type packet with VLAN Tag */
+#define ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000U) /*!< The packet is a type packet with Double VLAN Tag */
+#define ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000U) /*!< The packet is a MAC Control packet type */
+#define ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000U) /*!< The packet is a OAM packet type */
+#define ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error Summary */
+#define ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFFU) /*!< Packet Length */
+
+/*
+ DMA Rx context Descriptor
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES0 | Timestamp Low[31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES1 | Timestamp High[31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES2 | Reserved |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES3 | OWN(31) | CTXT(30) | Reserved[29:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of Rx context descriptor register 0
+ */
+#define ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp Low */
+
+/**
+ * @brief Bit definition of Rx context descriptor register 1
+ */
+#define ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp High */
+
+/**
+ * @brief Bit definition of Rx context descriptor register 3
+ */
+#define ETH_DMARXCDESC_OWN ((uint32_t)0x80000000U) /*!< Own Bit */
+#define ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Frame_settings ETH frame settings
+ * @{
+ */
+#define ETH_MAX_PACKET_SIZE ((uint32_t)1528U) /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */
+#define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */
+#define ETH_MAX_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Error_Code ETH Error Code
+ * @{
+ */
+#define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Busy error */
+#define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U) /*!< Parameter error */
+#define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */
+#define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
+#define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U) /*!< MAC transfer error */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+#define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
+ * @{
+ */
+#define ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001U)
+#define ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002U)
+#define ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004U)
+#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008U)
+#define ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010U)
+#define ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020U)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
+ * @{
+ */
+#define ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE
+#define ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT
+#define ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
+ * @{
+ */
+#define ETH_CRC_PAD_DISABLE ETH_DMATXNDESCRF_CPC_DISABLE
+#define ETH_CRC_PAD_INSERT ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
+#define ETH_CRC_INSERT ETH_DMATXNDESCRF_CPC_CRC_INSERT
+#define ETH_CRC_REPLACE ETH_DMATXNDESCRF_CPC_CRC_REPLACE
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
+ * @{
+ */
+#define ETH_CHECKSUM_DISABLE ETH_DMATXNDESCRF_CIC_DISABLE
+#define ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
+#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
+#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
+ * @{
+ */
+#define ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE
+#define ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE
+#define ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT
+#define ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
+ * @{
+ */
+#define ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE
+#define ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE
+#define ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT
+#define ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status
+ * @{
+ */
+#define ETH_CHECKSUM_BYPASSED ETH_DMARXNDESCWBF_IPCB
+#define ETH_CHECKSUM_IP_HEADER_ERROR ETH_DMARXNDESCWBF_IPHE
+#define ETH_CHECKSUM_IP_PAYLOAD_ERROR ETH_DMARXNDESCWBF_IPCE
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type
+ * @{
+ */
+#define ETH_IP_HEADER_IPV4 ETH_DMARXNDESCWBF_IPV4
+#define ETH_IP_HEADER_IPV6 ETH_DMARXNDESCWBF_IPV6
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type
+ * @{
+ */
+#define ETH_IP_PAYLOAD_UNKNOWN ETH_DMARXNDESCWBF_PT_UNKNOWN
+#define ETH_IP_PAYLOAD_UDP ETH_DMARXNDESCWBF_PT_UDP
+#define ETH_IP_PAYLOAD_TCP ETH_DMARXNDESCWBF_PT_TCP
+#define ETH_IP_PAYLOAD_ICMPN ETH_DMARXNDESCWBF_PT_ICMP
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
+ * @{
+ */
+#define ETH_HASH_FILTER_PASS ETH_DMARXNDESCWBF_HF
+#define ETH_VLAN_FILTER_PASS ETH_DMARXNDESCWBF_VF
+#define ETH_DEST_ADDRESS_FAIL ETH_DMARXNDESCWBF_DAF
+#define ETH_SOURCE_ADDRESS_FAIL ETH_DMARXNDESCWBF_SAF
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
+ * @{
+ */
+#define ETH_L3_FILTER0_MATCH ETH_DMARXNDESCWBF_L3FM
+#define ETH_L3_FILTER1_MATCH (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status
+ * @{
+ */
+#define ETH_L4_FILTER0_MATCH ETH_DMARXNDESCWBF_L4FM
+#define ETH_L4_FILTER1_MATCH (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
+ * @{
+ */
+#define ETH_DRIBBLE_BIT_ERROR ETH_DMARXNDESCWBF_DE
+#define ETH_RECEIVE_ERROR ETH_DMARXNDESCWBF_RE
+#define ETH_RECEIVE_OVERFLOW ETH_DMARXNDESCWBF_OE
+#define ETH_WATCHDOG_TIMEOUT ETH_DMARXNDESCWBF_RWT
+#define ETH_GIANT_PACKET ETH_DMARXNDESCWBF_GP
+#define ETH_CRC_ERROR ETH_DMARXNDESCWBF_CE
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
+ * @{
+ */
+#define ETH_DMAARBITRATION_RX ETH_DMAMR_DA
+#define ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000U)
+#define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1
+#define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1
+#define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1
+#define ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1
+#define ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1
+#define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1
+#define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1
+#define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
+#define ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000U)
+#define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
+#define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
+#define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
+#define ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
+#define ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
+#define ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
+#define ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)
+/**
+ * @}
+ */
+
+ /** @defgroup ETH_Burst_Mode ETH Burst Mode
+ * @{
+ */
+#define ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB
+#define ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB
+#define ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000U)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
+ * @{
+ */
+#define ETH_TXDMABURSTLENGTH_1BEAT ETH_DMACTCR_TPBL_1PBL
+#define ETH_TXDMABURSTLENGTH_2BEAT ETH_DMACTCR_TPBL_2PBL
+#define ETH_TXDMABURSTLENGTH_4BEAT ETH_DMACTCR_TPBL_4PBL
+#define ETH_TXDMABURSTLENGTH_8BEAT ETH_DMACTCR_TPBL_8PBL
+#define ETH_TXDMABURSTLENGTH_16BEAT ETH_DMACTCR_TPBL_16PBL
+#define ETH_TXDMABURSTLENGTH_32BEAT ETH_DMACTCR_TPBL_32PBL
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
+ * @{
+ */
+#define ETH_RXDMABURSTLENGTH_1BEAT ETH_DMACRCR_RPBL_1PBL
+#define ETH_RXDMABURSTLENGTH_2BEAT ETH_DMACRCR_RPBL_2PBL
+#define ETH_RXDMABURSTLENGTH_4BEAT ETH_DMACRCR_RPBL_4PBL
+#define ETH_RXDMABURSTLENGTH_8BEAT ETH_DMACRCR_RPBL_8PBL
+#define ETH_RXDMABURSTLENGTH_16BEAT ETH_DMACRCR_RPBL_16PBL
+#define ETH_RXDMABURSTLENGTH_32BEAT ETH_DMACRCR_RPBL_32PBL
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
+ * @{
+ */
+#define ETH_DMA_NORMAL_IT ETH_DMACIER_NIE
+#define ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE
+#define ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE
+#define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE
+#define ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE
+#define ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE
+#define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE
+#define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE
+#define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE
+#define ETH_DMA_RX_IT ETH_DMACIER_RIE
+#define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE
+#define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE
+#define ETH_DMA_TX_IT ETH_DMACIER_TIE
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
+ * @{
+ */
+#define ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
+#define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
+#define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
+#define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
+#define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2
+#define ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
+#define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
+#define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
+#define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
+#define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2
+#define ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE
+#define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE
+#define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI
+#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT
+#define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS
+#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU
+#define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Mode ETH Transmit Mode
+ * @{
+ */
+#define ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF
+#define ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS
+#define ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS
+#define ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS
+#define ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS
+#define ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS
+#define ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS
+#define ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS
+#define ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Mode ETH Receive Mode
+ * @{
+ */
+#define ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF
+#define ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS
+#define ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS
+#define ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS
+#define ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
+ * @{
+ */
+#define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4
+#define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28
+#define ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36
+#define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144
+#define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256
+#define ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
+ * @{
+ */
+#define ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB
+#define ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB
+#define ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB
+#define ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB
+#define ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB
+#define ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB
+#define ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB
+#define ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB
+#define ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB
+#define ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB
+#define ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB
+#define ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB
+#define ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB
+#define ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB
+#define ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
+ * @{
+ */
+#define ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT
+#define ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT
+#define ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT
+#define ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT
+#define ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT
+#define ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT
+#define ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT
+#define ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Speed ETH Speed
+ * @{
+ */
+#define ETH_SPEED_10M ((uint32_t)0x00000000U)
+#define ETH_SPEED_100M ETH_MACCR_FES
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
+ * @{
+ */
+#define ETH_FULLDUPLEX_MODE ETH_MACCR_DM
+#define ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000U)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
+ * @{
+ */
+#define ETH_BACKOFFLIMIT_10 ETH_MACCR_BL_10
+#define ETH_BACKOFFLIMIT_8 ETH_MACCR_BL_8
+#define ETH_BACKOFFLIMIT_4 ETH_MACCR_BL_4
+#define ETH_BACKOFFLIMIT_1 ETH_MACCR_BL_1
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Preamble_Length ETH Preamble Length
+ * @{
+ */
+#define ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7
+#define ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5
+#define ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
+ * @{
+ */
+#define ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000U)
+#define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0
+#define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1
+#define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0
+#define ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
+ * @{
+ */
+#define ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL
+#define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
+#define ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL
+#define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
+/**
+ * @}
+ */
+
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
+ * @{
+ */
+#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
+#define ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses ETH MAC addresses
+ * @{
+ */
+#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
+#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
+#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
+#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
+ * @{
+ */
+#define ETH_MAC_RX_STATUS_IT ETH_MACIER_RXSTSIE
+#define ETH_MAC_TX_STATUS_IT ETH_MACIER_TXSTSIE
+#define ETH_MAC_TIMESTAMP_IT ETH_MACIER_TSIE
+#define ETH_MAC_LPI_IT ETH_MACIER_LPIIE
+#define ETH_MAC_PMT_IT ETH_MACIER_PMTIE
+#define ETH_MAC_PHY_IT ETH_MACIER_PHYIE
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
+ * @{
+ */
+#define ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD
+#define ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
+ * @{
+ */
+#define ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT
+#define ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL
+#define ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL
+#define ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF
+#define ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR
+#define ETH_NO_CARRIER ETH_MACRXTXSR_NCARR
+#define ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_StateTypeDef ETH States
+ * @{
+ */
+#define HAL_ETH_STATE_RESET ((uint32_t)0x00000000U) /*!< Peripheral not yet Initialized or disabled */
+#define HAL_ETH_STATE_READY ((uint32_t)0x00000010U) /*!< Peripheral Communication started */
+#define HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U) /*!< an internal process is ongoing */
+#define HAL_ETH_STATE_BUSY_TX ((uint32_t)0x00000021U) /*!< Transmission process is ongoing */
+#define HAL_ETH_STATE_BUSY_RX ((uint32_t)0x00000022U) /*!< Reception process is ongoing */
+#define HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U) /*!< Error State */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ETH_Exported_Macros ETH Exported Macros
+ * @{
+ */
+
+/** @brief Reset ETH handle state
+ * @param __HANDLE__: specifies the ETH handle.
+ * @retval None
+ */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \
+ } while(0)
+#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enables the specified ETHERNET DMA interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+ * enabled @ref ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET DMA interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+ * disabled. @ref ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Gets the ETHERNET DMA IT source enabled or disabled.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
+ * @retval The ETH DMA IT Source enabled or disabled
+ */
+#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Gets the ETHERNET DMA IT pending bit.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
+ * @retval The state of ETH DMA IT (SET or RESET)
+ */
+#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Clears the ETHERNET DMA IT pending bit.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.
+* @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
+ * @retval The state of ETH DMA FLAG (SET or RESET).
+ */
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Clears the specified ETHERNET DMA flag.
+* @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
+ * @retval The state of ETH DMA FLAG (SET or RESET).
+ */
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
+
+/**
+ * @brief Enables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+ * enabled @ref ETH_MAC_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+ * enabled @ref ETH_MAC_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified ETHERNET MAC flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
+ * @retval The state of ETH MAC IT (SET or RESET).
+ */
+#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
+
+/*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
+#define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000U) /* !< 86 - 64 = 22 */
+
+/**
+ * @brief Enable the ETH WAKEUP Exti Line.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
+ * @arg ETH_WAKEUP_EXTI_LINE
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 |= (__EXTI_LINE__))
+
+/**
+ * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
+ * @arg ETH_WAKEUP_EXTI_LINE
+ * @retval EXTI ETH WAKEUP Line Status.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__))
+
+/**
+ * @brief Clear the ETH WAKEUP Exti flag.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
+ * @arg ETH_WAKEUP_EXTI_LINE
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
+
+#if defined(DUAL_CORE)
+/**
+ * @brief Enable the ETH WAKEUP Exti Line by Core2.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
+ * @arg ETH_WAKEUP_EXTI_LINE
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI_D2->IMR3 |= (__EXTI_LINE__))
+
+/**
+ * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
+ * @arg ETH_WAKEUP_EXTI_LINE
+ * @retval EXTI ETH WAKEUP Line Status.
+ */
+#define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 & (__EXTI_LINE__))
+
+/**
+ * @brief Clear the ETH WAKEUP Exti flag.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
+ * @arg ETH_WAKEUP_EXTI_LINE
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__))
+#endif
+
+/**
+ * @brief enable rising edge interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+ * @arg ETH_WAKEUP_EXTI_LINE
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
+ (EXTI->RTSR3 |= (__EXTI_LINE__))
+
+/**
+ * @brief enable falling edge interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+ * @arg ETH_WAKEUP_EXTI_LINE
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
+ (EXTI->FTSR3 |= (__EXTI_LINE__))
+
+/**
+ * @brief enable falling edge interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+ * @arg ETH_WAKEUP_EXTI_LINE
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
+ (EXTI->FTSR3 |= (__EXTI_LINE__))
+
+/**
+ * @brief Generates a Software interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+ * @arg ETH_WAKEUP_EXTI_LINE
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
+
+/**
+ * @}
+ */
+
+/* Include ETH HAL Extension module */
+#include "stm32h7xx_hal_eth_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup ETH_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ETH_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de initialization functions **********************************/
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ETH_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
+
+uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer);
+HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length);
+HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo);
+HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth);
+
+HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
+
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue);
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue);
+
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
+/**
+ * @}
+ */
+
+/** @addtogroup ETH_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions **********************************************/
+/* MAC & DMA Configuration APIs **********************************************/
+HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
+HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
+void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
+
+/* MAC VLAN Processing APIs ************************************************/
+void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier);
+
+/* MAC L2 Packet Filtering APIs **********************************************/
+HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
+HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
+
+/* MAC Power Down APIs *****************************************************/
+void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
+void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
+
+/**
+ * @}
+ */
+
+/** @addtogroup ETH_Exported_Functions_Group4
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
+uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth);
+uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
+uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
+uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ETH */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_ETH_LEGACY_H */
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h
index dded758227..7547acb116 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h
@@ -104,7 +104,7 @@ typedef struct
uint16_t OwnAddress; /*!< Own addresses configuration
This parameter can be a value of @ref CEC_OWN_ADDRESS */
- uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
+ uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
} CEC_InitTypeDef;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h
index 4974bd32ff..e73cd9c176 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h
@@ -21,7 +21,7 @@
#define STM32H7xx_HAL_ETH_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
@@ -40,12 +40,24 @@
/* Exported types ------------------------------------------------------------*/
#ifndef ETH_TX_DESC_CNT
- #define ETH_TX_DESC_CNT 4U
-#endif
+#define ETH_TX_DESC_CNT 4U
+#endif /* ETH_TX_DESC_CNT */
#ifndef ETH_RX_DESC_CNT
- #define ETH_RX_DESC_CNT 4U
-#endif
+#define ETH_RX_DESC_CNT 4U
+#endif /* ETH_RX_DESC_CNT */
+
+#ifndef ETH_SWRESET_TIMEOUT
+#define ETH_SWRESET_TIMEOUT ((uint32_t)500U)
+#endif /* ETH_SWRESET_TIMEOUT */
+
+#ifndef ETH_MDIO_BUS_TIMEOUT
+#define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U)
+#endif /* ETH_MDIO_BUS_TIMEOUT */
+
+#ifndef ETH_MAC_US_TICK
+#define ETH_MAC_US_TICK ((uint32_t)1000000U)
+#endif /* ETH_MAC_US_TICK */
/*********************** Descriptors struct def section ************************/
/** @defgroup ETH_Exported_Types ETH Exported Types
@@ -63,7 +75,7 @@ typedef struct
__IO uint32_t DESC3;
uint32_t BackupAddr0; /* used to store rx buffer 1 address */
uint32_t BackupAddr1; /* used to store rx buffer 2 address */
-}ETH_DMADescTypeDef;
+} ETH_DMADescTypeDef;
/**
*
*/
@@ -78,7 +90,7 @@ typedef struct __ETH_BufferTypeDef
uint32_t len; /*<! buffer length */
struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
-}ETH_BufferTypeDef;
+} ETH_BufferTypeDef;
/**
*
*/
@@ -92,17 +104,19 @@ typedef struct
uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */
- uint32_t* PacketAddress[ETH_TX_DESC_CNT]; /*<! Ethernet packet addresses array */
+ uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*<! Ethernet packet addresses array */
- uint32_t* CurrentPacketAddress; /*<! Current transmit NX_PACKET addresses */
+ uint32_t *CurrentPacketAddress; /*<! Current transmit NX_PACKET addresses */
uint32_t BuffersInUse; /*<! Buffers in Use */
-}ETH_TxDescListTypeDef;
+
+ uint32_t releaseIndex; /*<! Release index */
+} ETH_TxDescListTypeDef;
/**
*
*/
- /**
+/**
* @brief Transmit Packet Configuration structure definition
*/
typedef struct
@@ -144,67 +158,67 @@ typedef struct
uint32_t InnerVlanCtrl; /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control */
-}ETH_TxPacketConfig;
+ void *pData; /*!< Specifies Application packet pointer to save */
+
+} ETH_TxPacketConfig;
/**
*
*/
/**
- * @brief DMA Receive Descriptors Wrapper structure definition
- */
+ * @brief ETH Timestamp structure definition
+ */
typedef struct
{
- uint32_t RxDesc[ETH_RX_DESC_CNT]; /*<! Rx DMA descriptors addresses. */
-
- uint32_t CurRxDesc; /*<! Current Rx descriptor, ready for next reception. */
-
- uint32_t FirstAppDesc; /*<! First descriptor of last received packet. */
+ uint32_t TimeStampLow;
+ uint32_t TimeStampHigh;
- uint32_t AppDescNbr; /*<! Number of descriptors of last received packet. */
-
- uint32_t AppContextDesc; /*<! If 1 a context descriptor is present in last received packet.
- If 0 no context descriptor is present in last received packet. */
+} ETH_TimeStampTypeDef;
+/**
+ *
+ */
- uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt.
- If 0, DMA will not generate the Rx complete interrupt. */
-}ETH_RxDescListTypeDef;
+/**
+ * @brief ETH Timeupdate structure definition
+ */
+typedef struct
+{
+ uint32_t Seconds;
+ uint32_t NanoSeconds;
+} ETH_TimeTypeDef;
/**
*
*/
/**
- * @brief Received Packet Information structure definition
+ * @brief DMA Receive Descriptors Wrapper structure definition
*/
typedef struct
{
- uint32_t SegmentCnt; /*<! Number of Rx Descriptors */
+ uint32_t RxDesc[ETH_RX_DESC_CNT]; /*<! Rx DMA descriptors addresses. */
- uint32_t VlanTag; /*<! Vlan Tag value */
+ uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt.
+ If 0, DMA will not generate the Rx complete interrupt. */
+
+ uint32_t RxDescIdx; /*<! Current Rx descriptor. */
- uint32_t InnerVlanTag; /*<! Inner Vlan Tag value */
+ uint32_t RxDescCnt; /*<! Number of descriptors . */
- uint32_t Checksum; /*<! Rx Checksum status.
- This parameter can be a value of @ref ETH_Rx_Checksum_Status */
+ uint32_t RxDataLength; /*<! Received Data Length. */
- uint32_t HeaderType; /*<! IP header type.
- This parameter can be a value of @ref ETH_Rx_IP_Header_Type */
+ uint32_t RxBuildDescIdx; /*<! Current Rx Descriptor for building descriptors. */
- uint32_t PayloadType; /*<! Payload type.
- This parameter can be a value of @ref ETH_Rx_Payload_Type */
+ uint32_t RxBuildDescCnt; /*<! Number of Rx Descriptors awaiting building. */
- uint32_t MacFilterStatus; /*<! MAC filter status.
- This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */
+ uint32_t pRxLastRxDesc; /*<! Last received descriptor. */
- uint32_t L3FilterStatus; /*<! L3 filter status
- This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */
+ ETH_TimeStampTypeDef TimeStamp; /*<! Time Stamp Low value for receive. */
- uint32_t L4FilterStatus; /*<! L4 filter status
- This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */
+ void *pRxStart; /*<! Pointer to the first buff. */
- uint32_t ErrorCode; /*<! Rx error code
- This parameter can be a combination of @ref ETH_Rx_Error_Code */
+ void *pRxEnd; /*<! Pointer to the last buff. */
-} ETH_RxPacketInfo;
+} ETH_RxDescListTypeDef;
/**
*
*/
@@ -214,10 +228,12 @@ typedef struct
*/
typedef struct
{
- uint32_t SourceAddrControl; /*!< Selects the Source Address Insertion or Replacement Control.
+ uint32_t
+ SourceAddrControl; /*!< Selects the Source Address Insertion or Replacement Control.
This parameter can be a value of @ref ETH_Source_Addr_Control */
- FunctionalState ChecksumOffload; /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
+ FunctionalState
+ ChecksumOffload; /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
uint32_t InterPacketGapVal; /*!< Sets the minimum IPG between Packet during transmission.
This parameter can be a value of @ref ETH_Inter_Packet_Gap */
@@ -230,13 +246,9 @@ typedef struct
FunctionalState AutomaticPadCRCStrip; /*!< Enables or disables the Automatic MAC Pad/CRC Stripping.*/
- FunctionalState Watchdog; /*!< Enables or disables the Watchdog timer on Rx path
- When enabled, the MAC allows no more then 2048 bytes to be received.
- When disabled, the MAC can receive up to 16384 bytes. */
+ FunctionalState Watchdog; /*!< Enables or disables the Watchdog timer on Rx path.*/
- FunctionalState Jabber; /*!< Enables or disables Jabber timer on Tx path
- When enabled, the MAC allows no more then 2048 bytes to be sent.
- When disabled, the MAC can send up to 16384 bytes. */
+ FunctionalState Jabber; /*!< Enables or disables Jabber timer on Tx path.*/
FunctionalState JumboPacket; /*!< Enables or disables receiving Jumbo Packet
When enabled, the MAC allows jumbo packets of 9,018 bytes
@@ -250,31 +262,39 @@ typedef struct
FunctionalState LoopbackMode; /*!< Enables or disables the loopback mode */
- FunctionalState CarrierSenseBeforeTransmit; /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
+ FunctionalState
+ CarrierSenseBeforeTransmit; /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
FunctionalState ReceiveOwn; /*!< Enables or disables the Receive Own in Half Duplex mode. */
- FunctionalState CarrierSenseDuringTransmit; /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
+ FunctionalState
+ CarrierSenseDuringTransmit; /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
- FunctionalState RetryTransmission; /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
+ FunctionalState
+ RetryTransmission; /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
This parameter can be a value of @ref ETH_Back_Off_Limit */
- FunctionalState DeferralCheck; /*!< Enables or disables the deferral check function in Half Duplex mode. */
+ FunctionalState
+ DeferralCheck; /*!< Enables or disables the deferral check function in Half Duplex mode. */
- uint32_t PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
+ uint32_t
+ PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
This parameter can be a value of @ref ETH_Preamble_Length */
- FunctionalState UnicastSlowProtocolPacketDetect; /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
+ FunctionalState
+ UnicastSlowProtocolPacketDetect; /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
FunctionalState SlowProtocolDetect; /*!< Enable or disables the Slow Protocol Detection. */
FunctionalState CRCCheckingRxPackets; /*!< Enable or disables the CRC Checking for Received Packets. */
- uint32_t GiantPacketSizeLimit; /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
- greater than the value programmed in this field in units of bytes
- This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/
+ uint32_t
+ GiantPacketSizeLimit; /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
+ greater than the value programmed in this field in units of bytes
+ This parameter must be a number between
+ Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte). */
FunctionalState ExtendedInterPacketGap; /*!< Enable or disables the extended inter packet gap. */
@@ -286,18 +306,24 @@ typedef struct
uint32_t WatchdogTimeout; /*!< This field is used as watchdog timeout for a received packet
This parameter can be a value of @ref ETH_Watchdog_Timeout */
- uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
+ uint32_t
+ PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
+ This parameter must be a number between
+ Min_Data = 0x0 and Max_Data = 0xFFFF.*/
- FunctionalState ZeroQuantaPause; /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
+ FunctionalState
+ ZeroQuantaPause; /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
- uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
+ uint32_t
+ PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
This parameter can be a value of @ref ETH_Pause_Low_Threshold */
- FunctionalState TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
+ FunctionalState
+ TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
or the MAC back pressure operation in Half Duplex mode */
- FunctionalState UnicastPausePacketDetect; /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
+ FunctionalState
+ UnicastPausePacketDetect; /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
FunctionalState ReceiveFlowControl; /*!< Enables or disables the MAC to decodes the received Pause packet
and disables its transmitter for a specified (Pause) time */
@@ -321,36 +347,41 @@ typedef struct
/**
* @brief ETH DMA Configuration Structure definition
*/
- typedef struct
- {
- uint32_t DMAArbitration; /*!< Sets the arbitration scheme between DMA Tx and Rx
+typedef struct
+{
+ uint32_t DMAArbitration; /*!< Sets the arbitration scheme between DMA Tx and Rx
This parameter can be a value of @ref ETH_DMA_Arbitration */
- FunctionalState AddressAlignedBeats; /*!< Enables or disables the AHB Master interface address aligned
+ FunctionalState AddressAlignedBeats; /*!< Enables or disables the AHB Master interface address aligned
burst transfers on Read and Write channels */
- uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers.
+ uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers.
This parameter can be a value of @ref ETH_Burst_Mode */
- FunctionalState RebuildINCRxBurst; /*!< Enables or disables the AHB Master to rebuild the pending beats
+ FunctionalState RebuildINCRxBurst; /*!< Enables or disables the AHB Master to rebuild the pending beats
of any initiated burst transfer with INCRx and SINGLE transfers. */
- FunctionalState PBLx8Mode; /*!< Enables or disables the PBL multiplication by eight. */
+ FunctionalState PBLx8Mode; /*!< Enables or disables the PBL multiplication by eight. */
- uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
+ uint32_t
+ TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
- FunctionalState SecondPacketOperate; /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
- Packet of Transmit data even before obtaining the status for the first one. */
+ FunctionalState
+ SecondPacketOperate; /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
+ Packet of Transmit data even before
+ obtaining the status for the first one. */
- uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
+ uint32_t
+ RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
- FunctionalState FlushRxPacket; /*!< Enables or disables the Rx Packet Flush */
+ FunctionalState FlushRxPacket; /*!< Enables or disables the Rx Packet Flush */
- FunctionalState TCPSegmentation; /*!< Enables or disables the TCP Segmentation */
+ FunctionalState TCPSegmentation; /*!< Enables or disables the TCP Segmentation */
- uint32_t MaximumSegmentSize; /*!< Sets the maximum segment size that should be used while segmenting the packet
+ uint32_t
+ MaximumSegmentSize; /*!< Sets the maximum segment size that should be used while segmenting the packet
This parameter can be a value from 0x40 to 0x3FFF */
} ETH_DMAConfigTypeDef;
/**
@@ -364,7 +395,19 @@ typedef enum
{
HAL_ETH_MII_MODE = 0x00U, /*!< Media Independent Interface */
HAL_ETH_RMII_MODE = 0x01U /*!< Reduced Media Independent Interface */
-}ETH_MediaInterfaceTypeDef;
+} ETH_MediaInterfaceTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief HAL ETH PTP Update type enum definition
+ */
+typedef enum
+{
+ HAL_ETH_PTP_POSITIVE_UPDATE = 0x00000000U, /*!< PTP positive time update */
+ HAL_ETH_PTP_NEGATIVE_UPDATE = 0x00000001U /*!< PTP negative time update */
+} ETH_PtpUpdateTypeDef;
/**
*
*/
@@ -375,17 +418,51 @@ typedef enum
typedef struct
{
- uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
+ uint8_t
+ *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
ETH_MediaInterfaceTypeDef MediaInterface; /*!< Selects the MII interface or the RMII interface. */
- ETH_DMADescTypeDef *TxDesc; /*!< Provides the address of the first DMA Tx descriptor in the list */
+ ETH_DMADescTypeDef
+ *TxDesc; /*!< Provides the address of the first DMA Tx descriptor in the list */
- ETH_DMADescTypeDef *RxDesc; /*!< Provides the address of the first DMA Rx descriptor in the list */
+ ETH_DMADescTypeDef
+ *RxDesc; /*!< Provides the address of the first DMA Rx descriptor in the list */
uint32_t RxBuffLen; /*!< Provides the length of Rx buffers size */
-}ETH_InitTypeDef;
+} ETH_InitTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH PTP Init Structure definition
+ */
+typedef struct
+{
+ uint32_t Timestamp; /*!< Enable Timestamp */
+ uint32_t TimestampUpdateMode; /*!< Fine or Coarse Timestamp Update */
+ uint32_t TimestampInitialize; /*!< Initialize Timestamp */
+ uint32_t TimestampUpdate; /*!< Timestamp Update */
+ uint32_t TimestampAddendUpdate; /*!< Timestamp Addend Update */
+ uint32_t TimestampAll; /*!< Enable Timestamp for All Packets */
+ uint32_t TimestampRolloverMode; /*!< Timestamp Digital or Binary Rollover Control */
+ uint32_t TimestampV2; /*!< Enable PTP Packet Processing for Version 2 Format */
+ uint32_t TimestampEthernet; /*!< Enable Processing of PTP over Ethernet Packets */
+ uint32_t TimestampIPv6; /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
+ uint32_t TimestampIPv4; /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
+ uint32_t TimestampEvent; /*!< Enable Timestamp Snapshot for Event Messages */
+ uint32_t TimestampMaster; /*!< Enable Timestamp Snapshot for Event Messages */
+ uint32_t TimestampSnapshots; /*!< Select PTP packets for Taking Snapshots */
+ uint32_t TimestampFilter; /*!< Enable MAC Address for PTP Packet Filtering */
+ uint32_t
+ TimestampChecksumCorrection; /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */
+ uint32_t TimestampStatusMode; /*!< Transmit Timestamp Status Mode */
+ uint32_t TimestampAddend; /*!< Timestamp addend value */
+ uint32_t TimestampSubsecondInc; /*!< Subsecond Increment */
+
+} ETH_PTP_ConfigTypeDef;
/**
*
*/
@@ -398,6 +475,40 @@ typedef uint32_t HAL_ETH_StateTypeDef;
*
*/
+/**
+ * @brief HAL ETH Rx Get Buffer Function definition
+ */
+typedef void (*pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer); /*!< pointer to an ETH Rx Get Buffer Function */
+/**
+ *
+ */
+
+/**
+ * @brief HAL ETH Rx Set App Data Function definition
+ */
+typedef void (*pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff,
+ uint16_t Length); /*!< pointer to an ETH Rx Set App Data Function */
+/**
+ *
+ */
+
+/**
+ * @brief HAL ETH Tx Free Function definition
+ */
+typedef void (*pETH_txFreeCallbackTypeDef)(uint32_t *buffer); /*!< pointer to an ETH Tx Free function */
+/**
+ *
+ */
+
+/**
+ * @brief HAL ETH Tx Free Function definition
+ */
+typedef void (*pETH_txPtpCallbackTypeDef)(uint32_t *buffer,
+ ETH_TimeStampTypeDef *timestamp); /*!< pointer to an ETH Tx Free function */
+/**
+ *
+ */
+
/**
* @brief ETH Handle Structure definition
*/
@@ -405,7 +516,7 @@ typedef uint32_t HAL_ETH_StateTypeDef;
typedef struct __ETH_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
{
ETH_TypeDef *Instance; /*!< Register base address */
@@ -417,45 +528,57 @@ typedef struct
ETH_RxDescListTypeDef RxDescList; /*!< Rx descriptor wrapper: holds all Rx descriptors list
addresses and current descriptor index */
- HAL_LockTypeDef Lock; /*!< Locking object */
+#ifdef HAL_ETH_USE_PTP
+ ETH_TimeStampTypeDef TxTimestamp; /*!< Tx Timestamp */
+#endif /* HAL_ETH_USE_PTP */
__IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_ETH_StateTypeDef */
-
- __IO HAL_ETH_StateTypeDef RxState; /*!< ETH state information related to Rx operations.
- This parameter can be a value of @ref HAL_ETH_StateTypeDef */
+ and also related to Tx operations. This parameter can
+ be a value of @ref HAL_ETH_StateTypeDef */
__IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine
- This parameter can be a value of of @ref ETH_Error_Code */
+ This parameter can be a value of @ref ETH_Error_Code.*/
- __IO uint32_t DMAErrorCode; /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
- This parameter can be a combination of @ref ETH_DMA_Status_Flags */
+ __IO uint32_t
+ DMAErrorCode; /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
+ This parameter can be a combination of
+ @ref ETH_DMA_Status_Flags */
- __IO uint32_t MACErrorCode; /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
- This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */
+ __IO uint32_t
+ MACErrorCode; /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
+ This parameter can be a combination of
+ @ref ETH_MAC_Rx_Tx_Status */
__IO uint32_t MACWakeUpEvent; /*!< Holds the Wake Up event when the MAC exit the power down mode
- This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */
+ This parameter can be a value of
+ @ref ETH_MAC_Wake_Up_Event */
__IO uint32_t MACLPIEvent; /*!< Holds the LPI event when the an LPI status interrupt occurs.
This parameter can be a value of @ref ETHEx_LPI_Event */
+ __IO uint32_t IsPtpConfigured; /*!< Holds the PTP configuration status.
+ This parameter can be a value of
+ @ref ETH_PTP_Config_Status */
+
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
- void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */
- void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */
- void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH DMA Error Callback */
- void (* MACErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH MAC Error Callback */
- void (* PMTCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Power Management Callback */
- void (* EEECallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH EEE Callback */
- void (* WakeUpCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Wake UP Callback */
+ void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Tx Complete Callback */
+ void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Rx Complete Callback */
+ void (* ErrorCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Error Callback */
+ void (* PMTCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Power Management Callback */
+ void (* EEECallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH EEE Callback */
+ void (* WakeUpCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Wake UP Callback */
- void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */
- void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */
+ void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp Init callback */
+ void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp DeInit callback */
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+ pETH_rxAllocateCallbackTypeDef rxAllocateCallback; /*!< ETH Rx Get Buffer Function */
+ pETH_rxLinkCallbackTypeDef rxLinkCallback; /*!< ETH Rx Set App Data Function */
+ pETH_txFreeCallbackTypeDef txFreeCallback; /*!< ETH Tx Free Function */
+ pETH_txPtpCallbackTypeDef txPtpCallback; /*!< ETH Tx Handle Ptp Function */
+
} ETH_HandleTypeDef;
/**
*
@@ -472,26 +595,26 @@ typedef enum
HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
- HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */
- HAL_ETH_MAC_ERROR_CB_ID = 0x05U, /*!< ETH MAC Error Callback ID */
- HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */
- HAL_ETH_EEE_CB_ID = 0x07U, /*!< ETH EEE Callback ID */
+ HAL_ETH_ERROR_CB_ID = 0x04U, /*!< ETH Error Callback ID */
+ HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */
+ HAL_ETH_EEE_CB_ID = 0x07U, /*!< ETH EEE Callback ID */
HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */
-}HAL_ETH_CallbackIDTypeDef;
+} HAL_ETH_CallbackIDTypeDef;
/**
* @brief HAL ETH Callback pointer definition
*/
-typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */
+typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth); /*!< pointer to an ETH callback function */
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @brief ETH MAC filter structure definition
*/
-typedef struct{
+typedef struct
+{
FunctionalState PromiscuousMode; /*!< Enable or Disable Promiscuous Mode */
FunctionalState ReceiveAllMode; /*!< Enable or Disable Receive All Mode */
@@ -514,7 +637,7 @@ typedef struct{
uint32_t ControlPacketsFilter; /*!< Set the control packets filter
This parameter can be a value of @ref ETH_Control_Packets_Filter */
-}ETH_MACFilterConfigTypeDef;
+} ETH_MACFilterConfigTypeDef;
/**
*
*/
@@ -522,7 +645,8 @@ typedef struct{
/**
* @brief ETH Power Down structure definition
*/
-typedef struct{
+typedef struct
+{
FunctionalState WakeUpPacket; /*!< Enable or Disable Wake up packet detection in power down mode */
FunctionalState MagicPacket; /*!< Enable or Disable Magic packet detection in power down mode */
@@ -531,7 +655,7 @@ typedef struct{
FunctionalState WakeUpForward; /*!< Enable or Disable Forwarding Wake up packets */
-}ETH_PowerDownConfigTypeDef;
+} ETH_PowerDownConfigTypeDef;
/**
*
*/
@@ -608,9 +732,13 @@ typedef struct{
#define ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is disabled */
#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000U) /*!< Only IP header checksum calculation and insertion are enabled. */
#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000U) /*!< IP header checksum and payload checksum calculation and insertion are
- enabled, but pseudo header checksum is not calculated in hardware */
+ enabled, but pseudo header
+ checksum is not
+ calculated in hardware */
#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000U) /*!< IP Header checksum and payload checksum calculation and insertion are
- enabled, and pseudo header checksum is calculated in hardware. */
+ enabled, and pseudo header
+ checksum is
+ calculated in hardware. */
#define ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFFU) /*!< TCP Payload Length */
#define ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFFU) /*!< Transmit End of Ring */
@@ -752,7 +880,7 @@ typedef struct{
DMA Rx Normal Descriptor write back format
---------------------------------------------------------------------------------------------------------------------
RDES0 | Inner VLAN Tag[31:16] | Outer VLAN Tag[15:0] |
- ---------------------------------------------------------------------------------------------------------------------
+ ---------------------------------------------------------------------------------------------------------------------
RDES1 | OAM code, or MAC Control Opcode [31:16] | Extended Status |
---------------------------------------------------------------------------------------------------------------------
RDES2 | MAC Filter Status[31:16] | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
@@ -843,7 +971,7 @@ typedef struct{
DMA Rx context Descriptor
---------------------------------------------------------------------------------------------------------------------
RDES0 | Timestamp Low[31:0] |
- ---------------------------------------------------------------------------------------------------------------------
+ ---------------------------------------------------------------------------------------------------------------------
RDES1 | Timestamp High[31:0] |
---------------------------------------------------------------------------------------------------------------------
RDES2 | Reserved |
@@ -1009,7 +1137,6 @@ typedef struct{
/**
* @}
*/
-
/** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
* @{
*/
@@ -1066,7 +1193,7 @@ typedef struct{
* @}
*/
- /** @defgroup ETH_Burst_Mode ETH Burst Mode
+/** @defgroup ETH_Burst_Mode ETH Burst Mode
* @{
*/
#define ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB
@@ -1348,9 +1475,17 @@ typedef struct{
#define HAL_ETH_STATE_RESET ((uint32_t)0x00000000U) /*!< Peripheral not yet Initialized or disabled */
#define HAL_ETH_STATE_READY ((uint32_t)0x00000010U) /*!< Peripheral Communication started */
#define HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U) /*!< an internal process is ongoing */
-#define HAL_ETH_STATE_BUSY_TX ((uint32_t)0x00000021U) /*!< Transmission process is ongoing */
-#define HAL_ETH_STATE_BUSY_RX ((uint32_t)0x00000022U) /*!< Reception process is ongoing */
+#define HAL_ETH_STATE_STARTED ((uint32_t)0x00000023U) /*!< an internal process is started */
#define HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U) /*!< Error State */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
+ * @{
+ */
+#define HAL_ETH_PTP_NOT_CONFIGURATED ((uint32_t)0x00000000U) /*!< ETH PTP Configuration not done */
+#define HAL_ETH_PTP_CONFIGURATED ((uint32_t)0x00000001U) /*!< ETH PTP Configuration done */
/**
* @}
*/
@@ -1369,16 +1504,14 @@ typedef struct{
*/
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+ (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \
- } while(0)
+ (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
+ } while(0)
#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
/**
@@ -1388,7 +1521,7 @@ typedef struct{
* enabled @ref ETH_DMA_Interrupts
* @retval None
*/
-#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
/**
* @brief Disables the specified ETHERNET DMA interrupts.
@@ -1397,7 +1530,7 @@ typedef struct{
* disabled. @ref ETH_DMA_Interrupts
* @retval None
*/
-#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
/**
* @brief Gets the ETHERNET DMA IT source enabled or disabled.
@@ -1405,7 +1538,8 @@ typedef struct{
* @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
* @retval The ETH DMA IT Source enabled or disabled
*/
-#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Gets the ETHERNET DMA IT pending bit.
@@ -1413,7 +1547,8 @@ typedef struct{
* @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
* @retval The state of ETH DMA IT (SET or RESET)
*/
-#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clears the ETHERNET DMA IT pending bit.
@@ -1421,23 +1556,23 @@ typedef struct{
* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
* @retval None
*/
-#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
/**
* @brief Checks whether the specified ETHERNET DMA flag is set or not.
-* @param __HANDLE__: ETH Handle
+ * @param __HANDLE__: ETH Handle
* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
* @retval The state of ETH DMA FLAG (SET or RESET).
*/
-#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
/**
* @brief Clears the specified ETHERNET DMA flag.
-* @param __HANDLE__: ETH Handle
+ * @param __HANDLE__: ETH Handle
* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
* @retval The state of ETH DMA FLAG (SET or RESET).
*/
-#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
/**
* @brief Enables the specified ETHERNET MAC interrupts.
@@ -1446,7 +1581,7 @@ typedef struct{
* enabled @ref ETH_MAC_Interrupts
* @retval None
*/
-#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
/**
* @brief Disables the specified ETHERNET MAC interrupts.
@@ -1455,7 +1590,7 @@ typedef struct{
* enabled @ref ETH_MAC_Interrupts
* @retval None
*/
-#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified ETHERNET MAC flag is set or not.
@@ -1463,7 +1598,8 @@ typedef struct{
* @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
* @retval The state of ETH MAC IT (SET or RESET).
*/
-#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
+#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
/*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
#define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000U) /* !< 86 - 64 = 22 */
@@ -1516,7 +1652,7 @@ typedef struct{
* @retval None.
*/
#define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__))
-#endif
+#endif /* DUAL_CORE */
/**
* @brief enable rising edge interrupt on selected EXTI line.
@@ -1525,7 +1661,7 @@ typedef struct{
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
- (EXTI->RTSR3 |= (__EXTI_LINE__))
+ (EXTI->RTSR3 |= (__EXTI_LINE__))
/**
* @brief enable falling edge interrupt on selected EXTI line.
@@ -1534,7 +1670,7 @@ typedef struct{
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
- (EXTI->FTSR3 |= (__EXTI_LINE__))
+ (EXTI->FTSR3 |= (__EXTI_LINE__))
/**
* @brief enable falling edge interrupt on selected EXTI line.
@@ -1543,7 +1679,7 @@ typedef struct{
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
- (EXTI->FTSR3 |= (__EXTI_LINE__))
+ (EXTI->FTSR3 |= (__EXTI_LINE__))
/**
* @brief Generates a Software interrupt on selected EXTI line.
@@ -1553,6 +1689,10 @@ typedef struct{
*/
#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
+#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->MACTSCR) & \
+ (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+
+#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->MACTSCR |= (__FLAG__))
/**
* @}
*/
@@ -1574,11 +1714,11 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,
+ pETH_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
@@ -1595,26 +1735,50 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
-uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer);
-HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length);
-HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo);
-HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff);
+HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
+ pETH_rxAllocateCallbackTypeDef rxAllocateCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
+HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);
+
+#ifdef HAL_ETH_USE_PTP
+HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
+HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
+HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
+HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
+HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
+ ETH_TimeTypeDef *timeoffset);
+HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
+HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
+HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);
+#endif /* HAL_ETH_USE_PTP */
HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue);
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue);
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+ uint32_t RegValue);
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+ uint32_t *pRegValue);
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_RxAllocateCallback(uint8_t **buff);
+void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length);
+void HAL_ETH_TxFreeCallback(uint32_t *buff);
+void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp);
/**
* @}
*/
@@ -1631,7 +1795,8 @@ HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp
void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
/* MAC VLAN Processing APIs ************************************************/
-void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier);
+void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits,
+ uint32_t VLANIdentifier);
/* MAC L2 Packet Filtering APIs **********************************************/
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
@@ -1682,4 +1847,3 @@ uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
#endif /* STM32H7xx_HAL_ETH_H */
-
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h
index 2ea0879daa..93003d55b9 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h
@@ -21,7 +21,7 @@
#define STM32H7xx_HAL_ETH_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if defined(ETH)
@@ -45,11 +45,13 @@
/**
* @brief ETH RX VLAN structure definition
*/
-typedef struct{
+typedef struct
+{
FunctionalState InnerVLANTagInStatus; /*!< Enables or disables Inner VLAN Tag in Rx Status */
uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive
- This parameter can be a value of @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
+ This parameter can be a value of
+ @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
FunctionalState InnerVLANTag; /*!< Enables or disables Inner VLAN Tag */
@@ -66,7 +68,7 @@ typedef struct{
This parameter can be a value of @ref ETHEx_VLAN_Type_Check */
FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */
-}ETH_RxVLANConfigTypeDef;
+} ETH_RxVLANConfigTypeDef;
/**
*
*/
@@ -74,14 +76,15 @@ typedef struct{
/**
* @brief ETH TX VLAN structure definition
*/
-typedef struct{
+typedef struct
+{
FunctionalState SourceTxDesc; /*!< Enable or Disable VLAN tag source from DMA tx descriptors */
FunctionalState SVLANType; /*!< Enable or Disable insertion of SVLAN type */
uint32_t VLANTagControl; /*!< Sets the VLAN tag control in tx packets
This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */
-}ETH_TxVLANConfigTypeDef;
+} ETH_TxVLANConfigTypeDef;
/**
*
*/
@@ -89,7 +92,8 @@ typedef struct{
/**
* @brief ETH L3 filter structure definition
*/
-typedef struct{
+typedef struct
+{
uint32_t Protocol; /*!< Sets the L3 filter protocol to IPv4 or IPv6
This parameter can be a value of @ref ETHEx_L3_Protocol */
@@ -113,7 +117,7 @@ typedef struct{
uint32_t Ip6Addr[4]; /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used
This parameter must be a table of 4 words (4* 32 bits) */
-}ETH_L3FilterConfigTypeDef;
+} ETH_L3FilterConfigTypeDef;
/**
*
*/
@@ -121,7 +125,8 @@ typedef struct{
/**
* @brief ETH L4 filter structure definition
*/
-typedef struct{
+typedef struct
+{
uint32_t Protocol; /*!< Sets the L4 filter protocol to TCP or UDP
This parameter can be a value of @ref ETHEx_L4_Protocol */
@@ -136,7 +141,7 @@ typedef struct{
uint32_t DestinationPort; /*!< Sets the L4 filter destination port
This parameter must be a value from 0x0 to 0xFFFF */
-}ETH_L4FilterConfigTypeDef;
+} ETH_L4FilterConfigTypeDef;
/**
*
*/
@@ -309,10 +314,14 @@ void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t
/* MAC L3 L4 Filtering APIs ***************************************************/
void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
-HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
-HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
-HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+ ETH_L3FilterConfigTypeDef *pL3FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+ ETH_L4FilterConfigTypeDef *pL4FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+ ETH_L3FilterConfigTypeDef *pL3FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+ ETH_L4FilterConfigTypeDef *pL4FilterConfig);
/* MAC VLAN Processing APIs ************************************************/
void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
@@ -320,12 +329,15 @@ void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
-HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
-HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
-void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier);
+HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
+ ETH_TxVLANConfigTypeDef *pVlanConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
+ ETH_TxVLANConfigTypeDef *pVlanConfig);
+void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier);
/* Energy Efficient Ethernet APIs *********************************************/
-void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop);
+void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate,
+ FunctionalState TxClockStop);
void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
index c74096fbce..47f1fac3c8 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h
@@ -303,12 +303,15 @@ typedef struct
uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element.
This parameter must be a number between:
- 0 and 127, if IdType is FDCAN_STANDARD_ID
- - 0 and 63, if IdType is FDCAN_EXTENDED_ID */
+ - 0 and 63, if IdType is FDCAN_EXTENDED_ID
+ When the frame is a Non-Filter matching frame, this parameter
+ is unused. */
uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
- Acceptance of non-matching frames may be enabled via
- HAL_FDCAN_ConfigGlobalFilter().
- This parameter can be 0 or 1 */
+ Acceptance of non-matching frames may be enabled via
+ HAL_FDCAN_ConfigGlobalFilter().
+ This parameter takes 0 if the frame matched an Rx filter or
+ 1 if it did not match any Rx filter */
} FDCAN_RxHeaderTypeDef;
@@ -2376,6 +2379,10 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
+
+#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
+
+#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/**
* @}
*/
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h
index eeeb225ad8..3ae7d76b8a 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h
@@ -750,11 +750,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
-#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\
+ ((__AUTORELOAD__) <= 0x0000FFFFUL))
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
-#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
+#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\
+ ((__PERIOD__) <= 0x0000FFFFUL))
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h
index 17f73a8143..4f8d940a2f 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h
@@ -79,28 +79,36 @@ typedef struct
This parameter can be one of value of @ref LTDC_PC_POLARITY */
uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ This parameter must be a number between
+ Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
- This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
+ This parameter must be a number between
+ Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
- This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
- This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
+ This parameter must be a number between
+ Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.
- This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
uint32_t TotalWidth; /*!< configures the total width.
- This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
+ This parameter must be a number between
+ Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
uint32_t TotalHeigh; /*!< configures the total height.
- This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
} LTDC_InitTypeDef;
@@ -111,25 +119,31 @@ typedef struct
typedef struct
{
uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ This parameter must be a number between
+ Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ This parameter must be a number between
+ Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x7FF. */
uint32_t PixelFormat; /*!< Specifies the pixel format.
This parameter can be one of value of @ref LTDC_Pixelformat */
uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+ This parameter must be a number between
+ Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t Alpha0; /*!< Configures the default alpha value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+ This parameter must be a number between
+ Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t BlendingFactor1; /*!< Select the blending factor 1.
This parameter can be one of value of @ref LTDC_BlendingFactor1 */
@@ -140,10 +154,12 @@ typedef struct
uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x1FFF. */
uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = 0x000 and Max_Data = 0x7FF. */
LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
} LTDC_LayerCfgTypeDef;
@@ -399,7 +415,7 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer
* @retval None
*/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
-#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_LTDC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
@@ -429,7 +445,8 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
-#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
+#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
+ |= (uint32_t)LTDC_LxCR_LEN)
/**
* @brief Disable the LTDC Layer.
@@ -438,7 +455,8 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
-#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
+#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
+ &= ~(uint32_t)LTDC_LxCR_LEN)
/**
* @brief Reload immediately all LTDC Layers.
@@ -544,7 +562,8 @@ void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID,
+ pLTDC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
@@ -582,9 +601,12 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
-HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg,
+ uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize,
+ uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0,
+ uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
@@ -620,12 +642,18 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
/** @defgroup LTDC_Private_Macros LTDC Private Macros
* @{
*/
-#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))
+#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(\
+ ((uint32_t)((__HANDLE__)->Instance))\
+ + 0x84U + (0x80U*(__LAYER__)))))
#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
-#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
-#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
-#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
-#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
+#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL)\
+ || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
+#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL)\
+ || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
+#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL)\
+ || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
+#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\
+ || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
@@ -641,10 +669,14 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))
-#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
- ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
- ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
- ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
+#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
@@ -654,7 +686,8 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
-#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
+#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \
+ ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
/**
* @}
*/
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ospi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ospi.h
index 1bcce97f26..78e991aadd 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ospi.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ospi.h
@@ -80,9 +80,6 @@ typedef struct
uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and
defines the boundary of bytes to release the chip select.
This parameter can be a value between 0 and 31 */
- uint32_t ClkChipSelectHighTime; /*!< It defines the number of clocks provided on the CLK/nCLK pins when
- the chip select is set to high at the end of a transaction.
- This parameter can be a value between 0 and 7 */
uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected
by the delay block.
This parameter can be a value of @ref OSPI_DelayBlockBypass */
@@ -1027,7 +1024,8 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeD
#define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U)
-#define IS_OSPI_CKCSHT(CLK_NB) ((CLK_NB) <= 7U)
+#define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \
+ ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))
#define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U)
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h
index 4d1f4a3355..bfdfb0b456 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h
@@ -21,7 +21,7 @@
#define STM32H7xx_HAL_OTFDEC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -60,7 +60,7 @@ typedef struct
uint16_t Version; /*!< OTFDEC region firmware version */
-}OTFDEC_RegionConfigTypeDef;
+} OTFDEC_RegionConfigTypeDef;
/**
* @}
@@ -78,7 +78,7 @@ typedef enum
HAL_OTFDEC_STATE_RESET = 0x00U, /*!< OTFDEC not yet initialized or disabled */
HAL_OTFDEC_STATE_READY = 0x01U, /*!< OTFDEC initialized and ready for use */
HAL_OTFDEC_STATE_BUSY = 0x02U, /*!< OTFDEC internal processing is ongoing */
-}HAL_OTFDEC_StateTypeDef;
+} HAL_OTFDEC_StateTypeDef;
/**
* @brief OTFDEC handle structure definition
@@ -105,7 +105,7 @@ typedef struct
void (* MspDeInitCallback)(struct __OTFDEC_HandleTypeDef *hotfdec); /*!< OTFDEC Msp DeInit callback */
#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
-}OTFDEC_HandleTypeDef;
+} OTFDEC_HandleTypeDef;
#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
/**
@@ -266,7 +266,7 @@ typedef void (*pOTFDEC_CallbackTypeDef)(OTFDEC_HandleTypeDef *hotfdec); /*!< po
*/
#define __HAL_OTFDEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(((__HANDLE__)->Instance->IER), (__INTERRUPT__))
- /** @brief Check whether the specified combination of OTFDEC interrupt flags is set or not.
+/** @brief Check whether the specified combination of OTFDEC interrupt flags is set or not.
* @param __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param __FLAG__ mask on combination of interrupts flags
@@ -278,7 +278,7 @@ typedef void (*pOTFDEC_CallbackTypeDef)(OTFDEC_HandleTypeDef *hotfdec); /*!< po
* @arg @ref OTFDEC_SEC_KEY_ERROR_INT OTFDEC security and key errors interrupts flags
* @arg @ref OTFDEC_EXE_KEY_ERROR_INT OTFDEC execution and key errors interrupts flag
* @arg @ref OTFDEC_ALL_INT OTFDEC all interrupts flags
- * @retval The state of __FLAG__ (TRUE or FALSE).
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_OTFDEC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
@@ -318,7 +318,7 @@ void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec);
#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID,
- pOTFDEC_CallbackTypeDef pCallback);
+ pOTFDEC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
/**
@@ -422,10 +422,11 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint
* @param __MODE__ OTFDEC region operating mode parameter.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
-#define IS_OTFDEC_REGION_OPERATING_MODE(__MODE__) (((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY) || \
- ((__MODE__) == OTFDEC_REG_MODE_DATA_ACCESSES_ONLY) || \
- ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \
- ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER))
+#define IS_OTFDEC_REGION_OPERATING_MODE(__MODE__) \
+ (((__MODE__)== OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY) || \
+ ((__MODE__) == OTFDEC_REG_MODE_DATA_ACCESSES_ONLY) || \
+ ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \
+ ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER))
/**
* @brief Verify the OTFDEC region index.
@@ -473,5 +474,3 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint
#endif
#endif /* STM32H7xx_HAL_OTFDEC_H */
-
-
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h
index e9c220bd33..27f7fdf6d2 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h
@@ -106,6 +106,7 @@ typedef struct
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
+ uint32_t FrameNumber; /*!< Store Current Frame number */
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
@@ -273,12 +274,10 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType
* @}
*/
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
- HAL_PCD_CallbackIDTypeDef CallbackID,
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
pPCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
- HAL_PCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataOutStageCallbackTypeDef pCallback);
@@ -300,14 +299,10 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
- pPCD_BcdCallbackTypeDef pCallback);
-
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
- pPCD_LpmCallbackTypeDef pCallback);
-
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
@@ -346,16 +341,10 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint16_t ep_mps, uint8_t ep_type);
-
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len);
-
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len);
-
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus.h
index 0a543d4e05..25b9a0908b 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus.h
@@ -655,6 +655,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
* @}
*/
+/* Include SMBUS HAL Extended module */
+#include "stm32h7xx_hal_smbus_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus_ex.h
new file mode 100644
index 0000000000..0fde990957
--- /dev/null
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus_ex.h
@@ -0,0 +1,152 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_smbus_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SMBUS HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_SMBUS_EX_H
+#define STM32H7xx_HAL_SMBUS_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SMBUSEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
+ * @{
+ */
+#define SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
+#define SMBUS_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
+#define SMBUS_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
+#define SMBUS_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
+#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
+#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
+#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
+#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
+#define SMBUS_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
+#if defined(SYSCFG_PMCR_I2C5_FMP)
+#define SMBUS_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus on I2C5 pins */
+#else
+#define SMBUS_FASTMODEPLUS_I2C5 (uint32_t)(0x00001000U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C5 not supported */
+#endif /* SYSCFG_PMCR_I2C5_FMP */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus);
+/**
+ * @}
+ */
+
+/** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
+ * @{
+ */
+void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
+ * @{
+ */
+#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & SMBUS_FASTMODEPLUS_PB6) == SMBUS_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB7) == SMBUS_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB8) == SMBUS_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB9) == SMBUS_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & SMBUS_FASTMODEPLUS_I2C1) == SMBUS_FASTMODEPLUS_I2C1) || \
+ (((__CONFIG__) & SMBUS_FASTMODEPLUS_I2C2) == SMBUS_FASTMODEPLUS_I2C2) || \
+ (((__CONFIG__) & SMBUS_FASTMODEPLUS_I2C3) == SMBUS_FASTMODEPLUS_I2C3) || \
+ (((__CONFIG__) & SMBUS_FASTMODEPLUS_I2C4) == SMBUS_FASTMODEPLUS_I2C4))
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32h7xx_hal_smbus_ex.c file */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_SMBUS_EX_H */
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spdifrx.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spdifrx.h
index 4d227876d1..99d17c4c28 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spdifrx.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spdifrx.h
@@ -21,7 +21,7 @@
#define STM32H7xx_HAL_SPDIFRX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -128,7 +128,7 @@ typedef enum
typedef struct __SPDIFRX_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
{
SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */
@@ -172,8 +172,8 @@ typedef struct
void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed callback */
void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */
void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */
- void (* MspInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp Init callback */
- void (* MspDeInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp DeInit callback */
+ void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp Init callback */
+ void (* MspDeInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp DeInit callback */
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
} SPDIFRX_HandleTypeDef;
@@ -194,12 +194,12 @@ typedef enum
HAL_SPDIFRX_ERROR_CB_ID = 0x04U, /*!< SPDIFRX error callback */
HAL_SPDIFRX_MSPINIT_CB_ID = 0x05U, /*!< SPDIFRX Msp Init callback ID */
HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U /*!< SPDIFRX Msp DeInit callback ID */
-}HAL_SPDIFRX_CallbackIDTypeDef;
+} HAL_SPDIFRX_CallbackIDTypeDef;
/**
* @brief HAL SPDIFRX Callback pointer definition
*/
-typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< pointer to an SPDIFRX callback function */
+typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback function */
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
/* Exported constants --------------------------------------------------------*/
@@ -272,8 +272,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
*/
/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
-* @{
-*/
+ * @{
+ */
#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)
#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
/**
@@ -373,10 +373,10 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
*/
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\
- (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\
- (__HANDLE__)->MspInitCallback = NULL;\
- (__HANDLE__)->MspDeInitCallback = NULL;\
- }while(0)
+ (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL;\
+ (__HANDLE__)->MspDeInitCallback = NULL;\
+ }while(0)
#else
#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET)
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
@@ -415,7 +415,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
* @retval None
*/
#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
-#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
+#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR\
+ &= (uint16_t)(~(__INTERRUPT__)))
/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the SPDIFRX Handle.
@@ -430,7 +431,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
* @arg SPDIFRX_IT_IFEIE
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified SPDIFRX flag is set or not.
* @param __HANDLE__ specifies the SPDIFRX Handle.
@@ -447,7 +449,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
* @arg SPDIFRX_FLAG_TERR
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\
+ & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
* @param __HANDLE__ specifies the USART Handle.
@@ -476,15 +479,17 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
-HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
+HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID,
+ pSPDIFRX_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif,
+ HAL_SPDIFRX_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
/**
* @}
@@ -494,9 +499,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif,
* @{
*/
/* I/O operation functions ***************************************************/
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
+ uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
@@ -522,8 +529,8 @@ void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
* @{
*/
/* Peripheral Control and State functions ************************************/
-HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif);
-uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif);
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif);
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif);
/**
* @}
*/
@@ -539,39 +546,39 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif);
* @{
*/
#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \
- ((INPUT) == SPDIFRX_INPUT_IN2) || \
- ((INPUT) == SPDIFRX_INPUT_IN3) || \
- ((INPUT) == SPDIFRX_INPUT_IN0))
+ ((INPUT) == SPDIFRX_INPUT_IN2) || \
+ ((INPUT) == SPDIFRX_INPUT_IN3) || \
+ ((INPUT) == SPDIFRX_INPUT_IN0))
#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
- ((RET) == SPDIFRX_MAXRETRIES_3) || \
- ((RET) == SPDIFRX_MAXRETRIES_15) || \
- ((RET) == SPDIFRX_MAXRETRIES_63))
+ ((RET) == SPDIFRX_MAXRETRIES_3) || \
+ ((RET) == SPDIFRX_MAXRETRIES_15) || \
+ ((RET) == SPDIFRX_MAXRETRIES_63))
#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
- ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
+ ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
- ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
+ ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
- ((VAL) == SPDIFRX_VALIDITYMASK_ON))
+ ((VAL) == SPDIFRX_VALIDITYMASK_ON))
#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
- ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
+ ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
- ((CHANNEL) == SPDIFRX_CHANNEL_B))
+ ((CHANNEL) == SPDIFRX_CHANNEL_B))
#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
- ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
- ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
+ ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
+ ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
- ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
+ ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
- ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
+ ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
#define IS_SYMBOL_CLOCK_GEN(VAL) (((VAL) == ENABLE) || ((VAL) == DISABLE))
/**
@@ -600,4 +607,4 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif);
#endif
-#endif /* __STM32H7xx_HAL_SPDIFRX_H */
+#endif /* STM32H7xx_HAL_SPDIFRX_H */
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
index 11a1165e9d..157cc9c2e3 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h
@@ -745,6 +745,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @}
*/
+/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
+ * @{
+ */
+#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */
+#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
+/**
+ * @}
+ */
+
/** @defgroup TIM_Flag_definition TIM Flag Definition
* @{
*/
@@ -785,16 +794,16 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
*/
-#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
+#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
+#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
+#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
+#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
-#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
-#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
-#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
-#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */
#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */
#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */
@@ -1041,10 +1050,6 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
-#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
-#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
-#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
-#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
#define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */
#define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */
#define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */
@@ -1055,6 +1060,10 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */
#define TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) */
#define TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) */
+#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
+#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
+#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
+#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
/**
* @}
@@ -1744,6 +1753,17 @@ mode.
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
}while(0)
+/** @brief Select the Capture/compare DMA request source.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __CCDMA__ specifies Capture/compare DMA request source
+ * This parameter can be one of the following values:
+ * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
+ * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
+ * @retval None
+ */
+#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \
+ MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
+
/**
* @}
*/
@@ -1869,15 +1889,15 @@ mode.
((__CHANNEL__) == TIM_CHANNEL_3))
#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
@@ -1998,31 +2018,31 @@ mode.
((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_ITR12) || \
+ ((__SELECTION__) == TIM_TS_ITR13) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || \
- ((__SELECTION__) == TIM_TS_ETRF) || \
- ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || \
- ((__SELECTION__) == TIM_TS_ITR12) || \
- ((__SELECTION__) == TIM_TS_ITR13))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_ITR4) || \
- ((__SELECTION__) == TIM_TS_ITR5) || \
- ((__SELECTION__) == TIM_TS_ITR6) || \
- ((__SELECTION__) == TIM_TS_ITR7) || \
- ((__SELECTION__) == TIM_TS_ITR8) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_ITR4) || \
+ ((__SELECTION__) == TIM_TS_ITR5) || \
+ ((__SELECTION__) == TIM_TS_ITR6) || \
+ ((__SELECTION__) == TIM_TS_ITR7) || \
+ ((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR12) || \
((__SELECTION__) == TIM_TS_ITR13) || \
((__SELECTION__) == TIM_TS_NONE))
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h
index 2f808741e6..7afa3c1050 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h
@@ -1112,7 +1112,8 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
*/
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h
index 11171b075f..44637a187f 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32h7xx_ll_bus.h
* @author MCD Application Team
- * @version $VERSION$
- * @date $DATE$
* @brief Header file of BUS LL module.
@verbatim
@@ -846,6 +844,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
* AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR ARTEN LL_AHB1_GRP1_EnableClock\n
+ * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n (*)
* AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock\n (*)
* AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock\n (*)
* AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock\n (*)
@@ -858,6 +857,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
@@ -920,6 +920,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
* AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR ARTEN LL_AHB1_GRP1_DisableClock\n (*)
+ * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n (*)
* AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock\n (*)
* AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock\n (*)
* AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock\n (*)
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h
index 6cf293137b..b798e7bf0b 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h
@@ -241,13 +241,13 @@ extern "C" {
* - @ref LL_CORDIC_SetNbRead()
* - @ref LL_CORDIC_SetInSize()
* - @ref LL_CORDIC_SetOutSize()
- * @rmtoll CSR FUNC LL_CORDIC_Configure\n
- * CSR PRECISION LL_CORDIC_Configure\n
- * CSR SCALE LL_CORDIC_Configure\n
- * CSR NARGS LL_CORDIC_Configure\n
- * CSR NRES LL_CORDIC_Configure\n
- * CSR ARGSIZE LL_CORDIC_Configure\n
- * CSR RESIZE LL_CORDIC_Configure
+ * @rmtoll CSR FUNC LL_CORDIC_Config\n
+ * CSR PRECISION LL_CORDIC_Config\n
+ * CSR SCALE LL_CORDIC_Config\n
+ * CSR NARGS LL_CORDIC_Config\n
+ * CSR NRES LL_CORDIC_Config\n
+ * CSR ARGSIZE LL_CORDIC_Config\n
+ * CSR RESIZE LL_CORDIC_Config
* @param CORDICx CORDIC instance
* @param Function parameter can be one of the following values:
* @arg @ref LL_CORDIC_FUNCTION_COSINE
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h
index ae0d12a856..5e8a401e77 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h
@@ -603,7 +603,7 @@ typedef struct
*/
#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
#define FMC_WRITE_FIFO_ENABLE (0x00000000U)
- #endif /* FMC_BCR1_WFDIS */
+#endif /* FMC_BCR1_WFDIS */
/**
* @}
*/
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h
index 25a174e706..39ba9807fb 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h
@@ -376,7 +376,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
}
@@ -418,7 +418,7 @@ __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
-__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *const LPTIMx)
{
CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
}
@@ -472,7 +472,7 @@ __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t Upda
* @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
* @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
}
@@ -487,7 +487,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
* @note autoreload value be strictly greater than the compare value.
* @rmtoll ARR ARR LL_LPTIM_SetAutoReload
* @param LPTIMx Low-Power Timer instance
- * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
@@ -499,9 +499,9 @@ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t Auto
* @brief Get actual auto reload value
* @rmtoll ARR ARR LL_LPTIM_GetAutoReload
* @param LPTIMx Low-Power Timer instance
- * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
}
@@ -543,7 +543,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
* @param LPTIMx Low-Power Timer instance
* @retval Counter value
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
}
@@ -571,7 +571,7 @@ __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t Cou
* @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
* @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
*/
-__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
}
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h
index ed282b435c..7c7e207dbc 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32h7xx_ll_rcc.h
* @author MCD Application Team
- * @version $VERSION$
- * @date $DATE$
* @brief Header file of RCC LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h
index fc6bbed024..3bc388b811 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h
@@ -2440,7 +2440,7 @@ __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
*/
__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
{
- return (uint16_t)(READ_REG(SPIx->RXDR));
+ return (*((__IO uint16_t *)&SPIx->RXDR));
}
/**
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h
index adf998ed74..dfb4ac48b0 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h
@@ -918,10 +918,6 @@ typedef struct
#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
#define LL_TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) is used as trigger input */
#define LL_TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
#define LL_TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
@@ -932,6 +928,10 @@ typedef struct
#define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
#define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) is used as trigger input */
#define LL_TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
/**
* @}
*/
@@ -1430,7 +1430,7 @@ typedef struct
* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
- (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
+ (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
@@ -3386,10 +3386,6 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
* @arg @ref LL_TIM_TS_ITR1
* @arg @ref LL_TIM_TS_ITR2
* @arg @ref LL_TIM_TS_ITR3
- * @arg @ref LL_TIM_TS_TI1F_ED
- * @arg @ref LL_TIM_TS_TI1FP1
- * @arg @ref LL_TIM_TS_TI2FP2
- * @arg @ref LL_TIM_TS_ETRF
* @arg @ref LL_TIM_TS_ITR4
* @arg @ref LL_TIM_TS_ITR5
* @arg @ref LL_TIM_TS_ITR6
@@ -3400,6 +3396,10 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
* @arg @ref LL_TIM_TS_ITR11 (*)
* @arg @ref LL_TIM_TS_ITR12 (*)
* @arg @ref LL_TIM_TS_ITR13 (*)
+ * @arg @ref LL_TIM_TS_TI1F_ED
+ * @arg @ref LL_TIM_TS_TI1FP1
+ * @arg @ref LL_TIM_TS_TI2FP2
+ * @arg @ref LL_TIM_TS_ETRF
*
* (*) Value not defined in all devices.
* @retval None
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h
index 05597227ec..7909971f5a 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h
@@ -131,6 +131,9 @@ typedef struct
uint8_t is_stall; /*!< Endpoint stall condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t is_iso_incomplete; /*!< Endpoint isoc condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_LL_EP_Type */
@@ -152,6 +155,8 @@ typedef struct
uint32_t xfer_len; /*!< Current transfer length */
+ uint32_t xfer_size; /*!< requested transfer size */
+
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
} USB_OTG_EPTypeDef;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/License.md b/system/Drivers/STM32H7xx_HAL_Driver/License.md
index 008472d5ab..479c4f6826 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/License.md
+++ b/system/Drivers/STM32H7xx_HAL_Driver/License.md
@@ -1 +1,27 @@
-License.md file kept for legacy purpose
\ No newline at end of file
+Copyright 2017 STMicroelectronics.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors
+may be used to endorse or promote products derived from this software without
+specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/README.md b/system/Drivers/STM32H7xx_HAL_Driver/README.md
index 2aa2da5769..65b1799a1b 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/README.md
+++ b/system/Drivers/STM32H7xx_HAL_Driver/README.md
@@ -39,6 +39,7 @@ Tag v1.8.0 | Tag v1.8.0 | Tag v5.4.0 | Tag v1.7.0 (and following, if any
Tag v1.9.0 | Tag v1.9.0 | Tag v5.4.0 | Tag v1.8.0 (and following, if any, till next HAL tag)
Tag v1.10.0 | Tag v1.10.0 | Tag v5.6.0 | Tag v1.9.0 (and following, if any, till next HAL tag)
Tag v1.10.1 | Tag v1.10.1 | Tag v5.6.0 | Tag v1.9.1 (and following, if any, till next HAL tag)
+Tag v1.10.2 | Tag v1.10.2 | Tag v5.6.0 | Tag v1.10.0 (and following, if any, till next HAL tag)
The full **STM32CubeH7** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeH7).
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html
index 71a78991d7..942ecb97aa 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html
@@ -5,14 +5,11 @@
<meta name="generator" content="pandoc" />
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
<title>Release Notes for STM32H7xx HAL Drivers</title>
- <style>
- code{white-space: pre-wrap;}
- span.smallcaps{font-variant: small-caps;}
- span.underline{text-decoration: underline;}
- div.column{display: inline-block; vertical-align: top; width: 50%;}
- div.hanging-indent{margin-left: 1.5em; text-indent: -1.5em;}
- ul.task-list{list-style: none;}
- .display.math{display: block; text-align: center; margin: 0.5rem auto;}
+ <style type="text/css">
+ code{white-space: pre-wrap;}
+ span.smallcaps{font-variant: small-caps;}
+ span.underline{text-decoration: underline;}
+ div.column{display: inline-block; vertical-align: top; width: 50%;}
</style>
<link rel="stylesheet" href="_htmresc/mini-st.css" />
<!--[if lt IE 9]>
@@ -43,14 +40,110 @@ <h1 id="purpose">Purpose</h1>
<li>Full features coverage of all the supported peripherals</li>
</ul>
</div>
-<section id="update-history" class="col-sm-12 col-lg-8">
-<h1><strong>Update History</strong></h1>
+<div class="col-sm-12 col-lg-8">
+<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section14" checked aria-hidden="true"> <label for="collapse-section14" aria-hidden="true"><strong>V1.10.1 / 06-December-2021</strong></label>
+<input type="checkbox" id="collapse-section15" checked aria-hidden="true"> <label for="collapse-section15" aria-hidden="true"><strong>V1.11.0 / 11-February-2022</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements.</li>
+<li><strong>The following changes done on the HAL drivers require an update of the application code based on older HAL versions</strong>
+<ul>
+<li>Rework of HAL Ethernet driver to resolve problems and improve performance.(compatibility break)</li>
+<li>A new HAL Ethernet driver has been redesigned with new APIs, to bypass limitations with previous HAL Ethernet driver version.</li>
+<li>The new HAL Ethernet driver is the recommended version. It is located as usual in Drivers/STM32H7xx_HAL_Driver/Src and Drivers/STM32H7xx_HAL_Driver/Inc folders.
+<ul>
+<li>It can be enabled through switch HAL_ETH_MODULE_ENABLED in stm32h7xx_hal_conf.h</li>
+</ul></li>
+<li>The legacy HAL Ethernet driver is also present in the release in Drivers/STM32H7xx_HAL_Driver/Src/Legacy and Drivers/STM32F4xx_HAL_Driver/Inc/Legacy folders for software compatibility reasons.
+<ul>
+<li>Its usage is not recommended as deprecated. It can however be enabled through switch HAL_ETH_LEGACY_MODULE_ENABLED in stm32h7xx_hal_conf.h</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL LTDC</strong>
+<ul>
+<li>Update HAL_LTDC_DeInit() to fix MCU Hang up during LCD turn OFF.</li>
+</ul></li>
+<li><strong>HAL QSPI</strong>
+<ul>
+<li>Update HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() APIs to check on QSPI BUSY flag status before executing the abort procedure.</li>
+</ul></li>
+<li><strong>LL TIM</strong>
+<ul>
+<li>__LL_TIM_CALC_PSC() macro update to round up the evaluate value when the fractional part of the division is greater than 0.5.</li>
+</ul></li>
+<li><strong>HAL NOR</strong>
+<ul>
+<li>FMC_WRITE_OPERATION_DISABLE for NOR cause Hardfault for Read operations</li>
+</ul></li>
+<li><strong>HAL OSPI</strong>
+<ul>
+<li>Remove unsupported Clocked Chip Select High Time feature:
+<ul>
+<li>ClkChipSelectHighTime parameter removed from the OSPI_InitTypeDef structure</li>
+<li>Update HAL_OSPI_Init() API to no longer configure the ClkChipSelectHighTime parameter in the OCTOSPI_DCR1 register</li>
+</ul></li>
+<li>Fix an MPU issue with OTFDEC examples and STM32H735G-DK BSP example.</li>
+<li>Update HAL_OSPI_Init() to fix DelayBlockBypass parameter configuration issue.</li>
+</ul></li>
+<li><strong>HAL SPI</strong>
+<ul>
+<li>Update SPI_IRQ_Handler() to overrun error occurrence in full duplex communication.
+<ul>
+<li>Add clear for transmission flag.</li>
+</ul></li>
+<li>Update HAL_SPI_Receive() API to avoid hardfault exception in Master RX, Polling mode 8 bits mode when 2 byte are available at the same time.</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong>
+<ul>
+<li>stm32h7xx_hal_smbus_ex.c/.h file added to support new <strong>HAL SMBUS extended feature</strong>.
+<ul>
+<li>Add Support for Fast Mode Plus to be SMBUS rev 3 compliant.
+<ul>
+<li>Add HAL_SMBUSEx_EnableFastModePlus() and HAL_SMBUSEx_DisableFastModePlus() APIs to manage Fm+.</li>
+</ul></li>
+<li>Add Support of wake up capability.
+<ul>
+<li>Add HAL_SMBUSEx_EnableWakeUp() and HAL_SMBUSEx_DisableWakeUp() APIs.</li>
+</ul></li>
+</ul></li>
+</ul></li>
+<li><strong>HAL ETH</strong>
+<ul>
+<li>Entire receive process reworked.</li>
+<li>Resolve the problem of received data corruption.</li>
+<li>Implement transmission in interrupt mode.</li>
+<li>Handle one interrupt for multiple transmitted packets.</li>
+<li>Implement APIs to handle PTP feature.</li>
+<li>Implement APIs to handle Timestamp feature.</li>
+<li>Add support of receive buffer unavailable.</li>
+<li>Update HAL_ETH_IRQHandler() to handle receive buffer unavailable.</li>
+</ul></li>
+<li><strong>HAL/LL USB</strong>
+<ul>
+<li>Update to report correct received amount of data with USB DMA enabled</li>
+<li>Update USB IRQ handler to enable EP OUT disable</li>
+<li>Add support of USB IN/OUT Iso incomplete</li>
+<li>Fix USB BCD data contact timeout</li>
+</ul></li>
+</ul>
+<h2 id="known-limitations">Known Limitations</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="backward-compatibility">Backward compatibility</h2>
+<ul>
+<li>Compatibility break with HAL ETH driver V1.10.0 available within STM32CubeFW_H7 V1.9.0</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true"><strong>V1.10.1 / 06-December-2021</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>General updates to fix known defects and implementation enhancements.</li>
<li>All source files: update disclaimer to add reference to the new license agreement.</li>
<li><strong>HAL RCC</strong>
<ul>
@@ -207,14 +300,14 @@ <h2 id="main-changes">Main Changes</h2>
<li>Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT).</li>
</ul></li>
</ul>
-<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="known-limitations-1">Known Limitations</h2>
<ul>
<li><strong>HAL/ETH</strong>
<ul>
<li>A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility">Backward compatibility</h2>
+<h2 id="backward-compatibility-1">Backward compatibility</h2>
<ul>
<li>None</li>
</ul>
@@ -223,11 +316,11 @@ <h2 id="backward-compatibility">Backward compatibility</h2>
<div class="collapse">
<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.10.0 / 12-February-2021</strong></label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li><p>General updates to fix known defects and implementation enhancements</p></li>
<li><p>Fix minor issues related to English typo in comments</p></li>
-<li><p>Update stm32h7xx_hal_def.h implementation to support MDK-ARM AC6 compiler</p>
+<li>Update stm32h7xx_hal_def.h implementation to support MDK-ARM AC6 compiler
<ul>
<li>Notes:
<ul>
@@ -236,7 +329,7 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Template projects updated with “Use default compiler version 6” setting and “AC5-like warning” setting</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL</strong>:</p>
+<li><strong>HAL</strong>:
<ul>
<li>stm32h7xx_hal.h and stm32h7xx_hal.c:
<ul>
@@ -252,7 +345,7 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Update USE_SD_TRANSCEIVER define default value to zero Notes: This define shall be set in the target project according to the given board: set to 1 in case of an SD transceiver is present or zero if not</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL ADC</strong>:</p>
+<li><strong>HAL/LL ADC</strong>:
<ul>
<li>stm32h7xx_hal_adc.h:
<ul>
@@ -263,14 +356,14 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Update timeout mechanism to avoid false timeout detection in case of preemption</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL CEC</strong>:</p>
+<li><strong>HAL CEC</strong>:
<ul>
<li>stm32h7xx_hal_cec.c:
<ul>
<li>Update “HAL_CEC_IRQHandler” implementation to avoid extra byte sent with CEC command</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL CRYP</strong>:</p>
+<li><strong>HAL CRYP</strong>:
<ul>
<li>stm32h7xx_hal_cryp.h:
<ul>
@@ -285,14 +378,14 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Update the implementation of the “HAL_CRYPEx_AESGCM_GenerateAuthTAG” function to support the header width unit setting</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL EXTI</strong>:</p>
+<li><strong>HAL/LL EXTI</strong>:
<ul>
<li>stm32h7xx_hal_exti.h:
<ul>
<li>Update IS_EXTI_PROPERTY to IS_EXTI_CONFIG_LINE macros implementation using “<strong>EXTI_LINE</strong>” instead of “<strong>LINE</strong>” o avoid clash with compiler key word “<strong>LINE</strong>”</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL ETH</strong>:</p>
+<li><strong>HAL/LL ETH</strong>:
<ul>
<li>stm32h7xx_hal_eth.h:
<ul>
@@ -307,7 +400,7 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>This implementation allows to improve packet transmission performance using NetX Duo TCPIP stack, however a more elaborated implementation will be provided in next release</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL FLASH</strong>:</p>
+<li><strong>HAL/LL FLASH</strong>:
<ul>
<li>stm32h7xx_hal_flash_ex.h:
<ul>
@@ -320,7 +413,7 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Update “HAL_FLASH_Program” description with details for “FlashAddress” and “DataAddress” alignment requirements</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL GPIO</strong>:</p>
+<li><strong>HAL/LL GPIO</strong>:
<ul>
<li>stm32h7xx_hal_gpio.c:
<ul>
@@ -331,28 +424,28 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Update and fix LL_GPIO_TogglePin implementation to allow toggle of multiple pin</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL HRTIM</strong>:</p>
+<li><strong>HAL/LL HRTIM</strong>:
<ul>
<li>stm32h7xx_hal_hrtim.c:
<ul>
<li>Update HRTIM_HRTIM_ISR implementation to optimize the read flags</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL IWDG</strong>:</p>
+<li><strong>HAL/LL IWDG</strong>:
<ul>
<li>stm32h7xx_hal_iwdg.c:
<ul>
<li>Update timeout mechanism to avoid false timeout detection in case of preemptio</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL LPTIM</strong></p>
+<li><strong>HAL/LL LPTIM</strong>
<ul>
<li>stm32h7xx_hal_lptim.c:
<ul>
<li>Update “HAL_LPTIM_Init” implementation to improve behavior for external clock configuration</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL NAND</strong>:</p>
+<li><strong>HAL NAND</strong>:
<ul>
<li>stm32h7xx_hal_nand.c:
<ul>
@@ -360,7 +453,7 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Update implementation of “HAL_NAND_Write_Page_16b” and “HAL_NAND_Read_Page_16b” APIs implementation to fix an issue with the page calculation of 8 bits memories</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL NOR</strong>:</p>
+<li><strong>HAL NOR</strong>:
<ul>
<li>stm32h7xx_hal_nor.c:
<ul>
@@ -368,7 +461,7 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Update NOR APIs implementation to support some specific memories</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL RCC</strong>:</p>
+<li><strong>HAL RCC</strong>:
<ul>
<li>stm32h7xx_hal_rcc.c:
<ul>
@@ -385,7 +478,7 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Update implementation of “HAL_RCCEx_GetPLL1ClockFreq” to use HSI in default case as per the specification</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL RNG</strong>:</p>
+<li><strong>HAL RNG</strong>:
<ul>
<li>stm32h7xx_hal_rng.h:
<ul>
@@ -406,7 +499,7 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Add “HAL_RNGEx_RecoverSeedError” function</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL SDMMC</strong>:</p>
+<li><strong>HAL/LL SDMMC</strong>:
<ul>
<li>stm32h7xx_hal_mmc.c:
<ul>
@@ -438,7 +531,7 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Add “SDMMC_CmdSetRelAddMmc” function to set relative address</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL SPI</strong></p>
+<li><strong>HAL/LL SPI</strong>
<ul>
<li>Update “HAL_SPI_TransmitReceive_IT” implementation to disable RXP and TXP interrupt when DXP is enabled</li>
<li>Update “HAL_SPI_Init” implementation with NSS Software Management</li>
@@ -447,14 +540,14 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Update “LL_SPI_Init” implementation to set the internal SS level</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL TIM</strong>:</p>
+<li><strong>HAL/LL TIM</strong>:
<ul>
<li>stm32h7xx_ll_tim.h:
<ul>
<li>Fix “LL_TIM_GetCounterMode” implementation to handle all possible return combinations</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL UART</strong>:</p>
+<li><strong>HAL/LL UART</strong>:
<ul>
<li>stm32h7xx_hal_uart.h:
<ul>
@@ -485,14 +578,14 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Update “LL_LPUART_SetBaudRate” implementation to avoid potential division by zero</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL USART</strong>:</p>
+<li><strong>HAL/LL USART</strong>:
<ul>
<li>stm32h7xx_ll_usart.h:
<ul>
<li>Update “LL_USART_SetBaudRate” implementation to avoid potential division by zero</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL USB</strong>:</p>
+<li><strong>HAL/LL USB</strong>:
<ul>
<li>Update to ensure to have coherency between USB APIs start and stop which should mainly control device connect and disconnect of the USB RPU</li>
<li>Fix ping with DMA OFF, fix Data toggle issue with DMA multi max packet size transfers and clean up device and core speeds</li>
@@ -501,7 +594,7 @@ <h2 id="main-changes-1">Main Changes</h2>
<li>Update to fix USB OTG read FIFO packet in stm32h7xx_ll_usb.c file</li>
<li>Update to support USB OTG FIFO with scatter gather</li>
</ul></li>
-<li><p><strong>LL SYSTEM</strong>:</p>
+<li><strong>LL SYSTEM</strong>:
<ul>
<li>stm32h7xx_ll_system.h:
<ul>
@@ -509,14 +602,14 @@ <h2 id="main-changes-1">Main Changes</h2>
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
<ul>
<li><strong>HAL/ETH</strong>
<ul>
<li>A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-1">Backward compatibility</h2>
+<h2 id="backward-compatibility-2">Backward compatibility</h2>
<ul>
<li>None</li>
</ul>
@@ -525,7 +618,7 @@ <h2 id="backward-compatibility-1">Backward compatibility</h2>
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>First official release of the STM32CubeH7 Firmware Package supporting <strong>STM32H72x/3x</strong> new devices</li>
<li>General updates to fix known defects and implementation enhancements</li>
@@ -597,7 +690,7 @@ <h2 id="main-changes-2">Main Changes</h2>
<li>stm32h7xx_hal_eth.h:
<ul>
<li><p>Update ETH_DMADescTypeDef definition: remove useless volatile of the BackupAddr0 and BackupAddr1 fields since they are not used by ETH DMA.</p></li>
-<li><p>stm32h7xx_hal_eth.c:</p>
+<li>stm32h7xx_hal_eth.c:
<ul>
<li>HAL_ETH_Start_IT:
<ul>
@@ -1119,11 +1212,11 @@ <h2 id="main-changes-2">Main Changes</h2>
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-2">Known Limitations</h2>
+<h2 id="known-limitations-3">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
-<h2 id="backward-compatibility-2">Backward compatibility</h2>
+<h2 id="backward-compatibility-3">Backward compatibility</h2>
<ul>
<li>Extension RTC APIs HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs prototypes updated with new parameters Instance (alignment with other STM32 families)</li>
</ul>
@@ -1132,7 +1225,7 @@ <h2 id="backward-compatibility-2">Backward compatibility</h2>
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic
@@ -1366,7 +1459,7 @@ <h2 id="main-changes-3">Main Changes</h2>
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-3">Known Limitations</h2>
+<h2 id="known-limitations-4">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -1376,7 +1469,7 @@ <h2 id="known-limitations-3">Known Limitations</h2>
</ul></li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-3">Backward compatibility</h2>
+<h2 id="backward-compatibility-4">Backward compatibility</h2>
<ul>
<li>None</li>
</ul>
@@ -1385,12 +1478,12 @@ <h2 id="backward-compatibility-3">Backward compatibility</h2>
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
-<li><p>Official release with support of STM32H7A3/B3xx/B0xx new devices<br />
-</p></li>
-<li><p>General updates to fix known defects and implementation enhancements</p></li>
-<li><p><strong>HAL</strong>: generic</p>
+<li>Official release with support of STM32H7A3/B3xx/B0xx new devices<br />
+</li>
+<li>General updates to fix known defects and implementation enhancements</li>
+<li><strong>HAL</strong>: generic
<ul>
<li>stm32h7xx_hal.h:
<ul>
@@ -1412,7 +1505,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Fix HAL_EXTI_D1_ClearFlag and HAL_EXTI_D2_ClearFlag APIs implementation: using direct write operation (instead of read/modify/write)</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL ADC</strong>:</p>
+<li><strong>HAL/LL ADC</strong>:
<ul>
<li>stm32h7xx_hal_adc.h:
<ul>
@@ -1449,7 +1542,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Update HAL_ADCEx_LinearCalibration_FactorLoad API implementation to consider ADC2 and ADC3 in addition to ADC1</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL COMP</strong>:</p>
+<li><strong>HAL/LL COMP</strong>:
<ul>
<li>stm32h7xx_hal_comp.h:
<ul>
@@ -1475,7 +1568,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Add LL_COMP_SetOutputAlternateFunction and LL_COMP_GetOutputAlternateFunction allowing to Set/Get the output alternate function in the Option register</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL CRYP</strong>:</p>
+<li><strong>HAL CRYP</strong>:
<ul>
<li>stm32h7xx_hal_cryp.h:
<ul>
@@ -1489,7 +1582,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Update to support user input/output buffers size that is not multiple of 4 words (size of the CRYP peripheral FIFO)</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL DAC</strong>:</p>
+<li><strong>HAL/LL DAC</strong>:
<ul>
<li>stm32h7xx_hal_dac.h:
<ul>
@@ -1529,7 +1622,7 @@ <h2 id="main-changes-4">Main Changes</h2>
</ul></li>
<li>stm32h7xx_ll_dac.h: Update to support STM32H7A3/B3xx/B0xx devices New DAC triggers</li>
</ul></li>
-<li><p><strong>HAL DCMI</strong>:</p>
+<li><strong>HAL DCMI</strong>:
<ul>
<li>stm32h7xx_hal_dcmi.h:
<ul>
@@ -1541,7 +1634,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Add implementation HAL_DCMI_ConfigSyncUnmask API</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL DFSDM</strong>:</p>
+<li><strong>HAL DFSDM</strong>:
<ul>
<li>stm32h7xx_hal_dfsdm.h:
<ul>
@@ -1560,7 +1653,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>New extension file with HAL_DFDSMEx_ChannelSetPulsesSkipping and HAL_DFDSMEx_ChannelGetPulsesSkipping APIs implementation</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL DMA</strong>:</p>
+<li><strong>HAL/LL DMA</strong>:
<ul>
<li>stm32h7xx_hal_dma.h:
<ul>
@@ -1586,7 +1679,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>HRTIM, SAI3, SAI4, ADC3 requests are available only when these peripherals are present on the given device (through CMSIS device mapping)</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL DMA2D</strong>:</p>
+<li><strong>HAL/LL DMA2D</strong>:
<ul>
<li>stm32h7xx_hal_dma2d.h:
<ul>
@@ -1617,28 +1710,28 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Update LL_DMA2D_StructInit API implementation to support byte swap and line offset modes</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL DTS</strong>:</p>
+<li><strong>HAL DTS</strong>:
<ul>
<li>Add New HAL DTS driver stm32h7xx_hal_dts.h/stm32h7xx_hal_dts.c (Digital Temperature Sensor). This peripheral is available on STM32H7A3/B3xx/B0xx devices only</li>
</ul></li>
-<li><p><strong>HAL/LL EXTI</strong>:</p>
+<li><strong>HAL/LL EXTI</strong>:
<ul>
<li>Update to consider STM32H7A3/B3xx/B0xx devices EXTI lines</li>
<li>Update EXTI Pend Clear Sources considering STM32H7A3/B3xx/B0xx devices: LPTIM2 and LPTIM3 used as SRD domain wakeup pend clear source versus LPTIM4/LPTIM5 in the legacy devices</li>
</ul></li>
-<li><p><strong>HAL FLASH</strong>:</p>
+<li><strong>HAL FLASH</strong>:
<ul>
<li>Update to consider Flash operations on STM32H7A3/B3xx/B0xx devices</li>
</ul></li>
-<li><p><strong>HAL GFXMMU</strong>:</p>
+<li><strong>HAL GFXMMU</strong>:
<ul>
<li>Add GFXMMU HAL driver stm32h7xx_hal_gfxmmu.h/stm32h7xx_hal_gfxmmu.c. This peripheral is available on STM32H7A3/B3xx/B0xx devices only</li>
</ul></li>
-<li><p><strong>HAL GPIO</strong>:</p>
+<li><strong>HAL GPIO</strong>:
<ul>
<li>Update GPIO Alternate functions definitions (in stm32h7xx_hal_gpio_ex.h file) for STM32H7A3/B3xx/B0xx devices</li>
</ul></li>
-<li><p><strong>HAL HASH</strong>:</p>
+<li><strong>HAL HASH</strong>:
<ul>
<li>stm32h7xx_hal_hash.h:
<ul>
@@ -1660,7 +1753,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Add implementation of HAL_HASHEx_SHA224_Accmlt_IT/HAL_HASHEx_SHA224_Accmlt_End_IT, HAL_HASHEx_SHA256_Accmlt_IT/HAL_HASHEx_SHA256_Accmlt_End_IT APIs</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL I2S</strong>:</p>
+<li><strong>HAL I2S</strong>:
<ul>
<li>stm32h7xx_hal_i2s.h:
<ul>
@@ -1676,7 +1769,7 @@ <h2 id="main-changes-4">Main Changes</h2>
</ul></li>
<li>stm32h7xx_hal_i2s_ex.h/stm32h7xx_hal_i2s_ex.c : These files are empty as full duplex feature is not available in this release</li>
</ul></li>
-<li><p><strong>HAL/LL LPTIM</strong>:</p>
+<li><strong>HAL/LL LPTIM</strong>:
<ul>
<li>stm32h7xx_hal_lptim.h:
<ul>
@@ -1687,7 +1780,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Add definition of LL_LPTIM_TRIG_SOURCE_LPTIM2 to LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK trigger sources</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL MDMA</strong>:</p>
+<li><strong>HAL/LL MDMA</strong>:
<ul>
<li>stm32h7xx_hal_mdma.h:
<ul>
@@ -1708,7 +1801,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Delimit definition of LTDC, QUADSPI and JPEG requests by the peripherals availability</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL MMC</strong>:</p>
+<li><strong>HAL MMC</strong>:
<ul>
<li>stm32h7xx_hal_mmc_ex.h:
<ul>
@@ -1724,7 +1817,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Fix HAL_MMCEx_ConfigDMAMultiBuffer API implementation regarding DMA block size</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL OPAMP</strong>:</p>
+<li><strong>HAL/LL OPAMP</strong>:
<ul>
<li>stm32h7xx_hal_opamp.h:
<ul>
@@ -1746,14 +1839,14 @@ <h2 id="main-changes-4">Main Changes</h2>
<li><p><strong>HAL OSPI</strong>: New HAL driver stm32h7xx_hal_ospi.h/stm32h7xx_hal_ospi.c to handle OctoSPI peripheral (available on STM32H7A3/B3xx/B0xx devices only)</p></li>
<li><p><strong>HAL OTFDEC</strong>: New HAL driver stm32h7xx_hal_otfdec.h/stm32h7xx_hal_otfdec.c to handle OTFDEC peripheral (available on STM32H7A3/B3xx/B0xx devices only)</p></li>
<li><p><strong>HAL PSSI</strong>: New HAL driver stm32h7xx_hal_pssi.h/stm32h7xx_hal_pssi.c to handle PSSI peripheral (available on STM32H7A3/B3xx/B0xx devices only)</p></li>
-<li><p><strong>HAL/LL PWR</strong>: Update to handle STM32H7A3/B3xx/B0xx devices</p>
+<li><strong>HAL/LL PWR</strong>: Update to handle STM32H7A3/B3xx/B0xx devices
<ul>
<li>2 power domains only (versus 3 in legacy STM32H7 devices)</li>
<li>VOS0 voltage scalling management</li>
<li>Wake up flag management</li>
<li>STOP2 Low Power mode management</li>
</ul></li>
-<li><p><strong>HAL RAMECC</strong>:</p>
+<li><strong>HAL RAMECC</strong>:
<ul>
<li>stm32h7xx_hal_ramecc.h:
<ul>
@@ -1767,7 +1860,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Add HAL_RAMECC_IsECCSingleErrorDetected, HAL_RAMECC_IsECCDoubleErrorDetected APIs implementation</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL RCC</strong>:</p>
+<li><strong>HAL/LL RCC</strong>:
<ul>
<li>stm32h7xx_hal_rcc.h: Update to support STM32H7A3/B3xx/B0xx devices</li>
<li>Add OCTOSPI1/2, OCTOSPIM, OTFDEC1/2, GFXMMU peripherals clock enabling/disabling, force reset/release reset macros</li>
@@ -1797,7 +1890,7 @@ <h2 id="main-changes-4">Main Changes</h2>
</ul></li>
<li>Update other peripherals clock source definitions according to the number of instance on STM32H7A3/B3xx/B0xx devices and on the legacy STM32H7 devices</li>
</ul></li>
-<li><p><strong>HAL/LL RNG</strong>:</p>
+<li><strong>HAL/LL RNG</strong>:
<ul>
<li>stm32h7xx_hal_rng.h: Update to support STM32H7A3/B3xx/B0xx devices</li>
<li>Add definition of HAL_RNG_ERROR_BUSY, HAL_RNG_ERROR_SEED and HAL_RNG_ERROR_CLOCK error codes</li>
@@ -1827,7 +1920,7 @@ <h2 id="main-changes-4">Main Changes</h2>
</ul></li>
</ul></li>
<li><p><strong>HAL/LL RTC</strong>: Update to support STM32H7A3/B3xx/B0xx devices new RTC features</p></li>
-<li><p><strong>HAL SAI</strong>:</p>
+<li><strong>HAL SAI</strong>:
<ul>
<li>Update to support STM32H7A3/B3xx/B0xx devices SAI instances:
<ul>
@@ -1836,11 +1929,11 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Usage of a giving SAI instance is conditioned with its presence on the given device (according to the CMSIS device memory mapping)</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL SAI</strong>:</p>
+<li><strong>HAL SAI</strong>:
<ul>
<li>Update to support STM32H7A3/B3xx/B0xx devices SAI instances:</li>
</ul></li>
-<li><p><strong>HAL SD</strong>:</p>
+<li><strong>HAL SD</strong>:
<ul>
<li>stm32h7xx_hal_sd_ex.h:
<ul>
@@ -1857,7 +1950,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Fix HAL_SDEx_ReadBlocksDMAMultiBuffer/HAL_SDEx_WriteBlocksDMAMultiBuffer APIs implementation to avoid losing data in read and dead lock in write</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL SPI</strong>:</p>
+<li><strong>HAL/LL SPI</strong>:
<ul>
<li>stm32h7xx_hal_spi.c:
<ul>
@@ -1869,14 +1962,14 @@ <h2 id="main-changes-4">Main Changes</h2>
</ul></li>
</ul></li>
</ul></li>
-<li><p><strong>HAL SPI</strong>:</p>
+<li><strong>HAL SPI</strong>:
<ul>
<li>stm32h7xx_hal_spi.c:
<ul>
<li>Fix GCC compilation war</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL TIM</strong>:</p>
+<li><strong>HAL/LL TIM</strong>:
<ul>
<li>stm32h7xx_hal_tim.h:
<ul>
@@ -1894,19 +1987,19 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Update TIM_SlaveTimer_SetConfig API implementation to handle TIM_TS_ITR9 to TIM_TS_ITR13 input triggers</li>
</ul></li>
</ul></li>
-<li><p><strong>LL BUS</strong>:</p>
+<li><strong>LL BUS</strong>:
<ul>
<li>stm32h7xx_ll_bus.h: Update to support STM32H7A3/B3xx/B0xx devices peripherals</li>
</ul></li>
-<li><p><strong>LL CRS</strong>:</p>
+<li><strong>LL CRS</strong>:
<ul>
<li>stm32h7xx_ll_crs.h/stm32h7xx_ll_crs.c: New LL driver allowing to handle CRS (Clock Recovery System) module</li>
</ul></li>
-<li><p><strong>LL SDMMC</strong> (LL core driver for HAL SD/MMC):</p>
+<li><strong>LL SDMMC</strong> (LL core driver for HAL SD/MMC):
<ul>
<li>stm32h7xx_ll_sdmmc.c: Fix SDMMC_CmdStopTransfer implementation to ignore address Out Of Range error that is not relevant at end of memory</li>
</ul></li>
-<li><p><strong>LL SYSTEM</strong>:</p>
+<li><strong>LL SYSTEM</strong>:
<ul>
<li>stm32h7xx_ll_system.h:
<ul>
@@ -1918,7 +2011,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Add LL_SYSCFG_VDMMCSetNMOSCompensationCode/LL_SYSCFG_VDMMCGetNMOSCompensationCode APIs</li>
</ul></li>
</ul></li>
-<li><p><strong>LL UTILS</strong>:</p>
+<li><strong>LL UTILS</strong>:
<ul>
<li>stm32h7xx_ll_utils.h:
<ul>
@@ -1926,7 +2019,7 @@ <h2 id="main-changes-4">Main Changes</h2>
<li>Update LL_GetPackageType API to support STM32H7A3/B3xx/B0xx devices package types</li>
</ul></li>
</ul></li>
-<li><p><strong>LL DELAY BLOCK</strong> (LL core driver for HAL SD):</p>
+<li><strong>LL DELAY BLOCK</strong> (LL core driver for HAL SD):
<ul>
<li>stm32h7xx_ll_delayblock.h:
<ul>
@@ -1940,7 +2033,7 @@ <h2 id="main-changes-4">Main Changes</h2>
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-4">Known Limitations</h2>
+<h2 id="known-limitations-5">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -1954,7 +2047,7 @@ <h2 id="known-limitations-4">Known Limitations</h2>
<li>New PSSI driver provided supporting both modes : DMA mode recommended/ polling mode has hardware limitation confirmed and mentioned in the STM32H7A3/B3xx/B0xx erratasheet.</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-4">Backward compatibility</h2>
+<h2 id="backward-compatibility-5">Backward compatibility</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -1978,10 +2071,10 @@ <h2 id="backward-compatibility-4">Backward compatibility</h2>
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
-<li><p>General updates to fix known defects and implementation enhancements</p></li>
-<li><p><strong>HAL</strong>: generic</p>
+<li>General updates to fix known defects and implementation enhancements</li>
+<li><strong>HAL</strong>: generic
<ul>
<li>stm32h7xx_hal.h:
<ul>
@@ -2001,7 +2094,7 @@ <h2 id="main-changes-5">Main Changes</h2>
<li>Add “USE_SPI_CRC” definition set to 1 by default and customizable by the HAL user</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL ADC</strong>:</p>
+<li><strong>HAL/LL ADC</strong>:
<ul>
<li>stm32h7xx_hal_adc.h:
<ul>
@@ -2037,7 +2130,7 @@ <h2 id="main-changes-5">Main Changes</h2>
<li>Update “HAL_ADCEx_InjectedConfigChannel” implementation to set the ADC selected offset right shift</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL CRYP</strong>:</p>
+<li><strong>HAL CRYP</strong>:
<ul>
<li>stm32h7xx_hal_cryp.c:
<ul>
@@ -2045,14 +2138,14 @@ <h2 id="main-changes-5">Main Changes</h2>
<li>Update “CRYP_Workaround” to fix the implementation of the authentication tags computation phase during a GCM encryption when the size of the last payload block is inferior to 128 bits</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL GPIO</strong>:</p>
+<li><strong>HAL GPIO</strong>:
<ul>
<li>stm32h7xx_hal_gpio.c:
<ul>
<li>Fix implementation of “HAL_GPIO_DeInit” API in order to clear the correct external interrupt/event in SYSCFG EXTICR register</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL HRTIM</strong>:</p>
+<li><strong>HAL/LL HRTIM</strong>:
<ul>
<li>stm32h7xx_hal_hrtim.h:
<ul>
@@ -2072,21 +2165,21 @@ <h2 id="main-changes-5">Main Changes</h2>
<li>Fix definitions of the output set sources (“LL_HRTIM_CROSSBAR_NONE” to “LL_HRTIM_CROSSBAR_UPDATE” replacing “LL_HRTIM_OUTPUTSET_NONE” to LL_HRTIM_OUTPUTSET_UPDATE) according to the reference manual (<strong>compatibility break</strong>)</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL HSEM</strong>:</p>
+<li><strong>HAL/LL HSEM</strong>:
<ul>
<li>stm32h7xx_hal_hsem.c:
<ul>
<li>Update “HAL_HSEM_Release” implementation to support dynamic CPU ID detection useful when code is intended to be shared between the Cortex-M4 and Cortex-M7 in a dual core device</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL IRDA</strong>:</p>
+<li><strong>HAL IRDA</strong>:
<ul>
<li>stm32h7xx_hal_irda.c:
<ul>
<li>Update description of “HAL_IRDA_Transmit_XXX”, “HAL_IRDA_Receive_XXX” APIs with more details about the data size management</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL LPTIM</strong>:</p>
+<li><strong>HAL LPTIM</strong>:
<ul>
<li>stm32h7xx_hal_lptim.c:
<ul>
@@ -2104,7 +2197,7 @@ <h2 id="main-changes-5">Main Changes</h2>
</ul></li>
</ul></li>
</ul></li>
-<li><p><strong>HAL MMC</strong>:</p>
+<li><strong>HAL MMC</strong>:
<ul>
<li>stm32h7xx_hal_mmc.h:
<ul>
@@ -2158,14 +2251,14 @@ <h2 id="main-changes-5">Main Changes</h2>
<li>Update “HAL_SD_ConfigSpeedBusOperation” implementation to handle “SDMMC_SPEED_MODE_AUTO” and “SDMMC_SPEED_MODE_HIGH” SD card speed modes in case of no transceiver present</li>
</ul></li>
</ul></li>
-<li><p><strong>LL SDMMC</strong>:</p>
+<li><strong>LL SDMMC</strong>:
<ul>
<li>Update “SDMMC_InitTypeDef” structure to add “TranceiverPresent” field in case of the define “USE_SD_TRANSCEIVER” is not zero:
<ul>
<li>This parameter allows to handle 2 SD instances with different settings regarding the transceiver presence as described above</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL RCC</strong>:</p>
+<li><strong>HAL/LL RCC</strong>:
<ul>
<li>stm32h7xx_ll_rcc.h:
<ul>
@@ -2180,7 +2273,7 @@ <h2 id="main-changes-5">Main Changes</h2>
<li>Update “HAL_RCCEx_GetPeriphCLKFreq” API implementation to add support of the SDMMC peripheral clock frequency calculation</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL TIM</strong>:</p>
+<li><strong>HAL TIM</strong>:
<ul>
<li>stm32h7xx_hal_tim.h:
<ul>
@@ -2201,7 +2294,7 @@ <h2 id="main-changes-5">Main Changes</h2>
<li>Update “HAL_TIMEx_ConfigBreakDeadTime” description to add details about interrupts enabling and generation</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL UART</strong>:</p>
+<li><strong>HAL UART</strong>:
<ul>
<li>Update to add UART Receiver timeout management (RTOF)</li>
<li>stm32h7xx_hal_uart.h:
@@ -2219,7 +2312,7 @@ <h2 id="main-changes-5">Main Changes</h2>
<li>Add implementation of “HAL_UART_ReceiverTimeout_Config”, “HAL_UART_EnableReceiverTimeout” and “HAL_UART_DisableReceiverTimeout” APIs</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL USB</strong>:</p>
+<li><strong>HAL USB</strong>:
<ul>
<li>stm32h7xx_hal_hcd.c
<ul>
@@ -2234,7 +2327,7 @@ <h2 id="main-changes-5">Main Changes</h2>
<li>Update “HAL_PCD_IRQHandler” to remove useless initialization of epnum variable in HAL_PCD_IRQHandler() for OTG instance</li>
</ul></li>
</ul></li>
-<li><p><strong>HAL/LL USART</strong>:</p>
+<li><strong>HAL/LL USART</strong>:
<ul>
<li>stm32h7xx_hal_usart.c:
<ul>
@@ -2245,7 +2338,7 @@ <h2 id="main-changes-5">Main Changes</h2>
<li>Update “LL_USART_SetBaudRate” implementation to avoid overflow in “USART_PRESCALER_TAB” table</li>
</ul></li>
</ul></li>
-<li><p><strong>LL SYSTEM</strong>:</p>
+<li><strong>LL SYSTEM</strong>:
<ul>
<li>stm32h7xx_ll_system.h:
<ul>
@@ -2253,11 +2346,11 @@ <h2 id="main-changes-5">Main Changes</h2>
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-5">Known Limitations</h2>
+<h2 id="known-limitations-6">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
-<h2 id="backward-compatibility-5">Backward compatibility</h2>
+<h2 id="backward-compatibility-6">Backward compatibility</h2>
<ul>
<li><strong>HAL TIM</strong>:
<ul>
@@ -2275,7 +2368,7 @@ <h2 id="backward-compatibility-5">Backward compatibility</h2>
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add support for VOS0 power regulator voltage scaling with 480MHz over clock</li>
@@ -2745,7 +2838,7 @@ <h2 id="main-changes-6">Main Changes</h2>
<li>Update LL_Init1msTick and LL_SetSystemCoreClock description for <strong>DUAL CORE</strong> lines</li>
</ul></li>
</ul>
-<h2 id="known-limitations-6">Known Limitations</h2>
+<h2 id="known-limitations-7">Known Limitations</h2>
<ul>
<li><strong>HAL SD</strong>:
<ul>
@@ -2759,7 +2852,7 @@ <h2 id="known-limitations-6">Known Limitations</h2>
<li>Full duplex Transmit/receive feature not available</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-6">Backward compatibility</h2>
+<h2 id="backward-compatibility-7">Backward compatibility</h2>
<ul>
<li><strong>HAL ADC</strong>:
<ul>
@@ -2811,7 +2904,7 @@ <h2 id="backward-compatibility-6">Backward compatibility</h2>
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add LL drivers : LL_ADC, LL_BDMA, LL_BUS, LL_COMP, LL_CORTEX, LL_CRC, LL_DAC, LL_DMA, LL_DMA2D, LL_DMAMUX, LL_EXTI, LL_GPIO, LL_HRTIM, LL_HSEM, LL_I2C, LL_IWDG, LL_LPTIM, LL_LPUART, LL_MDMA, LL_OPAMP,LL_PWR, LL_RCC, LL_RNG, LL_RTC, LL_SPI, LL_SWPMI, LL_SYSTEM, LL_TIM, LL_USART, LL_UTILS, LL_WWDG</li>
@@ -3080,7 +3173,7 @@ <h2 id="main-changes-7">Main Changes</h2>
<li>Protect the hcd driver to be used only if the USB_OTG_FS, USB_OTG_HS are enabled</li>
</ul></li>
</ul>
-<h2 id="known-limitations-7">Known Limitations</h2>
+<h2 id="known-limitations-8">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -3088,7 +3181,7 @@ <h2 id="known-limitations-7">Known Limitations</h2>
<li>A new version of this driver will be available in next release with full features tested</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-7">Backward compatibility</h2>
+<h2 id="backward-compatibility-8">Backward compatibility</h2>
<ul>
<li><strong>HAL ADC</strong>:
<ul>
@@ -3127,7 +3220,8 @@ <h2 id="backward-compatibility-7">Backward compatibility</h2>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
-<h2 id="main-changes-8">Main Changes</h2>
+<div>
+<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li>Updates to fix known defects on HAL Cortex, HAL RCC and HAL SDMMC drivers</li>
<li><strong>HAL Cortex</strong>: Driver update to support 16 MPU regions instead of 8. User can now select an MPU regions from MPU_REGION_NUMBER0 to MPU_REGION_NUMBER15</li>
@@ -3135,18 +3229,22 @@ <h2 id="main-changes-8">Main Changes</h2>
<li><strong>HAL SDMMC</strong>: Fix and enhancements to support high speed mode</li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
-<h2 id="main-changes-9">Main Changes</h2>
+<div>
+<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL SPI</strong>: Driver reworked to fix critical issues</li>
<li>HAL: Update HAL Tick implementation</li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
-<h2 id="main-changes-10">Main Changes</h2>
+<div>
+<h2 id="main-changes-11">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL FLASH</strong>: Add Mass Erase for both banks</li>
@@ -3157,14 +3255,17 @@ <h2 id="main-changes-10">Main Changes</h2>
<li><strong>HAL SPDIFRX</strong>: Add symbol clock generation</li>
</ul>
</div>
+</div>
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
-<h2 id="main-changes-11">Main Changes</h2>
+<div>
+<h2 id="main-changes-12">Main Changes</h2>
<ul>
<li>First official release for STM32H743xx/753xx devices</li>
</ul>
</div>
-</section>
+</div>
+</div>
</div>
<footer class="sticky">
For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span>
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/Legacy/stm32h7xx_hal_eth.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/Legacy/stm32h7xx_hal_eth.c
new file mode 100644
index 0000000000..547b7e87a3
--- /dev/null
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/Legacy/stm32h7xx_hal_eth.c
@@ -0,0 +1,3028 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_eth.c
+ * @author MCD Application Team
+ * @brief ETH HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Ethernet (ETH) peripheral:
+ * + Initialization and deinitialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The ETH HAL driver can be used as follows:
+
+ (#)Declare a ETH_HandleTypeDef handle structure, for example:
+ ETH_HandleTypeDef heth;
+
+ (#)Fill parameters of Init structure in heth handle
+
+ (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
+
+ (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
+ (##) Enable the Ethernet interface clock using
+ (+++) __HAL_RCC_ETH1MAC_CLK_ENABLE()
+ (+++) __HAL_RCC_ETH1TX_CLK_ENABLE()
+ (+++) __HAL_RCC_ETH1RX_CLK_ENABLE()
+
+ (##) Initialize the related GPIO clocks
+ (##) Configure Ethernet pinout
+ (##) Configure Ethernet NVIC interrupt (in Interrupt mode)
+
+ (#) Ethernet data reception is asynchronous, so call the following API
+ to start the listening mode:
+ (##) HAL_ETH_Start():
+ This API starts the MAC and DMA transmission and reception process,
+ without enabling end of transfer interrupts, in this mode user
+ has to poll for data availability by calling HAL_ETH_IsRxDataAvailable()
+ (##) HAL_ETH_Start_IT():
+ This API starts the MAC and DMA transmission and reception process,
+ end of transfer interrupts are enabled in this mode,
+ HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received
+
+ (#) When data is received (HAL_ETH_IsRxDataAvailable() returns 1 or Rx interrupt
+ occurred), user can call the following APIs to get received data:
+ (##) HAL_ETH_GetRxDataBuffer(): Get buffer address of received frame
+ (##) HAL_ETH_GetRxDataLength(): Get received frame length
+ (##) HAL_ETH_GetRxDataInfo(): Get received frame additional info,
+ please refer to ETH_RxPacketInfo typedef structure
+
+ (#) For transmission path, two APIs are available:
+ (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
+ (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode,
+ HAL_ETH_TxCpltCallback() will be executed when end of transfer occur
+
+ (#) Communication with an external PHY device:
+ (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY
+ (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register
+
+ (#) Configure the Ethernet MAC after ETH peripheral initialization
+ (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef
+ (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef
+
+ (#) Configure the Ethernet DMA after ETH peripheral initialization
+ (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
+ (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef
+
+ -@- The PTP protocol offload APIs are not supported in this driver.
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
+
+ Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) DMAErrorCallback : DMA Error Callback.
+ (+) MACErrorCallback : MAC Error Callback.
+ (+) PMTCallback : Power Management Callback
+ (+) EEECallback : EEE Callback.
+ (+) WakeUpCallback : Wake UP Callback
+ (+) MspInitCallback : MspInit Callback.
+ (+) MspDeInitCallback: MspDeInit Callback.
+
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) DMAErrorCallback : DMA Error Callback.
+ (+) MACErrorCallback : MAC Error Callback.
+ (+) PMTCallback : Power Management Callback
+ (+) EEECallback : EEE Callback.
+ (+) WakeUpCallback : Wake UP Callback
+ (+) MspInitCallback : MspInit Callback.
+ (+) MspDeInitCallback: MspDeInit Callback.
+
+ By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
+ or HAL_ETH_Init function.
+
+ When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+ * @{
+ */
+#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
+
+#if defined(ETH)
+
+/** @defgroup ETH ETH
+ * @brief ETH HAL module driver
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup ETH_Private_Constants ETH Private Constants
+ * @{
+ */
+#define ETH_MACCR_MASK ((uint32_t)0xFFFB7F7CU)
+#define ETH_MACECR_MASK ((uint32_t)0x3F077FFFU)
+#define ETH_MACPFR_MASK ((uint32_t)0x800007FFU)
+#define ETH_MACWTR_MASK ((uint32_t)0x0000010FU)
+#define ETH_MACTFCR_MASK ((uint32_t)0xFFFF00F2U)
+#define ETH_MACRFCR_MASK ((uint32_t)0x00000003U)
+#define ETH_MTLTQOMR_MASK ((uint32_t)0x00000072U)
+#define ETH_MTLRQOMR_MASK ((uint32_t)0x0000007BU)
+
+#define ETH_DMAMR_MASK ((uint32_t)0x00007802U)
+#define ETH_DMASBMR_MASK ((uint32_t)0x0000D001U)
+#define ETH_DMACCR_MASK ((uint32_t)0x00013FFFU)
+#define ETH_DMACTCR_MASK ((uint32_t)0x003F1010U)
+#define ETH_DMACRCR_MASK ((uint32_t)0x803F0000U)
+#define ETH_MACPCSR_MASK (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \
+ ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \
+ ETH_MACPCSR_RWKPFE)
+
+/* Timeout values */
+#define ETH_SWRESET_TIMEOUT ((uint32_t)500U)
+#define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U)
+
+#define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \
+ ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\
+ ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE))
+
+#define ETH_MAC_US_TICK ((uint32_t)1000000U)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ETH_Private_Macros ETH Private Macros
+ * @{
+ */
+/* Helper macros for TX descriptor handling */
+#define INCR_TX_DESC_INDEX(inx, offset) do {\
+ (inx) += (offset);\
+ if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\
+ (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\
+} while (0)
+
+/* Helper macros for RX descriptor handling */
+#define INCR_RX_DESC_INDEX(inx, offset) do {\
+ (inx) += (offset);\
+ if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\
+ (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\
+} while (0)
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ETH_Private_Functions ETH Private Functions
+ * @{
+ */
+static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth);
+static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
+static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
+static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
+static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
+static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode);
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup ETH_Exported_Functions ETH Exported Functions
+ * @{
+ */
+
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the ETH peripheral:
+
+ (+) User must Implement HAL_ETH_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO and NVIC ).
+
+ (+) Call the function HAL_ETH_Init() to configure the selected device with
+ the selected configuration:
+ (++) MAC address
+ (++) Media interface (MII or RMII)
+ (++) Rx DMA Descriptors Tab
+ (++) Tx DMA Descriptors Tab
+ (++) Length of Rx Buffers
+
+ (+) Call the function HAL_ETH_DescAssignMemory() to assign data buffers
+ for each Rx DMA Descriptor
+
+ (+) Call the function HAL_ETH_DeInit() to restore the default configuration
+ of the selected ETH peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the Ethernet peripheral registers.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
+{
+ uint32_t tickstart;
+
+ if(heth == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+
+ if(heth->gState == HAL_ETH_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ heth->Lock = HAL_UNLOCKED;
+
+ ETH_InitCallbacksToDefault(heth);
+
+ if(heth->MspInitCallback == NULL)
+ {
+ heth->MspInitCallback = HAL_ETH_MspInit;
+ }
+
+ /* Init the low level hardware */
+ heth->MspInitCallback(heth);
+ }
+
+#else
+
+ /* Check the ETH peripheral state */
+ if(heth->gState == HAL_ETH_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK, NVIC. */
+ HAL_ETH_MspInit(heth);
+ }
+#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
+
+ heth->gState = HAL_ETH_STATE_BUSY;
+
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ if(heth->Init.MediaInterface == HAL_ETH_MII_MODE)
+ {
+ HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
+ }
+ else
+ {
+ HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
+ }
+
+ /* Ethernet Software reset */
+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
+ /* After reset all the registers holds their respective reset values */
+ SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for software reset */
+ while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
+ {
+ if(((HAL_GetTick() - tickstart ) > ETH_SWRESET_TIMEOUT))
+ {
+ /* Set Error Code */
+ heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
+ /* Set State as Error */
+ heth->gState = HAL_ETH_STATE_ERROR;
+ /* Return Error */
+ return HAL_ERROR;
+ }
+ }
+
+ /*------------------ MDIO CSR Clock Range Configuration --------------------*/
+ ETH_MAC_MDIO_ClkConfig(heth);
+
+ /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
+ WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U));
+
+ /*------------------ MAC, MTL and DMA default Configuration ----------------*/
+ ETH_MACDMAConfig(heth);
+
+ /* SET DSL to 64 bit */
+ MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT);
+
+ /* Set Receive Buffers Length (must be a multiple of 4) */
+ if ((heth->Init.RxBuffLen % 0x4U) != 0x0U)
+ {
+ /* Set Error Code */
+ heth->ErrorCode = HAL_ETH_ERROR_PARAM;
+ /* Set State as Error */
+ heth->gState = HAL_ETH_STATE_ERROR;
+ /* Return Error */
+ return HAL_ERROR;
+ }
+ else
+ {
+ MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1));
+ }
+
+ /*------------------ DMA Tx Descriptors Configuration ----------------------*/
+ ETH_DMATxDescListInit(heth);
+
+ /*------------------ DMA Rx Descriptors Configuration ----------------------*/
+ ETH_DMARxDescListInit(heth);
+
+ /*--------------------- ETHERNET MAC Address Configuration ------------------*/
+ /* Set MAC addr bits 32 to 47 */
+ heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]);
+ /* Set MAC addr bits 0 to 31 */
+ heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
+ ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
+
+ heth->ErrorCode = HAL_ETH_ERROR_NONE;
+ heth->gState = HAL_ETH_STATE_READY;
+ heth->RxState = HAL_ETH_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the ETH peripheral.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
+{
+ /* Set the ETH peripheral state to BUSY */
+ heth->gState = HAL_ETH_STATE_BUSY;
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+
+ if(heth->MspDeInitCallback == NULL)
+ {
+ heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ heth->MspDeInitCallback(heth);
+#else
+
+ /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
+ HAL_ETH_MspDeInit(heth);
+
+#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
+
+ /* Set ETH HAL state to Disabled */
+ heth->gState= HAL_ETH_STATE_RESET;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the ETH MSP.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes ETH MSP.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_MspDeInit could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User ETH Callback
+ * To be used instead of the weak predefined callback
+ * @param heth eth handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
+ * @arg @ref HAL_ETH_MAC_ERROR_CB_ID MAC Error Callback ID
+ * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID
+ * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID
+ * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID
+ * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ /* Update the error code */
+ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(heth);
+
+ if(heth->gState == HAL_ETH_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ETH_TX_COMPLETE_CB_ID :
+ heth->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_ETH_RX_COMPLETE_CB_ID :
+ heth->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_ETH_DMA_ERROR_CB_ID :
+ heth->DMAErrorCallback = pCallback;
+ break;
+
+ case HAL_ETH_MAC_ERROR_CB_ID :
+ heth->MACErrorCallback = pCallback;
+ break;
+
+ case HAL_ETH_PMT_CB_ID :
+ heth->PMTCallback = pCallback;
+ break;
+
+ case HAL_ETH_EEE_CB_ID :
+ heth->EEECallback = pCallback;
+ break;
+
+ case HAL_ETH_WAKEUP_CB_ID :
+ heth->WakeUpCallback = pCallback;
+ break;
+
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(heth->gState == HAL_ETH_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(heth);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an ETH Callback
+ * ETH callabck is redirected to the weak predefined callback
+ * @param heth eth handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
+ * @arg @ref HAL_ETH_MAC_ERROR_CB_ID MAC Error Callback ID
+ * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID
+ * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID
+ * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID
+ * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(heth);
+
+ if(heth->gState == HAL_ETH_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ETH_TX_COMPLETE_CB_ID :
+ heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
+ break;
+
+ case HAL_ETH_RX_COMPLETE_CB_ID :
+ heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
+ break;
+
+ case HAL_ETH_DMA_ERROR_CB_ID :
+ heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback;
+ break;
+
+ case HAL_ETH_MAC_ERROR_CB_ID :
+ heth->MACErrorCallback = HAL_ETH_MACErrorCallback;
+ break;
+
+ case HAL_ETH_PMT_CB_ID :
+ heth->PMTCallback = HAL_ETH_PMTCallback;
+ break;
+
+ case HAL_ETH_EEE_CB_ID :
+ heth->EEECallback = HAL_ETH_EEECallback;
+ break;
+
+ case HAL_ETH_WAKEUP_CB_ID :
+ heth->WakeUpCallback = HAL_ETH_WakeUpCallback;
+ break;
+
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = HAL_ETH_MspInit;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(heth->gState == HAL_ETH_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = HAL_ETH_MspInit;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(heth);
+
+ return status;
+}
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+ * @brief Assign memory buffers to a DMA Rx descriptor
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param Index : index of the DMA Rx descriptor
+ * this parameter can be a value from 0x0 to (ETH_RX_DESC_CNT -1)
+ * @param pBuffer1: address of buffer 1
+ * @param pBuffer2: address of buffer 2 if available
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1, uint8_t *pBuffer2)
+{
+ ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[Index];
+
+ if((pBuffer1 == NULL) || (Index >= (uint32_t)ETH_RX_DESC_CNT))
+ {
+ /* Set Error Code */
+ heth->ErrorCode = HAL_ETH_ERROR_PARAM;
+ /* Return Error */
+ return HAL_ERROR;
+ }
+
+ /* write buffer address to RDES0 */
+ WRITE_REG(dmarxdesc->DESC0, (uint32_t)pBuffer1);
+ /* store buffer address */
+ WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)pBuffer1);
+ /* set buffer address valid bit to RDES3 */
+ SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
+
+ if(pBuffer2 != NULL)
+ {
+ /* write buffer 2 address to RDES1 */
+ WRITE_REG(dmarxdesc->DESC2, (uint32_t)pBuffer2);
+ /* store buffer 2 address */
+ WRITE_REG(dmarxdesc->BackupAddr1, (uint32_t)pBuffer2);
+ /* set buffer 2 address valid bit to RDES3 */
+ SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
+ }
+ /* set OWN bit to RDES3 */
+ SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
+ * @brief ETH Transmit and Receive functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the ETH
+ data transfer.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables Ethernet MAC and DMA reception and transmission
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
+{
+ if(heth->gState == HAL_ETH_STATE_READY)
+ {
+ heth->gState = HAL_ETH_STATE_BUSY;
+
+ /* Enable the MAC transmission */
+ SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+ /* Enable the MAC reception */
+ SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
+ /* Set the Flush Transmit FIFO bit */
+ SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
+
+ /* Enable the DMA transmission */
+ SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
+
+ /* Enable the DMA reception */
+ SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
+
+ /* Clear Tx and Rx process stopped flags */
+ heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
+
+ heth->gState = HAL_ETH_STATE_READY;
+ heth->RxState = HAL_ETH_STATE_BUSY_RX;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enables Ethernet MAC and DMA reception/transmission in Interrupt mode
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
+{
+ uint32_t descindex;
+
+ ETH_DMADescTypeDef *dmarxdesc;
+
+ if(heth->gState == HAL_ETH_STATE_READY)
+ {
+ heth->gState = HAL_ETH_STATE_BUSY;
+
+ /* Set IOC bit to all Rx descriptors */
+ for(descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
+ {
+ dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
+ SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
+ }
+
+ /* save IT mode to ETH Handle */
+ heth->RxDescList.ItMode = 1U;
+
+ /* Enable the MAC transmission */
+ SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+ /* Enable the MAC reception */
+ SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
+ /* Set the Flush Transmit FIFO bit */
+ SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
+
+ /* Enable the DMA transmission */
+ SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
+
+ /* Enable the DMA reception */
+ SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
+
+ /* Clear Tx and Rx process stopped flags */
+ heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
+
+ /* Enable ETH DMA interrupts:
+ - Tx complete interrupt
+ - Rx complete interrupt
+ - Fatal bus interrupt
+ */
+ __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE |
+ ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
+
+ heth->gState = HAL_ETH_STATE_READY;
+ heth->RxState = HAL_ETH_STATE_BUSY_RX;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Stop Ethernet MAC and DMA reception/transmission
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
+{
+ if(heth->gState != HAL_ETH_STATE_RESET)
+ {
+ /* Set the ETH peripheral state to BUSY */
+ heth->gState = HAL_ETH_STATE_BUSY;
+
+ /* Disable the DMA transmission */
+ CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
+
+ /* Disable the DMA reception */
+ CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
+
+ /* Disable the MAC reception */
+ CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
+
+ /* Set the Flush Transmit FIFO bit */
+ SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
+
+ /* Disable the MAC transmission */
+ CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+ heth->gState = HAL_ETH_STATE_READY;
+ heth->RxState = HAL_ETH_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Stop Ethernet MAC and DMA reception/transmission in Interrupt mode
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
+{
+ ETH_DMADescTypeDef *dmarxdesc;
+ uint32_t descindex;
+
+ if(heth->gState != HAL_ETH_STATE_RESET)
+ {
+ /* Set the ETH peripheral state to BUSY */
+ heth->gState = HAL_ETH_STATE_BUSY;
+
+ /* Disable interrupts:
+ - Tx complete interrupt
+ - Rx complete interrupt
+ - Fatal bus interrupt
+ */
+ __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE |
+ ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
+
+ /* Disable the DMA transmission */
+ CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
+
+ /* Disable the DMA reception */
+ CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
+
+ /* Disable the MAC reception */
+ CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
+
+ /* Set the Flush Transmit FIFO bit */
+ SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
+
+ /* Disable the MAC transmission */
+ CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+ /* Clear IOC bit to all Rx descriptors */
+ for(descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
+ {
+ dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
+ CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
+ }
+
+ heth->RxDescList.ItMode = 0U;
+
+ heth->gState = HAL_ETH_STATE_READY;
+ heth->RxState = HAL_ETH_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Sends an Ethernet Packet in polling mode.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param pTxConfig: Hold the configuration of packet to be transmitted
+ * @param Timeout: timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ const ETH_DMADescTypeDef *dmatxdesc;
+
+ if(pTxConfig == NULL)
+ {
+ heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(heth->gState == HAL_ETH_STATE_READY)
+ {
+ /* Config DMA Tx descriptor by Tx Packet info */
+ if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)
+ {
+ /* Set the ETH error code */
+ heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+
+ dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc];
+
+ /* Incr current tx desc index */
+ INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
+
+ /* Start transmission */
+ /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
+ WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
+
+ tickstart = HAL_GetTick();
+
+ /* Wait for data to be transmitted or timeout occurred */
+ while((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
+ {
+ if((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)
+ {
+ heth->ErrorCode |= HAL_ETH_ERROR_DMA;
+ heth->DMAErrorCode = heth->Instance->DMACSR;
+ /* Set ETH HAL State to Ready */
+ heth->gState = HAL_ETH_STATE_ERROR;
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
+ {
+ heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
+ heth->gState = HAL_ETH_STATE_ERROR;
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Sends an Ethernet Packet in interrupt mode.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param pTxConfig: Hold the configuration of packet to be transmitted
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
+{
+ if(pTxConfig == NULL)
+ {
+ heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(heth->gState == HAL_ETH_STATE_READY)
+ {
+ /* Config DMA Tx descriptor by Tx Packet info */
+ if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
+ {
+ heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+
+ /* Incr current tx desc index */
+ INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
+
+ /* Start transmission */
+ /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
+ WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
+
+ return HAL_OK;
+
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Checks for received Packets.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval 1: A Packet is received
+ * 0: no Packet received
+ */
+uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth)
+{
+ ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
+ uint32_t descidx = dmarxdesclist->CurRxDesc;
+ ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ uint32_t descscancnt = 0;
+ uint32_t appdesccnt = 0, firstappdescidx = 0;
+
+ if(dmarxdesclist->AppDescNbr != 0U)
+ {
+ /* data already received by not yet processed*/
+ return 0;
+ }
+
+ /* Check if descriptor is not owned by DMA */
+ while((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (descscancnt < (uint32_t)ETH_RX_DESC_CNT))
+ {
+ descscancnt++;
+
+ /* Check if last descriptor */
+ if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
+ {
+ /* Increment the number of descriptors to be passed to the application */
+ appdesccnt += 1U;
+
+ if(appdesccnt == 1U)
+ {
+ WRITE_REG(firstappdescidx, descidx);
+ }
+
+ /* Increment current rx descriptor index */
+ INCR_RX_DESC_INDEX(descidx, 1U);
+
+ /* Check for Context descriptor */
+ /* Get current descriptor address */
+ dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+
+ if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET)
+ {
+ if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET)
+ {
+ /* Increment the number of descriptors to be passed to the application */
+ dmarxdesclist->AppContextDesc = 1;
+ /* Increment current rx descriptor index */
+ INCR_RX_DESC_INDEX(descidx, 1U);
+ }
+ }
+ /* Fill information to Rx descriptors list */
+ dmarxdesclist->CurRxDesc = descidx;
+ dmarxdesclist->FirstAppDesc = firstappdescidx;
+ dmarxdesclist->AppDescNbr = appdesccnt;
+
+ /* Return function status */
+ return 1;
+ }
+ /* Check if first descriptor */
+ else if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
+ {
+ WRITE_REG(firstappdescidx, descidx);
+ /* Increment the number of descriptors to be passed to the application */
+ appdesccnt = 1U;
+
+ /* Increment current rx descriptor index */
+ INCR_RX_DESC_INDEX(descidx, 1U);
+ /* Get current descriptor address */
+ dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ }
+ /* It should be an intermediate descriptor */
+ else
+ {
+ /* Increment the number of descriptors to be passed to the application */
+ appdesccnt += 1U;
+
+ /* Increment current rx descriptor index */
+ INCR_RX_DESC_INDEX(descidx, 1U);
+ /* Get current descriptor address */
+ dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ }
+ }
+
+ /* Build Descriptors if an incomplete Packet is received */
+ if(appdesccnt > 0U)
+ {
+ dmarxdesclist->CurRxDesc = descidx;
+ dmarxdesclist->FirstAppDesc = firstappdescidx;
+ descidx = firstappdescidx;
+ dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+
+ for(descscancnt = 0; descscancnt < appdesccnt; descscancnt++)
+ {
+ WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
+ WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
+
+ if (READ_REG(dmarxdesc->BackupAddr1) != ((uint32_t)RESET))
+ {
+ WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
+ SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
+ }
+
+ SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
+
+ if(dmarxdesclist->ItMode != ((uint32_t)RESET))
+ {
+ SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
+ }
+ if(descscancnt < (appdesccnt - 1U))
+ {
+ /* Increment rx descriptor index */
+ INCR_RX_DESC_INDEX(descidx, 1U);
+ /* Get descriptor address */
+ dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ }
+ }
+
+ /* Set the Tail pointer address to the last rx descriptor hold by the app */
+ WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
+ }
+
+ /* Fill information to Rx descriptors list: No received Packet */
+ dmarxdesclist->AppDescNbr = 0U;
+
+ return 0;
+}
+
+/**
+ * @brief This function gets the buffer address of last received Packet.
+ * @note Please insure to allocate the RxBuffer structure before calling this function
+ * how to use example:
+ * HAL_ETH_GetRxDataLength(heth, &Length);
+ * BuffersNbr = (Length / heth->Init.RxBuffLen) + 1;
+ * RxBuffer = (ETH_BufferTypeDef *)malloc(BuffersNbr * sizeof(ETH_BufferTypeDef));
+ * HAL_ETH_GetRxDataBuffer(heth, RxBuffer);
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param RxBuffer: Pointer to a ETH_BufferTypeDef structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer)
+{
+ ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
+ uint32_t descidx = dmarxdesclist->FirstAppDesc;
+ uint32_t index, accumulatedlen = 0, lastdesclen;
+ __IO const ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ ETH_BufferTypeDef *rxbuff = RxBuffer;
+
+ if(rxbuff == NULL)
+ {
+ heth->ErrorCode = HAL_ETH_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(dmarxdesclist->AppDescNbr == 0U)
+ {
+ if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
+ {
+ /* No data to be transferred to the application */
+ return HAL_ERROR;
+ }
+ else
+ {
+ descidx = dmarxdesclist->FirstAppDesc;
+ dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ }
+ }
+
+ /* Get intermediate descriptors buffers: in case of the Packet is split into multi descriptors */
+ for(index = 0; index < (dmarxdesclist->AppDescNbr - 1U); index++)
+ {
+ /* Get Address and length of the first buffer address */
+ rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
+ rxbuff->len = heth->Init.RxBuffLen;
+
+ /* Check if the second buffer address of this descriptor is valid */
+ if(dmarxdesc->BackupAddr1 != 0U)
+ {
+ /* Point to next buffer */
+ rxbuff = rxbuff->next;
+ /* Get Address and length of the second buffer address */
+ rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
+ rxbuff->len = heth->Init.RxBuffLen;
+ }
+ else
+ {
+ /* Nothing to do here */
+ }
+
+ /* get total length until this descriptor */
+ accumulatedlen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
+
+ /* Increment to next descriptor */
+ INCR_RX_DESC_INDEX(descidx, 1U);
+ dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+
+ /* Point to next buffer */
+ rxbuff = rxbuff->next;
+ }
+
+ /* last descriptor data length */
+ lastdesclen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - accumulatedlen;
+
+ /* Get Address of the first buffer address */
+ rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
+
+ /* data is in only one buffer */
+ if(lastdesclen <= heth->Init.RxBuffLen)
+ {
+ rxbuff->len = lastdesclen;
+ }
+ /* data is in two buffers */
+ else if(dmarxdesc->BackupAddr1 != 0U)
+ {
+ /* Get the Length of the first buffer address */
+ rxbuff->len = heth->Init.RxBuffLen;
+ /* Point to next buffer */
+ rxbuff = rxbuff->next;
+ /* Get the Address the Length of the second buffer address */
+ rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
+ rxbuff->len = lastdesclen - (heth->Init.RxBuffLen);
+ }
+ else /* Buffer 2 not valid*/
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function gets the length of last received Packet.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param Length: parameter to hold Rx packet length
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length)
+{
+ ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
+ uint32_t descidx = dmarxdesclist->FirstAppDesc;
+ __IO const ETH_DMADescTypeDef *dmarxdesc;
+
+ if(dmarxdesclist->AppDescNbr == 0U)
+ {
+ if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
+ {
+ /* No data to be transferred to the application */
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get index of last descriptor */
+ INCR_RX_DESC_INDEX(descidx, (dmarxdesclist->AppDescNbr - 1U));
+ /* Point to last descriptor */
+ dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+
+ *Length = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the Rx data info (Packet type, VLAN tag, Filters status, ...)
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param RxPacketInfo: parameter to hold info of received buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo)
+{
+ ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
+ uint32_t descidx = dmarxdesclist->FirstAppDesc;
+ __IO const ETH_DMADescTypeDef *dmarxdesc;
+
+ if(dmarxdesclist->AppDescNbr == 0U)
+ {
+ if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
+ {
+ /* No data to be transferred to the application */
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get index of last descriptor */
+ INCR_RX_DESC_INDEX(descidx, ((dmarxdesclist->AppDescNbr) - 1U));
+ /* Point to last descriptor */
+ dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+
+ if((dmarxdesc->DESC3 & ETH_DMARXNDESCWBF_ES) != (uint32_t)RESET)
+ {
+ RxPacketInfo->ErrorCode = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_ERRORS_MASK);
+ }
+ else
+ {
+ if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS0V) != 0U)
+ {
+
+ if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LT) == ETH_DMARXNDESCWBF_LT_DVLAN)
+ {
+ RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
+ RxPacketInfo->InnerVlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_IVT) >> 16;
+ }
+ else
+ {
+ RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
+ }
+ }
+
+ if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS1V) != 0U)
+ {
+ /* Get Payload type */
+ RxPacketInfo->PayloadType =READ_BIT( dmarxdesc->DESC1, ETH_DMARXNDESCWBF_PT);
+ /* Get Header type */
+ RxPacketInfo->HeaderType = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPV4 | ETH_DMARXNDESCWBF_IPV6));
+ /* Get Checksum status */
+ RxPacketInfo->Checksum = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPCE | ETH_DMARXNDESCWBF_IPCB | ETH_DMARXNDESCWBF_IPHE));
+ }
+
+ if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS2V) != 0U)
+ {
+ RxPacketInfo->MacFilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_HF | ETH_DMARXNDESCWBF_DAF | ETH_DMARXNDESCWBF_SAF | ETH_DMARXNDESCWBF_VF));
+ RxPacketInfo->L3FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM));
+ RxPacketInfo->L4FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM));
+ }
+ }
+
+ /* Get the segment count */
+ WRITE_REG(RxPacketInfo->SegmentCnt, dmarxdesclist->AppDescNbr);
+
+ return HAL_OK;
+}
+
+/**
+* @brief This function gives back Rx Desc of the last received Packet
+* to the DMA, so ETH DMA will be able to use these descriptors
+* to receive next Packets.
+* It should be called after processing the received Packet.
+* @param heth: pointer to a ETH_HandleTypeDef structure that contains
+* the configuration information for ETHERNET module
+* @retval HAL status.
+*/
+HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth)
+{
+ ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
+ uint32_t descindex = dmarxdesclist->FirstAppDesc;
+ __IO ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
+ uint32_t totalappdescnbr = dmarxdesclist->AppDescNbr;
+ uint32_t descscan;
+
+ if(dmarxdesclist->AppDescNbr == 0U)
+ {
+ /* No Rx descriptors to build */
+ return HAL_ERROR;
+ }
+
+ if(dmarxdesclist->AppContextDesc != 0U)
+ {
+ /* A context descriptor is available */
+ totalappdescnbr += 1U;
+ }
+
+ for(descscan =0; descscan < totalappdescnbr; descscan++)
+ {
+ WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
+ WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
+
+ if (READ_REG(dmarxdesc->BackupAddr1) != 0U)
+ {
+ WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
+ SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
+ }
+
+ SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
+
+ if(dmarxdesclist->ItMode != 0U)
+ {
+ SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
+ }
+
+ if(descscan < (totalappdescnbr - 1U))
+ {
+ /* Increment rx descriptor index */
+ INCR_RX_DESC_INDEX(descindex, 1U);
+ /* Get descriptor address */
+ dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
+ }
+ }
+
+ /* Set the Tail pointer address to the last rx descriptor hold by the app */
+ WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
+
+ /* reset the Application desc number */
+ WRITE_REG(dmarxdesclist->AppDescNbr, 0);
+
+ /* reset the application context descriptor */
+ WRITE_REG(heth->RxDescList.AppContextDesc, 0);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief This function handles ETH interrupt request.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
+{
+ /* Packet received */
+ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
+ {
+ if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
+ {
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /*Call registered Receive complete callback*/
+ heth->RxCpltCallback(heth);
+#else
+ /* Receive complete callback */
+ HAL_ETH_RxCpltCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+ /* Clear the Eth DMA Rx IT pending bits */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
+ }
+ }
+
+ /* Packet transmitted */
+ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI))
+ {
+ if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
+ {
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /*Call registered Transmit complete callback*/
+ heth->TxCpltCallback(heth);
+#else
+ /* Transfer complete callback */
+ HAL_ETH_TxCpltCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+ /* Clear the Eth DMA Tx IT pending bits */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
+ }
+ }
+
+
+ /* ETH DMA Error */
+ if(__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
+ {
+ if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
+ {
+ heth->ErrorCode |= HAL_ETH_ERROR_DMA;
+
+ /* if fatal bus error occurred */
+ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE))
+ {
+ /* Get DMA error code */
+ heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
+
+ /* Disable all interrupts */
+ __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
+
+ /* Set HAL state to ERROR */
+ heth->gState = HAL_ETH_STATE_ERROR;
+ }
+ else
+ {
+ /* Get DMA error status */
+ heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
+ ETH_DMACSR_RBU | ETH_DMACSR_AIS));
+
+ /* Clear the interrupt summary flag */
+ __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
+ ETH_DMACSR_RBU | ETH_DMACSR_AIS));
+ }
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /* Call registered DMA Error callback*/
+ heth->DMAErrorCallback(heth);
+#else
+ /* Ethernet DMA Error callback */
+ HAL_ETH_DMAErrorCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+ }
+ }
+
+ /* ETH MAC Error IT */
+ if(__HAL_ETH_MAC_GET_IT(heth, (ETH_MACIER_RXSTSIE | ETH_MACIER_TXSTSIE)))
+ {
+ /* Get MAC Rx Tx status and clear Status register pending bit */
+ heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
+
+ heth->gState = HAL_ETH_STATE_ERROR;
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /* Call registered MAC Error callback*/
+ heth->DMAErrorCallback(heth);
+#else
+ /* Ethernet MAC Error callback */
+ HAL_ETH_MACErrorCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+ heth->MACErrorCode = (uint32_t)(0x0U);
+ }
+
+ /* ETH PMT IT */
+ if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
+ {
+ /* Get MAC Wake-up source and clear the status register pending bit */
+ heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /* Call registered PMT callback*/
+ heth->PMTCallback(heth);
+#else
+ /* Ethernet PMT callback */
+ HAL_ETH_PMTCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+ heth->MACWakeUpEvent = (uint32_t)(0x0U);
+ }
+
+ /* ETH EEE IT */
+ if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
+ {
+ /* Get MAC LPI interrupt source and clear the status register pending bit */
+ heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU);
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /* Call registered EEE callback*/
+ heth->EEECallback(heth);
+#else
+ /* Ethernet EEE callback */
+ HAL_ETH_EEECallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+ heth->MACLPIEvent = (uint32_t)(0x0U);
+ }
+
+#if defined(DUAL_CORE)
+ if (HAL_GetCurrentCPUID() == CM7_CPUID)
+ {
+ /* check ETH WAKEUP exti flag */
+ if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+ {
+ /* Clear ETH WAKEUP Exti pending bit */
+ __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /* Call registered WakeUp callback*/
+ heth->WakeUpCallback(heth);
+#else
+ /* ETH WAKEUP callback */
+ HAL_ETH_WakeUpCallback(heth);
+#endif
+ }
+ }
+ else
+ {
+ /* check ETH WAKEUP exti flag */
+ if(__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+ {
+ /* Clear ETH WAKEUP Exti pending bit */
+ __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /* Call registered WakeUp callback*/
+ heth->WakeUpCallback(heth);
+#else
+ /* ETH WAKEUP callback */
+ HAL_ETH_WakeUpCallback(heth);
+#endif
+ }
+ }
+#else
+ /* check ETH WAKEUP exti flag */
+ if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+ {
+ /* Clear ETH WAKEUP Exti pending bit */
+ __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /* Call registered WakeUp callback*/
+ heth->WakeUpCallback(heth);
+#else
+ /* ETH WAKEUP callback */
+ HAL_ETH_WakeUpCallback(heth);
+#endif
+ }
+#endif
+}
+
+/**
+ * @brief Tx Transfer completed callbacks.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Ethernet DMA transfer error callbacks
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_DMAErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+* @brief Ethernet MAC transfer error callbacks
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_MACErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Ethernet Power Management module IT callback
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_PMTCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Energy Efficient Etherent IT callback
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_EEECallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief ETH WAKEUP interrupt callback
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_WakeUpCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Read a PHY register
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param PHYAddr: PHY port address, must be a value from 0 to 31
+ * @param PHYReg: PHY register address, must be a value from 0 to 31
+ * @param pRegValue: parameter to hold read value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
+{
+ uint32_t tmpreg, tickstart;
+
+ /* Check for the Busy flag */
+ if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get the MACMDIOAR value */
+ WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
+
+ /* Prepare the MDIO Address Register value
+ - Set the PHY device address
+ - Set the PHY register address
+ - Set the read mode
+ - Set the MII Busy bit */
+
+ MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
+ MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
+ MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD);
+ SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
+
+ /* Write the result value into the MDII Address register */
+ WRITE_REG(heth->Instance->MACMDIOAR, tmpreg);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait for the Busy flag */
+ while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
+ {
+ if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get MACMIIDR value */
+ WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Writes to a PHY register.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param PHYAddr: PHY port address, must be a value from 0 to 31
+ * @param PHYReg: PHY register address, must be a value from 0 to 31
+ * @param RegValue: the value to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
+{
+ uint32_t tmpreg, tickstart;
+
+ /* Check for the Busy flag */
+ if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get the MACMDIOAR value */
+ WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
+
+ /* Prepare the MDIO Address Register value
+ - Set the PHY device address
+ - Set the PHY register address
+ - Set the write mode
+ - Set the MII Busy bit */
+
+ MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
+ MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
+ MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
+ SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
+
+
+ /* Give the value to the MII data register */
+ WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue);
+
+ /* Write the result value into the MII Address register */
+ WRITE_REG(ETH->MACMDIOAR, tmpreg);
+
+ tickstart = HAL_GetTick();
+
+ /* Wait for the Busy flag */
+ while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
+ {
+ if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
+ * @brief ETH control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the ETH
+ peripheral.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Get the configuration of the MAC and MTL subsystems.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold
+ * the configuration of the MAC.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
+{
+ if (macconf == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get MAC parameters */
+ macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN);
+ macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC)>> 4) > 0U) ? ENABLE : DISABLE;
+ macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
+ macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE;
+ macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) ? ENABLE : DISABLE;
+ macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE;
+ macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE;
+ macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE;
+ macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
+ macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
+ macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE;
+ macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >>17) == 0U) ? ENABLE : DISABLE;
+ macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >>19) == 0U) ? ENABLE : DISABLE;
+ macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE;
+ macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE;
+ macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE;
+ macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE;
+ macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG);
+ macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE;
+ macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC);
+
+ macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL);
+ macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE;
+ macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE;
+ macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE;
+ macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) ? ENABLE : DISABLE;
+ macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
+
+
+ macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE;
+ macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
+
+ macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1) > 0U) ? ENABLE : DISABLE;
+ macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE;
+ macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT);
+ macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16);
+
+
+ macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE;
+ macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) ? ENABLE : DISABLE;
+
+ macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF));
+
+ macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF));
+ macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE;
+ macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE;
+ macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the configuration of the DMA.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
+ * the configuration of the ETH DMA.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
+{
+ if (dmaconf == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12) > 0U) ? ENABLE : DISABLE;
+ dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB);
+ dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB)>> 15) > 0U) ? ENABLE : DISABLE;
+
+ dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR |ETH_DMAMR_PR | ETH_DMAMR_DA));
+
+ dmaconf->PBLx8Mode = ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL)>> 16) > 0U) ? ENABLE : DISABLE;
+ dmaconf->MaximumSegmentSize = READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_MSS);
+
+ dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPF) >> 31) > 0U) ? ENABLE : DISABLE;
+ dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPBL);
+
+ dmaconf->SecondPacketOperate = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4) > 0U) ? ENABLE : DISABLE;
+ dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE;
+ dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the MAC configuration.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains
+ * the configuration of the MAC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
+{
+ if(macconf == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(heth->RxState == HAL_ETH_STATE_READY)
+ {
+ ETH_SetMACConfig(heth, macconf);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Set the ETH DMA configuration.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
+ * the configuration of the ETH DMA.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
+{
+ if(dmaconf == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(heth->RxState == HAL_ETH_STATE_READY)
+ {
+ ETH_SetDMAConfig(heth, dmaconf);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configures the Clock range of ETH MDIO interface.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
+{
+ uint32_t tmpreg, hclk;
+
+ /* Get the ETHERNET MACMDIOAR value */
+ tmpreg = (heth->Instance)->MACMDIOAR;
+
+ /* Clear CSR Clock Range bits */
+ tmpreg &= ~ETH_MACMDIOAR_CR;
+
+ /* Get hclk frequency value */
+ hclk = HAL_RCC_GetHCLKFreq();
+
+ /* Set CR bits depending on hclk value */
+ if((hclk >= 20000000U)&&(hclk < 35000000U))
+ {
+ /* CSR Clock Range between 20-35 MHz */
+ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
+ }
+ else if((hclk >= 35000000U)&&(hclk < 60000000U))
+ {
+ /* CSR Clock Range between 35-60 MHz */
+ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
+ }
+ else if((hclk >= 60000000U)&&(hclk < 100000000U))
+ {
+ /* CSR Clock Range between 60-100 MHz */
+ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
+ }
+ else if((hclk >= 100000000U)&&(hclk < 150000000U))
+ {
+ /* CSR Clock Range between 100-150 MHz */
+ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
+ }
+ else /* (hclk >= 150000000)&&(hclk <= 200000000) */
+ {
+ /* CSR Clock Range between 150-200 MHz */
+ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
+ }
+
+ /* Configure the CSR Clock Range */
+ (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
+}
+
+/**
+ * @brief Set the ETH MAC (L2) Filters configuration.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains
+ * the configuration of the ETH MAC filters.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
+{
+ uint32_t filterconfig;
+
+ if(pFilterConfig == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode |
+ ((uint32_t)pFilterConfig->HashUnicast << 1) |
+ ((uint32_t)pFilterConfig->HashMulticast << 2) |
+ ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
+ ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
+ ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) |
+ ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
+ ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
+ ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
+ ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
+ pFilterConfig->ControlPacketsFilter);
+
+ MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the ETH MAC (L2) Filters configuration.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold
+ * the configuration of the ETH MAC filters.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
+{
+ if(pFilterConfig == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR)) > 0U) ? ENABLE : DISABLE;
+ pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1) > 0U) ? ENABLE : DISABLE;
+ pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2) > 0U) ? ENABLE : DISABLE;
+ pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
+ pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE;
+ pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE;
+ pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF);
+ pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
+ pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE;
+ pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U) ? ENABLE : DISABLE;
+ pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31) > 0U) ? ENABLE : DISABLE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the source MAC Address to be matched.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param AddrNbr: The MAC address to configure
+ * This parameter must be a value of the following:
+ * ETH_MAC_ADDRESS1
+ * ETH_MAC_ADDRESS2
+ * ETH_MAC_ADDRESS3
+ * @param pMACAddr: Pointer to MAC address buffer data (6 bytes)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
+{
+ uint32_t macaddrhr, macaddrlr;
+
+ if(pMACAddr == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get mac addr high reg offset */
+ macaddrhr = ((uint32_t)&(heth->Instance->MACA0HR) + AddrNbr);
+ /* Get mac addr low reg offset */
+ macaddrlr = ((uint32_t)&(heth->Instance->MACA0LR) + AddrNbr);
+
+ /* Set MAC addr bits 32 to 47 */
+ (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]);
+ /* Set MAC addr bits 0 to 31 */
+ (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) |
+ ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]);
+
+ /* Enable address and set source address bit */
+ (*(__IO uint32_t *)macaddrhr) |= (ETH_MACAHR_SA | ETH_MACAHR_AE);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the ETH Hash Table Value.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param pHashTable: pointer to a table of two 32 bit values, that contains
+ * the 64 bits of the hash table.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable)
+{
+ if(pHashTable == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ heth->Instance->MACHT0R = pHashTable[0];
+ heth->Instance->MACHT1R = pHashTable[1];
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the VLAN Identifier for Rx packets
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param ComparisonBits: 12 or 16 bit comparison mode
+ must be a value of @ref ETH_VLAN_Tag_Comparison
+ * @param VLANIdentifier: VLAN Identifier value
+ * @retval None
+ */
+void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
+{
+ if(ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
+ {
+ MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL , VLANIdentifier);
+ CLEAR_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
+ }
+ else
+ {
+ MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID , VLANIdentifier);
+ SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
+ }
+}
+
+/**
+ * @brief Enters the Power down mode.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure
+ * that contains the Power Down configuration
+ * @retval None.
+ */
+void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
+{
+ uint32_t powerdownconfig;
+
+ powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) |
+ ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) |
+ ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) |
+ ((uint32_t)pPowerDownConfig->WakeUpForward << 10) |
+ ETH_MACPCSR_PWRDWN);
+
+ /* Enable PMT interrupt */
+ __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE);
+
+ MODIFY_REG(heth->Instance->MACPCSR, ETH_MACPCSR_MASK, powerdownconfig);
+}
+
+/**
+ * @brief Exits from the Power down mode.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None.
+ */
+void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth)
+{
+ /* clear wake up sources */
+ CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | ETH_MACPCSR_RWKPFE);
+
+ if(READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != 0U)
+ {
+ /* Exit power down mode */
+ CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN);
+ }
+
+ /* Disable PMT interrupt */
+ __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_PMTIE);
+}
+
+/**
+ * @brief Set the WakeUp filter.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param pFilter: pointer to filter registers values
+ * @param Count: number of filter registers, must be from 1 to 8.
+ * @retval None.
+ */
+HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
+{
+ uint32_t regindex;
+
+ if(pFilter == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Reset Filter Pointer */
+ SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST);
+
+ /* Wake up packet filter config */
+ for(regindex = 0; regindex < Count; regindex++)
+ {
+ /* Write filter regs */
+ WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief ETH State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of
+ ETH communication process, return Peripheral Errors occurred during communication
+ process
+
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the ETH state.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL state
+ */
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
+{
+ HAL_ETH_StateTypeDef ret;
+ HAL_ETH_StateTypeDef gstate = heth->gState;
+ HAL_ETH_StateTypeDef rxstate =heth->RxState;
+
+ ret = gstate;
+ ret |= rxstate;
+ return ret;
+}
+
+/**
+ * @brief Returns the ETH error code
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval ETH Error Code
+ */
+uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
+{
+ return heth->ErrorCode;
+}
+
+/**
+ * @brief Returns the ETH DMA error code
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval ETH DMA Error Code
+ */
+uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
+{
+ return heth->DMAErrorCode;
+}
+
+/**
+ * @brief Returns the ETH MAC error code
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval ETH MAC Error Code
+ */
+uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
+{
+ return heth->MACErrorCode;
+}
+
+/**
+ * @brief Returns the ETH MAC WakeUp event source
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval ETH MAC WakeUp event source
+ */
+uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
+{
+ return heth->MACWakeUpEvent;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ETH_Private_Functions ETH Private Functions
+ * @{
+ */
+
+static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
+{
+ uint32_t macregval;
+
+ /*------------------------ MACCR Configuration --------------------*/
+ macregval =(macconf->InterPacketGapVal |
+ macconf->SourceAddrControl |
+ ((uint32_t)macconf->ChecksumOffload<< 27) |
+ ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
+ ((uint32_t)macconf->Support2KPacket << 22) |
+ ((uint32_t)macconf->CRCStripTypePacket << 21) |
+ ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
+ ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
+ ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
+ ((uint32_t)macconf->JumboPacket << 16) |
+ macconf->Speed |
+ macconf->DuplexMode |
+ ((uint32_t)macconf->LoopbackMode << 12) |
+ ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11)|
+ ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10)|
+ ((uint32_t)macconf->CarrierSenseDuringTransmit << 9)|
+ ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8)|
+ macconf->BackOffLimit |
+ ((uint32_t)macconf->DeferralCheck << 4)|
+ macconf->PreambleLength);
+
+ /* Write to MACCR */
+ MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
+
+ /*------------------------ MACECR Configuration --------------------*/
+ macregval = ((macconf->ExtendedInterPacketGapVal << 25)|
+ ((uint32_t)macconf->ExtendedInterPacketGap << 24)|
+ ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18)|
+ ((uint32_t)macconf->SlowProtocolDetect << 17)|
+ ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U)<< 16) |
+ macconf->GiantPacketSizeLimit);
+
+ /* Write to MACECR */
+ MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
+
+ /*------------------------ MACWTR Configuration --------------------*/
+ macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) |
+ macconf->WatchdogTimeout);
+
+ /* Write to MACWTR */
+ MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval);
+
+ /*------------------------ MACTFCR Configuration --------------------*/
+ macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
+ macconf->PauseLowThreshold |
+ ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U)<< 7) |
+ (macconf->PauseTime << 16));
+
+ /* Write to MACTFCR */
+ MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval);
+
+ /*------------------------ MACRFCR Configuration --------------------*/
+ macregval = ((uint32_t)macconf->ReceiveFlowControl |
+ ((uint32_t)macconf->UnicastPausePacketDetect << 1));
+
+ /* Write to MACRFCR */
+ MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval);
+
+ /*------------------------ MTLTQOMR Configuration --------------------*/
+ /* Write to MTLTQOMR */
+ MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode);
+
+ /*------------------------ MTLRQOMR Configuration --------------------*/
+ macregval = (macconf->ReceiveQueueMode |
+ ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
+ ((uint32_t)macconf->ForwardRxErrorPacket << 4) |
+ ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3));
+
+ /* Write to MTLRQOMR */
+ MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
+}
+
+static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
+{
+ uint32_t dmaregval;
+
+ /*------------------------ DMAMR Configuration --------------------*/
+ MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration);
+
+ /*------------------------ DMASBMR Configuration --------------------*/
+ dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
+ dmaconf->BurstMode |
+ ((uint32_t)dmaconf->RebuildINCRxBurst << 15));
+
+ MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
+
+ /*------------------------ DMACCR Configuration --------------------*/
+ dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
+ dmaconf->MaximumSegmentSize);
+
+ MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
+
+ /*------------------------ DMACTCR Configuration --------------------*/
+ dmaregval = (dmaconf->TxDMABurstLength |
+ ((uint32_t)dmaconf->SecondPacketOperate << 4)|
+ ((uint32_t)dmaconf->TCPSegmentation << 12));
+
+ MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval);
+
+ /*------------------------ DMACRCR Configuration --------------------*/
+ dmaregval = (((uint32_t)dmaconf->FlushRxPacket << 31) |
+ dmaconf->RxDMABurstLength);
+
+ /* Write to DMACRCR */
+ MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval);
+}
+
+/**
+ * @brief Configures Ethernet MAC and DMA with default parameters.
+ * called by HAL_ETH_Init() API.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
+{
+ ETH_MACConfigTypeDef macDefaultConf;
+ ETH_DMAConfigTypeDef dmaDefaultConf;
+
+ /*--------------- ETHERNET MAC registers default Configuration --------------*/
+ macDefaultConf.AutomaticPadCRCStrip = ENABLE;
+ macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
+ macDefaultConf.CarrierSenseBeforeTransmit = DISABLE;
+ macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
+ macDefaultConf.ChecksumOffload = ENABLE;
+ macDefaultConf.CRCCheckingRxPackets = ENABLE;
+ macDefaultConf.CRCStripTypePacket = ENABLE;
+ macDefaultConf.DeferralCheck = DISABLE;
+ macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
+ macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
+ macDefaultConf.ExtendedInterPacketGap = DISABLE;
+ macDefaultConf.ExtendedInterPacketGapVal = 0x0;
+ macDefaultConf.ForwardRxErrorPacket = DISABLE;
+ macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
+ macDefaultConf.GiantPacketSizeLimit = 0x618;
+ macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
+ macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
+ macDefaultConf.Jabber = ENABLE;
+ macDefaultConf.JumboPacket = DISABLE;
+ macDefaultConf.LoopbackMode = DISABLE;
+ macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
+ macDefaultConf.PauseTime = 0x0;
+ macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
+ macDefaultConf.ProgrammableWatchdog = DISABLE;
+ macDefaultConf.ReceiveFlowControl = DISABLE;
+ macDefaultConf.ReceiveOwn = ENABLE;
+ macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD;
+ macDefaultConf.RetryTransmission = ENABLE;
+ macDefaultConf.SlowProtocolDetect = DISABLE;
+ macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0;
+ macDefaultConf.Speed = ETH_SPEED_100M;
+ macDefaultConf.Support2KPacket = DISABLE;
+ macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD;
+ macDefaultConf.TransmitFlowControl = DISABLE;
+ macDefaultConf.UnicastPausePacketDetect = DISABLE;
+ macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE;
+ macDefaultConf.Watchdog = ENABLE;
+ macDefaultConf.WatchdogTimeout = ETH_MACWTR_WTO_2KB;
+ macDefaultConf.ZeroQuantaPause = ENABLE;
+
+ /* MAC default configuration */
+ ETH_SetMACConfig(heth, &macDefaultConf);
+
+ /*--------------- ETHERNET DMA registers default Configuration --------------*/
+ dmaDefaultConf.AddressAlignedBeats = ENABLE;
+ dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
+ dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1;
+ dmaDefaultConf.FlushRxPacket = DISABLE;
+ dmaDefaultConf.PBLx8Mode = DISABLE;
+ dmaDefaultConf.RebuildINCRxBurst = DISABLE;
+ dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
+ dmaDefaultConf.SecondPacketOperate = DISABLE;
+ dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
+ dmaDefaultConf.TCPSegmentation = DISABLE;
+ dmaDefaultConf.MaximumSegmentSize = 536;
+
+ /* DMA default configuration */
+ ETH_SetDMAConfig(heth, &dmaDefaultConf);
+}
+
+/**
+ * @brief Configures the Clock range of SMI interface.
+ * called by HAL_ETH_Init() API.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth)
+{
+ uint32_t tmpreg, hclk;
+
+ /* Get the ETHERNET MACMDIOAR value */
+ tmpreg = (heth->Instance)->MACMDIOAR;
+
+ /* Clear CSR Clock Range bits */
+ tmpreg &= ~ETH_MACMDIOAR_CR;
+
+ /* Get hclk frequency value */
+ hclk = HAL_RCC_GetHCLKFreq();
+
+ /* Set CR bits depending on hclk value */
+ if((hclk >= 20000000U)&&(hclk < 35000000U))
+ {
+ /* CSR Clock Range between 20-35 MHz */
+ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
+ }
+ else if((hclk >= 35000000U)&&(hclk < 60000000U))
+ {
+ /* CSR Clock Range between 35-60 MHz */
+ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
+ }
+ else if((hclk >= 60000000U)&&(hclk < 100000000U))
+ {
+ /* CSR Clock Range between 60-100 MHz */
+ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
+ }
+ else if((hclk >= 100000000U)&&(hclk < 150000000U))
+ {
+ /* CSR Clock Range between 100-150 MHz */
+ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
+ }
+ else /* (hclk >= 150000000)&&(hclk <= 200000000) */
+ {
+ /* CSR Clock Range between 150-200 MHz */
+ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
+ }
+
+ /* Configure the CSR Clock Range */
+ (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
+}
+
+/**
+ * @brief Initializes the DMA Tx descriptors.
+ * called by HAL_ETH_Init() API.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
+{
+ ETH_DMADescTypeDef *dmatxdesc;
+ uint32_t i;
+
+ /* Fill each DMATxDesc descriptor with the right values */
+ for(i=0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
+ {
+ dmatxdesc = heth->Init.TxDesc + i;
+
+ WRITE_REG(dmatxdesc->DESC0, 0x0);
+ WRITE_REG(dmatxdesc->DESC1, 0x0);
+ WRITE_REG(dmatxdesc->DESC2, 0x0);
+ WRITE_REG(dmatxdesc->DESC3, 0x0);
+
+ WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
+ }
+
+ heth->TxDescList.CurTxDesc = 0;
+
+ /* Set Transmit Descriptor Ring Length */
+ WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT -1));
+
+ /* Set Transmit Descriptor List Address */
+ WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
+
+ /* Set Transmit Descriptor Tail pointer */
+ WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc);
+}
+
+/**
+ * @brief Initializes the DMA Rx descriptors in chain mode.
+ * called by HAL_ETH_Init() API.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
+{
+ ETH_DMADescTypeDef *dmarxdesc;
+ uint32_t i;
+
+ for(i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
+ {
+ dmarxdesc = heth->Init.RxDesc + i;
+
+ WRITE_REG(dmarxdesc->DESC0, 0x0);
+ WRITE_REG(dmarxdesc->DESC1, 0x0);
+ WRITE_REG(dmarxdesc->DESC2, 0x0);
+ WRITE_REG(dmarxdesc->DESC3, 0x0);
+ WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
+ WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
+
+ /* Set Rx descritors addresses */
+ WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
+ }
+
+ WRITE_REG(heth->RxDescList.CurRxDesc, 0);
+ WRITE_REG(heth->RxDescList.FirstAppDesc, 0);
+ WRITE_REG(heth->RxDescList.AppDescNbr, 0);
+ WRITE_REG(heth->RxDescList.ItMode, 0);
+ WRITE_REG(heth->RxDescList.AppContextDesc, 0);
+
+ /* Set Receive Descriptor Ring Length */
+ WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1)));
+
+ /* Set Receive Descriptor List Address */
+ WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
+
+ /* Set Receive Descriptor Tail pointer Address */
+ WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1))));
+}
+
+/**
+ * @brief Prepare Tx DMA descriptor before transmission.
+ * called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param pTxConfig: Tx packet configuration
+ * @param ItMode: Enable or disable Tx EOT interrept
+ * @retval Status
+ */
+static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
+{
+ ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
+ uint32_t descidx = dmatxdesclist->CurTxDesc;
+ uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
+ uint32_t descnbr = 0, idx;
+ ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+ ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer;
+ uint32_t bd_count = 0;
+
+ /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
+ if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL))
+ {
+ return HAL_ETH_ERROR_BUSY;
+ }
+
+ /***************************************************************************/
+ /***************** Context descriptor configuration (Optional) **********/
+ /***************************************************************************/
+ /* If VLAN tag is enabled for this packet */
+ if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
+ {
+ /* Set vlan tag value */
+ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);
+ /* Set vlan tag valid bit */
+ SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV);
+ /* Set the descriptor as the vlan input source */
+ SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
+
+ /* if inner VLAN is enabled */
+ if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != 0U)
+ {
+ /* Set inner vlan tag value */
+ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));
+ /* Set inner vlan tag valid bit */
+ SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV);
+
+ /* Set Vlan Tag control */
+ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl);
+
+ /* Set the descriptor as the inner vlan input source */
+ SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI);
+ /* Enable double VLAN processing */
+ SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
+ }
+ }
+
+ /* if tcp segmentation is enabled for this packet */
+ if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
+ {
+ /* Set MSS value */
+ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);
+ /* Set MSS valid bit */
+ SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);
+ }
+
+ if((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)|| (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U))
+ {
+ /* Set as context descriptor */
+ SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);
+ /* Set own bit */
+ SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
+ /* Increment current tx descriptor index */
+ INCR_TX_DESC_INDEX(descidx, 1U);
+ /* Get current descriptor address */
+ dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+ descnbr += 1U;
+
+ /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
+ if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
+ {
+ dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
+ /* Clear own bit */
+ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
+
+ return HAL_ETH_ERROR_BUSY;
+ }
+ }
+
+ /***************************************************************************/
+ /***************** Normal descriptors configuration *****************/
+ /***************************************************************************/
+
+ descnbr += 1U;
+
+ /* Set header or buffer 1 address */
+ WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
+ /* Set header or buffer 1 Length */
+ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
+
+ if(txbuffer->next != NULL)
+ {
+ txbuffer = txbuffer->next;
+ /* Set buffer 2 address */
+ WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
+ /* Set buffer 2 Length */
+ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
+ }
+ else
+ {
+ WRITE_REG(dmatxdesc->DESC1, 0x0);
+ /* Set buffer 2 Length */
+ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
+ }
+
+ if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
+ {
+ /* Set TCP Header length */
+ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));
+ /* Set TCP payload length */
+ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
+ /* Set TCP Segmentation Enabled bit */
+ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
+ }
+ else
+ {
+ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
+
+ if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
+ {
+ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
+ }
+
+ if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U)
+ {
+ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);
+ }
+ }
+
+ if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
+ {
+ /* Set Vlan Tag control */
+ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);
+ }
+
+ /* Mark it as First Descriptor */
+ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
+ /* Mark it as NORMAL descriptor */
+ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
+ /* set OWN bit of FIRST descriptor */
+ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
+
+ /* If source address insertion/replacement is enabled for this packet */
+ if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != 0U)
+ {
+ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
+ }
+
+ /* only if the packet is split into more than one descriptors > 1 */
+ while (txbuffer->next != NULL)
+ {
+ /* Clear the LD bit of previous descriptor */
+ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
+ /* Increment current tx descriptor index */
+ INCR_TX_DESC_INDEX(descidx, 1U);
+ /* Get current descriptor address */
+ dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+ /* Clear the FD bit of new Descriptor */
+ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
+
+ /* Current Tx Descriptor Owned by DMA: cannot be used by the application */
+ if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL))
+ {
+ descidx = firstdescidx;
+ dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+ /* clear previous desc own bit */
+ for(idx = 0; idx < descnbr; idx ++)
+ {
+ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
+
+ /* Increment current tx descriptor index */
+ INCR_TX_DESC_INDEX(descidx, 1U);
+ /* Get current descriptor address */
+ dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+ }
+
+ return HAL_ETH_ERROR_BUSY;
+ }
+
+ descnbr += 1U;
+
+ /* Get the next Tx buffer in the list */
+ txbuffer = txbuffer->next;
+
+ /* Set header or buffer 1 address */
+ WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
+ /* Set header or buffer 1 Length */
+ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
+
+ if (txbuffer->next != NULL)
+ {
+ /* Get the next Tx buffer in the list */
+ txbuffer = txbuffer->next;
+ /* Set buffer 2 address */
+ WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
+ /* Set buffer 2 Length */
+ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
+ }
+ else
+ {
+ WRITE_REG(dmatxdesc->DESC1, 0x0);
+ /* Set buffer 2 Length */
+ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
+ }
+
+ if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
+ {
+ /* Set TCP payload length */
+ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
+ /* Set TCP Segmentation Enabled bit */
+ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
+ }
+ else
+ {
+ /* Set the packet length */
+ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
+
+ if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
+ {
+ /* Checksum Insertion Control */
+ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
+ }
+ }
+
+ bd_count += 1U;
+ /* Set Own bit */
+ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
+ /* Mark it as NORMAL descriptor */
+ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
+ }
+
+ if(ItMode != ((uint32_t)RESET))
+ {
+ /* Set Interrupt on completion bit */
+ SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
+ }
+ else
+ {
+ /* Clear Interrupt on completion bit */
+ CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
+ }
+
+ /* Mark it as LAST descriptor */
+ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
+ /* Save the current packet address to expose it to the application */
+ dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress;
+
+ dmatxdesclist->CurTxDesc = descidx;
+
+ /* disable the interrupt */
+ __disable_irq();
+
+ dmatxdesclist->BuffersInUse += bd_count + 1U;
+
+ /* Enable interrupts back */
+ __enable_irq();
+
+
+ /* Return function status */
+ return HAL_ETH_ERROR_NONE;
+}
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
+{
+ /* Init the ETH Callback settings */
+ heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback; /* Legacy weak DMAErrorCallback */
+ heth->MACErrorCallback = HAL_ETH_MACErrorCallback; /* Legacy weak MACErrorCallback */
+ heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */
+ heth->EEECallback = HAL_ETH_EEECallback; /* Legacy weak EEECallback */
+ heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */
+}
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ETH */
+
+#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/Legacy/stm32h7xx_hal_eth_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/Legacy/stm32h7xx_hal_eth_ex.c
new file mode 100644
index 0000000000..52ccb9de42
--- /dev/null
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/Legacy/stm32h7xx_hal_eth_ex.c
@@ -0,0 +1,556 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_eth_ex.c
+ * @author MCD Application Team
+ * @brief ETH HAL Extended module driver.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+ * @{
+ */
+
+#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
+
+#if defined(ETH)
+
+/** @defgroup ETHEx ETHEx
+ * @brief ETH HAL Extended module driver
+ * @{
+ */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup ETHEx_Private_Constants ETHEx Private Constants
+ * @{
+ */
+#define ETH_MACL4CR_MASK (ETH_MACL3L4CR_L4PEN | ETH_MACL3L4CR_L4SPM | \
+ ETH_MACL3L4CR_L4SPIM | ETH_MACL3L4CR_L4DPM | \
+ ETH_MACL3L4CR_L4DPIM)
+
+#define ETH_MACL3CR_MASK (ETH_MACL3L4CR_L3PEN | ETH_MACL3L4CR_L3SAM | \
+ ETH_MACL3L4CR_L3SAIM | ETH_MACL3L4CR_L3DAM | \
+ ETH_MACL3L4CR_L3DAIM | ETH_MACL3L4CR_L3HSBM | \
+ ETH_MACL3L4CR_L3HDBM)
+
+#define ETH_MACRXVLAN_MASK (ETH_MACVTR_EIVLRXS | ETH_MACVTR_EIVLS | \
+ ETH_MACVTR_ERIVLT | ETH_MACVTR_EDVLP | \
+ ETH_MACVTR_VTHM | ETH_MACVTR_EVLRXS | \
+ ETH_MACVTR_EVLS | ETH_MACVTR_DOVLTC | \
+ ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL | \
+ ETH_MACVTR_VTIM | ETH_MACVTR_ETV)
+
+#define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
+ ETH_MACVIR_VLP | ETH_MACVIR_VLC)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup ETHEx_Exported_Functions ETH Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure ARP offload module
+ (+) Configure L3 and L4 filters
+ (+) Configure Extended VLAN features
+ (+) Configure Energy Efficient Ethernet module
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables ARP Offload.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
+{
+ SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
+}
+
+/**
+ * @brief Disables ARP Offload.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth)
+{
+ CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
+}
+
+/**
+ * @brief Set the ARP Match IP address
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param IpAddress: IP Address to be matched for incoming ARP requests
+ * @retval None
+ */
+void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
+{
+ WRITE_REG(heth->Instance->MACARPAR, IpAddress);
+}
+
+/**
+ * @brief Configures the L4 Filter, this function allow to:
+ * set the layer 4 protocol to be matched (TCP or UDP)
+ * enable/disable L4 source/destination port perfect/inverse match.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param Filter: L4 filter to configured, this parameter must be one of the following
+ * ETH_L4_FILTER_0
+ * ETH_L4_FILTER_1
+ * @param pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
+ * that contains L4 filter configuration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter , ETH_L4FilterConfigTypeDef *pL4FilterConfig)
+{
+ __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
+
+ if(pL4FilterConfig == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Write configuration to (MACL3L4C0R + filter )register */
+ MODIFY_REG(*configreg, ETH_MACL4CR_MASK ,(pL4FilterConfig->Protocol |
+ pL4FilterConfig->SrcPortFilterMatch |
+ pL4FilterConfig->DestPortFilterMatch));
+
+ configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
+
+ /* Write configuration to (MACL4A0R + filter )register */
+ MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP) , (pL4FilterConfig->SourcePort |
+ (pL4FilterConfig->DestinationPort << 16)));
+
+ /* Enable L4 filter */
+ SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the L4 Filter, this function allow to:
+ * set the layer 4 protocol to be matched (TCP or UDP)
+ * enable/disable L4 source/destination port perfect/inverse match.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param Filter: L4 filter to configured, this parameter must be one of the following
+ * ETH_L4_FILTER_0
+ * ETH_L4_FILTER_1
+ * @param pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
+ * that contains L4 filter configuration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
+{
+ if(pL4FilterConfig == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Get configuration to (MACL3L4C0R + filter )register */
+ pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L4PEN);
+ pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
+ pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
+
+ /* Get configuration to (MACL3L4C0R + filter )register */
+ pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4DP) >> 16);
+ pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the L3 Filter, this function allow to:
+ * set the layer 3 protocol to be matched (IPv4 or IPv6)
+ * enable/disable L3 source/destination port perfect/inverse match.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param Filter: L3 filter to configured, this parameter must be one of the following
+ * ETH_L3_FILTER_0
+ * ETH_L3_FILTER_1
+ * @param pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
+ * that contains L3 filter configuration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
+{
+ __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
+
+ if(pL3FilterConfig == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Write configuration to (MACL3L4C0R + filter )register */
+ MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
+ pL3FilterConfig->SrcAddrFilterMatch |
+ pL3FilterConfig->DestAddrFilterMatch |
+ (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
+ (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
+
+ /* Check if IPv6 protocol is selected */
+ if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+ {
+ /* Set the IPv6 address match */
+ /* Set Bits[31:0] of 128-bit IP addr */
+ *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0];
+ /* Set Bits[63:32] of 128-bit IP addr */
+ *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1];
+ /* update Bits[95:64] of 128-bit IP addr */
+ *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2];
+ /* update Bits[127:96] of 128-bit IP addr */
+ *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3];
+ }
+ else /* IPv4 protocol is selected */
+ {
+ /* Set the IPv4 source address match */
+ *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr;
+ /* Set the IPv4 destination address match */
+ *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the L3 Filter, this function allow to:
+ * set the layer 3 protocol to be matched (IPv4 or IPv6)
+ * enable/disable L3 source/destination port perfect/inverse match.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param Filter: L3 filter to configured, this parameter must be one of the following
+ * ETH_L3_FILTER_0
+ * ETH_L3_FILTER_1
+ * @param pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
+ * that will contain the L3 filter configuration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
+{
+ if(pL3FilterConfig == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3PEN);
+ pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
+ pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
+ pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HSBM) >> 6);
+ pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HDBM) >> 11);
+
+ if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+ {
+ pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
+ pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
+ pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter));
+ pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter));
+ }
+ else
+ {
+ pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
+ pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables L3 and L4 filtering process.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None.
+ */
+void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth)
+{
+ /* Enable L3/L4 filter */
+ SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
+}
+
+/**
+ * @brief Disables L3 and L4 filtering process.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None.
+ */
+void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
+{
+ /* Disable L3/L4 filter */
+ CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
+}
+
+/**
+ * @brief Get the VLAN Configuration for Receive Packets.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
+ * that will contain the VLAN filter configuration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
+{
+ if(pVlanConfig == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->StripInnerVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
+ pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
+ pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
+ pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U) ? DISABLE : ENABLE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the VLAN Configuration for Receive Packets.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
+ * that contains VLAN filter configuration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
+{
+ if(pVlanConfig == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Write config to MACVTR */
+ MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) |
+ pVlanConfig->StripInnerVLANTag |
+ ((uint32_t)pVlanConfig->InnerVLANTag << 27) |
+ ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
+ ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
+ ((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
+ pVlanConfig->StripVLANTag |
+ pVlanConfig->VLANTypeCheck |
+ ((uint32_t)pVlanConfig->VLANTagInverceMatch << 17)));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the VLAN Hash Table
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param VLANHashTable: VLAN hash table 16 bit value
+ * @retval None
+ */
+void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
+{
+ MODIFY_REG(heth->Instance->MACVHTR, ETH_MACVHTR_VLHT, VLANHashTable);
+}
+
+/**
+ * @brief Get the VLAN Configuration for Transmit Packets.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param VLANTag: Selects the vlan tag, this parameter must be one of the following
+ * ETH_OUTER_TX_VLANTAG
+ * ETH_INNER_TX_VLANTAG
+ * @param pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
+ * that will contain the Tx VLAN filter configuration.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
+{
+ if (pVlanConfig == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(VLANTag == ETH_INNER_TX_VLANTAG)
+ {
+ pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACIVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
+ }
+ else
+ {
+ pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
+ }
+
+ return HAL_OK;;
+}
+
+/**
+ * @brief Set the VLAN Configuration for Transmit Packets.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param VLANTag: Selects the vlan tag, this parameter must be one of the following
+ * ETH_OUTER_TX_VLANTAG
+ * ETH_INNER_TX_VLANTAG
+ * @param pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
+ * that contains Tx VLAN filter configuration.
+ * @retval HAL Status
+ */
+HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
+{
+ if(VLANTag == ETH_INNER_TX_VLANTAG)
+ {
+ MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
+ ((uint32_t)pVlanConfig->SVLANType << 19) |
+ pVlanConfig->VLANTagControl));
+ /* Enable Double VLAN processing */
+ SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
+ }
+ else
+ {
+ MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
+ ((uint32_t)pVlanConfig->SVLANType << 19) |
+ pVlanConfig->VLANTagControl));
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the VLAN Tag Identifier for Transmit Packets.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param VLANTag: Selects the vlan tag, this parameter must be one of the following
+ * ETH_OUTER_TX_VLANTAG
+ * ETH_INNER_TX_VLANTAG
+ * @param VLANIdentifier: VLAN Identifier 16 bit value
+ * @retval None
+ */
+void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier)
+{
+ if(VLANTag == ETH_INNER_TX_VLANTAG)
+ {
+ MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier);
+ }
+ else
+ {
+ MODIFY_REG(heth->Instance->MACVIR, ETH_MACVIR_VLT, VLANIdentifier);
+ }
+}
+
+/**
+ * @brief Enables the VLAN Tag Filtering process.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None.
+ */
+void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth)
+{
+ /* Enable VLAN processing */
+ SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
+}
+
+/**
+ * @brief Disables the VLAN Tag Filtering process.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None.
+ */
+void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth)
+{
+ /* Disable VLAN processing */
+ CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
+}
+
+/**
+ * @brief Enters the Low Power Idle (LPI) mode
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param TxAutomate: Enable/Disable automate enter/exit LPI mode.
+ * @param TxClockStop: Enable/Disable Tx clock stop in LPI mode.
+ * @retval None
+ */
+void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
+{
+ /* Enable LPI Interrupts */
+ __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE);
+
+ /* Write to LPI Control register: Enter low power mode */
+ MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), (((uint32_t)TxAutomate << 19) |
+ ((uint32_t)TxClockStop << 21) |
+ ETH_MACLCSR_LPIEN));
+}
+
+/**
+ * @brief Exits the Low Power Idle (LPI) mode.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval None
+ */
+void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
+{
+ /* Clear the LPI Config and exit low power mode */
+ CLEAR_BIT(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE));
+
+ /* Enable LPI Interrupts */
+ __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
+}
+
+
+/**
+ * @brief Returns the ETH MAC LPI event
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval ETH MAC WakeUp event
+ */
+uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
+{
+ return heth->MACLPIEvent;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ETH */
+
+#endif /* HAL_ETH_LEGACY_MODULE_ENABLED*/
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
index 3d19fbb522..8e9063f679 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
@@ -47,11 +47,11 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
- * @brief STM32H7xx HAL Driver version number V1.10.1
+ * @brief STM32H7xx HAL Driver version number V1.11.0
*/
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
-#define __STM32H7xx_HAL_VERSION_SUB1 (0x0AUL) /*!< [23:16] sub1 version */
-#define __STM32H7xx_HAL_VERSION_SUB2 (0x01UL) /*!< [15:8] sub2 version */
+#define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */
+#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
|(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c
index e9d04cf668..c3f408eb41 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c
@@ -497,7 +497,7 @@ HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_Call
/**
* @brief Unregister an CEC Callback
- * CEC callabck is redirected to the weak predefined callback
+ * CEC callback is redirected to the weak predefined callback
* @param hcec uart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c
index b1935625f5..293a48ac16 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c
@@ -173,7 +173,7 @@
/** @addtogroup DSI_Private_Constants
* @{
*/
-#define DSI_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */
+#define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
@@ -378,7 +378,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
/* Enable the DSI PLL */
__HAL_DSI_PLL_ENABLE(hdsi);
- /* Requires min of 400�s delay before reading the PLLLS flag */
+ /* Requires min of 400us delay before reading the PLLLS flag */
/* 1ms delay is inserted that is the minimum HAL delay granularity */
HAL_Delay(1);
@@ -710,7 +710,7 @@ HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Call
/**
* @brief Unregister a DSI Callback
- * DSI callabck is redirected to the weak predefined callback
+ * DSI callback is redirected to the weak predefined callback
* @param hdsi dsi handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c
index 9bcc5582f4..1b21dd4b34 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c
@@ -9,6 +9,7 @@
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
+ *
******************************************************************************
* @attention
*
@@ -49,18 +50,14 @@
(##) HAL_ETH_Start():
This API starts the MAC and DMA transmission and reception process,
without enabling end of transfer interrupts, in this mode user
- has to poll for data availability by calling HAL_ETH_IsRxDataAvailable()
+ has to poll for data reception by calling HAL_ETH_ReadData()
(##) HAL_ETH_Start_IT():
This API starts the MAC and DMA transmission and reception process,
end of transfer interrupts are enabled in this mode,
HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received
- (#) When data is received (HAL_ETH_IsRxDataAvailable() returns 1 or Rx interrupt
- occurred), user can call the following APIs to get received data:
- (##) HAL_ETH_GetRxDataBuffer(): Get buffer address of received frame
- (##) HAL_ETH_GetRxDataLength(): Get received frame length
- (##) HAL_ETH_GetRxDataInfo(): Get received frame additional info,
- please refer to ETH_RxPacketInfo typedef structure
+ (#) When data is received user can call the following API to get received data:
+ (##) HAL_ETH_ReadData(): Read a received packet
(#) For transmission path, two APIs are available:
(##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
@@ -79,20 +76,32 @@
(##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
(##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef
- -@- The PTP protocol offload APIs are not supported in this driver.
+ (#) Configure the Ethernet PTP after ETH peripheral initialization
+ (##) Define HAL_ETH_USE_PTP to use PTP APIs.
+ (##) HAL_ETH_PTP_GetConfig(): Get PTP actual configuration into ETH_PTP_ConfigTypeDef
+ (##) HAL_ETH_PTP_SetConfig(): Set PTP configuration based on ETH_PTP_ConfigTypeDef
+ (##) HAL_ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers
+ (##) HAL_ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers
+ (##) HAL_ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers
+ (##) HAL_ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission
+ (##) HAL_ETH_PTP_GetTxTimestamp(): Get transmission timestamp
+ (##) HAL_ETH_PTP_GetRxTimestamp(): Get reception timestamp
+
+ -@- The ARP offload feature is not supported in this driver.
+
+ -@- The PTP offload feature is not supported in this driver.
*** Callback registration ***
=============================================
The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
+ Use Function HAL_ETH_RegisterCallback() to register an interrupt callback.
- Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
+ Function HAL_ETH_RegisterCallback() allows to register following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
- (+) DMAErrorCallback : DMA Error Callback.
- (+) MACErrorCallback : MAC Error Callback.
+ (+) ErrorCallback : Error Callback.
(+) PMTCallback : Power Management Callback
(+) EEECallback : EEE Callback.
(+) WakeUpCallback : Wake UP Callback
@@ -102,28 +111,51 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
- Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
+ For specific callbacks RxAllocateCallback use dedicated register callbacks:
+ respectively HAL_ETH_RegisterRxAllocateCallback().
+
+ For specific callbacks RxLinkCallback use dedicated register callbacks:
+ respectively HAL_ETH_RegisterRxLinkCallback().
+
+ For specific callbacks TxFreeCallback use dedicated register callbacks:
+ respectively HAL_ETH_RegisterTxFreeCallback().
+
+ For specific callbacks TxPtpCallback use dedicated register callbacks:
+ respectively HAL_ETH_RegisterTxPtpCallback().
+
+ Use function HAL_ETH_UnRegisterCallback() to reset a callback to the default
weak function.
- @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
- (+) DMAErrorCallback : DMA Error Callback.
- (+) MACErrorCallback : MAC Error Callback.
+ (+) ErrorCallback : Error Callback.
(+) PMTCallback : Power Management Callback
(+) EEECallback : EEE Callback.
(+) WakeUpCallback : Wake UP Callback
(+) MspInitCallback : MspInit Callback.
(+) MspDeInitCallback: MspDeInit Callback.
+ For specific callbacks RxAllocateCallback use dedicated unregister callbacks:
+ respectively HAL_ETH_UnRegisterRxAllocateCallback().
+
+ For specific callbacks RxLinkCallback use dedicated unregister callbacks:
+ respectively HAL_ETH_UnRegisterRxLinkCallback().
+
+ For specific callbacks TxFreeCallback use dedicated unregister callbacks:
+ respectively HAL_ETH_UnRegisterTxFreeCallback().
+
+ For specific callbacks TxPtpCallback use dedicated unregister callbacks:
+ respectively HAL_ETH_UnRegisterTxPtpCallback().
+
By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
all callbacks are set to the corresponding weak functions:
- examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
+ examples HAL_ETH_TxCpltCallback(), HAL_ETH_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
+ reset to the legacy weak function in the HAL_ETH_Init/ HAL_ETH_DeInit only when
these callbacks are null (not registered beforehand).
- if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
+ if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ HAL_ETH_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
@@ -131,7 +163,7 @@
in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
+ using HAL_ETH_RegisterCallback() before calling HAL_ETH_DeInit
or HAL_ETH_Init function.
When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
@@ -181,14 +213,15 @@
ETH_MACPCSR_RWKPFE)
/* Timeout values */
-#define ETH_SWRESET_TIMEOUT ((uint32_t)500U)
-#define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U)
-
#define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \
ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\
ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE))
-#define ETH_MAC_US_TICK ((uint32_t)1000000U)
+#define ETH_MACTSCR_MASK ((uint32_t)0x0087FF2FU)
+
+#define ETH_MACSTSUR_VALUE ((uint32_t)0xFFFFFFFFU)
+#define ETH_MACSTNUR_VALUE ((uint32_t)0xBB9ACA00U)
+#define ETH_SEGMENT_SIZE_DEFAULT ((uint32_t)0x218U)
/**
* @}
*/
@@ -199,17 +232,17 @@
*/
/* Helper macros for TX descriptor handling */
#define INCR_TX_DESC_INDEX(inx, offset) do {\
- (inx) += (offset);\
- if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\
- (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\
-} while (0)
+ (inx) += (offset);\
+ if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\
+ (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\
+ } while (0)
/* Helper macros for RX descriptor handling */
#define INCR_RX_DESC_INDEX(inx, offset) do {\
- (inx) += (offset);\
- if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\
- (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\
-} while (0)
+ (inx) += (offset);\
+ if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\
+ (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\
+ } while (0)
/**
* @}
*/
@@ -217,13 +250,13 @@
/** @defgroup ETH_Private_Functions ETH Private Functions
* @{
*/
-static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth);
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode);
+static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth);
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
@@ -258,9 +291,6 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
(++) Tx DMA Descriptors Tab
(++) Length of Rx Buffers
- (+) Call the function HAL_ETH_DescAssignMemory() to assign data buffers
- for each Rx DMA Descriptor
-
(+) Call the function HAL_ETH_DeInit() to restore the default configuration
of the selected ETH peripheral.
@@ -278,44 +308,35 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
uint32_t tickstart;
- if(heth == NULL)
+ if (heth == NULL)
{
return HAL_ERROR;
}
+ if (heth->gState == HAL_ETH_STATE_RESET)
+ {
+ heth->gState = HAL_ETH_STATE_BUSY;
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
- if(heth->gState == HAL_ETH_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- heth->Lock = HAL_UNLOCKED;
-
ETH_InitCallbacksToDefault(heth);
- if(heth->MspInitCallback == NULL)
+ if (heth->MspInitCallback == NULL)
{
heth->MspInitCallback = HAL_ETH_MspInit;
}
/* Init the low level hardware */
heth->MspInitCallback(heth);
- }
-
#else
-
- /* Check the ETH peripheral state */
- if(heth->gState == HAL_ETH_STATE_RESET)
- {
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
- }
-#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
- heth->gState = HAL_ETH_STATE_BUSY;
+#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
+ }
__HAL_RCC_SYSCFG_CLK_ENABLE();
- if(heth->Init.MediaInterface == HAL_ETH_MII_MODE)
+ if (heth->Init.MediaInterface == HAL_ETH_MII_MODE)
{
HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
}
@@ -324,6 +345,9 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
}
+ /* Dummy read to sync with ETH */
+ (void)SYSCFG->PMCR;
+
/* Ethernet Software reset */
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
/* After reset all the registers holds their respective reset values */
@@ -335,7 +359,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
/* Wait for software reset */
while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
{
- if(((HAL_GetTick() - tickstart ) > ETH_SWRESET_TIMEOUT))
+ if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
{
/* Set Error Code */
heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
@@ -347,7 +371,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
}
/*------------------ MDIO CSR Clock Range Configuration --------------------*/
- ETH_MAC_MDIO_ClkConfig(heth);
+ HAL_ETH_SetMDIOClockRange(heth);
/*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U));
@@ -388,7 +412,6 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
heth->ErrorCode = HAL_ETH_ERROR_NONE;
heth->gState = HAL_ETH_STATE_READY;
- heth->RxState = HAL_ETH_STATE_READY;
return HAL_OK;
}
@@ -406,7 +429,7 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
- if(heth->MspDeInitCallback == NULL)
+ if (heth->MspDeInitCallback == NULL)
{
heth->MspDeInitCallback = HAL_ETH_MspDeInit;
}
@@ -420,7 +443,7 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
/* Set ETH HAL state to Disabled */
- heth->gState= HAL_ETH_STATE_RESET;
+ heth->gState = HAL_ETH_STATE_RESET;
/* Return function status */
return HAL_OK;
@@ -465,8 +488,7 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
* This parameter can be one of the following values:
* @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
* @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
- * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
- * @arg @ref HAL_ETH_MAC_ERROR_CB_ID MAC Error Callback ID
+ * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID
* @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID
* @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID
@@ -475,86 +497,81 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
* @param pCallback pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,
+ pETH_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(heth);
- if(heth->gState == HAL_ETH_STATE_READY)
+ if (heth->gState == HAL_ETH_STATE_READY)
{
switch (CallbackID)
{
- case HAL_ETH_TX_COMPLETE_CB_ID :
- heth->TxCpltCallback = pCallback;
- break;
-
- case HAL_ETH_RX_COMPLETE_CB_ID :
- heth->RxCpltCallback = pCallback;
- break;
-
- case HAL_ETH_DMA_ERROR_CB_ID :
- heth->DMAErrorCallback = pCallback;
- break;
-
- case HAL_ETH_MAC_ERROR_CB_ID :
- heth->MACErrorCallback = pCallback;
- break;
-
- case HAL_ETH_PMT_CB_ID :
- heth->PMTCallback = pCallback;
- break;
-
- case HAL_ETH_EEE_CB_ID :
- heth->EEECallback = pCallback;
- break;
-
- case HAL_ETH_WAKEUP_CB_ID :
- heth->WakeUpCallback = pCallback;
- break;
-
- case HAL_ETH_MSPINIT_CB_ID :
- heth->MspInitCallback = pCallback;
- break;
-
- case HAL_ETH_MSPDEINIT_CB_ID :
- heth->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Update the error code */
- heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_ETH_TX_COMPLETE_CB_ID :
+ heth->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_ETH_RX_COMPLETE_CB_ID :
+ heth->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_ETH_ERROR_CB_ID :
+ heth->ErrorCallback = pCallback;
+ break;
+
+ case HAL_ETH_PMT_CB_ID :
+ heth->PMTCallback = pCallback;
+ break;
+
+ case HAL_ETH_EEE_CB_ID :
+ heth->EEECallback = pCallback;
+ break;
+
+ case HAL_ETH_WAKEUP_CB_ID :
+ heth->WakeUpCallback = pCallback;
+ break;
+
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(heth->gState == HAL_ETH_STATE_RESET)
+ else if (heth->gState == HAL_ETH_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_ETH_MSPINIT_CB_ID :
- heth->MspInitCallback = pCallback;
- break;
-
- case HAL_ETH_MSPDEINIT_CB_ID :
- heth->MspDeInitCallback = pCallback;
- break;
-
- default :
- /* Update the error code */
- heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -565,9 +582,6 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(heth);
-
return status;
}
@@ -579,8 +593,7 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call
* This parameter can be one of the following values:
* @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
* @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
- * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID
- * @arg @ref HAL_ETH_MAC_ERROR_CB_ID MAC Error Callback ID
+ * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID
* @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID
* @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID
@@ -592,75 +605,68 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Ca
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(heth);
-
- if(heth->gState == HAL_ETH_STATE_READY)
+ if (heth->gState == HAL_ETH_STATE_READY)
{
switch (CallbackID)
{
- case HAL_ETH_TX_COMPLETE_CB_ID :
- heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
- break;
-
- case HAL_ETH_RX_COMPLETE_CB_ID :
- heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
- break;
-
- case HAL_ETH_DMA_ERROR_CB_ID :
- heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback;
- break;
-
- case HAL_ETH_MAC_ERROR_CB_ID :
- heth->MACErrorCallback = HAL_ETH_MACErrorCallback;
- break;
-
- case HAL_ETH_PMT_CB_ID :
- heth->PMTCallback = HAL_ETH_PMTCallback;
- break;
-
- case HAL_ETH_EEE_CB_ID :
- heth->EEECallback = HAL_ETH_EEECallback;
- break;
-
- case HAL_ETH_WAKEUP_CB_ID :
- heth->WakeUpCallback = HAL_ETH_WakeUpCallback;
- break;
-
- case HAL_ETH_MSPINIT_CB_ID :
- heth->MspInitCallback = HAL_ETH_MspInit;
- break;
-
- case HAL_ETH_MSPDEINIT_CB_ID :
- heth->MspDeInitCallback = HAL_ETH_MspDeInit;
- break;
-
- default :
- /* Update the error code */
- heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_ETH_TX_COMPLETE_CB_ID :
+ heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
+ break;
+
+ case HAL_ETH_RX_COMPLETE_CB_ID :
+ heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
+ break;
+
+ case HAL_ETH_ERROR_CB_ID :
+ heth->ErrorCallback = HAL_ETH_ErrorCallback;
+ break;
+
+ case HAL_ETH_PMT_CB_ID :
+ heth->PMTCallback = HAL_ETH_PMTCallback;
+ break;
+
+ case HAL_ETH_EEE_CB_ID :
+ heth->EEECallback = HAL_ETH_EEECallback;
+ break;
+
+ case HAL_ETH_WAKEUP_CB_ID :
+ heth->WakeUpCallback = HAL_ETH_WakeUpCallback;
+ break;
+
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = HAL_ETH_MspInit;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(heth->gState == HAL_ETH_STATE_RESET)
+ else if (heth->gState == HAL_ETH_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_ETH_MSPINIT_CB_ID :
- heth->MspInitCallback = HAL_ETH_MspInit;
- break;
-
- case HAL_ETH_MSPDEINIT_CB_ID :
- heth->MspDeInitCallback = HAL_ETH_MspDeInit;
- break;
-
- default :
- /* Update the error code */
- heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_ETH_MSPINIT_CB_ID :
+ heth->MspInitCallback = HAL_ETH_MspInit;
+ break;
+
+ case HAL_ETH_MSPDEINIT_CB_ID :
+ heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -671,57 +677,10 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Ca
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(heth);
-
return status;
}
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-/**
- * @brief Assign memory buffers to a DMA Rx descriptor
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @param Index : index of the DMA Rx descriptor
- * this parameter can be a value from 0x0 to (ETH_RX_DESC_CNT -1)
- * @param pBuffer1: address of buffer 1
- * @param pBuffer2: address of buffer 2 if available
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1, uint8_t *pBuffer2)
-{
- ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[Index];
-
- if((pBuffer1 == NULL) || (Index >= (uint32_t)ETH_RX_DESC_CNT))
- {
- /* Set Error Code */
- heth->ErrorCode = HAL_ETH_ERROR_PARAM;
- /* Return Error */
- return HAL_ERROR;
- }
-
- /* write buffer address to RDES0 */
- WRITE_REG(dmarxdesc->DESC0, (uint32_t)pBuffer1);
- /* store buffer address */
- WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)pBuffer1);
- /* set buffer address valid bit to RDES3 */
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
-
- if(pBuffer2 != NULL)
- {
- /* write buffer 2 address to RDES1 */
- WRITE_REG(dmarxdesc->DESC2, (uint32_t)pBuffer2);
- /* store buffer 2 address */
- WRITE_REG(dmarxdesc->BackupAddr1, (uint32_t)pBuffer2);
- /* set buffer 2 address valid bit to RDES3 */
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
- }
- /* set OWN bit to RDES3 */
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
-
- return HAL_OK;
-}
-
/**
* @}
*/
@@ -749,10 +708,16 @@ HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Ind
*/
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
{
- if(heth->gState == HAL_ETH_STATE_READY)
+ if (heth->gState == HAL_ETH_STATE_READY)
{
heth->gState = HAL_ETH_STATE_BUSY;
+ /* Set nombre of descriptors to build */
+ heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
+
+ /* Build all descriptors */
+ ETH_UpdateDescriptor(heth);
+
/* Enable the MAC transmission */
SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
@@ -771,8 +736,7 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
/* Clear Tx and Rx process stopped flags */
heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
- heth->gState = HAL_ETH_STATE_READY;
- heth->RxState = HAL_ETH_STATE_BUSY_RX;
+ heth->gState = HAL_ETH_STATE_STARTED;
return HAL_OK;
}
@@ -790,23 +754,25 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
*/
HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
{
- uint32_t descindex;
-
- ETH_DMADescTypeDef *dmarxdesc;
-
- if(heth->gState == HAL_ETH_STATE_READY)
+ if (heth->gState == HAL_ETH_STATE_READY)
{
heth->gState = HAL_ETH_STATE_BUSY;
- /* Set IOC bit to all Rx descriptors */
- for(descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
- {
- dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
- }
-
/* save IT mode to ETH Handle */
heth->RxDescList.ItMode = 1U;
+ /* Disable Rx MMC Interrupts */
+ SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
+ ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
+
+ /* Disable Tx MMC Interrupts */
+ SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
+ ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
+
+ /* Set nombre of descriptors to build */
+ heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
+
+ /* Build all descriptors */
+ ETH_UpdateDescriptor(heth);
/* Enable the MAC transmission */
SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
@@ -832,11 +798,9 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
- Fatal bus interrupt
*/
__HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE |
- ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
-
- heth->gState = HAL_ETH_STATE_READY;
- heth->RxState = HAL_ETH_STATE_BUSY_RX;
+ ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE));
+ heth->gState = HAL_ETH_STATE_STARTED;
return HAL_OK;
}
else
@@ -853,11 +817,10 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
*/
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
{
- if(heth->gState != HAL_ETH_STATE_RESET)
+ if (heth->gState == HAL_ETH_STATE_STARTED)
{
- /* Set the ETH peripheral state to BUSY */
+ /* Set the ETH peripheral state to BUSY */
heth->gState = HAL_ETH_STATE_BUSY;
-
/* Disable the DMA transmission */
CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
@@ -865,7 +828,7 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
/* Disable the MAC reception */
- CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
+ CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
/* Set the Flush Transmit FIFO bit */
SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
@@ -874,7 +837,6 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
heth->gState = HAL_ETH_STATE_READY;
- heth->RxState = HAL_ETH_STATE_READY;
/* Return function status */
return HAL_OK;
@@ -896,7 +858,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
ETH_DMADescTypeDef *dmarxdesc;
uint32_t descindex;
- if(heth->gState != HAL_ETH_STATE_RESET)
+ if (heth->gState == HAL_ETH_STATE_STARTED)
{
/* Set the ETH peripheral state to BUSY */
heth->gState = HAL_ETH_STATE_BUSY;
@@ -907,7 +869,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
- Fatal bus interrupt
*/
__HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE |
- ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
+ ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE));
/* Disable the DMA transmission */
CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
@@ -916,8 +878,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
/* Disable the MAC reception */
- CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
-
+ CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
/* Set the Flush Transmit FIFO bit */
SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
@@ -925,7 +886,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
/* Clear IOC bit to all Rx descriptors */
- for(descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
+ for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
{
dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
@@ -934,7 +895,6 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
heth->RxDescList.ItMode = 0U;
heth->gState = HAL_ETH_STATE_READY;
- heth->RxState = HAL_ETH_STATE_READY;
/* Return function status */
return HAL_OK;
@@ -956,15 +916,15 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
{
uint32_t tickstart;
- const ETH_DMADescTypeDef *dmatxdesc;
+ ETH_DMADescTypeDef *dmatxdesc;
- if(pTxConfig == NULL)
+ if (pTxConfig == NULL)
{
heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
return HAL_ERROR;
}
- if(heth->gState == HAL_ETH_STATE_READY)
+ if (heth->gState == HAL_ETH_STATE_STARTED)
{
/* Config DMA Tx descriptor by Tx Packet info */
if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)
@@ -974,6 +934,9 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *
return HAL_ERROR;
}
+ /* Ensure completion of descriptor preparation before transmission start */
+ __DSB();
+
dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc];
/* Incr current tx desc index */
@@ -986,25 +949,24 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *
tickstart = HAL_GetTick();
/* Wait for data to be transmitted or timeout occurred */
- while((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
+ while ((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
{
- if((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)
+ if ((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)
{
heth->ErrorCode |= HAL_ETH_ERROR_DMA;
heth->DMAErrorCode = heth->Instance->DMACSR;
- /* Set ETH HAL State to Ready */
- heth->gState = HAL_ETH_STATE_ERROR;
/* Return function status */
return HAL_ERROR;
}
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
- heth->gState = HAL_ETH_STATE_ERROR;
+ /* Clear TX descriptor so that we can proceed */
+ dmatxdesc->DESC3 = (ETH_DMATXNDESCWBF_FD | ETH_DMATXNDESCWBF_LD);
return HAL_ERROR;
}
}
@@ -1028,14 +990,17 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *
*/
HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
{
- if(pTxConfig == NULL)
+ if (pTxConfig == NULL)
{
heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
return HAL_ERROR;
}
- if(heth->gState == HAL_ETH_STATE_READY)
+ if (heth->gState == HAL_ETH_STATE_STARTED)
{
+ /* Save the packet pointer to release. */
+ heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData;
+
/* Config DMA Tx descriptor by Tx Packet info */
if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
{
@@ -1043,6 +1008,9 @@ HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfi
return HAL_ERROR;
}
+ /* Ensure completion of descriptor preparation before transmission start */
+ __DSB();
+
/* Incr current tx desc index */
INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
@@ -1060,410 +1028,800 @@ HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfi
}
/**
- * @brief Checks for received Packets.
+ * @brief Read a received packet.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @retval 1: A Packet is received
- * 0: no Packet received
+ * @param pAppBuff: Pointer to an application buffer to receive the packet.
+ * @retval HAL status
*/
-uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth)
+HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
{
- ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
- uint32_t descidx = dmarxdesclist->CurRxDesc;
- ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
- uint32_t descscancnt = 0;
- uint32_t appdesccnt = 0, firstappdescidx = 0;
+ uint32_t descidx;
+ ETH_DMADescTypeDef *dmarxdesc;
+ uint32_t desccnt = 0U;
+ uint32_t desccntmax;
+ uint32_t bufflength;
+ uint8_t rxdataready = 0U;
- if(dmarxdesclist->AppDescNbr != 0U)
+
+ if (pAppBuff == NULL)
{
- /* data already received by not yet processed*/
- return 0;
+ heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
+ return HAL_ERROR;
}
- /* Check if descriptor is not owned by DMA */
- while((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (descscancnt < (uint32_t)ETH_RX_DESC_CNT))
+ if (heth->gState != HAL_ETH_STATE_STARTED)
{
- descscancnt++;
+ return HAL_ERROR;
+ }
- /* Check if last descriptor */
- if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
- {
- /* Increment the number of descriptors to be passed to the application */
- appdesccnt += 1U;
+ descidx = heth->RxDescList.RxDescIdx;
+ dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
+ desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt;
- if(appdesccnt == 1U)
+ /* Check if descriptor is not owned by DMA */
+ while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax)
+ && (rxdataready == 0U))
+ {
+ if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET)
+ {
+ /* Get timestamp high */
+ heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC1;
+ /* Get timestamp low */
+ heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC0;
+ }
+ if ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL))
+ {
+ /* Check if first descriptor */
+ if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
{
- WRITE_REG(firstappdescidx, descidx);
+ heth->RxDescList.RxDescCnt = 0;
+ heth->RxDescList.RxDataLength = 0;
}
- /* Increment current rx descriptor index */
- INCR_RX_DESC_INDEX(descidx, 1U);
+ /* Check if last descriptor */
+ bufflength = heth->Init.RxBuffLen;
+ if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
+ {
+ bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength;
- /* Check for Context descriptor */
- /* Get current descriptor address */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ /* Save Last descriptor index */
+ heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3;
- if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET)
- {
- if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET)
- {
- /* Increment the number of descriptors to be passed to the application */
- dmarxdesclist->AppContextDesc = 1;
- /* Increment current rx descriptor index */
- INCR_RX_DESC_INDEX(descidx, 1U);
- }
+ /* Packet ready */
+ rxdataready = 1;
}
- /* Fill information to Rx descriptors list */
- dmarxdesclist->CurRxDesc = descidx;
- dmarxdesclist->FirstAppDesc = firstappdescidx;
- dmarxdesclist->AppDescNbr = appdesccnt;
- /* Return function status */
- return 1;
+ /* Link data */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /*Call registered Link callback*/
+ heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
+ (uint8_t *)dmarxdesc->BackupAddr0, bufflength);
+#else
+ /* Link callback */
+ HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
+ (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+ heth->RxDescList.RxDescCnt++;
+ heth->RxDescList.RxDataLength += bufflength;
+
+ /* Clear buffer pointer */
+ dmarxdesc->BackupAddr0 = 0;
}
- /* Check if first descriptor */
- else if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
- {
- WRITE_REG(firstappdescidx, descidx);
- /* Increment the number of descriptors to be passed to the application */
- appdesccnt = 1U;
- /* Increment current rx descriptor index */
- INCR_RX_DESC_INDEX(descidx, 1U);
- /* Get current descriptor address */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ /* Increment current rx descriptor index */
+ INCR_RX_DESC_INDEX(descidx, 1U);
+ /* Get current descriptor address */
+ dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
+ desccnt++;
+ }
+
+ heth->RxDescList.RxBuildDescCnt += desccnt;
+ if ((heth->RxDescList.RxBuildDescCnt) != 0U)
+ {
+ /* Update Descriptors */
+ ETH_UpdateDescriptor(heth);
+ }
+
+ heth->RxDescList.RxDescIdx = descidx;
+
+ if (rxdataready == 1U)
+ {
+ /* Return received packet */
+ *pAppBuff = heth->RxDescList.pRxStart;
+ /* Reset first element */
+ heth->RxDescList.pRxStart = NULL;
+
+ return HAL_OK;
+ }
+
+ /* Packet not ready */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief This function gives back Rx Desc of the last received Packet
+ * to the DMA, so ETH DMA will be able to use these descriptors
+ * to receive next Packets.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
+{
+ uint32_t descidx;
+ uint32_t desccount;
+ ETH_DMADescTypeDef *dmarxdesc;
+ uint8_t *buff = NULL;
+ uint8_t allocStatus = 1U;
+
+ descidx = heth->RxDescList.RxBuildDescIdx;
+ dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
+ desccount = heth->RxDescList.RxBuildDescCnt;
+
+ while ((desccount > 0U) && (allocStatus != 0U))
+ {
+ /* Check if a buffer's attached the descriptor */
+ if (READ_REG(dmarxdesc->BackupAddr0) == 0U)
+ {
+ /* Get a new buffer. */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /*Call registered Allocate callback*/
+ heth->rxAllocateCallback(&buff);
+#else
+ /* Allocate callback */
+ HAL_ETH_RxAllocateCallback(&buff);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+ if (buff == NULL)
+ {
+ allocStatus = 0U;
+ }
+ else
+ {
+ WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff);
+ WRITE_REG(dmarxdesc->DESC0, (uint32_t)buff);
+ }
}
- /* It should be an intermediate descriptor */
- else
+
+ if (allocStatus != 0U)
{
- /* Increment the number of descriptors to be passed to the application */
- appdesccnt += 1U;
+ /* Ensure rest of descriptor is written to RAM before the OWN bit */
+ __DMB();
+
+ if (heth->RxDescList.ItMode != 0U)
+ {
+ WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V | ETH_DMARXNDESCRF_IOC);
+ }
+ else
+ {
+ WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V);
+ }
/* Increment current rx descriptor index */
INCR_RX_DESC_INDEX(descidx, 1U);
/* Get current descriptor address */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
+ desccount--;
}
}
- /* Build Descriptors if an incomplete Packet is received */
- if(appdesccnt > 0U)
+ if (heth->RxDescList.RxBuildDescCnt != desccount)
+ {
+ /* Set the Tail pointer address */
+ WRITE_REG(heth->Instance->DMACRDTPR, 0);
+
+ heth->RxDescList.RxBuildDescIdx = descidx;
+ heth->RxDescList.RxBuildDescCnt = desccount;
+ }
+}
+
+/**
+ * @brief Register the Rx alloc callback.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param rxAllocateCallback: pointer to function to alloc buffer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
+ pETH_rxAllocateCallbackTypeDef rxAllocateCallback)
+{
+ if (rxAllocateCallback == NULL)
+ {
+ /* No buffer to save */
+ return HAL_ERROR;
+ }
+
+ /* Set function to allocate buffer */
+ heth->rxAllocateCallback = rxAllocateCallback;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Unregister the Rx alloc callback.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth)
+{
+ /* Set function to allocate buffer */
+ heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Rx Allocate callback.
+ * @param buff: pointer to allocated buffer
+ * @retval None
+ */
+__weak void HAL_ETH_RxAllocateCallback(uint8_t **buff)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(buff);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_RxAllocateCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Link callback.
+ * @param pStart: pointer to packet start
+ * @param pStart: pointer to packet end
+ * @param buff: pointer to received data
+ * @param Length: received data length
+ * @retval None
+ */
+__weak void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(pStart);
+ UNUSED(pEnd);
+ UNUSED(buff);
+ UNUSED(Length);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_RxLinkCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Set the Rx link data function.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param rxLinkCallback: pointer to function to link data
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback)
+{
+ if (rxLinkCallback == NULL)
+ {
+ /* No buffer to save */
+ return HAL_ERROR;
+ }
+
+ /* Set function to link data */
+ heth->rxLinkCallback = rxLinkCallback;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Unregister the Rx link callback.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth)
+{
+ /* Set function to allocate buffer */
+ heth->rxLinkCallback = HAL_ETH_RxLinkCallback;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the error state of the last received packet.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param pErrorCode: pointer to uint32_t to hold the error code
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
+{
+ /* Get error bits. */
+ *pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXNDESCWBF_ERRORS_MASK);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the Tx free function.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param txFreeCallback: pointer to function to release the packet
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback)
+{
+ if (txFreeCallback == NULL)
{
- dmarxdesclist->CurRxDesc = descidx;
- dmarxdesclist->FirstAppDesc = firstappdescidx;
- descidx = firstappdescidx;
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ /* No buffer to save */
+ return HAL_ERROR;
+ }
+
+ /* Set function to free transmmitted packet */
+ heth->txFreeCallback = txFreeCallback;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Unregister the Tx free callback.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth)
+{
+ /* Set function to allocate buffer */
+ heth->txFreeCallback = HAL_ETH_TxFreeCallback;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Tx Free callback.
+ * @param buff: pointer to buffer to free
+ * @retval None
+ */
+__weak void HAL_ETH_TxFreeCallback(uint32_t *buff)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(buff);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_TxFreeCallback could be implemented in the user file
+ */
+}
- for(descscancnt = 0; descscancnt < appdesccnt; descscancnt++)
+/**
+ * @brief Release transmitted Tx packets.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
+{
+ ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
+ uint32_t numOfBuf = dmatxdesclist->BuffersInUse;
+ uint32_t idx = dmatxdesclist->releaseIndex;
+ uint8_t pktTxStatus = 1U;
+ uint8_t pktInUse;
+#ifdef HAL_ETH_USE_PTP
+ ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp;
+#endif /* HAL_ETH_USE_PTP */
+
+ /* Loop through buffers in use. */
+ while ((numOfBuf != 0U) && (pktTxStatus != 0U))
+ {
+ pktInUse = 1U;
+ numOfBuf--;
+ /* If no packet, just examine the next packet. */
+ if (dmatxdesclist->PacketAddress[idx] == NULL)
{
- WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
- WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
+ /* No packet in use, skip to next. */
+ idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U);
+ pktInUse = 0U;
+ }
- if (READ_REG(dmarxdesc->BackupAddr1) != ((uint32_t)RESET))
+ if (pktInUse != 0U)
+ {
+ /* Determine if the packet has been transmitted. */
+ if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCRF_OWN) == 0U)
{
- WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
- }
+#ifdef HAL_ETH_USE_PTP
+ /* Disable Ptp transmission */
+ CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, ((uint32_t)0x40000000U));
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
+ /* Get timestamp low */
+ timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0;
+ /* Get timestamp high */
+ timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1;
+#endif /* HAL_ETH_USE_PTP */
- if(dmarxdesclist->ItMode != ((uint32_t)RESET))
- {
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /*Call registered callbacks*/
+#ifdef HAL_ETH_USE_PTP
+ /* Handle Ptp */
+ heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
+#endif /* HAL_ETH_USE_PTP */
+ /* Release the packet. */
+ heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]);
+#else
+ /* Call callbacks */
+#ifdef HAL_ETH_USE_PTP
+ /* Handle Ptp */
+ HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
+#endif /* HAL_ETH_USE_PTP */
+ /* Release the packet. */
+ HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+ /* Clear the entry in the in-use array. */
+ dmatxdesclist->PacketAddress[idx] = NULL;
+
+ /* Update the transmit relesae index and number of buffers in use. */
+ idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U);
+ dmatxdesclist->BuffersInUse = numOfBuf;
+ dmatxdesclist->releaseIndex = idx;
}
- if(descscancnt < (appdesccnt - 1U))
+ else
{
- /* Increment rx descriptor index */
- INCR_RX_DESC_INDEX(descidx, 1U);
- /* Get descriptor address */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ /* Get out of the loop! */
+ pktTxStatus = 0U;
}
}
-
- /* Set the Tail pointer address to the last rx descriptor hold by the app */
- WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
}
-
- /* Fill information to Rx descriptors list: No received Packet */
- dmarxdesclist->AppDescNbr = 0U;
-
- return 0;
+ return HAL_OK;
}
+#ifdef HAL_ETH_USE_PTP
/**
- * @brief This function gets the buffer address of last received Packet.
- * @note Please insure to allocate the RxBuffer structure before calling this function
- * how to use example:
- * HAL_ETH_GetRxDataLength(heth, &Length);
- * BuffersNbr = (Length / heth->Init.RxBuffLen) + 1;
- * RxBuffer = (ETH_BufferTypeDef *)malloc(BuffersNbr * sizeof(ETH_BufferTypeDef));
- * HAL_ETH_GetRxDataBuffer(heth, RxBuffer);
+ * @brief Set the Ethernet PTP configuration.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param RxBuffer: Pointer to a ETH_BufferTypeDef structure
+ * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains
+ * the configuration information for PTP
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer)
+HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig)
{
- ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
- uint32_t descidx = dmarxdesclist->FirstAppDesc;
- uint32_t index, accumulatedlen = 0, lastdesclen;
- __IO const ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
- ETH_BufferTypeDef *rxbuff = RxBuffer;
+ uint32_t tmpTSCR;
+ ETH_TimeTypeDef time;
- if(rxbuff == NULL)
+ if (ptpconfig == NULL)
{
- heth->ErrorCode = HAL_ETH_ERROR_PARAM;
return HAL_ERROR;
}
- if(dmarxdesclist->AppDescNbr == 0U)
+ tmpTSCR = ptpconfig->Timestamp |
+ ((uint32_t)ptpconfig->TimestampUpdate << ETH_MACTSCR_TSUPDT_Pos) |
+ ((uint32_t)ptpconfig->TimestampAll << ETH_MACTSCR_TSENALL_Pos) |
+ ((uint32_t)ptpconfig->TimestampRolloverMode << ETH_MACTSCR_TSCTRLSSR_Pos) |
+ ((uint32_t)ptpconfig->TimestampV2 << ETH_MACTSCR_TSVER2ENA_Pos) |
+ ((uint32_t)ptpconfig->TimestampEthernet << ETH_MACTSCR_TSIPENA_Pos) |
+ ((uint32_t)ptpconfig->TimestampIPv6 << ETH_MACTSCR_TSIPV6ENA_Pos) |
+ ((uint32_t)ptpconfig->TimestampIPv4 << ETH_MACTSCR_TSIPV4ENA_Pos) |
+ ((uint32_t)ptpconfig->TimestampEvent << ETH_MACTSCR_TSEVNTENA_Pos) |
+ ((uint32_t)ptpconfig->TimestampMaster << ETH_MACTSCR_TSMSTRENA_Pos) |
+ ((uint32_t)ptpconfig->TimestampSnapshots << ETH_MACTSCR_SNAPTYPSEL_Pos) |
+ ((uint32_t)ptpconfig->TimestampFilter << ETH_MACTSCR_TSENMACADDR_Pos) |
+ ((uint32_t)ptpconfig->TimestampChecksumCorrection << ETH_MACTSCR_CSC_Pos) |
+ ((uint32_t)ptpconfig->TimestampStatusMode << ETH_MACTSCR_TXTSSTSM_Pos);
+
+ /* Write to MACTSCR */
+ MODIFY_REG(heth->Instance->MACTSCR, ETH_MACTSCR_MASK, tmpTSCR);
+
+ /* Enable Timestamp */
+ SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA);
+ WRITE_REG(heth->Instance->MACSSIR, ptpconfig->TimestampSubsecondInc);
+ WRITE_REG(heth->Instance->MACTSAR, ptpconfig->TimestampAddend);
+
+ /* Enable Timestamp */
+ if (ptpconfig->TimestampAddendUpdate == ENABLE)
{
- if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
- {
- /* No data to be transferred to the application */
- return HAL_ERROR;
- }
- else
- {
- descidx = dmarxdesclist->FirstAppDesc;
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
- }
+ SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSADDREG);
+ while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0) {}
}
- /* Get intermediate descriptors buffers: in case of the Packet is split into multi descriptors */
- for(index = 0; index < (dmarxdesclist->AppDescNbr - 1U); index++)
+ /* Enable Update mode */
+ if (ptpconfig->TimestampUpdateMode == ENABLE)
{
- /* Get Address and length of the first buffer address */
- rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
- rxbuff->len = heth->Init.RxBuffLen;
-
- /* Check if the second buffer address of this descriptor is valid */
- if(dmarxdesc->BackupAddr1 != 0U)
- {
- /* Point to next buffer */
- rxbuff = rxbuff->next;
- /* Get Address and length of the second buffer address */
- rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
- rxbuff->len = heth->Init.RxBuffLen;
- }
- else
- {
- /* Nothing to do here */
- }
-
- /* get total length until this descriptor */
- accumulatedlen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
+ SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT);
+ }
- /* Increment to next descriptor */
- INCR_RX_DESC_INDEX(descidx, 1U);
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ /* Initialize Time */
+ time.Seconds = 0;
+ time.NanoSeconds = 0;
+ HAL_ETH_PTP_SetTime(heth, &time);
- /* Point to next buffer */
- rxbuff = rxbuff->next;
- }
+ /* Ptp Init */
+ SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT);
- /* last descriptor data length */
- lastdesclen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - accumulatedlen;
+ /* Set PTP Configuration done */
+ heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURATED;
- /* Get Address of the first buffer address */
- rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
+ /* Return function status */
+ return HAL_OK;
+}
- /* data is in only one buffer */
- if(lastdesclen <= heth->Init.RxBuffLen)
- {
- rxbuff->len = lastdesclen;
- }
- /* data is in two buffers */
- else if(dmarxdesc->BackupAddr1 != 0U)
- {
- /* Get the Length of the first buffer address */
- rxbuff->len = heth->Init.RxBuffLen;
- /* Point to next buffer */
- rxbuff = rxbuff->next;
- /* Get the Address the Length of the second buffer address */
- rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
- rxbuff->len = lastdesclen - (heth->Init.RxBuffLen);
- }
- else /* Buffer 2 not valid*/
+/**
+ * @brief Get the Ethernet PTP configuration.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains
+ * the configuration information for PTP
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig)
+{
+ if (ptpconfig == NULL)
{
return HAL_ERROR;
}
+ ptpconfig->Timestamp = READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA);
+ ptpconfig->TimestampUpdate = ((READ_BIT(heth->Instance->MACTSCR,
+ ETH_MACTSCR_TSCFUPDT) >> ETH_MACTSCR_TSUPDT_Pos) > 0U) ? ENABLE : DISABLE;
+ ptpconfig->TimestampAll = ((READ_BIT(heth->Instance->MACTSCR,
+ ETH_MACTSCR_TSENALL) >> ETH_MACTSCR_TSENALL_Pos) > 0U) ? ENABLE : DISABLE;
+ ptpconfig->TimestampRolloverMode = ((READ_BIT(heth->Instance->MACTSCR,
+ ETH_MACTSCR_TSCTRLSSR) >> ETH_MACTSCR_TSCTRLSSR_Pos) > 0U)
+ ? ENABLE : DISABLE;
+ ptpconfig->TimestampV2 = ((READ_BIT(heth->Instance->MACTSCR,
+ ETH_MACTSCR_TSVER2ENA) >> ETH_MACTSCR_TSVER2ENA_Pos) > 0U) ? ENABLE : DISABLE;
+ ptpconfig->TimestampEthernet = ((READ_BIT(heth->Instance->MACTSCR,
+ ETH_MACTSCR_TSIPENA) >> ETH_MACTSCR_TSIPENA_Pos) > 0U) ? ENABLE : DISABLE;
+ ptpconfig->TimestampIPv6 = ((READ_BIT(heth->Instance->MACTSCR,
+ ETH_MACTSCR_TSIPV6ENA) >> ETH_MACTSCR_TSIPV6ENA_Pos) > 0U) ? ENABLE : DISABLE;
+ ptpconfig->TimestampIPv4 = ((READ_BIT(heth->Instance->MACTSCR,
+ ETH_MACTSCR_TSIPV4ENA) >> ETH_MACTSCR_TSIPV4ENA_Pos) > 0U) ? ENABLE : DISABLE;
+ ptpconfig->TimestampEvent = ((READ_BIT(heth->Instance->MACTSCR,
+ ETH_MACTSCR_TSEVNTENA) >> ETH_MACTSCR_TSEVNTENA_Pos) > 0U) ? ENABLE : DISABLE;
+ ptpconfig->TimestampMaster = ((READ_BIT(heth->Instance->MACTSCR,
+ ETH_MACTSCR_TSMSTRENA) >> ETH_MACTSCR_TSMSTRENA_Pos) > 0U) ? ENABLE : DISABLE;
+ ptpconfig->TimestampSnapshots = ((READ_BIT(heth->Instance->MACTSCR,
+ ETH_MACTSCR_SNAPTYPSEL) >> ETH_MACTSCR_SNAPTYPSEL_Pos) > 0U)
+ ? ENABLE : DISABLE;
+ ptpconfig->TimestampFilter = ((READ_BIT(heth->Instance->MACTSCR,
+ ETH_MACTSCR_TSENMACADDR) >> ETH_MACTSCR_TSENMACADDR_Pos) > 0U)
+ ? ENABLE : DISABLE;
+ ptpconfig->TimestampChecksumCorrection = ((READ_BIT(heth->Instance->MACTSCR,
+ ETH_MACTSCR_CSC) >> ETH_MACTSCR_CSC_Pos) > 0U) ? ENABLE : DISABLE;
+ ptpconfig->TimestampStatusMode = ((READ_BIT(heth->Instance->MACTSCR,
+ ETH_MACTSCR_TXTSSTSM) >> ETH_MACTSCR_TXTSSTSM_Pos) > 0U)
+ ? ENABLE : DISABLE;
+ /* Return function status */
return HAL_OK;
}
/**
- * @brief This function gets the length of last received Packet.
+ * @brief Set Seconds and Nanoseconds for the Ethernet PTP registers.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param Length: parameter to hold Rx packet length
- * @retval HAL Status
+ * @param heth: pointer to a ETH_TimeTypeDef structure that contains
+ * time to set
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length)
+HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
{
- ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
- uint32_t descidx = dmarxdesclist->FirstAppDesc;
- __IO const ETH_DMADescTypeDef *dmarxdesc;
-
- if(dmarxdesclist->AppDescNbr == 0U)
+ if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
{
- if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
- {
- /* No data to be transferred to the application */
- return HAL_ERROR;
- }
- }
-
- /* Get index of last descriptor */
- INCR_RX_DESC_INDEX(descidx, (dmarxdesclist->AppDescNbr - 1U));
- /* Point to last descriptor */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ /* Set Seconds */
+ heth->Instance->MACSTSUR = time->Seconds;
- *Length = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
+ /* Set NanoSeconds */
+ heth->Instance->MACSTNUR = time->NanoSeconds;
- return HAL_OK;
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Return function status */
+ return HAL_ERROR;
+ }
}
/**
- * @brief Get the Rx data info (Packet type, VLAN tag, Filters status, ...)
+ * @brief Get Seconds and Nanoseconds for the Ethernet PTP registers.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param RxPacketInfo: parameter to hold info of received buffer
+ * @param heth: pointer to a ETH_TimeTypeDef structure that contains
+ * time to get
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo)
+HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
{
- ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
- uint32_t descidx = dmarxdesclist->FirstAppDesc;
- __IO const ETH_DMADescTypeDef *dmarxdesc;
-
- if(dmarxdesclist->AppDescNbr == 0U)
+ if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
{
- if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
- {
- /* No data to be transferred to the application */
- return HAL_ERROR;
- }
- }
+ /* Get Seconds */
+ time->Seconds = heth->Instance->MACSTSUR;
- /* Get index of last descriptor */
- INCR_RX_DESC_INDEX(descidx, ((dmarxdesclist->AppDescNbr) - 1U));
- /* Point to last descriptor */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+ /* Get NanoSeconds */
+ time->NanoSeconds = heth->Instance->MACSTNUR;
- if((dmarxdesc->DESC3 & ETH_DMARXNDESCWBF_ES) != (uint32_t)RESET)
- {
- RxPacketInfo->ErrorCode = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_ERRORS_MASK);
+ /* Return function status */
+ return HAL_OK;
}
else
{
- if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS0V) != 0U)
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Update time for the Ethernet PTP registers.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param timeupdate: pointer to a ETH_TIMEUPDATETypeDef structure that contains
+ * the time update information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
+ ETH_TimeTypeDef *timeoffset)
+{
+ if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
+ {
+ if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE)
{
+ /* Set Seconds update */
+ heth->Instance->MACSTSUR = ETH_MACSTSUR_VALUE - timeoffset->Seconds + 1U;
- if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LT) == ETH_DMARXNDESCWBF_LT_DVLAN)
+ if (READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCTRLSSR) == ETH_MACTSCR_TSCTRLSSR)
{
- RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
- RxPacketInfo->InnerVlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_IVT) >> 16;
+ /* Set nanoSeconds update */
+ heth->Instance->MACSTNUR = ETH_MACSTNUR_VALUE - timeoffset->NanoSeconds;
}
else
{
- RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
+ /* Set nanoSeconds update */
+ heth->Instance->MACSTNUR = ETH_MACSTSUR_VALUE - timeoffset->NanoSeconds + 1U;
}
}
-
- if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS1V) != 0U)
+ else
{
- /* Get Payload type */
- RxPacketInfo->PayloadType =READ_BIT( dmarxdesc->DESC1, ETH_DMARXNDESCWBF_PT);
- /* Get Header type */
- RxPacketInfo->HeaderType = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPV4 | ETH_DMARXNDESCWBF_IPV6));
- /* Get Checksum status */
- RxPacketInfo->Checksum = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPCE | ETH_DMARXNDESCWBF_IPCB | ETH_DMARXNDESCWBF_IPHE));
+ /* Set Seconds update */
+ heth->Instance->MACSTSUR = timeoffset->Seconds;
+ /* Set nanoSeconds update */
+ heth->Instance->MACSTNUR = timeoffset->NanoSeconds;
}
- if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS2V) != 0U)
- {
- RxPacketInfo->MacFilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_HF | ETH_DMARXNDESCWBF_DAF | ETH_DMARXNDESCWBF_SAF | ETH_DMARXNDESCWBF_VF));
- RxPacketInfo->L3FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM));
- RxPacketInfo->L4FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM));
- }
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Return function status */
+ return HAL_ERROR;
}
-
- /* Get the segment count */
- WRITE_REG(RxPacketInfo->SegmentCnt, dmarxdesclist->AppDescNbr);
-
- return HAL_OK;
}
/**
-* @brief This function gives back Rx Desc of the last received Packet
-* to the DMA, so ETH DMA will be able to use these descriptors
-* to receive next Packets.
-* It should be called after processing the received Packet.
-* @param heth: pointer to a ETH_HandleTypeDef structure that contains
-* the configuration information for ETHERNET module
-* @retval HAL status.
-*/
-HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth)
+ * @brief Insert Timestamp in transmission.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param txtimestampconf: Enable or Disable timestamp in transmission
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth)
{
- ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
- uint32_t descindex = dmarxdesclist->FirstAppDesc;
- __IO ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
- uint32_t totalappdescnbr = dmarxdesclist->AppDescNbr;
- uint32_t descscan;
+ ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
+ uint32_t descidx = dmatxdesclist->CurTxDesc;
+ ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
- if(dmarxdesclist->AppDescNbr == 0U)
+ if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
{
- /* No Rx descriptors to build */
- return HAL_ERROR;
- }
+ /* Enable Time Stamp transmission */
+ SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE);
- if(dmarxdesclist->AppContextDesc != 0U)
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
{
- /* A context descriptor is available */
- totalappdescnbr += 1U;
+ /* Return function status */
+ return HAL_ERROR;
}
+}
- for(descscan =0; descscan < totalappdescnbr; descscan++)
- {
- WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
- WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
+/**
+ * @brief Get transmission timestamp.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains
+ * transmission timestamp
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
+{
+ ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
+ uint32_t idx = dmatxdesclist->releaseIndex;
+ ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx];
- if (READ_REG(dmarxdesc->BackupAddr1) != 0U)
- {
- WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
- }
+ if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
+ {
+ /* Get timestamp low */
+ timestamp->TimeStampLow = dmatxdesc->DESC0;
+ /* Get timestamp high */
+ timestamp->TimeStampHigh = dmatxdesc->DESC1;
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
- if(dmarxdesclist->ItMode != 0U)
- {
- SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
- }
+/**
+ * @brief Get receive timestamp.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains
+ * receive timestamp
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
+{
+ if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
+ {
+ /* Get timestamp low */
+ timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow;
+ /* Get timestamp high */
+ timestamp->TimeStampHigh = heth->RxDescList.TimeStamp.TimeStampHigh;
- if(descscan < (totalappdescnbr - 1U))
- {
- /* Increment rx descriptor index */
- INCR_RX_DESC_INDEX(descindex, 1U);
- /* Get descriptor address */
- dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
- }
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Return function status */
+ return HAL_ERROR;
}
+}
- /* Set the Tail pointer address to the last rx descriptor hold by the app */
- WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
+/**
+ * @brief Register the Tx Ptp callback.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @param txPtpCallback: Function to handle Ptp transmission
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback)
+{
+ if (txPtpCallback == NULL)
+ {
+ /* No buffer to save */
+ return HAL_ERROR;
+ }
+ /* Set Function to handle Tx Ptp */
+ heth->txPtpCallback = txPtpCallback;
- /* reset the Application desc number */
- WRITE_REG(dmarxdesclist->AppDescNbr, 0);
+ return HAL_OK;
+}
- /* reset the application context descriptor */
- WRITE_REG(heth->RxDescList.AppContextDesc, 0);
+/**
+ * @brief Unregister the Tx Ptp callback.
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth)
+{
+ /* Set function to allocate buffer */
+ heth->txPtpCallback = HAL_ETH_TxPtpCallback;
return HAL_OK;
}
+/**
+ * @brief Tx Ptp callback.
+ * @param buff: pointer to application buffer
+ * @retval None
+ */
+__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(buff);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_ETH_TxPtpCallback could be implemented in the user file
+ */
+}
+#endif /* HAL_ETH_USE_PTP */
/**
* @brief This function handles ETH interrupt request.
@@ -1473,11 +1831,14 @@ HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth)
*/
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
{
+ uint32_t macirqenable;
/* Packet received */
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
{
- if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
+ if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
{
+ /* Clear the Eth DMA Rx IT pending bits */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/*Call registered Receive complete callback*/
@@ -1486,35 +1847,32 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
/* Receive complete callback */
HAL_ETH_RxCpltCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
- /* Clear the Eth DMA Rx IT pending bits */
- __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
}
}
/* Packet transmitted */
if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI))
{
- if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
+ if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
{
+ /* Clear the Eth DMA Tx IT pending bits */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
+
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
- /*Call registered Transmit complete callback*/
- heth->TxCpltCallback(heth);
+ /*Call registered Transmit complete callback*/
+ heth->TxCpltCallback(heth);
#else
/* Transfer complete callback */
HAL_ETH_TxCpltCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
- /* Clear the Eth DMA Tx IT pending bits */
- __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
}
}
/* ETH DMA Error */
- if(__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
+ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
{
- if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
+ if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
{
heth->ErrorCode |= HAL_ETH_ERROR_DMA;
@@ -1533,45 +1891,49 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
else
{
/* Get DMA error status */
- heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
- ETH_DMACSR_RBU | ETH_DMACSR_AIS));
+ heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
+ ETH_DMACSR_RBU | ETH_DMACSR_AIS));
/* Clear the interrupt summary flag */
__HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
- ETH_DMACSR_RBU | ETH_DMACSR_AIS));
+ ETH_DMACSR_RBU | ETH_DMACSR_AIS));
}
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
- /* Call registered DMA Error callback*/
- heth->DMAErrorCallback(heth);
+ /* Call registered Error callback*/
+ heth->ErrorCallback(heth);
#else
/* Ethernet DMA Error callback */
- HAL_ETH_DMAErrorCallback(heth);
+ HAL_ETH_ErrorCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
}
/* ETH MAC Error IT */
- if(__HAL_ETH_MAC_GET_IT(heth, (ETH_MACIER_RXSTSIE | ETH_MACIER_TXSTSIE)))
+ macirqenable = heth->Instance->MACIER;
+ if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
+ ((macirqenable & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE))
{
+ heth->ErrorCode |= HAL_ETH_ERROR_MAC;
+
/* Get MAC Rx Tx status and clear Status register pending bit */
heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
heth->gState = HAL_ETH_STATE_ERROR;
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
- /* Call registered MAC Error callback*/
- heth->MACErrorCallback(heth);
+ /* Call registered Error callback*/
+ heth->ErrorCallback(heth);
#else
- /* Ethernet MAC Error callback */
- HAL_ETH_MACErrorCallback(heth);
+ /* Ethernet Error callback */
+ HAL_ETH_ErrorCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
heth->MACErrorCode = (uint32_t)(0x0U);
}
/* ETH PMT IT */
- if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
+ if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
{
/* Get MAC Wake-up source and clear the status register pending bit */
heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
@@ -1588,7 +1950,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
}
/* ETH EEE IT */
- if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
+ if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
{
/* Get MAC LPI interrupt source and clear the status register pending bit */
heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU);
@@ -1608,7 +1970,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* check ETH WAKEUP exti flag */
- if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+ if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
{
/* Clear ETH WAKEUP Exti pending bit */
__HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
@@ -1618,13 +1980,13 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
#else
/* ETH WAKEUP callback */
HAL_ETH_WakeUpCallback(heth);
-#endif
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
}
else
{
/* check ETH WAKEUP exti flag */
- if(__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+ if (__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
{
/* Clear ETH WAKEUP Exti pending bit */
__HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
@@ -1634,24 +1996,24 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
#else
/* ETH WAKEUP callback */
HAL_ETH_WakeUpCallback(heth);
-#endif
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
}
-#else
+#else /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* check ETH WAKEUP exti flag */
- if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+ if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
{
/* Clear ETH WAKEUP Exti pending bit */
__HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
- /* Call registered WakeUp callback*/
- heth->WakeUpCallback(heth);
+ /* Call registered WakeUp callback*/
+ heth->WakeUpCallback(heth);
#else
- /* ETH WAKEUP callback */
- HAL_ETH_WakeUpCallback(heth);
-#endif
+ /* ETH WAKEUP callback */
+ HAL_ETH_WakeUpCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
-#endif
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
/**
@@ -1685,32 +2047,17 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
}
/**
- * @brief Ethernet DMA transfer error callbacks
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-__weak void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(heth);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_DMAErrorCallback could be implemented in the user file
- */
-}
-
-/**
-* @brief Ethernet MAC transfer error callbacks
+ * @brief Ethernet transfer error callbacks
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
-__weak void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth)
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_ETH_MACErrorCallback could be implemented in the user file
+ the HAL_ETH_ErrorCallback could be implemented in the user file
*/
}
@@ -1768,12 +2115,14 @@ __weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
* @param pRegValue: parameter to hold read value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+ uint32_t *pRegValue)
{
- uint32_t tmpreg, tickstart;
+ uint32_t tickstart;
+ uint32_t tmpreg;
/* Check for the Busy flag */
- if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
+ if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET)
{
return HAL_ERROR;
}
@@ -1787,7 +2136,7 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA
- Set the read mode
- Set the MII Busy bit */
- MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
+ MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21));
MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD);
SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
@@ -1798,9 +2147,9 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA
tickstart = HAL_GetTick();
/* Wait for the Busy flag */
- while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
+ while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
{
- if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
+ if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT))
{
return HAL_ERROR;
}
@@ -1822,12 +2171,14 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA
* @param RegValue: the value to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+ uint32_t RegValue)
{
- uint32_t tmpreg, tickstart;
+ uint32_t tickstart;
+ uint32_t tmpreg;
/* Check for the Busy flag */
- if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
+ if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET)
{
return HAL_ERROR;
}
@@ -1841,7 +2192,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHY
- Set the write mode
- Set the MII Busy bit */
- MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
+ MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21));
MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
@@ -1856,9 +2207,9 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHY
tickstart = HAL_GetTick();
/* Wait for the Busy flag */
- while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
+ while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
{
- if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
+ if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT))
{
return HAL_ERROR;
}
@@ -1902,22 +2253,25 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp
/* Get MAC parameters */
macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN);
- macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC)>> 4) > 0U) ? ENABLE : DISABLE;
+ macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE;
macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE;
- macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) ? ENABLE : DISABLE;
+ macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U)
+ ? ENABLE : DISABLE;
macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE;
- macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE;
+ macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR,
+ ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE;
macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE;
macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE;
- macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >>17) == 0U) ? ENABLE : DISABLE;
- macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >>19) == 0U) ? ENABLE : DISABLE;
+ macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 17) == 0U) ? ENABLE : DISABLE;
+ macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 19) == 0U) ? ENABLE : DISABLE;
macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE;
macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE;
macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE;
- macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE;
+ macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR,
+ ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE;
macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG);
macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE;
macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC);
@@ -1925,8 +2279,10 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp
macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL);
macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE;
macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE;
- macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE;
- macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) ? ENABLE : DISABLE;
+ macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR,
+ ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE;
+ macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U)
+ ? ENABLE : DISABLE;
macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
@@ -1940,14 +2296,17 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp
macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE;
- macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) ? ENABLE : DISABLE;
+ macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U)
+ ? ENABLE : DISABLE;
macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF));
macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF));
- macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE;
+ macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
+ ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE;
macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE;
- macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE;
+ macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
+ ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE;
return HAL_OK;
}
@@ -1969,11 +2328,11 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp
dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12) > 0U) ? ENABLE : DISABLE;
dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB);
- dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB)>> 15) > 0U) ? ENABLE : DISABLE;
+ dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB) >> 15) > 0U) ? ENABLE : DISABLE;
- dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR |ETH_DMAMR_PR | ETH_DMAMR_DA));
+ dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR | ETH_DMAMR_PR | ETH_DMAMR_DA));
- dmaconf->PBLx8Mode = ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL)>> 16) > 0U) ? ENABLE : DISABLE;
+ dmaconf->PBLx8Mode = ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL) >> 16) > 0U) ? ENABLE : DISABLE;
dmaconf->MaximumSegmentSize = READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_MSS);
dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPF) >> 31) > 0U) ? ENABLE : DISABLE;
@@ -1982,7 +2341,6 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp
dmaconf->SecondPacketOperate = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4) > 0U) ? ENABLE : DISABLE;
dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE;
dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL);
-
return HAL_OK;
}
@@ -1996,12 +2354,12 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp
*/
HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
{
- if(macconf == NULL)
+ if (macconf == NULL)
{
return HAL_ERROR;
}
- if(heth->RxState == HAL_ETH_STATE_READY)
+ if (heth->gState == HAL_ETH_STATE_READY)
{
ETH_SetMACConfig(heth, macconf);
@@ -2023,12 +2381,12 @@ HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTy
*/
HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
{
- if(dmaconf == NULL)
+ if (dmaconf == NULL)
{
return HAL_ERROR;
}
- if(heth->RxState == HAL_ETH_STATE_READY)
+ if (heth->gState == HAL_ETH_STATE_READY)
{
ETH_SetDMAConfig(heth, dmaconf);
@@ -2048,34 +2406,35 @@ HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTy
*/
void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
{
- uint32_t tmpreg, hclk;
+ uint32_t hclk;
+ uint32_t tmpreg;
/* Get the ETHERNET MACMDIOAR value */
tmpreg = (heth->Instance)->MACMDIOAR;
- /* Clear CSR Clock Range bits */
+ /* Clear CSR Clock Range bits */
tmpreg &= ~ETH_MACMDIOAR_CR;
- /* Get hclk frequency value */
+ /* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
- /* Set CR bits depending on hclk value */
- if((hclk >= 20000000U)&&(hclk < 35000000U))
+ /* Set CR bits depending on hclk value */
+ if ((hclk >= 20000000U) && (hclk < 35000000U))
{
/* CSR Clock Range between 20-35 MHz */
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
}
- else if((hclk >= 35000000U)&&(hclk < 60000000U))
+ else if ((hclk >= 35000000U) && (hclk < 60000000U))
{
/* CSR Clock Range between 35-60 MHz */
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
}
- else if((hclk >= 60000000U)&&(hclk < 100000000U))
+ else if ((hclk >= 60000000U) && (hclk < 100000000U))
{
/* CSR Clock Range between 60-100 MHz */
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
}
- else if((hclk >= 100000000U)&&(hclk < 150000000U))
+ else if ((hclk >= 100000000U) && (hclk < 150000000U))
{
/* CSR Clock Range between 100-150 MHz */
tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
@@ -2102,22 +2461,22 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil
{
uint32_t filterconfig;
- if(pFilterConfig == NULL)
+ if (pFilterConfig == NULL)
{
return HAL_ERROR;
}
filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode |
((uint32_t)pFilterConfig->HashUnicast << 1) |
- ((uint32_t)pFilterConfig->HashMulticast << 2) |
- ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
- ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
- ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) |
- ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
- ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
- ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
- ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
- pFilterConfig->ControlPacketsFilter);
+ ((uint32_t)pFilterConfig->HashMulticast << 2) |
+ ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
+ ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
+ ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) |
+ ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
+ ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
+ ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
+ ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
+ pFilterConfig->ControlPacketsFilter);
MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig);
@@ -2134,7 +2493,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil
*/
HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
{
- if(pFilterConfig == NULL)
+ if (pFilterConfig == NULL)
{
return HAL_ERROR;
}
@@ -2142,13 +2501,16 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil
pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR)) > 0U) ? ENABLE : DISABLE;
pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1) > 0U) ? ENABLE : DISABLE;
pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2) > 0U) ? ENABLE : DISABLE;
- pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
+ pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR,
+ ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE;
pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE;
pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF);
- pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
+ pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR,
+ ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE;
- pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U) ? ENABLE : DISABLE;
+ pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U)
+ ? ENABLE : DISABLE;
pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31) > 0U) ? ENABLE : DISABLE;
return HAL_OK;
@@ -2168,17 +2530,18 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil
*/
HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
{
- uint32_t macaddrhr, macaddrlr;
+ uint32_t macaddrlr;
+ uint32_t macaddrhr;
- if(pMACAddr == NULL)
+ if (pMACAddr == NULL)
{
return HAL_ERROR;
}
/* Get mac addr high reg offset */
- macaddrhr = ((uint32_t)&(heth->Instance->MACA0HR) + AddrNbr);
+ macaddrhr = ((uint32_t) &(heth->Instance->MACA0HR) + AddrNbr);
/* Get mac addr low reg offset */
- macaddrlr = ((uint32_t)&(heth->Instance->MACA0LR) + AddrNbr);
+ macaddrlr = ((uint32_t) &(heth->Instance->MACA0LR) + AddrNbr);
/* Set MAC addr bits 32 to 47 */
(*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]);
@@ -2186,7 +2549,7 @@ HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_
(*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) |
((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]);
- /* Enable address and set source address bit */
+ /* Enable address and set source address bit */
(*(__IO uint32_t *)macaddrhr) |= (ETH_MACAHR_SA | ETH_MACAHR_AE);
return HAL_OK;
@@ -2202,7 +2565,7 @@ HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_
*/
HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable)
{
- if(pHashTable == NULL)
+ if (pHashTable == NULL)
{
return HAL_ERROR;
}
@@ -2224,14 +2587,14 @@ HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashT
*/
void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
{
- if(ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
+ if (ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
{
- MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL , VLANIdentifier);
+ MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL, VLANIdentifier);
CLEAR_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
}
else
{
- MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID , VLANIdentifier);
+ MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID, VLANIdentifier);
SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
}
}
@@ -2250,9 +2613,9 @@ void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigType
powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) |
((uint32_t)pPowerDownConfig->WakeUpPacket << 2) |
- ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) |
- ((uint32_t)pPowerDownConfig->WakeUpForward << 10) |
- ETH_MACPCSR_PWRDWN);
+ ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) |
+ ((uint32_t)pPowerDownConfig->WakeUpForward << 10) |
+ ETH_MACPCSR_PWRDWN);
/* Enable PMT interrupt */
__HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE);
@@ -2269,9 +2632,10 @@ void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigType
void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth)
{
/* clear wake up sources */
- CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | ETH_MACPCSR_RWKPFE);
+ CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST |
+ ETH_MACPCSR_RWKPFE);
- if(READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != 0U)
+ if (READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != (uint32_t)RESET)
{
/* Exit power down mode */
CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN);
@@ -2293,7 +2657,7 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi
{
uint32_t regindex;
- if(pFilter == NULL)
+ if (pFilter == NULL)
{
return HAL_ERROR;
}
@@ -2302,7 +2666,7 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi
SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST);
/* Wake up packet filter config */
- for(regindex = 0; regindex < Count; regindex++)
+ for (regindex = 0; regindex < Count; regindex++)
{
/* Write filter regs */
WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]);
@@ -2340,13 +2704,7 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi
*/
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
{
- HAL_ETH_StateTypeDef ret;
- HAL_ETH_StateTypeDef gstate = heth->gState;
- HAL_ETH_StateTypeDef rxstate =heth->RxState;
-
- ret = gstate;
- ret |= rxstate;
- return ret;
+ return heth->gState;
}
/**
@@ -2405,42 +2763,43 @@ uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
* @{
*/
+
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
{
uint32_t macregval;
/*------------------------ MACCR Configuration --------------------*/
- macregval =(macconf->InterPacketGapVal |
- macconf->SourceAddrControl |
- ((uint32_t)macconf->ChecksumOffload<< 27) |
- ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
- ((uint32_t)macconf->Support2KPacket << 22) |
- ((uint32_t)macconf->CRCStripTypePacket << 21) |
- ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
- ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
- ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
- ((uint32_t)macconf->JumboPacket << 16) |
- macconf->Speed |
- macconf->DuplexMode |
- ((uint32_t)macconf->LoopbackMode << 12) |
- ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11)|
- ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10)|
- ((uint32_t)macconf->CarrierSenseDuringTransmit << 9)|
- ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8)|
- macconf->BackOffLimit |
- ((uint32_t)macconf->DeferralCheck << 4)|
- macconf->PreambleLength);
+ macregval = (macconf->InterPacketGapVal |
+ macconf->SourceAddrControl |
+ ((uint32_t)macconf->ChecksumOffload << 27) |
+ ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
+ ((uint32_t)macconf->Support2KPacket << 22) |
+ ((uint32_t)macconf->CRCStripTypePacket << 21) |
+ ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
+ ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
+ ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
+ ((uint32_t)macconf->JumboPacket << 16) |
+ macconf->Speed |
+ macconf->DuplexMode |
+ ((uint32_t)macconf->LoopbackMode << 12) |
+ ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) |
+ ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) |
+ ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) |
+ ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) |
+ macconf->BackOffLimit |
+ ((uint32_t)macconf->DeferralCheck << 4) |
+ macconf->PreambleLength);
/* Write to MACCR */
MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
/*------------------------ MACECR Configuration --------------------*/
- macregval = ((macconf->ExtendedInterPacketGapVal << 25)|
- ((uint32_t)macconf->ExtendedInterPacketGap << 24)|
- ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18)|
- ((uint32_t)macconf->SlowProtocolDetect << 17)|
- ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U)<< 16) |
- macconf->GiantPacketSizeLimit);
+ macregval = ((macconf->ExtendedInterPacketGapVal << 25) |
+ ((uint32_t)macconf->ExtendedInterPacketGap << 24) |
+ ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) |
+ ((uint32_t)macconf->SlowProtocolDetect << 17) |
+ ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U) << 16) |
+ macconf->GiantPacketSizeLimit);
/* Write to MACECR */
MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
@@ -2455,8 +2814,8 @@ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *mac
/*------------------------ MACTFCR Configuration --------------------*/
macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
macconf->PauseLowThreshold |
- ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U)<< 7) |
- (macconf->PauseTime << 16));
+ ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7) |
+ (macconf->PauseTime << 16));
/* Write to MACTFCR */
MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval);
@@ -2475,8 +2834,8 @@ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *mac
/*------------------------ MTLRQOMR Configuration --------------------*/
macregval = (macconf->ReceiveQueueMode |
((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
- ((uint32_t)macconf->ForwardRxErrorPacket << 4) |
- ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3));
+ ((uint32_t)macconf->ForwardRxErrorPacket << 4) |
+ ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3));
/* Write to MTLRQOMR */
MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
@@ -2492,7 +2851,7 @@ static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dma
/*------------------------ DMASBMR Configuration --------------------*/
dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
dmaconf->BurstMode |
- ((uint32_t)dmaconf->RebuildINCRxBurst << 15));
+ ((uint32_t)dmaconf->RebuildINCRxBurst << 15));
MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
@@ -2504,8 +2863,8 @@ static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dma
/*------------------------ DMACTCR Configuration --------------------*/
dmaregval = (dmaconf->TxDMABurstLength |
- ((uint32_t)dmaconf->SecondPacketOperate << 4)|
- ((uint32_t)dmaconf->TCPSegmentation << 12));
+ ((uint32_t)dmaconf->SecondPacketOperate << 4) |
+ ((uint32_t)dmaconf->TCPSegmentation << 12));
MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval);
@@ -2584,62 +2943,12 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
dmaDefaultConf.SecondPacketOperate = DISABLE;
dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
dmaDefaultConf.TCPSegmentation = DISABLE;
- dmaDefaultConf.MaximumSegmentSize = 536;
+ dmaDefaultConf.MaximumSegmentSize = ETH_SEGMENT_SIZE_DEFAULT;
/* DMA default configuration */
ETH_SetDMAConfig(heth, &dmaDefaultConf);
}
-/**
- * @brief Configures the Clock range of SMI interface.
- * called by HAL_ETH_Init() API.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
- * the configuration information for ETHERNET module
- * @retval None
- */
-static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth)
-{
- uint32_t tmpreg, hclk;
-
- /* Get the ETHERNET MACMDIOAR value */
- tmpreg = (heth->Instance)->MACMDIOAR;
-
- /* Clear CSR Clock Range bits */
- tmpreg &= ~ETH_MACMDIOAR_CR;
-
- /* Get hclk frequency value */
- hclk = HAL_RCC_GetHCLKFreq();
-
- /* Set CR bits depending on hclk value */
- if((hclk >= 20000000U)&&(hclk < 35000000U))
- {
- /* CSR Clock Range between 20-35 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
- }
- else if((hclk >= 35000000U)&&(hclk < 60000000U))
- {
- /* CSR Clock Range between 35-60 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
- }
- else if((hclk >= 60000000U)&&(hclk < 100000000U))
- {
- /* CSR Clock Range between 60-100 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
- }
- else if((hclk >= 100000000U)&&(hclk < 150000000U))
- {
- /* CSR Clock Range between 100-150 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
- }
- else /* (hclk >= 150000000)&&(hclk <= 200000000) */
- {
- /* CSR Clock Range between 150-200 MHz */
- tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
- }
-
- /* Configure the CSR Clock Range */
- (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
-}
/**
* @brief Initializes the DMA Tx descriptors.
@@ -2654,7 +2963,7 @@ static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
uint32_t i;
/* Fill each DMATxDesc descriptor with the right values */
- for(i=0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
+ for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
{
dmatxdesc = heth->Init.TxDesc + i;
@@ -2664,12 +2973,13 @@ static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
WRITE_REG(dmatxdesc->DESC3, 0x0);
WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
+
}
heth->TxDescList.CurTxDesc = 0;
/* Set Transmit Descriptor Ring Length */
- WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT -1));
+ WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT - 1U));
/* Set Transmit Descriptor List Address */
WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
@@ -2690,7 +3000,7 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
ETH_DMADescTypeDef *dmarxdesc;
uint32_t i;
- for(i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
+ for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
{
dmarxdesc = heth->Init.RxDesc + i;
@@ -2701,24 +3011,26 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
+
/* Set Rx descritors addresses */
WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
+
}
- WRITE_REG(heth->RxDescList.CurRxDesc, 0);
- WRITE_REG(heth->RxDescList.FirstAppDesc, 0);
- WRITE_REG(heth->RxDescList.AppDescNbr, 0);
+ WRITE_REG(heth->RxDescList.RxDescIdx, 0);
+ WRITE_REG(heth->RxDescList.RxDescCnt, 0);
+ WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0);
+ WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0);
WRITE_REG(heth->RxDescList.ItMode, 0);
- WRITE_REG(heth->RxDescList.AppContextDesc, 0);
/* Set Receive Descriptor Ring Length */
- WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1)));
+ WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U)));
/* Set Receive Descriptor List Address */
WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
/* Set Receive Descriptor Tail pointer Address */
- WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1))));
+ WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1U))));
}
/**
@@ -2735,14 +3047,16 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
uint32_t descidx = dmatxdesclist->CurTxDesc;
uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
- uint32_t descnbr = 0, idx;
+ uint32_t idx;
+ uint32_t descnbr = 0;
ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer;
uint32_t bd_count = 0;
/* Current Tx Descriptor Owned by DMA: cannot be used by the application */
- if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL))
+ if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
+ || (dmatxdesclist->PacketAddress[descidx] != NULL))
{
return HAL_ETH_ERROR_BUSY;
}
@@ -2751,7 +3065,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
/***************** Context descriptor configuration (Optional) **********/
/***************************************************************************/
/* If VLAN tag is enabled for this packet */
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
+ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
{
/* Set vlan tag value */
MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);
@@ -2761,7 +3075,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
/* if inner VLAN is enabled */
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != 0U)
+ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != (uint32_t)RESET)
{
/* Set inner vlan tag value */
MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));
@@ -2779,7 +3093,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
}
/* if tcp segmentation is enabled for this packet */
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
+ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
{
/* Set MSS value */
MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);
@@ -2787,10 +3101,13 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);
}
- if((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)|| (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U))
+ if ((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
+ || (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET))
{
/* Set as context descriptor */
SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);
+ /* Ensure rest of descriptor is written to RAM before the OWN bit */
+ __DMB();
/* Set own bit */
SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
/* Increment current tx descriptor index */
@@ -2801,9 +3118,11 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
descnbr += 1U;
/* Current Tx Descriptor Owned by DMA: cannot be used by the application */
- if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
+ if (READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
{
dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
+ /* Ensure rest of descriptor is written to RAM before the OWN bit */
+ __DMB();
/* Clear own bit */
CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
@@ -2822,7 +3141,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
/* Set header or buffer 1 Length */
MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
- if(txbuffer->next != NULL)
+ if (txbuffer->next != NULL)
{
txbuffer = txbuffer->next;
/* Set buffer 2 address */
@@ -2837,7 +3156,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
}
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
+ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
{
/* Set TCP Header length */
MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));
@@ -2850,18 +3169,18 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
{
MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
+ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET)
{
MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
}
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U)
+ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)RESET)
{
MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);
}
}
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
+ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
{
/* Set Vlan Tag control */
MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);
@@ -2871,11 +3190,13 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
/* Mark it as NORMAL descriptor */
CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
+ /* Ensure rest of descriptor is written to RAM before the OWN bit */
+ __DMB();
/* set OWN bit of FIRST descriptor */
SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
/* If source address insertion/replacement is enabled for this packet */
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != 0U)
+ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != (uint32_t)RESET)
{
MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
}
@@ -2894,14 +3215,18 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
/* Current Tx Descriptor Owned by DMA: cannot be used by the application */
- if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL))
+ if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN)
+ || (dmatxdesclist->PacketAddress[descidx] != NULL))
{
descidx = firstdescidx;
dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
/* clear previous desc own bit */
- for(idx = 0; idx < descnbr; idx ++)
+ for (idx = 0; idx < descnbr; idx ++)
{
+ /* Ensure rest of descriptor is written to RAM before the OWN bit */
+ __DMB();
+
CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
/* Increment current tx descriptor index */
@@ -2939,7 +3264,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
}
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
+ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
{
/* Set TCP payload length */
MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
@@ -2951,7 +3276,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
/* Set the packet length */
MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
- if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
+ if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET)
{
/* Checksum Insertion Control */
MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
@@ -2959,13 +3284,16 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
}
bd_count += 1U;
+
+ /* Ensure rest of descriptor is written to RAM before the OWN bit */
+ __DMB();
/* Set Own bit */
SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
/* Mark it as NORMAL descriptor */
CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
}
- if(ItMode != ((uint32_t)RESET))
+ if (ItMode != ((uint32_t)RESET))
{
/* Set Interrupt on completion bit */
SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
@@ -3002,8 +3330,7 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
/* Init the ETH Callback settings */
heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */
heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */
- heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback; /* Legacy weak DMAErrorCallback */
- heth->MACErrorCallback = HAL_ETH_MACErrorCallback; /* Legacy weak MACErrorCallback */
+ heth->ErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak ErrorCallback */
heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */
heth->EEECallback = HAL_ETH_EEECallback; /* Legacy weak EEECallback */
heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c
index 46c6a5f324..ad9870c037 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c
@@ -3,6 +3,7 @@
* @file stm32h7xx_hal_eth_ex.c
* @author MCD Application Team
* @brief ETH HAL Extended module driver.
+ *
******************************************************************************
* @attention
*
@@ -69,7 +70,7 @@
/** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
- *
+ *
@verbatim
===============================================================================
##### Extended features functions #####
@@ -131,25 +132,26 @@ void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
* that contains L4 filter configuration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter , ETH_L4FilterConfigTypeDef *pL4FilterConfig)
+HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+ ETH_L4FilterConfigTypeDef *pL4FilterConfig)
{
__IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
- if(pL4FilterConfig == NULL)
+ if (pL4FilterConfig == NULL)
{
return HAL_ERROR;
}
/* Write configuration to (MACL3L4C0R + filter )register */
- MODIFY_REG(*configreg, ETH_MACL4CR_MASK ,(pL4FilterConfig->Protocol |
+ MODIFY_REG(*configreg, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
pL4FilterConfig->SrcPortFilterMatch |
- pL4FilterConfig->DestPortFilterMatch));
+ pL4FilterConfig->DestPortFilterMatch));
configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
/* Write configuration to (MACL4A0R + filter )register */
- MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP) , (pL4FilterConfig->SourcePort |
- (pL4FilterConfig->DestinationPort << 16)));
+ MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP), (pL4FilterConfig->SourcePort |
+ (pL4FilterConfig->DestinationPort << 16)));
/* Enable L4 filter */
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
@@ -170,20 +172,25 @@ HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t
* that contains L4 filter configuration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
+HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+ ETH_L4FilterConfigTypeDef *pL4FilterConfig)
{
- if(pL4FilterConfig == NULL)
+ if (pL4FilterConfig == NULL)
{
return HAL_ERROR;
}
/* Get configuration to (MACL3L4C0R + filter )register */
- pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L4PEN);
- pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
- pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
+ pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+ ETH_MACL3L4CR_L4PEN);
+ pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+ (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
+ pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+ (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
/* Get configuration to (MACL3L4C0R + filter )register */
- pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4DP) >> 16);
+ pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)),
+ ETH_MACL4AR_L4DP) >> 16);
pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP);
return HAL_OK;
@@ -202,11 +209,12 @@ HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t
* that contains L3 filter configuration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
+HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+ ETH_L3FilterConfigTypeDef *pL3FilterConfig)
{
__IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
- if(pL3FilterConfig == NULL)
+ if (pL3FilterConfig == NULL)
{
return HAL_ERROR;
}
@@ -214,12 +222,12 @@ HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t
/* Write configuration to (MACL3L4C0R + filter )register */
MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
pL3FilterConfig->SrcAddrFilterMatch |
- pL3FilterConfig->DestAddrFilterMatch |
- (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
- (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
+ pL3FilterConfig->DestAddrFilterMatch |
+ (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
+ (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
/* Check if IPv6 protocol is selected */
- if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+ if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
{
/* Set the IPv6 address match */
/* Set Bits[31:0] of 128-bit IP addr */
@@ -255,20 +263,26 @@ HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t
* that will contain the L3 filter configuration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
+HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+ ETH_L3FilterConfigTypeDef *pL3FilterConfig)
{
- if(pL3FilterConfig == NULL)
+ if (pL3FilterConfig == NULL)
{
return HAL_ERROR;
}
- pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3PEN);
- pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
- pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
- pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HSBM) >> 6);
- pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HDBM) >> 11);
-
- if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+ pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+ ETH_MACL3L4CR_L3PEN);
+ pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+ (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
+ pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+ (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
+ pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+ ETH_MACL3L4CR_L3HSBM) >> 6);
+ pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+ ETH_MACL3L4CR_L3HDBM) >> 11);
+
+ if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
{
pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
@@ -318,20 +332,25 @@ void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
*/
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
{
- if(pVlanConfig == NULL)
+ if (pVlanConfig == NULL)
{
return HAL_ERROR;
}
- pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR,
+ ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
pVlanConfig->StripInnerVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
- pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
- pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR,
+ ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR,
+ ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
- pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
- pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR,
+ (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
+ pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U)
+ ? DISABLE : ENABLE;
return HAL_OK;
}
@@ -346,7 +365,7 @@ HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANC
*/
HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
{
- if(pVlanConfig == NULL)
+ if (pVlanConfig == NULL)
{
return HAL_ERROR;
}
@@ -354,13 +373,13 @@ HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANC
/* Write config to MACVTR */
MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) |
pVlanConfig->StripInnerVLANTag |
- ((uint32_t)pVlanConfig->InnerVLANTag << 27) |
- ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
- ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
- ((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
- pVlanConfig->StripVLANTag |
- pVlanConfig->VLANTypeCheck |
- ((uint32_t)pVlanConfig->VLANTagInverceMatch << 17)));
+ ((uint32_t)pVlanConfig->InnerVLANTag << 27) |
+ ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
+ ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
+ ((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
+ pVlanConfig->StripVLANTag |
+ pVlanConfig->VLANTypeCheck |
+ ((uint32_t)pVlanConfig->VLANTagInverceMatch << 17)));
return HAL_OK;
}
@@ -388,14 +407,15 @@ void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
* that will contain the Tx VLAN filter configuration.
* @retval HAL Status.
*/
-HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
+HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
+ ETH_TxVLANConfigTypeDef *pVlanConfig)
{
if (pVlanConfig == NULL)
{
return HAL_ERROR;
}
- if(VLANTag == ETH_INNER_TX_VLANTAG)
+ if (VLANTag == ETH_INNER_TX_VLANTAG)
{
pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
@@ -422,13 +442,14 @@ HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL
* that contains Tx VLAN filter configuration.
* @retval HAL Status
*/
-HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
+HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
+ ETH_TxVLANConfigTypeDef *pVlanConfig)
{
- if(VLANTag == ETH_INNER_TX_VLANTAG)
+ if (VLANTag == ETH_INNER_TX_VLANTAG)
{
MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
- ((uint32_t)pVlanConfig->SVLANType << 19) |
- pVlanConfig->VLANTagControl));
+ ((uint32_t)pVlanConfig->SVLANType << 19) |
+ pVlanConfig->VLANTagControl));
/* Enable Double VLAN processing */
SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
}
@@ -436,7 +457,7 @@ HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL
{
MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
((uint32_t)pVlanConfig->SVLANType << 19) |
- pVlanConfig->VLANTagControl));
+ pVlanConfig->VLANTagControl));
}
return HAL_OK;
@@ -452,9 +473,9 @@ HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL
* @param VLANIdentifier: VLAN Identifier 16 bit value
* @retval None
*/
-void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier)
+void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier)
{
- if(VLANTag == ETH_INNER_TX_VLANTAG)
+ if (VLANTag == ETH_INNER_TX_VLANTAG)
{
MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier);
}
@@ -502,9 +523,10 @@ void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate,
__HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE);
/* Write to LPI Control register: Enter low power mode */
- MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), (((uint32_t)TxAutomate << 19) |
- ((uint32_t)TxClockStop << 21) |
- ETH_MACLCSR_LPIEN));
+ MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE),
+ (((uint32_t)TxAutomate << 19) |
+ ((uint32_t)TxClockStop << 21) |
+ ETH_MACLCSR_LPIEN));
}
/**
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
index 7306fc474b..950ea150eb 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c
@@ -5264,6 +5264,10 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
uint32_t TTFatalErrors;
uint32_t SWTime;
uint32_t SWCycleCount;
+ uint32_t itsourceIE;
+ uint32_t itsourceTTIE;
+ uint32_t itflagIR;
+ uint32_t itflagTTIR;
ClkCalibrationITs = (FDCAN_CCU->IR << 30);
ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
@@ -5277,11 +5281,13 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
Errors &= hfdcan->Instance->IE;
ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
ErrorStatusITs &= hfdcan->Instance->IE;
+ itsourceIE = hfdcan->Instance->IE;
+ itflagIR = hfdcan->Instance->IR;
/* High Priority Message interrupt management *******************************/
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U)
+ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET)
{
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U)
+ if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET)
{
/* Clear the High Priority Message flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
@@ -5297,9 +5303,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* Transmission Abort interrupt management **********************************/
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
{
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U)
+ if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET)
{
/* List of aborted monitored buffers */
AbortedBuffers = hfdcan->Instance->TXBCF;
@@ -5379,9 +5385,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* Tx FIFO empty interrupt management ***************************************/
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U)
+ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_FIFO_EMPTY) != RESET)
{
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U)
+ if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET)
{
/* Clear the Tx FIFO empty flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
@@ -5397,9 +5403,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* Transmission Complete interrupt management *******************************/
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U)
+ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_COMPLETE) != RESET)
{
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U)
+ if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_COMPLETE) != RESET)
{
/* List of transmitted monitored buffers */
TransmittedBuffers = hfdcan->Instance->TXBTO;
@@ -5419,9 +5425,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* Rx Buffer New Message interrupt management *******************************/
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != 0U)
+ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET)
{
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != 0U)
+ if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET)
{
/* Clear the Rx Buffer New Message flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
@@ -5437,9 +5443,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* Timestamp Wraparound interrupt management ********************************/
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U)
+ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET)
{
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U)
+ if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET)
{
/* Clear the Timestamp Wraparound flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
@@ -5455,9 +5461,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* Timeout Occurred interrupt management ************************************/
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U)
+ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMEOUT_OCCURRED) != RESET)
{
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U)
+ if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET)
{
/* Clear the Timeout Occurred flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
@@ -5473,9 +5479,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* Message RAM access failure interrupt management **************************/
- if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U)
+ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET)
{
- if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U)
+ if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET)
{
/* Clear the Message RAM access failure flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
@@ -5524,6 +5530,8 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
TTDistErrors &= hfdcan->ttcan->TTIE;
TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
TTFatalErrors &= hfdcan->ttcan->TTIE;
+ itsourceTTIE = hfdcan->ttcan->TTIE;
+ itflagTTIR = hfdcan->ttcan->TTIR;
/* TT Schedule Synchronization interrupts management **********************/
if (TTSchedSyncITs != 0U)
@@ -5556,9 +5564,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
}
/* TT Stop Watch interrupt management *************************************/
- if (__HAL_FDCAN_TT_GET_IT_SOURCE(hfdcan, FDCAN_TT_IT_STOP_WATCH) != 0U)
+ if (FDCAN_CHECK_IT_SOURCE(itsourceTTIE, FDCAN_TT_IT_STOP_WATCH) != RESET)
{
- if (__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH) != 0U)
+ if (FDCAN_CHECK_FLAG(itflagTTIR, FDCAN_TT_FLAG_STOP_WATCH) != RESET)
{
/* Retrieve Stop watch Time and Cycle count */
SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos);
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c
index 13b6521eec..6182ab4f2a 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c
@@ -1240,22 +1240,12 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
}
- else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
+ else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) ||
+ (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC))
{
USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
hhcd->hc[ch_num].urb_state = URB_DONE;
-#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
- hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
-#else
- HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
-#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
- }
- else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)
- {
- hhcd->hc[ch_num].urb_state = URB_DONE;
- hhcd->hc[ch_num].toggle_in ^= 1U;
-
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#else
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c
index eb1233cd97..ac9a8dc51c 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c
@@ -1530,7 +1530,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
/* Enable the Rx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr,
- hi2s->RxXferCount))
+ hi2s->RxXferCount))
{
/* Update I2S error code */
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
@@ -1922,8 +1922,8 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
/* I2S Underrun error interrupt occurred --------------------------------*/
if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR))
{
- /* Disable TXP and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
+ /* Disable TXP, RXP and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR));
/* Clear Underrun flag */
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
@@ -1944,8 +1944,8 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
/* I2S Overrun error interrupt occurred -------------------------------------*/
if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR))
{
- /* Disable RXP and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
+ /* Disable TXP, RXP and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR));
/* Clear Overrun flag */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c
index 16bcdfc848..afaaa3eeb8 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c
@@ -469,7 +469,7 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
* @brief Start the LPTIM PWM generation.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
@@ -517,7 +517,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -534,7 +534,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- /* Set the LPTIM state */
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
@@ -545,7 +545,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
return HAL_TIMEOUT;
}
- /* Change the LPTIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -556,7 +556,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
* @brief Start the LPTIM PWM generation in interrupt mode.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF
+ * This parameter must be a value between 0x0001 and 0xFFFF
* @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF
* @retval HAL status
@@ -634,7 +634,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -651,7 +651,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
- /* Set the LPTIM state */
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
@@ -681,7 +681,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
}
- /* Change the LPTIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -692,7 +692,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
* @brief Start the LPTIM One pulse generation.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
@@ -740,7 +740,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -768,7 +768,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
return HAL_TIMEOUT;
}
- /* Change the LPTIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -779,7 +779,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
* @brief Start the LPTIM One pulse generation in interrupt mode.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
@@ -857,7 +857,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -877,6 +877,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@@ -904,7 +905,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
}
- /* Change the LPTIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -915,7 +916,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
* @brief Start the LPTIM in Set once mode.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
@@ -963,7 +964,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -991,7 +992,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
return HAL_TIMEOUT;
}
- /* Change the LPTIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1080,7 +1081,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1127,7 +1128,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
}
- /* Change the LPTIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1138,7 +1139,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
* @brief Start the Encoder interface.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
@@ -1188,7 +1189,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1219,7 +1220,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
/* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1298,7 +1299,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1335,7 +1336,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable "switch to up direction" interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1348,7 +1349,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
* trigger event will reset the counter and the timer restarts.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @param Timeout Specifies the TimeOut value to reset the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
@@ -1396,7 +1397,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1427,7 +1428,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
/* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1440,7 +1441,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
* trigger event will reset the counter and the timer restarts.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @param Timeout Specifies the TimeOut value to reset the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
@@ -1502,7 +1503,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1536,7 +1537,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable Compare match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1547,7 +1548,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
* @brief Start the Counter mode.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
@@ -1587,7 +1588,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1615,7 +1616,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
return HAL_TIMEOUT;
}
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1626,7 +1627,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
* @brief Start the Counter mode in interrupt mode.
* @param hlptim LPTIM handle
* @param Period Specifies the Autoreload value.
- * This parameter must be a value between 0x0000 and 0xFFFF.
+ * This parameter must be a value between 0x0001 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
@@ -1683,7 +1684,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
@@ -1716,7 +1717,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable Autoreload match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
- /* Change the TIM state*/
+ /* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c
index 5f2b79baeb..cbead1ee7b 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c
@@ -178,6 +178,7 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+#define LTDC_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -211,7 +212,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
*/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
{
- uint32_t tmp, tmp1;
+ uint32_t tmp;
+ uint32_t tmp1;
/* Check the LTDC peripheral state */
if (hltdc == NULL)
@@ -320,6 +322,44 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
{
+ uint32_t tickstart;
+
+ /* Check the LTDC peripheral state */
+ if (hltdc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
+
+ /* Disable LTDC Layer 1 */
+ __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_1);
+
+#if defined(LTDC_Layer2_BASE)
+ /* Disable LTDC Layer 2 */
+ __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_2);
+#endif /* LTDC_Layer2_BASE */
+
+ /* Reload during vertical blanking period */
+ __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(hltdc);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for VSYNC Interrupt */
+ while (READ_BIT(hltdc->Instance->CDSR, LTDC_CDSR_VSYNCS) == 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > LTDC_TIMEOUT_VALUE)
+ {
+ break;
+ }
+ }
+
+ /* Disable LTDC */
+ __HAL_LTDC_DISABLE(hltdc);
+
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
if (hltdc->MspDeInitCallback == NULL)
{
@@ -391,7 +431,8 @@ __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc)
* @param pCallback pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID,
+ pLTDC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -473,7 +514,7 @@ HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_
/**
* @brief Unregister an LTDC Callback
- * LTDC callabck is redirected to the weak predefined callback
+ * LTDC callback is redirected to the weak predefined callback
* @param hltdc ltdc handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -887,11 +928,13 @@ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT
{
if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
{
- tmp = (((counter + (16U*counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
+ tmp = (((counter + (16U * counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \
+ ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
}
else
{
- tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
+ tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \
+ ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
}
pcolorlut++;
@@ -1345,12 +1388,14 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres
}
/**
- * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
- * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
- * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
- * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
- * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
- * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+ * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width
+ * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to
+ * layer for which we want to read and display on screen only a portion 320x240 taken in the center
+ * of the buffer.
+ * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous
+ * call to HAL_LTDC_ConfigLayer().
+ * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default
+ * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
@@ -1504,7 +1549,8 @@ HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadTyp
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg,
+ uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
@@ -1553,7 +1599,8 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize,
+ uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
@@ -1607,7 +1654,8 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0,
+ uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
@@ -1774,12 +1822,14 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32
}
/**
- * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
- * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
- * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
- * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
- * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
- * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+ * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width
+ * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to
+ * layer for which we want to read and display on screen only a portion 320x240 taken in the center
+ * of the buffer.
+ * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by
+ * previous call to HAL_LTDC_ConfigLayer().
+ * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default
+ * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
* Variant of the function HAL_LTDC_SetPitch without immediate reload.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
@@ -2082,7 +2132,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
/* Configure the horizontal start and stop position */
tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
- LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
+ LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
+ ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
/* Configure the vertical start and stop position */
tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
@@ -2097,7 +2148,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
tmp2 = (pLayerCfg->Alpha0 << 24U);
- LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
+ LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED |
+ LTDC_LxDCCR_DCALPHA);
LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
/* Specifies the constant alpha value */
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c
index b299937fc2..ec4bf02b2e 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c
@@ -75,7 +75,8 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
/* Note 1 : Code in line w/ Current LTDC specification */
- hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
+ hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \
+ DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
@@ -87,8 +88,10 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc
/* Retrieve vertical timing parameters from DSI */
hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U;
hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
- hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U;
- hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
+ hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
+ VidCfg->VerticalActive - 1U;
+ hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
+ VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
return HAL_OK;
}
@@ -113,7 +116,8 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD
LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
/* Note 1 : Code in line w/ Current LTDC specification */
- hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
+ hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \
+ DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c
index 3e5714895e..880a9e828b 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c
@@ -64,7 +64,7 @@
SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
This function provide the following operations:
- (#) Initialize the SDMMC peripheral interface with defaullt configuration.
+ (#) Initialize the SDMMC peripheral interface with default configuration.
The initialization process is done at 400KHz. You can change or adapt
this frequency by adjusting the "ClockDiv" field.
The MMC Card frequency (SDMMC_CK) is computed as follows:
@@ -3214,7 +3214,7 @@ HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc)
sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX / 4)] >>
MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS) & 0x000000FFU);
- /* Sleep/Awake Timeout = 10µs * 2^SLEEP_NOTIFICATION_TIME */
+ /* Sleep/Awake Timeout = 10us * 2^SLEEP_NOTIFICATION_TIME */
/* In HAL, the tick interrupt occurs each ms */
if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
{
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c
index 3454bb109f..2780e99c98 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c
@@ -302,21 +302,21 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
deviceaddress = NOR_MEMORY_ADRESS4;
}
- FMC_NORSRAM_WriteOperation_Enable(hnor->Instance,hnor->Init.NSBank);
-
- /* Get the value of the command set */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
- hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
-
- status = HAL_NOR_ReturnToReadMode(hnor);
-
if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE)
{
- FMC_NORSRAM_WriteOperation_Disable(hnor->Instance,hnor->Init.NSBank);
+ (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_PROTECTED;
}
+ else
+ {
+ /* Get the value of the command set */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+ hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
+
+ status = HAL_NOR_ReturnToReadMode(hnor);
+ }
return status;
}
@@ -441,7 +441,11 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
{
return HAL_BUSY;
}
- else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ else if (state == HAL_NOR_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+ else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -528,7 +532,11 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
{
return HAL_BUSY;
}
- else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ else if (state == HAL_NOR_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+ else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -602,7 +610,11 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
{
return HAL_BUSY;
}
- else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ else if (state == HAL_NOR_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+ else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -771,7 +783,11 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
{
return HAL_BUSY;
}
- else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ else if (state == HAL_NOR_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+ else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -1131,7 +1147,11 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
{
return HAL_BUSY;
}
- else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ else if (state == HAL_NOR_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+ else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c
index 62cfcbb618..d009ee1c1e 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c
@@ -365,7 +365,7 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting));
assert_param(IS_OSPI_DHQC (hospi->Init.DelayHoldQuarterCycle));
assert_param(IS_OSPI_CS_BOUNDARY (hospi->Init.ChipSelectBoundary));
- assert_param(IS_OSPI_CKCSHT (hospi->Init.ClkChipSelectHighTime));
+ assert_param(IS_OSPI_DLYBYP (hospi->Init.DelayBlockBypass));
assert_param(IS_OSPI_MAXTRAN (hospi->Init.MaxTran));
/* Initialize error code */
@@ -402,13 +402,14 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
/* Configure the default timeout for the OSPI memory access */
(void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
- /* Configure memory type, device size, chip select high time, clocked chip select high time, free running clock, clock mode */
+ /* Configure memory type, device size, chip select high time, delay block bypass,
+ free running clock, clock mode */
MODIFY_REG(hospi->Instance->DCR1,
- (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_CKCSHT |
+ (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_DLYBYP |
OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE),
(hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) |
((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) |
- (hospi->Init.ClkChipSelectHighTime << OCTOSPI_DCR1_CKCSHT_Pos) | hospi->Init.ClockMode));
+ hospi->Init.DelayBlockBypass | hospi->Init.ClockMode));
/* Configure wrap size */
MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize);
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c
index eb1929093b..af78206b19 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c
@@ -85,7 +85,7 @@
weak function.
[..]
- HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : OTFDEC error callback
@@ -97,11 +97,11 @@
all callbacks are set to the corresponding weak functions:
example HAL_OTFDEC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the HAL_OTFDEC_Init()/ HAL_OTFDEC_DeInit() only when
+ reset to the legacy weak functions in the HAL_OTFDEC_Init()HAL_OTFDEC_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
- If MspInit or MspDeInit are not null, the HAL_OTFDEC_Init()/ HAL_OTFDEC_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_OTFDEC_Init()/HAL_OTFDEC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
@@ -121,6 +121,7 @@
are set to the corresponding weak functions.
@endverbatim
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -147,16 +148,14 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
-
- /* Exported functions --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @addtogroup OTFDEC_Exported_Functions
* @{
*/
/** @defgroup OTFDEC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -175,7 +174,7 @@
HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec)
{
/* Check the OTFDEC handle allocation */
- if(hotfdec == NULL)
+ if (hotfdec == NULL)
{
return HAL_ERROR;
}
@@ -183,7 +182,7 @@ HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec)
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
- if(hotfdec->State == HAL_OTFDEC_STATE_RESET)
+ if (hotfdec->State == HAL_OTFDEC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
__HAL_UNLOCK(hotfdec);
@@ -221,7 +220,7 @@ HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec)
HAL_StatusTypeDef HAL_OTFDEC_DeInit(OTFDEC_HandleTypeDef *hotfdec)
{
/* Check the OTFDEC handle allocation */
- if(hotfdec == NULL)
+ if (hotfdec == NULL)
{
return HAL_ERROR;
}
@@ -456,8 +455,8 @@ HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, H
*/
/** @defgroup OTFDEC_Exported_Functions_Group2 OTFDEC IRQ handler management
- * @brief OTFDEC IRQ handler.
- *
+ * @brief OTFDEC IRQ handler.
+ *
@verbatim
==============================================================================
##### OTFDEC IRQ handler management #####
@@ -481,17 +480,17 @@ void HAL_OTFDEC_IRQHandler(OTFDEC_HandleTypeDef *hotfdec)
isr_reg = READ_REG(hotfdec->Instance->ISR);
if ((isr_reg & OTFDEC_ISR_SEIF) == OTFDEC_ISR_SEIF)
{
- SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_SEIF );
+ SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_SEIF);
hotfdec->ErrorCode |= HAL_OTFDEC_SECURITY_ERROR;
}
if ((isr_reg & OTFDEC_ISR_XONEIF) == OTFDEC_ISR_XONEIF)
{
- SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_XONEIF );
+ SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_XONEIF);
hotfdec->ErrorCode |= HAL_OTFDEC_EXECUTE_ERROR;
}
if ((isr_reg & OTFDEC_ISR_KEIF) == OTFDEC_ISR_KEIF)
{
- SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_KEIF );
+ SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_KEIF);
hotfdec->ErrorCode |= HAL_OTFDEC_KEY_ERROR;
}
@@ -526,8 +525,8 @@ __weak void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec)
/** @defgroup OTFDEC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral control functions.
- *
+ * @brief Peripheral control functions.
+ *
@verbatim
==============================================================================
##### Peripheral Control functions #####
@@ -549,7 +548,7 @@ __weak void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec)
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
{
- OTFDEC_Region_TypeDef * region;
+ OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
@@ -559,10 +558,10 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32
/* Take Lock */
__HAL_LOCK(hotfdec);
- address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
- SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_KEYLOCK );
+ SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_KEYLOCK);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
@@ -583,7 +582,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey)
{
- OTFDEC_Region_TypeDef * region;
+ OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
@@ -599,26 +598,26 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_
/* Take Lock */
__HAL_LOCK(hotfdec);
- address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
/* Set Key */
- WRITE_REG( region->REG_KEYR0, pKey[0]);
+ WRITE_REG(region->REG_KEYR0, pKey[0]);
__DSB();
__ISB();
- WRITE_REG( region->REG_KEYR1, pKey[1]);
+ WRITE_REG(region->REG_KEYR1, pKey[1]);
__DSB();
__ISB();
- WRITE_REG( region->REG_KEYR2, pKey[2]);
+ WRITE_REG(region->REG_KEYR2, pKey[2]);
__DSB();
__ISB();
- WRITE_REG( region->REG_KEYR3, pKey[3]);
+ WRITE_REG(region->REG_KEYR3, pKey[3]);
/* Compute theoretically expected CRC and compare it with that reported by the peripheral */
if (HAL_OTFDEC_KeyCRCComputation(pKey) != HAL_OTFDEC_RegionGetKeyCRC(hotfdec, RegionIndex))
@@ -656,7 +655,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode)
{
- OTFDEC_Region_TypeDef * region;
+ OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
@@ -667,7 +666,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32
/* Take Lock */
__HAL_LOCK(hotfdec);
- address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
/* Set mode */
@@ -696,7 +695,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32
HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
OTFDEC_RegionConfigTypeDef *Config, uint32_t lock)
{
- OTFDEC_Region_TypeDef * region;
+ OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
@@ -714,30 +713,30 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_
/* Take Lock */
__HAL_LOCK(hotfdec);
- address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
/* Set Nonce */
- WRITE_REG( region->REG_NONCER0, Config->Nonce[0]);
+ WRITE_REG(region->REG_NONCER0, Config->Nonce[0]);
- WRITE_REG( region->REG_NONCER1, Config->Nonce[1]);
+ WRITE_REG(region->REG_NONCER1, Config->Nonce[1]);
/* Write region protected area start and end addresses */
- WRITE_REG( region->REG_START_ADDR, Config->StartAddress);
+ WRITE_REG(region->REG_START_ADDR, Config->StartAddress);
- WRITE_REG( region->REG_END_ADDR, Config->EndAddress);
+ WRITE_REG(region->REG_END_ADDR, Config->EndAddress);
/* Write Version */
- MODIFY_REG( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION,
- (uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos );
+ MODIFY_REG(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION,
+ (uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos);
/* Enable region deciphering or enciphering (depending of OTFDEC_CR ENC bit setting) */
- SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
+ SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
/* Lock the region configuration according to lock parameter value */
if (lock == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
{
- SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE);
+ SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE);
}
/* Release Lock */
@@ -763,7 +762,7 @@ uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey)
uint32_t j;
uint32_t keyval;
uint32_t k;
- uint32_t * temp = pKey;
+ uint32_t *temp = pKey;
for (j = 0U; j < 4U; j++)
{
@@ -781,15 +780,15 @@ uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey)
crc = 0;
for (i = 0; i < (uint8_t)32; i++)
{
- k = ((((uint32_t)crc >> 7) ^ ((keyval >> ((uint8_t)31-i))&((uint8_t)0xF)))) & 1U;
+ k = ((((uint32_t)crc >> 7) ^ ((keyval >> ((uint8_t)31 - i)) & ((uint8_t)0xF)))) & 1U;
crc <<= 1;
if (k != 0U)
{
crc ^= crc7_poly;
- }
+ }
}
- crc^=(uint8_t)0x55;
+ crc ^= (uint8_t)0x55;
}
return (uint32_t) crc;
@@ -806,7 +805,7 @@ uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey)
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
{
- OTFDEC_Region_TypeDef * region;
+ OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
@@ -816,19 +815,19 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_
/* Take Lock */
__HAL_LOCK(hotfdec);
- address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
- if (READ_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
+ if (READ_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
{
/* Configuration is locked, REG_EN bit can't be modified */
__HAL_UNLOCK(hotfdec);
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Enable region processing */
- SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
+ SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
@@ -847,7 +846,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
{
- OTFDEC_Region_TypeDef * region;
+ OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
@@ -857,19 +856,19 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32
/* Take Lock */
__HAL_LOCK(hotfdec);
- address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
- if (READ_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
+ if (READ_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
{
/* Configuration is locked, REG_EN bit can't be modified */
__HAL_UNLOCK(hotfdec);
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Disable region processing */
- CLEAR_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
+ CLEAR_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
@@ -883,8 +882,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32
*/
/** @defgroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions
- * @brief Peripheral State functions.
- *
+ * @brief Peripheral State functions.
+ *
@verbatim
==============================================================================
##### Peripheral State functions #####
@@ -917,7 +916,7 @@ HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec)
*/
uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
{
- OTFDEC_Region_TypeDef * region;
+ OTFDEC_Region_TypeDef *region;
uint32_t address;
uint32_t keycrc;
@@ -925,10 +924,10 @@ uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t Regi
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
- address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
- keycrc = (READ_REG( region->REG_CONFIGR )) & OTFDEC_REG_CONFIGR_KEYCRC;
+ keycrc = (READ_REG(region->REG_CONFIGR)) & OTFDEC_REG_CONFIGR_KEYCRC;
keycrc >>= OTFDEC_REG_CONFIGR_KEYCRC_Pos;
@@ -946,7 +945,7 @@ uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t Regi
HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
OTFDEC_RegionConfigTypeDef *Config)
{
- OTFDEC_Region_TypeDef * region;
+ OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
@@ -962,7 +961,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint
/* Take Lock */
__HAL_LOCK(hotfdec);
- address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+ address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
/* Read Nonce */
@@ -975,7 +974,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint
/* Read Version */
Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) &
- OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos;
+ OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos;
/* Release Lock */
__HAL_UNLOCK(hotfdec);
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c
index 1f9eae383e..3695b21a4b 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c
@@ -422,7 +422,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
/**
* @brief Unregister an USB PCD Callback
- * USB PCD callabck is redirected to the weak predefined callback
+ * USB PCD callback is redirected to the weak predefined callback
* @param hpcd USB PCD handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1061,7 +1061,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
uint32_t epint;
uint32_t epnum;
uint32_t fifoemptymsk;
- uint32_t temp;
+ uint32_t RegVal;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
@@ -1072,6 +1072,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
return;
}
+ /* store current frame number */
+ hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos;
+
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
{
/* incorrect mode, acknowledge the interrupt */
@@ -1083,25 +1086,25 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
- temp = USBx->GRXSTSP;
+ RegVal = USBx->GRXSTSP;
- ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
+ ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM];
- if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
+ if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
{
- if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
+ if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U)
{
(void)USB_ReadPacket(USBx, ep->xfer_buff,
- (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
+ (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4));
- ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
+ ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
}
}
- else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
+ else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
{
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
}
else
{
@@ -1142,6 +1145,30 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
}
+ /* Clear OUT Endpoint disable interrupt */
+ if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD)
+ {
+ if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF)
+ {
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
+ }
+
+ ep = &hpcd->OUT_ep[epnum];
+
+ if (ep->is_iso_incomplete == 1U)
+ {
+ ep->is_iso_incomplete = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+
+ CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD);
+ }
+
/* Clear Status Phase Received interrupt */
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
@@ -1212,6 +1239,20 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
{
(void)USB_FlushTxFifo(USBx, epnum);
+
+ ep = &hpcd->IN_ep[epnum];
+
+ if (ep->is_iso_incomplete == 1U)
+ {
+ ep->is_iso_incomplete = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+ HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
}
if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
@@ -1373,18 +1414,37 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
}
+ /* Handle Global OUT NAK effective Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF))
+ {
+ USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM;
+
+ for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
+ {
+ if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U)
+ {
+ /* Abort current transaction and disable the EP */
+ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum);
+ }
+ }
+ }
+
/* Handle Incomplete ISO IN Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
{
- /* Keep application checking the corresponding Iso IN endpoint
- causing the incomplete Interrupt */
- epnum = 0U;
+ for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
+ {
+ RegVal = USBx_INEP(epnum)->DIEPCTL;
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
-#else
- HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
+ ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA))
+ {
+ hpcd->IN_ep[epnum].is_iso_incomplete = 1U;
+
+ /* Abort current transaction and disable the EP */
+ (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U));
+ }
+ }
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
}
@@ -1392,15 +1452,25 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Handle Incomplete ISO OUT Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
- /* Keep application checking the corresponding Iso OUT endpoint
- causing the incomplete Interrupt */
- epnum = 0U;
+ for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
+ {
+ RegVal = USBx_OUTEP(epnum)->DOEPCTL;
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
-#else
- HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
+ ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
+ ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U)))
+ {
+ hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
+
+ USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM;
+
+ if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U)
+ {
+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
+ break;
+ }
+ }
+ }
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
@@ -1420,9 +1490,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* Handle Disconnection event Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
{
- temp = hpcd->Instance->GOTGINT;
+ RegVal = hpcd->Instance->GOTGINT;
- if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
+ if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DisconnectCallback(hpcd);
@@ -1430,7 +1500,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
HAL_PCD_DisconnectCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
- hpcd->Instance->GOTGINT |= temp;
+ hpcd->Instance->GOTGINT |= RegVal;
}
}
}
@@ -2033,7 +2103,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
/**
* @brief Set the USB Device high speed test mode.
* @param hpcd PCD handle
- * @param address test mode
+ * @param testmode USB Device high speed test mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode)
@@ -2048,7 +2118,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode)
case TEST_SE0_NAK:
case TEST_PACKET:
case TEST_FORCE_EN:
- USBx_DEVICE->DCTL |= testmode << 4;
+ USBx_DEVICE->DCTL |= (uint32_t)testmode << 4;
break;
default:
@@ -2138,6 +2208,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
*/
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
+ USB_OTG_EPTypeDef *ep;
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
@@ -2168,18 +2239,24 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint
}
else
{
- /* out data packet received over EP0 */
- hpcd->OUT_ep[epnum].xfer_count =
- hpcd->OUT_ep[epnum].maxpacket -
- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
+ ep = &hpcd->OUT_ep[epnum];
- hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
+ /* out data packet received over EP */
+ ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
- if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+ if (epnum == 0U)
{
- /* this is ZLP, so prepare EP0 for next setup */
- (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ if (ep->xfer_len == 0U)
+ {
+ /* this is ZLP, so prepare EP0 for next setup */
+ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+ }
+ else
+ {
+ ep->xfer_buff += ep->xfer_count;
+ }
}
+
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c
index 34f25ff152..58dc661cda 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c
@@ -163,26 +163,10 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
/* Enable DCD : Data Contact Detect */
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
- /* Wait Detect flag or a timeout is happen */
- while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
- {
- /* Check for the Timeout */
- if ((HAL_GetTick() - tickstart) > 1000U)
- {
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
-#else
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
- return;
- }
- }
-
- /* Right response got */
- HAL_Delay(200U);
+ /* Wait for Min DCD Timeout */
+ HAL_Delay(300U);
- /* Check Detect flag*/
+ /* Check Detect flag */
if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
@@ -192,7 +176,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
- /*Primary detection: checks if connected to Standard Downstream Port
+ /* Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
HAL_Delay(50U);
@@ -228,7 +212,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
}
else
{
- /* case Charging Downstream Port */
+ /* case Charging Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#else
@@ -240,11 +224,23 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
/* Battery Charging capability discovery finished */
(void)HAL_PCDEx_DeActivateBCD(hpcd);
+ /* Check for the Timeout, else start USB Device */
+ if ((HAL_GetTick() - tickstart) > 1000U)
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ else
+ {
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+ hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#else
- HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
}
/**
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c
index 0a7dfa47af..91f8b3a0b9 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c
@@ -2176,25 +2176,33 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
}
}
- /* Configure QSPI: CR register with Abort request */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+ if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
+ {
+ /* Configure QSPI: CR register with Abort request */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
- /* Wait until TC flag is set to go back in idle state */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
+ /* Wait until TC flag is set to go back in idle state */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
- if (status == HAL_OK)
- {
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+ if (status == HAL_OK)
+ {
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
- /* Wait until BUSY flag is reset */
- status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
- }
+ /* Wait until BUSY flag is reset */
+ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+ }
- if (status == HAL_OK)
- {
- /* Reset functional mode configuration to indirect write mode by default */
- CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+ if (status == HAL_OK)
+ {
+ /* Reset functional mode configuration to indirect write mode by default */
+ CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
+ }
+ else
+ {
/* Update state */
hqspi->State = HAL_QSPI_STATE_READY;
}
@@ -2247,14 +2255,22 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
}
else
{
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+ if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
+ {
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
- /* Enable the QSPI Transfer Complete Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+ /* Enable the QSPI Transfer Complete Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
- /* Configure QSPI: CR register with Abort request */
- SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+ /* Configure QSPI: CR register with Abort request */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+ }
+ else
+ {
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
+ }
}
}
return status;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c
index 2ec055471d..105fd26d0d 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c
@@ -479,7 +479,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call
/**
* @brief Unregister an RNG Callback
- * RNG callabck is redirected to the weak predefined callback
+ * RNG callback is redirected to the weak predefined callback
* @param hrng RNG handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c
new file mode 100644
index 0000000000..354966a13e
--- /dev/null
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c
@@ -0,0 +1,258 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_smbus_ex.c
+ * @author MCD Application Team
+ * @brief SMBUS Extended HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of SMBUS Extended peripheral:
+ * + Extended features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### SMBUS peripheral Extended features #####
+ ==============================================================================
+
+ [..] Comparing to other previous devices, the SMBUS interface for STM32H7xx
+ devices contains the following additional features
+
+ (+) Disable or enable wakeup from Stop mode(s)
+ (+) Disable or enable Fast Mode Plus
+
+ ##### How to use this driver #####
+ ==============================================================================
+ (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions :
+ (++) HAL_SMBUSEx_EnableWakeUp()
+ (++) HAL_SMBUSEx_DisableWakeUp()
+ (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+ (++) HAL_SMBUSEx_EnableFastModePlus()
+ (++) HAL_SMBUSEx_DisableFastModePlus()
+ @endverbatim
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SMBUSEx SMBUSEx
+ * @brief SMBUS Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
+ * @brief WakeUp Mode Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### WakeUp Mode Functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Wake Up Feature
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable SMBUS wakeup from Stop mode(s).
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Enable wakeup from stop mode */
+ hsmbus->Instance->CR1 |= I2C_CR1_WUPEN;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable SMBUS wakeup from Stop mode(s).
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUSx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Disable wakeup from stop mode */
+ hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
+ * @brief Fast Mode Plus Functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Fast Mode Plus Functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure Fast Mode Plus
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable the SMBUS fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref SMBUSEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be enabled on all selected
+ * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
+ * @note For all I2C2 pins fast mode plus driving capability can be enabled
+ * only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
+ * @note For all I2C3 pins fast mode plus driving capability can be enabled
+ * only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
+ * @note For all I2C4 pins fast mode plus driving capability can be enabled
+ * only by using SMBUS_FASTMODEPLUS_I2C4 parameter.
+ * @note For all I2C5 pins fast mode plus driving capability can be enabled
+ * only by using SMBUS_FASTMODEPLUS_I2C5 parameter.
+ * @retval None
+ */
+void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Enable fast mode plus driving capability for selected pin */
+ SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the SMBUS fast mode plus driving capability.
+ * @param ConfigFastModePlus Selects the pin.
+ * This parameter can be one of the @ref SMBUSEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be disabled on all selected
+ * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
+ * @note For all I2C2 pins fast mode plus driving capability can be disabled
+ * only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
+ * @note For all I2C3 pins fast mode plus driving capability can be disabled
+ * only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
+ * @note For all I2C4 pins fast mode plus driving capability can be disabled
+ * only by using SMBUS_FASTMODEPLUS_I2C4 parameter.
+ * @note For all I2C5 pins fast mode plus driving capability can be disabled
+ * only by using SMBUS_FASTMODEPLUS_I2C5 parameter.
+ * @retval None
+ */
+void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Disable fast mode plus driving capability for selected pin */
+ CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spdifrx.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spdifrx.c
index 68f8ae26d7..7bef68a090 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spdifrx.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spdifrx.c
@@ -188,7 +188,8 @@ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);
static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);
static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
-static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart);
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag,
+ FlagStatus Status, uint32_t Timeout, uint32_t tickstart);
/**
* @}
*/
@@ -238,7 +239,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
uint32_t tmpreg;
/* Check the SPDIFRX handle allocation */
- if(hspdif == NULL)
+ if (hspdif == NULL)
{
return HAL_ERROR;
}
@@ -258,7 +259,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
assert_param(IS_SYMBOL_CLOCK_GEN(hspdif->Init.BackupSymbolClockGen));
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
- if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
+ if (hspdif->State == HAL_SPDIFRX_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hspdif->Lock = HAL_UNLOCKED;
@@ -269,7 +270,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback; /* Legacy weak CxCpltCallback */
hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback; /* Legacy weak ErrorCallback */
- if(hspdif->MspInitCallback == NULL)
+ if (hspdif->MspInitCallback == NULL)
{
hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit */
}
@@ -278,7 +279,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
hspdif->MspInitCallback(hspdif);
}
#else
- if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
+ if (hspdif->State == HAL_SPDIFRX_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hspdif->Lock = HAL_UNLOCKED;
@@ -313,14 +314,14 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
hspdif->Init.ChannelStatusMask |
hspdif->Init.ValidityBitMask |
hspdif->Init.ParityErrorMask
- );
+ );
- if(hspdif->Init.SymbolClockGen == ENABLE)
+ if (hspdif->Init.SymbolClockGen == ENABLE)
{
tmpreg |= SPDIFRX_CR_CKSEN;
}
- if(hspdif->Init.BackupSymbolClockGen == ENABLE)
+ if (hspdif->Init.BackupSymbolClockGen == ENABLE)
{
tmpreg |= SPDIFRX_CR_CKSBKPEN;
}
@@ -343,7 +344,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
{
/* Check the SPDIFRX handle allocation */
- if(hspdif == NULL)
+ if (hspdif == NULL)
{
return HAL_ERROR;
}
@@ -357,7 +358,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
__HAL_SPDIFRX_IDLE(hspdif);
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
- if(hspdif->MspDeInitCallback == NULL)
+ if (hspdif->MspDeInitCallback == NULL)
{
hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspDeInit */
}
@@ -427,11 +428,12 @@ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID,
+ pSPDIFRX_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
@@ -440,7 +442,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA
/* Process locked */
__HAL_LOCK(hspdif);
- if(HAL_SPDIFRX_STATE_READY == hspdif->State)
+ if (HAL_SPDIFRX_STATE_READY == hspdif->State)
{
switch (CallbackID)
{
@@ -480,7 +482,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA
break;
}
}
- else if(HAL_SPDIFRX_STATE_RESET == hspdif->State)
+ else if (HAL_SPDIFRX_STATE_RESET == hspdif->State)
{
switch (CallbackID)
{
@@ -495,7 +497,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA
default :
/* Update the error code */
hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
- /* Return error status */
+ /* Return error status */
status = HAL_ERROR;
break;
}
@@ -515,7 +517,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA
/**
* @brief Unregister a SPDIFRX Callback
- * SPDIFRX callabck is redirected to the weak predefined callback
+ * SPDIFRX callback is redirected to the weak predefined callback
* @param hspdif SPDIFRX handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -528,14 +530,15 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA
* @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID)
+HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif,
+ HAL_SPDIFRX_CallbackIDTypeDef CallbackID)
{
-HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hspdif);
- if(HAL_SPDIFRX_STATE_READY == hspdif->State)
+ if (HAL_SPDIFRX_STATE_READY == hspdif->State)
{
switch (CallbackID)
{
@@ -562,12 +565,12 @@ HAL_StatusTypeDef status = HAL_OK;
default :
/* Update the error code */
hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
- /* Return error status */
+ /* Return error status */
status = HAL_ERROR;
break;
}
}
- else if(HAL_SPDIFRX_STATE_RESET == hspdif->State)
+ else if (HAL_SPDIFRX_STATE_RESET == hspdif->State)
{
switch (CallbackID)
{
@@ -613,7 +616,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
uint32_t tmpreg;
/* Check the SPDIFRX handle allocation */
- if(hspdif == NULL)
+ if (hspdif == NULL)
{
return HAL_ERROR;
}
@@ -629,9 +632,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
/* Reset the old SPDIFRX CR configuration */
tmpreg = hspdif->Instance->CR;
- if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
- (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
- ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
+ if (((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
+ (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
+ ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
{
return HAL_ERROR;
}
@@ -695,8 +698,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
(++) HAL_SPDIFRX_CxCpltCallback()
@endverbatim
-* @{
-*/
+ * @{
+ */
/**
* @brief Receives an amount of data (Data Flow) in blocking mode.
@@ -707,18 +710,19 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
uint32_t tickstart;
uint16_t sizeCounter = Size;
uint32_t *pTmpBuf = pData;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(hspdif->State == HAL_SPDIFRX_STATE_READY)
+ if (hspdif->State == HAL_SPDIFRX_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hspdif);
@@ -732,7 +736,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
tickstart = HAL_GetTick();
/* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
+ if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -741,13 +745,13 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
__HAL_SPDIFRX_RCV(hspdif);
/* Receive data flow */
- while(sizeCounter > 0U)
+ while (sizeCounter > 0U)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until RXNE flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+ if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -780,18 +784,19 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
uint32_t tickstart;
uint16_t sizeCounter = Size;
uint32_t *pTmpBuf = pData;
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(hspdif->State == HAL_SPDIFRX_STATE_READY)
+ if (hspdif->State == HAL_SPDIFRX_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hspdif);
@@ -805,7 +810,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uin
tickstart = HAL_GetTick();
/* Wait until SYNCD flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
+ if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -814,13 +819,13 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uin
__HAL_SPDIFRX_RCV(hspdif);
/* Receive control flow */
- while(sizeCounter > 0U)
+ while (sizeCounter > 0U)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until CSRNE flag is set */
- if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK)
+ if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -857,9 +862,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
- if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
+ if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -885,7 +890,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
/* Enable the SPDIFRX RXNE interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
- if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
@@ -904,7 +909,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
- hspdif->State= HAL_SPDIFRX_STATE_READY;
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspdif);
@@ -942,9 +947,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
- if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
+ if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -970,7 +975,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
/* Enable the SPDIFRX CSRNE interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
- if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
@@ -989,7 +994,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
- hspdif->State= HAL_SPDIFRX_STATE_READY;
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspdif);
@@ -1027,12 +1032,12 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
+ if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
{
/* Process Locked */
__HAL_LOCK(hspdif);
@@ -1054,7 +1059,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
/* Enable the DMA request */
- if(HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK)
+ if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK)
{
/* Set SPDIFRX error */
hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
@@ -1071,7 +1076,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
/* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
- if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
@@ -1090,7 +1095,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
- hspdif->State= HAL_SPDIFRX_STATE_READY;
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspdif);
@@ -1128,12 +1133,12 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
+ if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
{
hspdif->pCsBuffPtr = pData;
hspdif->CsXferSize = Size;
@@ -1155,7 +1160,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
/* Enable the DMA request */
- if(HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK)
+ if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK)
{
/* Set SPDIFRX error */
hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
@@ -1172,7 +1177,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
/* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
- if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
+ if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
@@ -1191,7 +1196,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
- hspdif->State= HAL_SPDIFRX_STATE_READY;
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspdif);
@@ -1256,21 +1261,21 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
uint32_t itSource = hspdif->Instance->IMR;
/* SPDIFRX in mode Data Flow Reception */
- if(((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource & SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE))
+ if (((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource & SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE))
{
__HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
SPDIFRX_ReceiveDataFlow_IT(hspdif);
}
/* SPDIFRX in mode Control Flow Reception */
- if(((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource & SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE))
+ if (((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource & SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE))
{
__HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
SPDIFRX_ReceiveControlFlow_IT(hspdif);
}
/* SPDIFRX Overrun error interrupt occurred */
- if(((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource & SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE))
+ if (((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource & SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE))
{
__HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_OVRIE);
@@ -1282,7 +1287,7 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
}
/* SPDIFRX Parity error interrupt occurred */
- if(((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource & SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE))
+ if (((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource & SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE))
{
__HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_PERRIE);
@@ -1393,7 +1398,7 @@ and the data flow.
* @param hspdif SPDIFRX handle
* @retval HAL state
*/
-HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif)
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif)
{
return hspdif->State;
}
@@ -1403,7 +1408,7 @@ HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * cons
* @param hspdif SPDIFRX handle
* @retval SPDIFRX Error Code
*/
-uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif)
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif)
{
return hspdif->ErrorCode;
}
@@ -1419,10 +1424,10 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif)
*/
static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
{
- SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable Rx DMA Request */
- if(hdma->Init.Mode != DMA_CIRCULAR)
+ if (hdma->Init.Mode != DMA_CIRCULAR)
{
hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
hspdif->RxXferCount = 0;
@@ -1442,7 +1447,7 @@ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
*/
static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
hspdif->RxHalfCpltCallback(hspdif);
@@ -1459,7 +1464,7 @@ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
*/
static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
{
- SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable Cb DMA Request */
hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
@@ -1480,7 +1485,7 @@ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
*/
static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
{
- SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
hspdif->CxHalfCpltCallback(hspdif);
@@ -1496,13 +1501,13 @@ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
*/
static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
{
- SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable Rx and Cb DMA Request */
hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));
hspdif->RxXferCount = 0;
- hspdif->State= HAL_SPDIFRX_STATE_READY;
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
/* Set the error code and execute error callback*/
hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
@@ -1528,7 +1533,7 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
hspdif->pRxBuffPtr++;
hspdif->RxXferCount--;
- if(hspdif->RxXferCount == 0U)
+ if (hspdif->RxXferCount == 0U)
{
/* Disable RXNE/PE and OVR interrupts */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
@@ -1539,9 +1544,9 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
__HAL_UNLOCK(hspdif);
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
- hspdif->RxCpltCallback(hspdif);
+ hspdif->RxCpltCallback(hspdif);
#else
- HAL_SPDIFRX_RxCpltCallback(hspdif);
+ HAL_SPDIFRX_RxCpltCallback(hspdif);
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
}
@@ -1558,7 +1563,7 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
hspdif->pCsBuffPtr++;
hspdif->CsXferCount--;
- if(hspdif->CsXferCount == 0U)
+ if (hspdif->CsXferCount == 0U)
{
/* Disable CSRNE interrupt */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
@@ -1569,9 +1574,9 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
__HAL_UNLOCK(hspdif);
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
- hspdif->CxCpltCallback(hspdif);
+ hspdif->CxCpltCallback(hspdif);
#else
- HAL_SPDIFRX_CxCpltCallback(hspdif);
+ HAL_SPDIFRX_CxCpltCallback(hspdif);
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
}
}
@@ -1585,15 +1590,16 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
* @param tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout, uint32_t tickstart)
{
/* Wait until flag is set */
- while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status)
+ while (__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
@@ -1604,7 +1610,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
- hspdif->State= HAL_SPDIFRX_STATE_READY;
+ hspdif->State = HAL_SPDIFRX_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspdif);
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c
index 55ff09bd48..1cbe0679bb 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c
@@ -1117,25 +1117,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Transfer loop */
while (hspi->RxXferCount > 0UL)
{
- /* Check the RXWNE/FRLVL flag */
- if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL)
+ /* Check the RXP flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
{
- if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
- {
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- hspi->RxXferCount -= (uint16_t)2UL;
- }
- else
- {
#if defined (__GNUC__)
- *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
#else
- *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
#endif /* __GNUC__ */
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
- }
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
}
else
{
@@ -1161,31 +1152,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Transfer loop */
while (hspi->RxXferCount > 0UL)
{
- /* Check the RXWNE/FRLVL flag */
- if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL)
+ /* Check the RXP flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
{
- if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
- {
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- hspi->RxXferCount -= (uint16_t)4UL;
- }
- else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET)
- {
-#if defined (__GNUC__)
- *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
-#else
- *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
-#endif /* __GNUC__ */
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount -= (uint16_t)2UL;
- }
- else
- {
- *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint8_t);
- hspi->RxXferCount--;
- }
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount--;
}
else
{
@@ -1361,50 +1333,30 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
{
- /* Check TXP flag */
+ /* Check the TXP flag */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL))
{
- if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
- {
- *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint32_t);
- hspi->TxXferCount -= (uint16_t)2UL;
- initial_TxXferCount = hspi->TxXferCount;
- }
- else
- {
#if defined (__GNUC__)
- *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+ *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
#else
- *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
#endif /* __GNUC__ */
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
- initial_TxXferCount = hspi->TxXferCount;
- }
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ initial_TxXferCount = hspi->TxXferCount;
}
- /* Check RXWNE/FRLVL flag */
- if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL))
+ /* Check the RXP flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL))
{
- if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
- {
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- hspi->RxXferCount -= (uint16_t)2UL;
- initial_RxXferCount = hspi->RxXferCount;
- }
- else
- {
#if defined (__GNUC__)
- *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
#else
- *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
#endif /* __GNUC__ */
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
- initial_RxXferCount = hspi->RxXferCount;
- }
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ initial_RxXferCount = hspi->RxXferCount;
}
/* Timeout management */
@@ -1427,64 +1379,22 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
{
while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
{
- /* check TXP flag */
+ /* Check the TXP flag */
if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL))
{
- if ((initial_TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
- {
- *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint32_t);
- hspi->TxXferCount -= (uint16_t)4UL;
- initial_TxXferCount = hspi->TxXferCount;
- }
- else if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
- {
-#if defined (__GNUC__)
- *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
-#else
- *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
-#endif /* __GNUC__ */
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= (uint16_t)2UL;
- initial_TxXferCount = hspi->TxXferCount;
- }
- else
- {
- *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint8_t);
- hspi->TxXferCount--;
- initial_TxXferCount = hspi->TxXferCount;
- }
+ *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ initial_TxXferCount = hspi->TxXferCount;
}
- /* Wait until RXWNE/FRLVL flag is reset */
- if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL))
+ /* Check the RXP flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL))
{
- if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
- {
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- hspi->RxXferCount -= (uint16_t)4UL;
- initial_RxXferCount = hspi->RxXferCount;
- }
- else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET)
- {
-#if defined (__GNUC__)
- *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
-#else
- *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
-#endif /* __GNUC__ */
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount -= (uint16_t)2UL;
- initial_RxXferCount = hspi->RxXferCount;
- }
- else
- {
- *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint8_t);
- hspi->RxXferCount--;
- initial_RxXferCount = hspi->RxXferCount;
- }
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount--;
+ initial_RxXferCount = hspi->RxXferCount;
}
/* Timeout management */
@@ -2629,7 +2539,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+ }
+ while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
}
/* Disable the SPI DMA Tx request if enabled */
@@ -2735,7 +2646,8 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+ }
+ while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
}
/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized
@@ -2938,57 +2850,51 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
/* Disable EOT interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
- /* DMA Normal Mode */
- if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) ||
- ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmatx->Init.Mode == DMA_NORMAL)) ||
- ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmarx->Init.Mode == DMA_NORMAL)))
+ /* For the IT based receive extra polling maybe required for last packet */
+ if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
{
- /* For the IT based receive extra polling maybe required for last packet */
- if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
+ /* Pooling remaining data */
+ while (hspi->RxXferCount != 0UL)
{
- /* Pooling remaining data */
- while (hspi->RxXferCount != 0UL)
+ /* Receive data in 32 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ }
+ /* Receive data in 16 Bit mode */
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- /* Receive data in 32 Bit mode */
- if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
- {
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- }
- /* Receive data in 16 Bit mode */
- else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
#if defined (__GNUC__)
- *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
#else
- *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
#endif /* __GNUC__ */
- hspi->pRxBuffPtr += sizeof(uint16_t);
- }
- /* Receive data in 8 Bit mode */
- else
- {
- *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint8_t);
- }
-
- hspi->RxXferCount--;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ }
+ /* Receive data in 8 Bit mode */
+ else
+ {
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
}
+
+ hspi->RxXferCount--;
}
+ }
- /* Call SPI Standard close procedure */
- SPI_CloseTransfer(hspi);
+ /* Call SPI Standard close procedure */
+ SPI_CloseTransfer(hspi);
- hspi->State = HAL_SPI_STATE_READY;
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
+ hspi->State = HAL_SPI_STATE_READY;
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
- hspi->ErrorCallback(hspi);
+ hspi->ErrorCallback(hspi);
#else
- HAL_SPI_ErrorCallback(hspi);
+ HAL_SPI_ErrorCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
- return;
- }
+ return;
}
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
index 8114f55658..a1edfa78c2 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
@@ -7772,10 +7772,6 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
* @arg TIM_TS_ITR1: Internal Trigger 1
* @arg TIM_TS_ITR2: Internal Trigger 2
* @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
* @arg TIM_TS_ITR4: Internal Trigger 4 (*)
* @arg TIM_TS_ITR5: Internal Trigger 5
* @arg TIM_TS_ITR6: Internal Trigger 6
@@ -7786,6 +7782,10 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
* @arg TIM_TS_ITR11: Internal Trigger 11 (*)
* @arg TIM_TS_ITR12: Internal Trigger 12 (*)
* @arg TIM_TS_ITR13: Internal Trigger 13 (*)
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
*
* (*) Value not defined in all devices.
*
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c
index bab45bf653..4dbf0483cd 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c
@@ -748,7 +748,8 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
+ uint32_t Timeout)
{
const uint8_t *ptxdata8bits;
const uint16_t *ptxdata16bits;
@@ -1233,7 +1234,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
/* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */
if (husart->Init.Parity != USART_PARITY_NONE)
{
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
}
SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
}
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c
index bd2cd5fd7d..38e7697ed6 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c
@@ -1169,7 +1169,7 @@ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
/* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
/* CMD Response: R1 */
- sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN;*/
+ sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN*/
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH;
sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c
index 879ed23753..9076a3838f 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c
@@ -342,6 +342,7 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
ErrorStatus status = ERROR;
uint32_t tmp_nss;
uint32_t tmp_mode;
+ uint32_t tmp_nss_polarity;
/* Check the SPI Instance SPIx*/
assert_param(IS_SPI_ALL_INSTANCE(SPIx));
@@ -371,11 +372,12 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
tmp_nss = SPI_InitStruct->NSS;
tmp_mode = SPI_InitStruct->Mode;
+ tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx);
/* Checks to setup Internal SS signal level and avoid a MODF Error */
- if ((tmp_nss == LL_SPI_NSS_SOFT) && (((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && \
- (tmp_mode == LL_SPI_MODE_MASTER)) || \
- ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && \
+ if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW) && \
+ (tmp_mode == LL_SPI_MODE_MASTER)) || \
+ ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \
(tmp_mode == LL_SPI_MODE_SLAVE))))
{
LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c
index 5f7412b949..e32c56ea43 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c
@@ -459,7 +459,9 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
/* Wait for AHB master IDLE state. */
do
{
- if (++count > 200000U)
+ count++;
+
+ if (count > 200000U)
{
return HAL_TIMEOUT;
}
@@ -471,7 +473,9 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
do
{
- if (++count > 200000U)
+ count++;
+
+ if (count > 200000U)
{
return HAL_TIMEOUT;
}
@@ -492,7 +496,9 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
/* Wait for AHB master IDLE state. */
do
{
- if (++count > 200000U)
+ count++;
+
+ if (count > 200000U)
{
return HAL_TIMEOUT;
}
@@ -504,7 +510,9 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
do
{
- if (++count > 200000U)
+ count++;
+
+ if (count > 200000U)
{
return HAL_TIMEOUT;
}
@@ -839,8 +847,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
else
{
pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
+ ep->xfer_size = ep->maxpacket * pktcnt;
+
USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
- USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);
+ USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size;
}
if (dma == 1U)
@@ -948,8 +958,11 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe
ep->xfer_len = ep->maxpacket;
}
+ /* Store transfer size, for EP0 this is equal to endpoint max packet size */
+ ep->xfer_size = ep->maxpacket;
+
USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
- USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
+ USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size);
if (dma == 1U)
{
@@ -990,7 +1003,9 @@ HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
do
{
- if (++count > 10000U)
+ count++;
+
+ if (count > 10000U)
{
ret = HAL_ERROR;
break;
@@ -1007,7 +1022,9 @@ HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
do
{
- if (++count > 10000U)
+ count++;
+
+ if (count > 10000U)
{
ret = HAL_ERROR;
break;
@@ -1429,7 +1446,9 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
/* Wait for AHB master IDLE state. */
do
{
- if (++count > 200000U)
+ count++;
+
+ if (count > 200000U)
{
return HAL_TIMEOUT;
}
@@ -1441,7 +1460,9 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
do
{
- if (++count > 200000U)
+ count++;
+
+ if (count > 200000U)
{
return HAL_TIMEOUT;
}
@@ -1796,9 +1817,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
(((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
- if (ep_type == EP_TYPE_INTR)
+ if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC))
{
- USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
+ USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
}
return ret;
@@ -1994,7 +2015,9 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
do
{
- if (++count > 1000U)
+ count++;
+
+ if (count > 1000U)
{
break;
}
@@ -2016,7 +2039,9 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
do
{
- if (++count > 1000U)
+ count++;
+
+ if (count > 1000U)
{
break;
}
@@ -2104,7 +2129,9 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
do
{
- if (++count > 1000U)
+ count++;
+
+ if (count > 1000U)
{
break;
}
diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md
index 9a7ac8de06..f450ad6aa1 100644
--- a/system/Drivers/STM32YYxx_HAL_Driver_version.md
+++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md
@@ -8,7 +8,7 @@
* STM32F7: 1.2.10
* STM32G0: 1.4.2
* STM32G4: 1.2.2
- * STM32H7: 1.10.1
+ * STM32H7: 1.11.0
* STM32L0: 1.10.5
* STM32L1: 1.4.4
* STM32L4: 1.13.2
diff --git a/system/STM32H7xx/system_stm32h7xx.c b/system/STM32H7xx/system_stm32h7xx.c
index 8b94c38136..f64f68d894 100644
--- a/system/STM32H7xx/system_stm32h7xx.c
+++ b/system/STM32H7xx/system_stm32h7xx.c
@@ -78,25 +78,25 @@
#ifndef VECT_TAB_OFFSET
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
+ This value must be a multiple of 0x300. */
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
- This value must be a multiple of 0x200. */
+ This value must be a multiple of 0x300. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
- This value must be a multiple of 0x200. */
+ This value must be a multiple of 0x300. */
#endif /* VECT_TAB_SRAM */
#else
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
- This value must be a multiple of 0x200. */
+ This value must be a multiple of 0x300. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
- This value must be a multiple of 0x200. */
+ This value must be a multiple of 0x300. */
#endif /* VECT_TAB_SRAM */
#endif /* DUAL_CORE && CORE_CM4 */