From 803d0b31e580cbe546184095bd1252ea6086b55b Mon Sep 17 00:00:00 2001 From: ag88 Date: Sun, 12 Dec 2021 02:12:54 +0800 Subject: [PATCH 1/3] fix variant WeActMiniH7xx: ena peripheral pll clks in previous commmit some clocks from PLL2, PLL3 are not distributed to some peripherals https://github.com/stm32duino/Arduino_Core_STM32/pull/1552 originally to save some power. However, users using those pheriperials may mistake that it is not working this fix distributes the missed out PLL clocks to all pheripherals those clocks are at 80 Mhz --- .../variant_WeActMiniH7xx.cpp | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.cpp b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.cpp index ee43aa92c2..0058a8b0e3 100644 --- a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.cpp +++ b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.cpp @@ -235,29 +235,23 @@ WEAK void SystemClock_Config(void) // QSPI from PLL1 qclk PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL; // SDMMC from PLL1 qclk - PeriphClkInitStruct.SdmmcClockSelection = 0; - //PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; + PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; // LPUART from PLL2 qclk - PeriphClkInitStruct.Lpuart1ClockSelection = 0; - //PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2; // USART from PLL2 qclk PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_PLL2; // USART from PLL2 qclk - PeriphClkInitStruct.Usart234578ClockSelection = 0; - //PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PLL2; + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PLL2; // I2C123 from PLL3 rclk PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_PLL3; // I2C4 from PLL3 rclk - PeriphClkInitStruct.I2c4ClockSelection = 0; - //PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PLL3; + PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PLL3; // SPI123 from PLL2 pclk PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL2; // SPI45 from PLL2 qclk - PeriphClkInitStruct.Spi45ClockSelection = 0; - //PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2; + PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2; // SPI6 from PLL2 qclk - PeriphClkInitStruct.Spi6ClockSelection = 0; - //PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL2; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL2; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { From 535e1b4bd897a289136e3b898299e70c59cc8741 Mon Sep 17 00:00:00 2001 From: ag88 Date: Sun, 12 Dec 2021 02:12:54 +0800 Subject: [PATCH 2/3] fix variant WeActMiniH7xx: ena peripheral pll clks in previous commit (https://github.com/stm32duino/Arduino_Core_STM32/pull/1552) some clocks from PLL2, PLL3 are not distributed to some peripherals originally to save some power. However, users using those pheriperials may mistake that it is not working this fix distributes the missed out PLL clocks to all pheripherals those clocks are at 80 Mhz --- .../variant_WeActMiniH7xx.cpp | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.cpp b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.cpp index ee43aa92c2..0058a8b0e3 100644 --- a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.cpp +++ b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_WeActMiniH7xx.cpp @@ -235,29 +235,23 @@ WEAK void SystemClock_Config(void) // QSPI from PLL1 qclk PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL; // SDMMC from PLL1 qclk - PeriphClkInitStruct.SdmmcClockSelection = 0; - //PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; + PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; // LPUART from PLL2 qclk - PeriphClkInitStruct.Lpuart1ClockSelection = 0; - //PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2; // USART from PLL2 qclk PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_PLL2; // USART from PLL2 qclk - PeriphClkInitStruct.Usart234578ClockSelection = 0; - //PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PLL2; + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PLL2; // I2C123 from PLL3 rclk PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_PLL3; // I2C4 from PLL3 rclk - PeriphClkInitStruct.I2c4ClockSelection = 0; - //PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PLL3; + PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PLL3; // SPI123 from PLL2 pclk PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL2; // SPI45 from PLL2 qclk - PeriphClkInitStruct.Spi45ClockSelection = 0; - //PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2; + PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2; // SPI6 from PLL2 qclk - PeriphClkInitStruct.Spi6ClockSelection = 0; - //PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL2; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL2; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { From 31892b2be980c5dc5acc765f349d8ecc29505620 Mon Sep 17 00:00:00 2001 From: ag88 Date: Sun, 12 Dec 2021 03:32:48 +0800 Subject: [PATCH 3/3] fix DevEBoxH7xx: ena peripheral pll clks make the same fixes from https://github.com/stm32duino/Arduino_Core_STM32/pull/1585 --- in previous commit (stm32duino#1552) some clocks from PLL2, PLL3 are not distributed to some peripherals originally to save some power. However, users using those pheriperials may mistake that it is not working this fix distributes the missed out PLL clocks to all pheripherals those clocks are at 80 Mhz --- --- .../variant_DevEBoxH7xx.cpp | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_DevEBoxH7xx.cpp b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_DevEBoxH7xx.cpp index b18c9d28dd..c36090e0da 100644 --- a/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_DevEBoxH7xx.cpp +++ b/variants/STM32H7xx/H742V(G-I)(H-T)_H743V(G-I)(H-T)_H750VBT_H753VI(H-T)/variant_DevEBoxH7xx.cpp @@ -235,29 +235,23 @@ WEAK void SystemClock_Config(void) // QSPI from PLL1 qclk PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL; // SDMMC from PLL1 qclk - PeriphClkInitStruct.SdmmcClockSelection = 0; - //PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; + PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; // LPUART from PLL2 qclk - PeriphClkInitStruct.Lpuart1ClockSelection = 0; - //PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2; // USART from PLL2 qclk PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_PLL2; // USART from PLL2 qclk - PeriphClkInitStruct.Usart234578ClockSelection = 0; - //PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PLL2; + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PLL2; // I2C123 from PLL3 rclk PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_PLL3; // I2C4 from PLL3 rclk - PeriphClkInitStruct.I2c4ClockSelection = 0; - //PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PLL3; + PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PLL3; // SPI123 from PLL2 pclk PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL2; // SPI45 from PLL2 qclk - PeriphClkInitStruct.Spi45ClockSelection = 0; - //PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2; + PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2; // SPI6 from PLL2 qclk - PeriphClkInitStruct.Spi6ClockSelection = 0; - //PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL2; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL2; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {