From 6f731e5a9467352f21e5f2f95b148755ce0c6d1f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 3 Nov 2020 10:36:05 +0100 Subject: [PATCH 1/7] [MP1] Update STM32MP1xx HAL Drivers to v1.3.0 Included in STM32CubeMP1 FW 1.3.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 30 +- .../Inc/stm32mp1xx_hal_adc.h | 81 +- .../Inc/stm32mp1xx_hal_adc_ex.h | 11 +- .../Inc/stm32mp1xx_hal_conf_template.h | 11 + .../Inc/stm32mp1xx_hal_cryp.h | 23 + .../Inc/stm32mp1xx_hal_dfsdm.h | 26 +- .../Inc/stm32mp1xx_hal_exti.h | 3 +- .../Inc/stm32mp1xx_hal_mdma.h | 457 ++-- .../Inc/stm32mp1xx_hal_rcc.h | 1144 ++++---- .../Inc/stm32mp1xx_hal_rcc_ex.h | 348 +-- .../Inc/stm32mp1xx_hal_rtc.h | 4 +- .../Inc/stm32mp1xx_hal_sai.h | 302 ++- .../Inc/stm32mp1xx_hal_smartcard.h | 1074 ++++++++ .../Inc/stm32mp1xx_hal_smartcard_ex.h | 337 +++ .../Inc/stm32mp1xx_ll_adc.h | 407 +-- .../Inc/stm32mp1xx_ll_rcc.h | 514 ++-- .../STM32MP1xx_HAL_Driver/Release_Notes.html | 13 +- .../Src/stm32mp1xx_hal.c | 2 +- .../Src/stm32mp1xx_hal_adc.c | 107 +- .../Src/stm32mp1xx_hal_adc_ex.c | 32 +- .../Src/stm32mp1xx_hal_cryp.c | 527 +++- .../Src/stm32mp1xx_hal_cryp_ex.c | 2 +- .../Src/stm32mp1xx_hal_dfsdm.c | 90 +- .../Src/stm32mp1xx_hal_mdma.c | 1418 +++++----- .../Src/stm32mp1xx_hal_pwr.c | 20 +- .../Src/stm32mp1xx_hal_rcc.c | 28 +- .../Src/stm32mp1xx_hal_rtc_ex.c | 3 + .../Src/stm32mp1xx_hal_sai.c | 524 +++- .../Src/stm32mp1xx_hal_sai_ex.c | 24 +- .../Src/stm32mp1xx_hal_sd.c | 4 +- .../Src/stm32mp1xx_hal_smartcard.c | 2323 +++++++++++++++++ .../Src/stm32mp1xx_hal_smartcard_ex.c | 192 ++ .../Src/stm32mp1xx_ll_adc.c | 68 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 34 files changed, 7442 insertions(+), 2709 deletions(-) create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smartcard.h create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smartcard_ex.h create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_smartcard.c create mode 100644 system/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_smartcard_ex.c diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index bb24db0309..a7d495009d 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -38,7 +38,6 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - /** * @} */ @@ -315,6 +314,11 @@ #if defined(STM32G0) #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM #endif #if defined(STM32H7) @@ -643,6 +647,10 @@ #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL #endif /* STM32G4 */ #if defined(STM32H7) @@ -887,7 +895,6 @@ #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - /** * @} */ @@ -1450,7 +1457,7 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY -#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End @@ -1472,7 +1479,7 @@ #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT -#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */ +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1531,18 +1538,18 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT @@ -3243,9 +3250,8 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3373,7 +3379,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3751,7 +3757,7 @@ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE #endif /* STM32L4 || STM32F4 || STM32F7 */ /** diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h index 0eb482215e..04a1976de5 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h @@ -117,8 +117,8 @@ typedef struct This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. - Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag - to free the IRQ vector sequencer. + Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). + Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ @@ -152,7 +152,7 @@ typedef struct If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_regular_external_trigger_edge */ - uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register. + uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transferred to DFSDM register. Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. This parameter can be a value of @ref ADC_ConversionDataManagement. Note: This parameter must be modified when no conversion is on going on both regular and injected groups @@ -334,7 +334,7 @@ typedef struct external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ /* States of ADC group injected */ #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, @@ -361,7 +361,7 @@ typedef struct typedef struct __ADC_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ { ADC_TypeDef *Instance; /*!< Register base address */ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ @@ -715,7 +715,6 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @} */ - /** @defgroup ADC_Event_type ADC Event type * @{ */ @@ -813,10 +812,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @param __HANDLE__ ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ -#define ADC_IS_ENABLE(__HANDLE__) \ - (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ - ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ - ) ? SET : RESET) +#define ADC_IS_ENABLE(__HANDLE__) \ + ((((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ + ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ + ) ? SET : RESET) /** * @brief Check if conversion is on going on regular group. @@ -1063,7 +1062,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #else #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ ((__HANDLE__)->State = HAL_ADC_STATE_RESET) -#endif +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @brief Enable ADC interrupt. @@ -1214,7 +1213,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_CHANNEL_VBAT (1) * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) - * + * * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). @@ -1257,7 +1256,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_CHANNEL_VBAT (1) * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) - * + * * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual).\n @@ -1312,7 +1311,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_CHANNEL_VBAT (1) * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) - * + * * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). @@ -1362,7 +1361,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_CHANNEL_VBAT (1) * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) - * + * * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). @@ -1411,7 +1410,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_CHANNEL_VBAT (1) * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) - * + * * (1) On STM32MP1, parameter available only on ADC instance: ADC2. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected. @@ -1435,7 +1434,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Helper macro to select the ADC common instance @@ -1509,10 +1508,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ - __ADC_RESOLUTION_TARGET__) \ - __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \ - (__ADC_RESOLUTION_CURRENT__), \ - (__ADC_RESOLUTION_TARGET__)) + __ADC_RESOLUTION_TARGET__) \ +__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ + (__ADC_RESOLUTION_CURRENT__),\ + (__ADC_RESOLUTION_TARGET__)) /** * @brief Helper macro to calculate the voltage (unit: mVolt) @@ -1533,10 +1532,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ - __ADC_RESOLUTION__) \ - __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \ - (__ADC_DATA__), \ - (__ADC_RESOLUTION__)) + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ + (__ADC_DATA__),\ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate analog reference voltage (Vref+) @@ -1548,7 +1547,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * connected to pin Vref+. * On devices with small package, the pin Vref+ is not present * and internally bonded to pin Vdda. - * @note On this STM32 serie, calibration data of internal voltage reference + * @note On this STM32 series, calibration data of internal voltage reference * VrefInt corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * internal voltage reference VrefInt. @@ -1565,9 +1564,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @retval Analog reference voltage (unit: mV) */ #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \ - (__ADC_RESOLUTION__)) + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -1596,7 +1595,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note On this STM32 serie, calibration data of temperature sensor + * @note On this STM32 series, calibration data of temperature sensor * corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * temperature sensor. @@ -1617,10 +1616,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \ - (__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__)) + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -1672,13 +1671,13 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to __TEMPSENSOR_CALX_TEMP__,\ __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \ - (__TEMPSENSOR_TYP_CALX_V__), \ - (__TEMPSENSOR_CALX_TEMP__), \ - (__VREFANALOG_VOLTAGE__), \ - (__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__)) + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ + (__TEMPSENSOR_TYP_CALX_V__),\ + (__TEMPSENSOR_CALX_TEMP__),\ + (__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) /** * @} diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h index 698ec56906..53bd652933 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h @@ -396,7 +396,7 @@ typedef struct * Usage of this macro is not the Standard way of multimode * configuration and can lead to have HAL ADC handles status * misaligned. Usage of this macro must be limited to cases - * mentionned above. + * mentioned above. * @param __HANDLE__ ADC handle. * @retval None */ @@ -439,7 +439,8 @@ typedef struct * @param __RANKNB__ Rank number. * @retval None */ -#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) +#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\ + & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) /** * @brief Configure ADC injected context queue @@ -509,7 +510,8 @@ typedef struct * @param __CALIBRATION_FACTOR__ Calibration factor value. * @retval None */ -#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) +#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__)\ + & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) /** * @brief Calibration factor in differential mode to be retrieved from calibration register. @@ -1078,7 +1080,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected); +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, + ADC_InjectionConfTypeDef *sConfigInjected); #if defined(ADC_MULTIMODE_SUPPORT) HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); #endif /* ADC_MULTIMODE_SUPPORT */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_conf_template.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_conf_template.h index 7004397599..1eb725058f 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_conf_template.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_conf_template.h @@ -58,9 +58,11 @@ #define HAL_RTC_MODULE_ENABLED #define HAL_SAI_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED #define HAL_SMBUS_MODULE_ENABLED #define HAL_SPDIFRX_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED #define HAL_USART_MODULE_ENABLED @@ -76,6 +78,7 @@ #define USE_HAL_I2C_REGISTER_CALLBACKS 0u #define USE_HAL_RNG_REGISTER_CALLBACKS 0u #define USE_HAL_SPI_REGISTER_CALLBACKS 0u +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U #define USE_HAL_UART_REGISTER_CALLBACKS 0u #define USE_HAL_USART_REGISTER_CALLBACKS 0u #define USE_HAL_WWDG_REGISTER_CALLBACKS 0u @@ -291,6 +294,10 @@ #include "stm32mp1xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32mp1xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + #ifdef HAL_SMBUS_MODULE_ENABLED #include "stm32mp1xx_hal_smbus.h" #endif /* HAL_SMBUS_MODULE_ENABLED */ @@ -303,6 +310,10 @@ #include "stm32mp1xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32mp1xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + #ifdef HAL_TIM_MODULE_ENABLED #include "stm32mp1xx_hal_tim.h" #endif /* HAL_TIM_MODULE_ENABLED */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_cryp.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_cryp.h index d1b060ccad..d3cf8ce78f 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_cryp.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_cryp.h @@ -64,6 +64,9 @@ typedef struct uint32_t HeaderSize; /*!< The size of header buffer in word */ uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ + uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization + Vector only once and to skip configuration for consecutive processings. + This parameter can be a value of @ref CRYP_Configuration_Skip */ } CRYP_ConfigTypeDef; @@ -128,6 +131,13 @@ typedef struct uint32_t Version; /*!< CRYP1 IP version*/ + uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when + configuration can be skipped */ + + uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored + for a single signature computation after several + messages processing */ + #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */ void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */ @@ -286,6 +296,16 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @} */ +/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode + * @{ + */ + +#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */ +#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */ + +/** + * @} + */ /** * @} @@ -468,6 +488,9 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); ((DATATYPE) == CRYP_DATATYPE_8B) || \ ((DATATYPE) == CRYP_DATATYPE_1B)) +#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \ + ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) + /** * @} */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dfsdm.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dfsdm.h index cb55f171cf..6ac3bbf111 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dfsdm.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dfsdm.h @@ -116,12 +116,16 @@ typedef struct /** * @brief DFSDM channel handle structure definition */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) typedef struct __DFSDM_Channel_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ { DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ -#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U) +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) void (*CkabCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */ void (*ScdCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */ void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */ @@ -129,7 +133,7 @@ typedef struct __DFSDM_Channel_HandleTypeDef #endif }DFSDM_Channel_HandleTypeDef; -#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U) +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) /** * @brief DFSDM channel callback ID enumeration definition */ @@ -212,7 +216,11 @@ typedef struct /** * @brief DFSDM filter handle structure definition */ +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) typedef struct __DFSDM_Filter_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ { DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ @@ -227,7 +235,7 @@ typedef struct __DFSDM_Filter_HandleTypeDef uint32_t InjConvRemaining; /*!< Injected conversions remaining */ HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ uint32_t ErrorCode; /*!< DFSDM filter error code */ -#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U) +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */ @@ -259,7 +267,7 @@ typedef struct This parameter can be a values combination of @ref DFSDM_BreakSignals */ }DFSDM_Filter_AwdParamTypeDef; -#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U) +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) /** * @brief DFSDM filter callback ID enumeration definition */ @@ -437,7 +445,7 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ #define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */ -#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U) +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) #define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */ #endif /** @@ -511,7 +519,7 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf * @param __HANDLE__ DFSDM channel handle. * @retval None */ -#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U) +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ @@ -525,7 +533,7 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf * @param __HANDLE__ DFSDM filter handle. * @retval None */ -#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U) +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ @@ -557,7 +565,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U) +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) /* Channel callbacks register/unregister functions ****************************/ HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, @@ -613,7 +621,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filt void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U) +#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) /* Filter callbacks register/unregister functions ****************************/ HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h index c16c8f7f7a..6b5a5d869a 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h @@ -254,7 +254,8 @@ typedef struct #define EXTI_REG_SHIFT 16u #define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT) #define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT) -#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) +#define EXTI_REG3 (0x02uL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3) #define EXTI_PIN_MASK 0x0000001Fu /** diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_mdma.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_mdma.h index 5f4585bc1e..4a74a11d5a 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_mdma.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_mdma.h @@ -2,13 +2,11 @@ ****************************************************************************** * @file stm32mp1xx_hal_mdma.h * @author MCD Application Team - * @version V0.3.0 - * @date 9-December-2016 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. + *

© COPYRIGHT(c) 2017 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -17,11 +15,11 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32MP1xx_HAL_MDMA_H -#define __STM32MP1xx_HAL_MDMA_H +#ifndef STM32MP1xx_HAL_MDMA_H +#define STM32MP1xx_HAL_MDMA_H #ifdef __cplusplus extern "C" { @@ -36,131 +34,132 @@ /** @addtogroup MDMA * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup MDMA_Exported_Types MDMA Exported Types - * @brief MDMA Exported Types + * @brief MDMA Exported Types * @{ */ -/** +/** * @brief MDMA Configuration Structure definition */ typedef struct { - + uint32_t Request; /*!< Specifies the MDMA request. This parameter can be a value of @ref MDMA_Request_selection*/ - + uint32_t TransferTriggerMode; /*!< Specifies the Trigger Transfer mode : each request triggers a : - a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer - This parameter can be a value of @ref MDMA_Transfer_TriggerMode */ - + a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer + This parameter can be a value of @ref MDMA_Transfer_TriggerMode */ + uint32_t Priority; /*!< Specifies the software priority for the MDMAy channelx. This parameter can be a value of @ref MDMA_Priority_level */ - uint32_t SecureMode; /*!< Specifies if the MDMA master transactions are done in secure mode. - This parameter can be a value of @ref MDMA_Secure_Mode */ - - uint32_t Endianess; /*!< Specifies if the MDMA transactions preserve the Little endianess. - This parameter can be a value of @ref MDMA_Endianess */ - + uint32_t SecureMode; /*!< Specifies if the MDMA master transactions are done in secure mode. + This parameter can be a value of @ref MDMA_Secure_Mode */ + + uint32_t Endianness; /*!< Specifies if the MDMA transactions preserve the Little endianness. + This parameter can be a value of @ref MDMA_Endianness */ + uint32_t SourceInc; /*!< Specifies if the Source increment mode . This parameter can be a value of @ref MDMA_Source_increment_mode */ - + uint32_t DestinationInc; /*!< Specifies if the Destination increment mode . This parameter can be a value of @ref MDMA_Destination_increment_mode */ - + uint32_t SourceDataSize; /*!< Specifies the source data size. This parameter can be a value of @ref MDMA_Source_data_size */ - + uint32_t DestDataSize; /*!< Specifies the destination data size. This parameter can be a value of @ref MDMA_Destination_data_size */ - - + + uint32_t DataAlignment; /*!< Specifies the source to destination Memory data packing/padding mode. - This parameter can be a value of @ref MDMA_data_Alignment */ + This parameter can be a value of @ref MDMA_data_Alignment */ uint32_t BufferTransferLength; /*!< Specifies the buffer Transfer Length (number of bytes), this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/ - - uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers. - It specifies the amount of data to be transferred in a single non interruptable + + uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers. + It specifies the amount of data to be transferred in a single non interruptable transaction. - This parameter can be a value of @ref MDMA_Source_burst + This parameter can be a value of @ref MDMA_Source_burst @note : the burst may be FIXED/INCR based on SourceInc value , the BURST must be programmed as to ensure that the burst size will be lower than than BufferTransferLength */ - - uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers. - It specifies the amount of data to be transferred in a single non interruptable + + uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers. + It specifies the amount of data to be transferred in a single non interruptable transaction. - This parameter can be a value of @ref MDMA_Destination_burst + This parameter can be a value of @ref MDMA_Destination_burst @note : the burst may be FIXED/INCR based on DestinationInc value , the BURST must be programmed as to ensure that the burst size will be lower than than BufferTransferLength */ - + int32_t SourceBlockAddressOffset; /*!< this field specifies the Next block source address offset signed value : if > 0 then increment the next block source Address by offset from where the last block ends if < 0 then decrement the next block source Address by offset from where the last block ends if == 0, the next block source address starts from where the last block ends - */ + */ int32_t DestBlockAddressOffset; /*!< this field specifies the Next block destination address offset signed value : if > 0 then increment the next block destination Address by offset from where the last block ends if < 0 then decrement the next block destination Address by offset from where the last block ends if == 0, the next block destination address starts from where the last block ends - */ - + */ + }MDMA_InitTypeDef; -/** - * @brief HAL MDMA linked list node structure definition - * @note The Linked list node allows to define a new MDMA configuration +/** + * @brief HAL MDMA linked list node structure definition + * @note The Linked list node allows to define a new MDMA configuration * (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers). * When CLAR register is configured to a non NULL value , each time a transfer ends, - * a new configuration (linked list node) is automatically loaded from the address given in CLAR register. + * a new configuration (linked list node) is automatically loaded from the address given in CLAR register. */ typedef struct { - uint32_t CTCR; /*!< New CTCR register configuration for the given MDMA linked list node */ - uint32_t CBNDTR; /*!< New CBNDTR register configuration for the given MDMA linked list node */ - uint32_t CSAR; /*!< New CSAR register configuration for the given MDMA linked list node */ - uint32_t CDAR; /*!< New CDAR register configuration for the given MDMA linked list node */ - uint32_t CBRUR; /*!< New CBRUR register configuration for the given MDMA linked list node */ - uint32_t CLAR; /*!< New CLAR register configuration for the given MDMA linked list node */ - uint32_t CTBR; /*!< New CTBR register configuration for the given MDMA linked list node */ - uint32_t CMAR; /*!< New CMAR register configuration for the given MDMA linked list node */ - uint32_t CMDR; /*!< New CMDR register configuration for the given MDMA linked list node */ - + __IO uint32_t CTCR; /*!< New CTCR register configuration for the given MDMA linked list node */ + __IO uint32_t CBNDTR; /*!< New CBNDTR register configuration for the given MDMA linked list node */ + __IO uint32_t CSAR; /*!< New CSAR register configuration for the given MDMA linked list node */ + __IO uint32_t CDAR; /*!< New CDAR register configuration for the given MDMA linked list node */ + __IO uint32_t CBRUR; /*!< New CBRUR register configuration for the given MDMA linked list node */ + __IO uint32_t CLAR; /*!< New CLAR register configuration for the given MDMA linked list node */ + __IO uint32_t CTBR; /*!< New CTBR register configuration for the given MDMA linked list node */ + __IO uint32_t Reserved; /*!< Reserved register */ + __IO uint32_t CMAR; /*!< New CMAR register configuration for the given MDMA linked list node */ + __IO uint32_t CMDR; /*!< New CMDR register configuration for the given MDMA linked list node */ + }MDMA_LinkNodeTypeDef; -/** - * @brief HAL MDMA linked list node configuration structure definition - * @note used with HAL_MDMA_LinkedList_CreateNode function +/** + * @brief HAL MDMA linked list node configuration structure definition + * @note used with HAL_MDMA_LinkedList_CreateNode function */ typedef struct -{ - MDMA_InitTypeDef Init; /* !< configuration of the specified MDMA Linked List Node */ - uint32_t SrcAddress; /* !< The source memory address for the Linked list Node */ - uint32_t DstAddress; /* !< The destination memory address for the Linked list Node */ - uint32_t BlockDataLength; /* !< The length of a block transfer in bytes */ - uint32_t BlockCount; /* !< The number of a blocks to be transfer */ +{ + MDMA_InitTypeDef Init; /*!< configuration of the specified MDMA Linked List Node */ + uint32_t SrcAddress; /*!< The source memory address for the Linked list Node */ + uint32_t DstAddress; /*!< The destination memory address for the Linked list Node */ + uint32_t BlockDataLength; /*!< The data length of a block in bytes */ + uint32_t BlockCount; /*!< The number of blocks to be transferred */ uint32_t PostRequestMaskAddress; /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served. PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */ uint32_t PostRequestMaskData; /*!< specifies the value to be written to PostRequestMaskAddress after a request is served. PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */ - - + + }MDMA_LinkNodeConfTypeDef; -/** +/** * @brief HAL MDMA State structure definition */ typedef enum @@ -168,13 +167,13 @@ typedef enum HAL_MDMA_STATE_RESET = 0x00U, /*!< MDMA not yet initialized or disabled */ HAL_MDMA_STATE_READY = 0x01U, /*!< MDMA initialized and ready for use */ HAL_MDMA_STATE_BUSY = 0x02U, /*!< MDMA process is ongoing */ - HAL_MDMA_STATE_TIMEOUT = 0x03U, /*!< MDMA timeout state */ - HAL_MDMA_STATE_ERROR = 0x04U, /*!< MDMA error state */ - HAL_MDMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ + HAL_MDMA_STATE_ERROR = 0x03U, /*!< MDMA error state */ + HAL_MDMA_STATE_ABORT = 0x04U, /*!< MDMA Abort state */ + HAL_MDMA_STATE_TIMEOUT = 0x05U, /*!< MDMA timeout state */ }HAL_MDMA_StateTypeDef; -/** +/** * @brief HAL MDMA Level Complete structure definition */ typedef enum @@ -183,10 +182,10 @@ typedef enum HAL_MDMA_BUFFER_TRANSFER = 0x01U, /*!< Buffer Transfer */ HAL_MDMA_BLOCK_TRANSFER = 0x02U, /*!< Block Transfer */ HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U /*!< repeat block Transfer */ - + }HAL_MDMA_LevelCompleteTypeDef; -/** +/** * @brief HAL MDMA Callbacks IDs structure definition */ typedef enum @@ -202,47 +201,46 @@ typedef enum }HAL_MDMA_CallbackIDTypeDef; -/** +/** * @brief MDMA handle Structure definition */ typedef struct __MDMA_HandleTypeDef { MDMA_Channel_TypeDef *Instance; /*!< Register base address */ - - MDMA_InitTypeDef Init; /*!< MDMA communication parameters */ + MDMA_InitTypeDef Init; /*!< MDMA communication parameters */ HAL_LockTypeDef Lock; /*!< MDMA locking object */ - + __IO HAL_MDMA_StateTypeDef State; /*!< MDMA transfer state */ void *Parent; /*!< Parent object state */ void (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer complete callback */ - + void (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA buffer transfer complete callback */ void (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer complete callback */ - + void (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback */ void (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer error callback */ - void (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer Abort callback */ - + void (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer Abort callback */ - MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress; /*!< specifies the first node address of the transfer list + + MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress; /*!< specifies the first node address of the transfer list (after the initial node defined by the Init struct) - this parameter is used internally by the MDMA driver - to construct the liked list node + this parameter is used internally by the MDMA driver + to construct the linked list node */ MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress; /*!< specifies the last node address of the transfer list this parameter is used internally by the MDMA driver - to construct the liked list node + to construct the linked list node */ - uint32_t LinkedListNodeCounter; /*!< Number of nodes in the MDMA linked list */ - + uint32_t LinkedListNodeCounter; /*!< Number of nodes in the MDMA linked list */ + __IO uint32_t ErrorCode; /*!< MDMA Error code */ } MDMA_HandleTypeDef; @@ -254,14 +252,14 @@ typedef struct __MDMA_HandleTypeDef /* Exported constants --------------------------------------------------------*/ /** @defgroup MDMA_Exported_Constants MDMA Exported Constants - * @brief MDMA Exported constants + * @brief MDMA Exported constants * @{ */ /** @defgroup MDMA_Error_Codes MDMA Error Codes - * @brief MDMA Error Codes + * @brief MDMA Error Codes * @{ - */ + */ #define HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ #define HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U) /*!< Read Transfer error */ #define HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U) /*!< Write Transfer error */ @@ -270,9 +268,9 @@ typedef struct __MDMA_HandleTypeDef #define HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U) /*!< Address/Size alignment error */ #define HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U) /*!< Block Size error */ #define HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */ -#define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort or SW trigger requested with no Xfer ongoing */ -#define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) /*!< DeInit or SW trigger requested with Xfer ongoing */ - +#define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort or SW trigger requested with no Xfer ongoing */ +#define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) /*!< DeInit or SW trigger requested with Xfer ongoing */ + /** * @} */ @@ -316,7 +314,6 @@ typedef struct __MDMA_HandleTypeDef #define MDMA_REQUEST_I2C6_RX ((uint32_t)0x00000026U) /*!< MDMA HW request is I2C6 Rx Transfer Complete Flag */ #define MDMA_REQUEST_I2C6_TX ((uint32_t)0x00000027U) /*!< MDMA HW request is I2C6 Tx Transfer Complete Flag */ #define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA SW request */ - /** * @} */ @@ -325,12 +322,12 @@ typedef struct __MDMA_HandleTypeDef * @brief MDMA Transfer Trigger Mode * @{ */ -#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */ -#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */ -#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */ +#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */ +#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */ +#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */ #define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */ -/** +/** * @} */ @@ -345,8 +342,8 @@ typedef struct __MDMA_HandleTypeDef /** * @} - */ - + */ + /** @defgroup MDMA_Secure_Mode MDMA Secure Mode * @brief MDMA Secure Mode * @{ @@ -358,64 +355,64 @@ typedef struct __MDMA_HandleTypeDef * @} */ -/** @defgroup MDMA_Endianess MDMA Endianess - * @brief MDMA Endianess +/** @defgroup MDMA_Endianness MDMA Endianness + * @brief MDMA Endianness * @{ */ -#define MDMA_LITTLE_ENDIANESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianess preserve */ -#define MDMA_LITTLE_BYTE_ENDIANESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianess exchange when destination data size is > Byte */ -#define MDMA_LITTLE_HALFWORD_ENDIANESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianess exchange when destination data size is > HALF WORD*/ -#define MDMA_LITTLE_WORD_ENDIANESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianess exchange when destination data size is > DOUBLE WORD */ +#define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */ +#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */ +#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */ +#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */ /** * @} */ - + /** @defgroup MDMA_Source_increment_mode MDMA Source increment mode * @brief MDMA Source increment mode * @{ */ -#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ -#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/ -#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ -#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/ +#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ +#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ +#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ +#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ #define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ -#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/ -#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ -#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/ +#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ +#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ +#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ #define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ /** * @} - */ - + */ + /** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode * @brief MDMA Destination increment mode * @{ */ -#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ -#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/ -#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ -#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/ +#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ +#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ +#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ +#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ #define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ -#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/ -#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ -#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/ +#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ +#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ +#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ #define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ /** * @} - */ - + */ + /** @defgroup MDMA_Source_data_size MDMA Source data size * @brief MDMA Source data size * @{ */ -#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */ -#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */ -#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */ +#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */ +#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */ +#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */ #define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) /*!< Source data size is double word */ - + /** * @} */ @@ -424,88 +421,88 @@ typedef struct __MDMA_HandleTypeDef * @brief MDMA Destination data size * @{ */ -#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */ -#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */ -#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */ +#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */ +#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */ +#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */ #define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) /*!< Destination data size is double word */ - + /** * @} */ /** @defgroup MDMA_data_Alignment MDMA data alignment - * @brief MDMA MDMA data alignment + * @brief MDMA data alignment * @{ */ #define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) /*!< The source data is packed/un-packed into the destination data size - All data are right aligned, in Little Endien mode. */ -#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */ -#define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended , - Note : this mode is allowed only if the Source data size smaller than Destination data size */ -#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */ - + All data are right aligned, in Little Endien mode. */ +#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */ +#define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended , + Note : this mode is allowed only if the Source data size is smaller than Destination data size */ +#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */ + /** * @} */ - + /** @defgroup MDMA_Source_burst MDMA Source burst * @brief MDMA Source burst * @{ */ -#define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ -#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */ -#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */ -#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */ -#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */ -#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */ -#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */ -#define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */ - +#define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ +#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */ +#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */ +#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */ +#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */ +#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */ +#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */ +#define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */ + /** * @} */ - + /** @defgroup MDMA_Destination_burst MDMA Destination burst * @brief MDMA Destination burst * @{ */ -#define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ -#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */ -#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */ -#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */ -#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */ -#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */ -#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */ -#define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */ +#define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ +#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */ +#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */ +#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */ +#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */ +#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */ +#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */ +#define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */ /** * @} */ - + /** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions * @brief MDMA interrupt enable definitions * @{ */ -#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */ +#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */ #define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) /*!< Channel Transfer Complete interrupt */ -#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */ -#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */ -#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */ +#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */ +#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */ +#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */ /** * @} - */ - + */ + /** @defgroup MDMA_flag_definitions MDMA flag definitions * @brief MDMA flag definitions * @{ */ -#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */ -#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */ +#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */ +#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */ #define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */ -#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */ -#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */ -#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */ +#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */ +#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */ +#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */ /** * @} @@ -527,9 +524,9 @@ typedef struct __MDMA_HandleTypeDef * @retval None */ #define __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN) - + /** - * @brief Disable the specified DMA Channel. + * @brief Disable the specified MDMA Channel. * @param __HANDLE__: MDMA handle * @retval None */ @@ -545,10 +542,10 @@ typedef struct __MDMA_HandleTypeDef * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag. * @arg MDMA_FLAG_BT : Block Transfer complete flag. * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. - * @arg MDMA_FLAG_CRQA : Channel ReQest Active flag. + * @arg MDMA_FLAG_CRQA : Channel ReQest Active flag. * @retval The state of FLAG (SET or RESET). */ -#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__)) +#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__)) /** * @brief Clear the MDMA Stream pending flags. @@ -559,21 +556,21 @@ typedef struct __MDMA_HandleTypeDef * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag. * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag. * @arg MDMA_FLAG_BT : Block Transfer complete flag. - * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. + * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. * @retval None */ #define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__)) /** - * @brief Enables the specified DMA Channel interrupts. + * @brief Enables the specified MDMA Channel interrupts. * @param __HANDLE__: MDMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg MDMA_IT_TE : Transfer Error interrupt mask * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask * @arg MDMA_IT_BT : Block Transfer interrupt mask - * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask + * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask * @retval None */ #define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) @@ -581,34 +578,49 @@ typedef struct __MDMA_HandleTypeDef /** * @brief Disables the specified MDMA Channel interrupts. * @param __HANDLE__: MDMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg MDMA_IT_TE : Transfer Error interrupt mask * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask * @arg MDMA_IT_BT : Block Transfer interrupt mask - * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask + * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask * @retval None */ #define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) /** * @brief Checks whether the specified MDMA Channel interrupt is enabled or not. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * @param __HANDLE__: MDMA handle + * @param __INTERRUPT__: specifies the MDMA interrupt source to check. * @arg MDMA_IT_TE : Transfer Error interrupt mask * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask * @arg MDMA_IT_BT : Block Transfer interrupt mask - * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask + * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask * @retval The state of MDMA_IT (SET or RESET). */ #define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) +/** + * @brief Writes the number of data in bytes to be transferred on the MDMA Channelx. + * @param __HANDLE__ : MDMA handle + * @param __COUNTER__: Number of data in bytes to be transferred. + * @retval None + */ +#define __HAL_MDMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CBNDTR |= ((__COUNTER__) & MDMA_CBNDTR_BNDT)) + +/** + * @brief Returns the number of remaining data in bytes in the current MDMA Channelx transfer. + * @param __HANDLE__ : MDMA handle + * @retval The number of remaining data in bytes in the current MDMA Channelx transfer. + */ +#define __HAL_MDMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CBNDTR & MDMA_CBNDTR_BNDT) + /** * @} */ - + /* Exported functions --------------------------------------------------------*/ /** @defgroup MDMA_Exported_Functions MDMA Exported Functions * @{ @@ -616,7 +628,7 @@ typedef struct __MDMA_HandleTypeDef /* Initialization and de-initialization functions *****************************/ /** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions + * @brief Initialization and de-initialization functions * @{ */ HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma); @@ -628,43 +640,45 @@ HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDM /** * @} - */ + */ /* Linked list operation functions ********************************************/ /** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions - * @brief Linked list operation functions + * @brief Linked list operation functions * @{ */ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig); HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode); HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode); +HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma); /** * @} - */ + */ /* IO operation functions *****************************************************/ /** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions - * @brief I/O operation functions + * @brief I/O operation functions * @{ */ HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma); HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma); -HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout); +HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma); void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma); /** * @} - */ + */ /* Peripheral State and Error functions ***************************************/ /** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions + * @brief Peripheral State functions * @{ */ HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma); @@ -672,13 +686,14 @@ uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma); void HAL_MDMA_MspInit(MDMA_HandleTypeDef *hmdma); void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma); + /** * @} */ /** * @} - */ + */ /* Private types -------------------------------------------------------------*/ /** @defgroup MDMA_Private_Types MDMA Private Types @@ -687,7 +702,7 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma); /** * @} - */ + */ /* Private defines -----------------------------------------------------------*/ /** @defgroup MDMA_Private_Defines MDMA Private Defines @@ -696,8 +711,8 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma); /** * @} - */ - + */ + /* Private variables ---------------------------------------------------------*/ /** @defgroup MDMA_Private_Variables MDMA Private Variables * @{ @@ -705,7 +720,7 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma); /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup MDMA_Private_Constants MDMA Private Constants @@ -714,36 +729,30 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma); /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup MDMA_Private_Macros MDMA Private Macros * @{ */ -/** @defgroup MDMA_IS_Definitions MDMA Private macros to check input parameters - * @{ - */ - #define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER ) || \ ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \ ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \ ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER )) -#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \ - ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \ - ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \ - ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH)) +#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \ + ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \ + ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \ + ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH)) #define IS_MDMA_SECURE_MODE(__SECURE_MODE__) (((__SECURE_MODE__) == MDMA_SECURE_MODE_DISABLE ) || \ ((__SECURE_MODE__) == MDMA_SECURE_MODE_ENABLE)) - -#define IS_MDMA_ENDIANESS_MODE(__ENDIANESS__) (((__ENDIANESS__) == MDMA_LITTLE_ENDIANESS_PRESERVE ) || \ - ((__ENDIANESS__) == MDMA_LITTLE_BYTE_ENDIANESS_EXCHANGE) || \ - ((__ENDIANESS__) == MDMA_LITTLE_HALFWORD_ENDIANESS_EXCHANGE) || \ - ((__ENDIANESS__) == MDMA_LITTLE_WORD_ENDIANESS_EXCHANGE)) - +#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE)) #define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_I2C6_TX)) @@ -778,9 +787,9 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma); ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD)) #define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || \ - ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \ - ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \ - ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT)) + ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \ + ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \ + ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT)) #define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \ @@ -792,7 +801,7 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma); ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \ ((__BURST__) == MDMA_SOURCE_BURST_128BEATS)) - + #define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \ ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \ ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \ @@ -803,25 +812,21 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma); ((__BURST__) == MDMA_DEST_BURST_128BEATS)) #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || \ - ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \ - ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \ - ((__MODE__) == MDMA_FULL_TRANSFER)) + ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \ + ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \ + ((__MODE__) == MDMA_FULL_TRANSFER)) -#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001) && ((__LENGTH__) < 0x000000FF)) +#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU)) -#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0 ) && ((__COUNT__) <= 4096)) +#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U)) -#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0) && ((SIZE) <= 65536)) +#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U)) #define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536)) /** * @} - */ - -/** - * @} - */ + */ /* Private functions prototypes ----------------------------------------------*/ /** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes @@ -853,6 +858,6 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma); } #endif -#endif /* __STM32MP1xx_HAL_MDMA_H */ +#endif /* STM32MP1xx_HAL_MDMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc.h index b20a6303a5..6166c1684f 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc.h @@ -325,10 +325,10 @@ typedef struct /** @defgroup RCC_HSI_Clock_Prescaler RCC_HSI_Clock_Prescaler * @{ */ -#define RCC_HSI_DIV1 RCC_HSICFGR_HSIDIV_0 /* Division by 1, ck_hsi(_ker) = 64 MHz (default after reset)*/ -#define RCC_HSI_DIV2 RCC_HSICFGR_HSIDIV_1 /* Division by 2, ck_hsi(_ker) = 32 MHz*/ -#define RCC_HSI_DIV4 RCC_HSICFGR_HSIDIV_2 /* Division by 4, ck_hsi(_ker) = 16 MHz*/ -#define RCC_HSI_DIV8 RCC_HSICFGR_HSIDIV_3 /* Division by 8, ck_hsi(_ker) = 8 MHz*/ +#define RCC_HSI_DIV1 0U /* Division by 1, ck_hsi(_ker) = 64 MHz (default after reset)*/ +#define RCC_HSI_DIV2 RCC_HSICFGR_HSIDIV_0 /* Division by 2, ck_hsi(_ker) = 32 MHz*/ +#define RCC_HSI_DIV4 RCC_HSICFGR_HSIDIV_1 /* Division by 4, ck_hsi(_ker) = 16 MHz*/ +#define RCC_HSI_DIV8 (RCC_HSICFGR_HSIDIV_0 | RCC_HSICFGR_HSIDIV_1) /* Division by 8, ck_hsi(_ker) = 8 MHz*/ #define IS_RCC_HSIDIV(DIV) (((DIV) == RCC_HSI_DIV1) || ((DIV) == RCC_HSI_DIV2) || \ ((DIV) == RCC_HSI_DIV4) || ((DIV) == RCC_HSI_DIV8) ) @@ -374,11 +374,11 @@ typedef struct /** @defgroup RCC_MCO1_Clock_Source RCC_MCO1_Clock_Source * @{ */ -#define RCC_MCO1SOURCE_HSI RCC_MCO1CFGR_MCO1SEL_0 -#define RCC_MCO1SOURCE_HSE RCC_MCO1CFGR_MCO1SEL_1 -#define RCC_MCO1SOURCE_CSI RCC_MCO1CFGR_MCO1SEL_2 -#define RCC_MCO1SOURCE_LSI RCC_MCO1CFGR_MCO1SEL_3 -#define RCC_MCO1SOURCE_LSE RCC_MCO1CFGR_MCO1SEL_4 +#define RCC_MCO1SOURCE_HSI 0U +#define RCC_MCO1SOURCE_HSE RCC_MCO1CFGR_MCO1SEL_0 +#define RCC_MCO1SOURCE_CSI RCC_MCO1CFGR_MCO1SEL_1 +#define RCC_MCO1SOURCE_LSI (RCC_MCO1CFGR_MCO1SEL_0 | RCC_MCO1CFGR_MCO1SEL_1) +#define RCC_MCO1SOURCE_LSE RCC_MCO1CFGR_MCO1SEL_2 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ @@ -391,12 +391,12 @@ typedef struct /** @defgroup RCC_MCO2_Clock_Source RCC_MCO2_Clock_Source * @{ */ -#define RCC_MCO2SOURCE_MPU RCC_MCO2CFGR_MCO2SEL_0 -#define RCC_MCO2SOURCE_AXI RCC_MCO2CFGR_MCO2SEL_1 -#define RCC_MCO2SOURCE_MCU RCC_MCO2CFGR_MCO2SEL_2 -#define RCC_MCO2SOURCE_PLL4 RCC_MCO2CFGR_MCO2SEL_3 -#define RCC_MCO2SOURCE_HSE RCC_MCO2CFGR_MCO2SEL_4 -#define RCC_MCO2SOURCE_HSI RCC_MCO2CFGR_MCO2SEL_5 +#define RCC_MCO2SOURCE_MPU 0U +#define RCC_MCO2SOURCE_AXI RCC_MCO2CFGR_MCO2SEL_0 +#define RCC_MCO2SOURCE_MCU RCC_MCO2CFGR_MCO2SEL_1 +#define RCC_MCO2SOURCE_PLL4 (RCC_MCO2CFGR_MCO2SEL_1 | RCC_MCO2CFGR_MCO2SEL_0) +#define RCC_MCO2SOURCE_HSE RCC_MCO2CFGR_MCO2SEL_2 +#define RCC_MCO2SOURCE_HSI (RCC_MCO2CFGR_MCO2SEL_2 | RCC_MCO2CFGR_MCO2SEL_0) #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_MPU) || ((SOURCE) == RCC_MCO2SOURCE_AXI) || \ ((SOURCE) == RCC_MCO2SOURCE_MCU) || ((SOURCE) == RCC_MCO2SOURCE_PLL4) || \ @@ -409,22 +409,22 @@ typedef struct * @{ * @note: MCO1 division factors are used for MCODIV values as they are the same for MCO2 */ -#define RCC_MCODIV_1 RCC_MCO1CFGR_MCO1DIV_0 -#define RCC_MCODIV_2 RCC_MCO1CFGR_MCO1DIV_1 -#define RCC_MCODIV_3 RCC_MCO1CFGR_MCO1DIV_2 -#define RCC_MCODIV_4 RCC_MCO1CFGR_MCO1DIV_3 -#define RCC_MCODIV_5 RCC_MCO1CFGR_MCO1DIV_4 -#define RCC_MCODIV_6 RCC_MCO1CFGR_MCO1DIV_5 -#define RCC_MCODIV_7 RCC_MCO1CFGR_MCO1DIV_6 -#define RCC_MCODIV_8 RCC_MCO1CFGR_MCO1DIV_7 -#define RCC_MCODIV_9 RCC_MCO1CFGR_MCO1DIV_8 -#define RCC_MCODIV_10 RCC_MCO1CFGR_MCO1DIV_9 -#define RCC_MCODIV_11 RCC_MCO1CFGR_MCO1DIV_10 -#define RCC_MCODIV_12 RCC_MCO1CFGR_MCO1DIV_11 -#define RCC_MCODIV_13 RCC_MCO1CFGR_MCO1DIV_12 -#define RCC_MCODIV_14 RCC_MCO1CFGR_MCO1DIV_13 -#define RCC_MCODIV_15 RCC_MCO1CFGR_MCO1DIV_14 -#define RCC_MCODIV_16 RCC_MCO1CFGR_MCO1DIV_15 +#define RCC_MCODIV_1 0U +#define RCC_MCODIV_2 RCC_MCO1CFGR_MCO1DIV_0 +#define RCC_MCODIV_3 RCC_MCO1CFGR_MCO1DIV_1 +#define RCC_MCODIV_4 (RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) +#define RCC_MCODIV_5 RCC_MCO1CFGR_MCO1DIV_2 +#define RCC_MCODIV_6 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0) +#define RCC_MCODIV_7 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1) +#define RCC_MCODIV_8 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) +#define RCC_MCODIV_9 RCC_MCO1CFGR_MCO1DIV_3 +#define RCC_MCODIV_10 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_0) +#define RCC_MCODIV_11 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1) +#define RCC_MCODIV_12 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) +#define RCC_MCODIV_13 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2) +#define RCC_MCODIV_14 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0) +#define RCC_MCODIV_15 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1) +#define RCC_MCODIV_16 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) @@ -444,10 +444,10 @@ typedef struct /** @defgroup RCC_MPU_Clock_Source RCC_MPU_Clock_Source * @{ */ -#define RCC_MPUSOURCE_HSI RCC_MPCKSELR_MPUSRC_0 -#define RCC_MPUSOURCE_HSE RCC_MPCKSELR_MPUSRC_1 -#define RCC_MPUSOURCE_PLL1 RCC_MPCKSELR_MPUSRC_2 -#define RCC_MPUSOURCE_MPUDIV RCC_MPCKSELR_MPUSRC_3 +#define RCC_MPUSOURCE_HSI 0U +#define RCC_MPUSOURCE_HSE RCC_MPCKSELR_MPUSRC_0 +#define RCC_MPUSOURCE_PLL1 RCC_MPCKSELR_MPUSRC_1 +#define RCC_MPUSOURCE_MPUDIV (RCC_MPCKSELR_MPUSRC_0 | RCC_MPCKSELR_MPUSRC_1) #define IS_RCC_MPUSOURCE(SOURCE) (((SOURCE) == RCC_MPUSOURCE_HSI) || \ ((SOURCE) == RCC_MPUSOURCE_HSE) || \ @@ -460,10 +460,10 @@ typedef struct /** @defgroup RCC_AXISS_Clock_Source RCC_AXISS_Clock_Source * @{ */ -#define RCC_AXISSOURCE_HSI RCC_ASSCKSELR_AXISSRC_0 -#define RCC_AXISSOURCE_HSE RCC_ASSCKSELR_AXISSRC_1 -#define RCC_AXISSOURCE_PLL2 RCC_ASSCKSELR_AXISSRC_2 -#define RCC_AXISSOURCE_OFF RCC_ASSCKSELR_AXISSRC_3 +#define RCC_AXISSOURCE_HSI 0U +#define RCC_AXISSOURCE_HSE RCC_ASSCKSELR_AXISSRC_0 +#define RCC_AXISSOURCE_PLL2 RCC_ASSCKSELR_AXISSRC_1 +#define RCC_AXISSOURCE_OFF (RCC_ASSCKSELR_AXISSRC_1 | RCC_ASSCKSELR_AXISSRC_0) #define IS_RCC_AXISSOURCE(SOURCE) (((SOURCE) == RCC_AXISSOURCE_HSI) || \ ((SOURCE) == RCC_AXISSOURCE_HSE) || \ @@ -476,10 +476,10 @@ typedef struct /** @defgroup RCC_MCU_Clock_Source RCC_MCU_Clock_Source * @{ */ -#define RCC_MCUSSOURCE_HSI RCC_MSSCKSELR_MCUSSRC_0 -#define RCC_MCUSSOURCE_HSE RCC_MSSCKSELR_MCUSSRC_1 -#define RCC_MCUSSOURCE_CSI RCC_MSSCKSELR_MCUSSRC_2 -#define RCC_MCUSSOURCE_PLL3 RCC_MSSCKSELR_MCUSSRC_3 +#define RCC_MCUSSOURCE_HSI 0U +#define RCC_MCUSSOURCE_HSE RCC_MSSCKSELR_MCUSSRC_0 +#define RCC_MCUSSOURCE_CSI RCC_MSSCKSELR_MCUSSRC_1 +#define RCC_MCUSSOURCE_PLL3 (RCC_MSSCKSELR_MCUSSRC_1 | RCC_MSSCKSELR_MCUSSRC_0) #define IS_RCC_MCUSSOURCE(SOURCE) (((SOURCE) == RCC_MCUSSOURCE_HSI) || \ ((SOURCE) == RCC_MCUSSOURCE_HSE) || \ @@ -493,7 +493,7 @@ typedef struct /** @defgroup RCC_RTC_Division_Factor RCC_RTC_Division_Factor * @{ */ -#define RCC_RTCDIV(x) RCC_RTCDIVR_RTCDIV_(y) +#define RCC_RTCDIV(x) (uint32_t)(x - 1U) #define IS_RCC_RTC_HSEDIV(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64)) /** @@ -503,11 +503,11 @@ typedef struct /** @defgroup RCC_MPU_Clock_Divider RCC_MPU_Clock_Divider * @{ */ -#define RCC_MPU_DIV_OFF RCC_MPCKDIVR_MPUDIV_0 -#define RCC_MPU_DIV2 RCC_MPCKDIVR_MPUDIV_1 -#define RCC_MPU_DIV4 RCC_MPCKDIVR_MPUDIV_2 -#define RCC_MPU_DIV8 RCC_MPCKDIVR_MPUDIV_3 -#define RCC_MPU_DIV16 RCC_MPCKDIVR_MPUDIV_4 +#define RCC_MPU_DIV_OFF 0U +#define RCC_MPU_DIV2 RCC_MPCKDIVR_MPUDIV_0 +#define RCC_MPU_DIV4 RCC_MPCKDIVR_MPUDIV_1 +#define RCC_MPU_DIV8 (RCC_MPCKDIVR_MPUDIV_1 | RCC_MPCKDIVR_MPUDIV_0) +#define RCC_MPU_DIV16 RCC_MPCKDIVR_MPUDIV_2 #define IS_RCC_MPUDIV(DIVIDER) ( ((DIVIDER) == RCC_MPU_DIV2) || \ ((DIVIDER) == RCC_MPU_DIV4) || \ @@ -520,10 +520,10 @@ typedef struct /** @defgroup RCC_AXI_Clock_Divider RCC_AXI_Clock_Divider * @{ */ -#define RCC_AXI_DIV1 RCC_AXIDIVR_AXIDIV_0 -#define RCC_AXI_DIV2 RCC_AXIDIVR_AXIDIV_1 -#define RCC_AXI_DIV3 RCC_AXIDIVR_AXIDIV_2 -#define RCC_AXI_DIV4 RCC_AXIDIVR_AXIDIV_3 +#define RCC_AXI_DIV1 0U +#define RCC_AXI_DIV2 RCC_AXIDIVR_AXIDIV_0 +#define RCC_AXI_DIV3 RCC_AXIDIVR_AXIDIV_1 +#define RCC_AXI_DIV4 (RCC_AXIDIVR_AXIDIV_0 | RCC_AXIDIVR_AXIDIV_1) #define IS_RCC_AXIDIV(DIVIDER) (((DIVIDER) == RCC_AXI_DIV1) || \ ((DIVIDER) == RCC_AXI_DIV2) || \ @@ -536,11 +536,11 @@ typedef struct /** @defgroup RCC_APB4_Clock_Divider RCC_APB4_Clock_Divider * @{ */ -#define RCC_APB4_DIV1 RCC_APB4DIVR_APB4DIV_0 -#define RCC_APB4_DIV2 RCC_APB4DIVR_APB4DIV_1 -#define RCC_APB4_DIV4 RCC_APB4DIVR_APB4DIV_2 -#define RCC_APB4_DIV8 RCC_APB4DIVR_APB4DIV_3 -#define RCC_APB4_DIV16 RCC_APB4DIVR_APB4DIV_4 +#define RCC_APB4_DIV1 0U +#define RCC_APB4_DIV2 RCC_APB4DIVR_APB4DIV_0 +#define RCC_APB4_DIV4 RCC_APB4DIVR_APB4DIV_1 +#define RCC_APB4_DIV8 (RCC_APB4DIVR_APB4DIV_1 | RCC_APB4DIVR_APB4DIV_0) +#define RCC_APB4_DIV16 RCC_APB4DIVR_APB4DIV_2 #define IS_RCC_APB4DIV(DIVIDER) (((DIVIDER) == RCC_APB4_DIV1) || \ ((DIVIDER) == RCC_APB4_DIV2) || \ @@ -554,11 +554,11 @@ typedef struct /** @defgroup RCC_APB5_Clock_Divider RCC_APB5_Clock_Divider * @{ */ -#define RCC_APB5_DIV1 RCC_APB5DIVR_APB5DIV_0 -#define RCC_APB5_DIV2 RCC_APB5DIVR_APB5DIV_1 -#define RCC_APB5_DIV4 RCC_APB5DIVR_APB5DIV_2 -#define RCC_APB5_DIV8 RCC_APB5DIVR_APB5DIV_3 -#define RCC_APB5_DIV16 RCC_APB5DIVR_APB5DIV_4 +#define RCC_APB5_DIV1 0U +#define RCC_APB5_DIV2 RCC_APB5DIVR_APB5DIV_0 +#define RCC_APB5_DIV4 RCC_APB5DIVR_APB5DIV_1 +#define RCC_APB5_DIV8 (RCC_APB5DIVR_APB5DIV_1 | RCC_APB5DIVR_APB5DIV_0) +#define RCC_APB5_DIV16 RCC_APB5DIVR_APB5DIV_2 #define IS_RCC_APB5DIV(DIVIDER) (((DIVIDER) == RCC_APB5_DIV1) || \ ((DIVIDER) == RCC_APB5_DIV2) || \ @@ -572,16 +572,16 @@ typedef struct /** @defgroup RCC_MCU_Clock_Divider RCC_MCU_Clock_Divider * @{ */ -#define RCC_MCU_DIV1 RCC_MCUDIVR_MCUDIV_0 -#define RCC_MCU_DIV2 RCC_MCUDIVR_MCUDIV_1 -#define RCC_MCU_DIV4 RCC_MCUDIVR_MCUDIV_2 -#define RCC_MCU_DIV8 RCC_MCUDIVR_MCUDIV_3 -#define RCC_MCU_DIV16 RCC_MCUDIVR_MCUDIV_4 -#define RCC_MCU_DIV32 RCC_MCUDIVR_MCUDIV_5 -#define RCC_MCU_DIV64 RCC_MCUDIVR_MCUDIV_6 -#define RCC_MCU_DIV128 RCC_MCUDIVR_MCUDIV_7 -#define RCC_MCU_DIV256 RCC_MCUDIVR_MCUDIV_8 -#define RCC_MCU_DIV512 RCC_MCUDIVR_MCUDIV_9 +#define RCC_MCU_DIV1 0U +#define RCC_MCU_DIV2 RCC_MCUDIVR_MCUDIV_0 +#define RCC_MCU_DIV4 RCC_MCUDIVR_MCUDIV_1 +#define RCC_MCU_DIV8 (RCC_MCUDIVR_MCUDIV_1 | RCC_MCUDIVR_MCUDIV_0) +#define RCC_MCU_DIV16 RCC_MCUDIVR_MCUDIV_2 +#define RCC_MCU_DIV32 (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_0) +#define RCC_MCU_DIV64 (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_1) +#define RCC_MCU_DIV128 (RCC_MCUDIVR_MCUDIV_2 | RCC_MCUDIVR_MCUDIV_1 | RCC_MCUDIVR_MCUDIV_0) +#define RCC_MCU_DIV256 RCC_MCUDIVR_MCUDIV_3 +#define RCC_MCU_DIV512 (RCC_MCUDIVR_MCUDIV_3 | RCC_MCUDIVR_MCUDIV_0) #define IS_RCC_MCUDIV(DIVIDER) (((DIVIDER) == RCC_MCU_DIV1) || \ ((DIVIDER) == RCC_MCU_DIV2) || \ @@ -600,11 +600,11 @@ typedef struct /** @defgroup RCC_APB1_Clock_Divider RCC_APB1_Clock_Divider * @{ */ -#define RCC_APB1_DIV1 RCC_APB1DIVR_APB1DIV_0 -#define RCC_APB1_DIV2 RCC_APB1DIVR_APB1DIV_1 -#define RCC_APB1_DIV4 RCC_APB1DIVR_APB1DIV_2 -#define RCC_APB1_DIV8 RCC_APB1DIVR_APB1DIV_3 -#define RCC_APB1_DIV16 RCC_APB1DIVR_APB1DIV_4 +#define RCC_APB1_DIV1 0U +#define RCC_APB1_DIV2 RCC_APB1DIVR_APB1DIV_0 +#define RCC_APB1_DIV4 RCC_APB1DIVR_APB1DIV_1 +#define RCC_APB1_DIV8 (RCC_APB1DIVR_APB1DIV_1 | RCC_APB1DIVR_APB1DIV_0) +#define RCC_APB1_DIV16 RCC_APB1DIVR_APB1DIV_2 #define IS_RCC_APB1DIV(DIVIDER) (((DIVIDER) == RCC_APB1_DIV1) || \ ((DIVIDER) == RCC_APB1_DIV2) || \ @@ -618,11 +618,11 @@ typedef struct /** @defgroup RCC_APB2_Clock_Divider RCC_APB2_Clock_Divider * @{ */ -#define RCC_APB2_DIV1 RCC_APB2DIVR_APB2DIV_0 -#define RCC_APB2_DIV2 RCC_APB2DIVR_APB2DIV_1 -#define RCC_APB2_DIV4 RCC_APB2DIVR_APB2DIV_2 -#define RCC_APB2_DIV8 RCC_APB2DIVR_APB2DIV_3 -#define RCC_APB2_DIV16 RCC_APB2DIVR_APB2DIV_4 +#define RCC_APB2_DIV1 0U +#define RCC_APB2_DIV2 RCC_APB2DIVR_APB2DIV_0 +#define RCC_APB2_DIV4 RCC_APB2DIVR_APB2DIV_1 +#define RCC_APB2_DIV8 (RCC_APB2DIVR_APB2DIV_1 | RCC_APB2DIVR_APB2DIV_0) +#define RCC_APB2_DIV16 RCC_APB2DIVR_APB2DIV_2 #define IS_RCC_APB2DIV(DIVIDER) (((DIVIDER) == RCC_APB2_DIV1) || \ ((DIVIDER) == RCC_APB2_DIV2) || \ @@ -636,11 +636,11 @@ typedef struct /** @defgroup RCC_APB3_Clock_Divider RCC_APB3_Clock_Divider * @{ */ -#define RCC_APB3_DIV1 RCC_APB3DIVR_APB3DIV_0 -#define RCC_APB3_DIV2 RCC_APB3DIVR_APB3DIV_1 -#define RCC_APB3_DIV4 RCC_APB3DIVR_APB3DIV_2 -#define RCC_APB3_DIV8 RCC_APB3DIVR_APB3DIV_3 -#define RCC_APB3_DIV16 RCC_APB3DIVR_APB3DIV_4 +#define RCC_APB3_DIV1 0U +#define RCC_APB3_DIV2 RCC_APB3DIVR_APB3DIV_0 +#define RCC_APB3_DIV4 RCC_APB3DIVR_APB3DIV_1 +#define RCC_APB3_DIV8 (RCC_APB3DIVR_APB3DIV_1| RCC_APB3DIVR_APB3DIV_0) +#define RCC_APB3_DIV16 RCC_APB3DIVR_APB3DIV_2 #define IS_RCC_APB3DIV(DIVIDER) (((DIVIDER) == RCC_APB3_DIV1) || \ ((DIVIDER) == RCC_APB3_DIV2) || \ @@ -744,9 +744,9 @@ typedef struct /** @defgroup RCC_PLL12_Clock_Source RCC_PLL12_Clock_Source * @{ */ -#define RCC_PLL12SOURCE_HSI RCC_RCK12SELR_PLL12SRC_0 -#define RCC_PLL12SOURCE_HSE RCC_RCK12SELR_PLL12SRC_1 -#define RCC_PLL12SOURCE_OFF RCC_RCK12SELR_PLL12SRC_2 +#define RCC_PLL12SOURCE_HSI 0U +#define RCC_PLL12SOURCE_HSE RCC_RCK12SELR_PLL12SRC_0 +#define RCC_PLL12SOURCE_OFF RCC_RCK12SELR_PLL12SRC_1 #define IS_RCC_PLL12SOURCE(SOURCE) (((SOURCE) == RCC_PLL12SOURCE_HSI) || \ ((SOURCE) == RCC_PLL12SOURCE_HSE) || \ @@ -759,10 +759,10 @@ typedef struct /** @defgroup RCC_PLL3_Clock_Source RCC_PLL3_Clock_Source * @{ */ -#define RCC_PLL3SOURCE_HSI RCC_RCK3SELR_PLL3SRC_0 -#define RCC_PLL3SOURCE_HSE RCC_RCK3SELR_PLL3SRC_1 -#define RCC_PLL3SOURCE_CSI RCC_RCK3SELR_PLL3SRC_2 -#define RCC_PLL3SOURCE_OFF RCC_RCK3SELR_PLL3SRC_3 +#define RCC_PLL3SOURCE_HSI 0U +#define RCC_PLL3SOURCE_HSE RCC_RCK3SELR_PLL3SRC_0 +#define RCC_PLL3SOURCE_CSI RCC_RCK3SELR_PLL3SRC_1 +#define RCC_PLL3SOURCE_OFF (RCC_RCK3SELR_PLL3SRC_1 | RCC_RCK3SELR_PLL3SRC_0) #define IS_RCC_PLL3SOURCE(SOURCE) (((SOURCE) == RCC_PLL3SOURCE_HSI) || \ @@ -778,10 +778,10 @@ typedef struct /** @defgroup RCC_PLL4_Clock_Source RCC_PLL4_Clock_Source * @{ */ -#define RCC_PLL4SOURCE_HSI RCC_RCK4SELR_PLL4SRC_0 -#define RCC_PLL4SOURCE_HSE RCC_RCK4SELR_PLL4SRC_1 -#define RCC_PLL4SOURCE_CSI RCC_RCK4SELR_PLL4SRC_2 -#define RCC_PLL4SOURCE_I2S_CKIN RCC_RCK4SELR_PLL4SRC_3 +#define RCC_PLL4SOURCE_HSI 0U +#define RCC_PLL4SOURCE_HSE RCC_RCK4SELR_PLL4SRC_0 +#define RCC_PLL4SOURCE_CSI RCC_RCK4SELR_PLL4SRC_1 +#define RCC_PLL4SOURCE_I2S_CKIN (RCC_RCK4SELR_PLL4SRC_1 | RCC_RCK4SELR_PLL4SRC_0) #define IS_RCC_PLL4SOURCE(SOURCE) (((SOURCE) == RCC_PLL4SOURCE_HSI) || \ @@ -911,8 +911,8 @@ typedef struct /** @defgroup RCC_PLL3_IF_Range RCC_PLL3_IF_Range * @{ */ -#define RCC_PLL3IFRANGE_0 RCC_PLL3CFGR1_IFRGE_0 -#define RCC_PLL3IFRANGE_1 RCC_PLL3CFGR1_IFRGE_1 +#define RCC_PLL3IFRANGE_0 0U +#define RCC_PLL3IFRANGE_1 RCC_PLL3CFGR1_IFRGE_0 /** * @} */ @@ -920,8 +920,8 @@ typedef struct /** @defgroup RCC_PLL4_IF_Range RCC_PLL4_IF_Range * @{ */ -#define RCC_PLL4IFRANGE_0 RCC_PLL4CFGR1_IFRGE_0 -#define RCC_PLL4IFRANGE_1 RCC_PLL4CFGR1_IFRGE_1 +#define RCC_PLL4IFRANGE_0 0U +#define RCC_PLL4IFRANGE_1 RCC_PLL4CFGR1_IFRGE_0 /** * @} */ @@ -930,10 +930,10 @@ typedef struct /** @defgroup RCC_RTC_Clock_Source RCC_RTC_Clock_Source * @{ */ -#define RCC_RTCCLKSOURCE_OFF RCC_BDCR_RTCSRC_0 /* No clock (default after backup domain reset)*/ -#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSRC_1 -#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSRC_2 -#define RCC_RTCCLKSOURCE_HSE_DIV RCC_BDCR_RTCSRC_3 /* HSE clock divided by RTCDIV value is used as RTC clock*/ +#define RCC_RTCCLKSOURCE_OFF 0U /* No clock (default after backup domain reset)*/ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSRC_0 +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSRC_1 +#define RCC_RTCCLKSOURCE_HSE_DIV (RCC_BDCR_RTCSRC_1 | RCC_BDCR_RTCSRC_0) /* HSE clock divided by RTCDIV value is used as RTC clock*/ #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_OFF) || ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \ ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV)) @@ -1117,10 +1117,10 @@ typedef struct /** @defgroup RCC_LSEDrive_Config RCC_LSEDrive_Config * @{ */ -#define RCC_LSEDRIVE_LOW RCC_BDCR_LSEDRV_0 /*!< LSE low drive capability */ -#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< LSE medium low drive capability */ -#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_2 /*!< LSE medium high drive capability */ -#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV_3 /*!< LSE high drive capability */ +#define RCC_LSEDRIVE_LOW 0U /*!< LSE low drive capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH (RCC_BDCR_LSEDRV_1 | RCC_BDCR_LSEDRV_0) /*!< LSE high drive capability */ #define IS_RCC_LSEDRIVE(VALUE) (((VALUE) == RCC_LSEDRIVE_LOW) || ((VALUE) == RCC_LSEDRIVE_MEDIUMLOW) || \ ((VALUE) == RCC_LSEDRIVE_MEDIUMHIGH) || ((VALUE) == RCC_LSEDRIVE_HIGH)) @@ -1285,7 +1285,6 @@ typedef struct #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_SYSCFGRST) #define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_VREFRST) #define __HAL_RCC_DTS_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_DTSRST) -#define __HAL_RCC_PMBCTRL_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_PMBCTRLRST) #define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTCLRR = 0x0003290FU) #define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM2RST) @@ -1296,7 +1295,6 @@ typedef struct #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_SYSCFGRST) #define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_VREFRST) #define __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_DTSRST) -#define __HAL_RCC_PMBCTRL_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_PMBCTRLRST) /** @brief Force or release the AHB2 peripheral reset. */ #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTSETR = 0x00010127U) @@ -1460,187 +1458,185 @@ typedef struct /** @brief Enable or disable the APB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. It shall be used to allocate a peripheral to the MCU. + * using it. It shall be used to allocate a peripheral to the MPU. */ -#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM2EN) -#define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM3EN) -#define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM4EN) -#define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM5EN) -#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM6EN) -#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM7EN) -#define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM12EN) -#define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM13EN) -#define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM14EN) -#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_LPTIM1EN) -#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_SPI2EN) -#define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_SPI3EN) -#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_USART2EN) -#define __HAL_RCC_USART3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_USART3EN) -#define __HAL_RCC_UART4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART4EN) -#define __HAL_RCC_UART5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART5EN) -#define __HAL_RCC_UART7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART7EN) -#define __HAL_RCC_UART8_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART8EN) -#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C1EN) -#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C2EN) -#define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C3EN) -#define __HAL_RCC_I2C5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C5EN) -#define __HAL_RCC_SPDIFRX_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_SPDIFEN) -#define __HAL_RCC_CEC_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_CECEN) -#define __HAL_RCC_DAC12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_DAC12EN) -#define __HAL_RCC_MDIOS_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_MDIOSEN) - -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM2EN) -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM3EN) -#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM4EN) -#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM5EN) -#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM6EN) -#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM7EN) -#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM12EN) -#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM13EN) -#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM14EN) -#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_LPTIM1EN) -#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI2EN) -#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI3EN) -#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART2EN) -#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART3EN) -#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART4EN) -#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART4EN) -#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART5EN) -#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART7EN) -#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART8EN) -#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C1EN) -#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C2EN) -#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C3EN) -#define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C5EN) -#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPDIFEN) -#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_CECEN) -#define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_DAC12EN) -#define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_MDIOSEN) +#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM2EN) +#define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM3EN) +#define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM4EN) +#define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM5EN) +#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM6EN) +#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM7EN) +#define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM12EN) +#define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM13EN) +#define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_TIM14EN) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_LPTIM1EN) +#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_SPI2EN) +#define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_SPI3EN) +#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_USART2EN) +#define __HAL_RCC_USART3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_USART3EN) +#define __HAL_RCC_UART4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART4EN) +#define __HAL_RCC_UART5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART5EN) +#define __HAL_RCC_UART7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART7EN) +#define __HAL_RCC_UART8_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_UART8EN) +#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C1EN) +#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C2EN) +#define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C3EN) +#define __HAL_RCC_I2C5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_I2C5EN) +#define __HAL_RCC_SPDIFRX_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_SPDIFEN) +#define __HAL_RCC_CEC_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_CECEN) +#define __HAL_RCC_DAC12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_DAC12EN) +#define __HAL_RCC_MDIOS_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MP_APB1ENSETR_MDIOSEN) + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM2EN) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM3EN) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM4EN) +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM5EN) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM6EN) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM7EN) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM12EN) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM13EN) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_TIM14EN) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_LPTIM1EN) +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_SPI2EN) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_SPI3EN) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_USART2EN) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_USART3EN) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART4EN) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART4EN) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART5EN) +#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART7EN) +#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_UART8EN) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C1EN) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C2EN) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C3EN) +#define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_I2C5EN) +#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_SPDIFEN) +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_CECEN) +#define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_DAC12EN) +#define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MP_APB1ENCLRR_MDIOSEN) /** @brief Enable or disable the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. It shall be used to allocate a peripheral to the MCU. - */ -#define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM1EN) -#define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM8EN) -#define __HAL_RCC_TIM15_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM15EN) -#define __HAL_RCC_TIM16_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM16EN) -#define __HAL_RCC_TIM17_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM17EN) -#define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SPI1EN) -#define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SPI4EN) -#define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SPI5EN) -#define __HAL_RCC_USART6_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_USART6EN) -#define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SAI1EN) -#define __HAL_RCC_SAI2_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SAI2EN) -#define __HAL_RCC_SAI3_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SAI3EN) -#define __HAL_RCC_DFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_DFSDMEN) -#define __HAL_RCC_ADFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_ADFSDMEN) -#define __HAL_RCC_FDCAN_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_FDCANEN) - -#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM1EN) -#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM8EN) -#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM15EN) -#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM16EN) -#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM17EN) -#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI1EN) -#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI4EN) -#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI5EN) -#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_USART6EN) -#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI1EN) -#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI2EN) -#define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI3EN) -#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_DFSDMEN) -#define __HAL_RCC_ADFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_ADFSDMEN) -#define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_FDCANEN) + * using it. It shall be used to allocate a peripheral to the MPU. + */ +#define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM1EN) +#define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM8EN) +#define __HAL_RCC_TIM15_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM15EN) +#define __HAL_RCC_TIM16_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM16EN) +#define __HAL_RCC_TIM17_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_TIM17EN) +#define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SPI1EN) +#define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SPI4EN) +#define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SPI5EN) +#define __HAL_RCC_USART6_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_USART6EN) +#define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SAI1EN) +#define __HAL_RCC_SAI2_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SAI2EN) +#define __HAL_RCC_SAI3_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_SAI3EN) +#define __HAL_RCC_DFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_DFSDMEN) +#define __HAL_RCC_ADFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_ADFSDMEN) +#define __HAL_RCC_FDCAN_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MP_APB2ENSETR_FDCANEN) + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM1EN) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM8EN) +#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM15EN) +#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM16EN) +#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_TIM17EN) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SPI1EN) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SPI4EN) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SPI5EN) +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_USART6EN) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SAI1EN) +#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SAI2EN) +#define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_SAI3EN) +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_DFSDMEN) +#define __HAL_RCC_ADFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_ADFSDMEN) +#define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MP_APB2ENCLRR_FDCANEN) /** @brief Enable or disable the APB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. It shall be used to allocate a peripheral to the MCU. - */ -#define __HAL_RCC_LPTIM2_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM2EN) -#define __HAL_RCC_LPTIM3_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM3EN) -#define __HAL_RCC_LPTIM4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM4EN) -#define __HAL_RCC_LPTIM5_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM5EN) -#define __HAL_RCC_SAI4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_SAI4EN) -#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_SYSCFGEN) -#define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_VREFEN) -#define __HAL_RCC_DTS_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_DTSEN) -#define __HAL_RCC_PMBCTRL_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_PMBCTRLEN) -#define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_HDPEN) - -#define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM2EN) -#define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM3EN) -#define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM4EN) -#define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM5EN) -#define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_SAI4EN) -#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_SYSCFGEN) -#define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_VREFEN) -#define __HAL_RCC_DTS_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_DTSEN) -#define __HAL_RCC_PMBCTRL_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_PMBCTRLEN) -#define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_HDPEN) + * using it. It shall be used to allocate a peripheral to the MPU. + */ +#define __HAL_RCC_LPTIM2_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM2EN) +#define __HAL_RCC_LPTIM3_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM3EN) +#define __HAL_RCC_LPTIM4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM4EN) +#define __HAL_RCC_LPTIM5_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_LPTIM5EN) +#define __HAL_RCC_SAI4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_SAI4EN) +#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_SYSCFGEN) +#define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_VREFEN) +#define __HAL_RCC_DTS_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_DTSEN) +#define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MP_APB3ENSETR_HDPEN) + +#define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM2EN) +#define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM3EN) +#define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM4EN) +#define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_LPTIM5EN) +#define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_SAI4EN) +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_SYSCFGEN) +#define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_VREFEN) +#define __HAL_RCC_DTS_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_DTSEN) +#define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MP_APB3ENCLRR_HDPEN) /** @brief Enable or disable the APB4 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. It shall be used to allocate a peripheral to the MCU. + * using it. It shall be used to allocate a peripheral to the MPU. */ -#define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_LTDCEN) -#define __HAL_RCC_DSI_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_DSIEN) -#define __HAL_RCC_DDRPERFM_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_DDRPERFMEN) +#define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_LTDCEN) +#define __HAL_RCC_DSI_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_DSIEN) +#define __HAL_RCC_DDRPERFM_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_DDRPERFMEN) #define __HAL_RCC_IWDG2APB_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_IWDG2APBEN) -#define __HAL_RCC_USBPHY_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_USBPHYEN) -#define __HAL_RCC_STGENRO_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_STGENROEN) +#define __HAL_RCC_USBPHY_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_USBPHYEN) +#define __HAL_RCC_STGENRO_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_STGENROEN) -#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_LTDCEN) -#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_DSIEN) -#define __HAL_RCC_DDRPERFM_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_DDRPERFMEN) +#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_LTDCEN) +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_DSIEN) +#define __HAL_RCC_DDRPERFM_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_DDRPERFMEN) #define __HAL_RCC_IWDG2APB_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_IWDG2APBEN) -#define __HAL_RCC_USBPHY_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_USBPHYEN) -#define __HAL_RCC_STGENRO_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_STGENROEN) +#define __HAL_RCC_USBPHY_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_USBPHYEN) +#define __HAL_RCC_STGENRO_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_STGENROEN) /** @brief Enable or disable the APB5 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. It shall be used to allocate a peripheral to the MCU. - */ -#define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_SPI6EN) -#define __HAL_RCC_I2C4_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_I2C4EN) -#define __HAL_RCC_I2C6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_I2C6EN) -#define __HAL_RCC_USART1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_USART1EN) -#define __HAL_RCC_RTCAPB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_RTCAPBEN) -#define __HAL_RCC_TZC1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_TZC1EN) -#define __HAL_RCC_TZC2_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_TZC2EN) -#define __HAL_RCC_TZPC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_TZPCEN) + * using it. It shall be used to allocate a peripheral to the MPU. + */ +#define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_SPI6EN) +#define __HAL_RCC_I2C4_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_I2C4EN) +#define __HAL_RCC_I2C6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_I2C6EN) +#define __HAL_RCC_USART1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_USART1EN) +#define __HAL_RCC_RTCAPB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_RTCAPBEN) +#define __HAL_RCC_TZC1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_TZC1EN) +#define __HAL_RCC_TZC2_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_TZC2EN) +#define __HAL_RCC_TZPC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_TZPCEN) #define __HAL_RCC_IWDG1APB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_IWDG1APBEN) -#define __HAL_RCC_BSEC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_BSECEN) -#define __HAL_RCC_STGEN_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_STGENEN) - -#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_SPI6EN) -#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C4EN) -#define __HAL_RCC_I2C6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C6EN) -#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_USART1EN) -#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_RTCAPBEN) -#define __HAL_RCC_TZC1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC1EN) -#define __HAL_RCC_TZC2_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC2EN) -#define __HAL_RCC_TZPC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZPCEN) +#define __HAL_RCC_BSEC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_BSECEN) +#define __HAL_RCC_STGEN_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_STGENEN) + +#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_SPI6EN) +#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_I2C4EN) +#define __HAL_RCC_I2C6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_I2C6EN) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_USART1EN) +#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_RTCAPBEN) +#define __HAL_RCC_TZC1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_TZC1EN) +#define __HAL_RCC_TZC2_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_TZC2EN) +#define __HAL_RCC_TZPC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_TZPCEN) #define __HAL_RCC_IWDG1APB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_IWDG1APBEN) -#define __HAL_RCC_BSEC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENSETR_BSECEN) -#define __HAL_RCC_STGEN_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENSETR_STGENEN) +#define __HAL_RCC_BSEC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENSETR_BSECEN) +#define __HAL_RCC_STGEN_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENSETR_STGENEN) /** @brief Enable or disable the AHB5 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. It shall be used to allocate a peripheral to the MCU. + * using it. It shall be used to allocate a peripheral to the MPU. */ -#define __HAL_RCC_GPIOZ_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_GPIOZEN) +#define __HAL_RCC_GPIOZ_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_GPIOZEN) #if defined(CRYP1) -#define __HAL_RCC_CRYP1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_CRYP1EN) +#define __HAL_RCC_CRYP1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_CRYP1EN) #endif -#define __HAL_RCC_HASH1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_HASH1EN) -#define __HAL_RCC_RNG1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_RNG1EN) -#define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_BKPSRAMEN) +#define __HAL_RCC_HASH1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_HASH1EN) +#define __HAL_RCC_RNG1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_RNG1EN) +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MP_AHB5ENSETR_BKPSRAMEN) #define __HAL_RCC_GPIOZ_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_GPIOZEN) #if defined(CRYP1) @@ -1653,116 +1649,116 @@ typedef struct /** @brief Enable or disable the AHB6 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. It shall be used to allocate a peripheral to the MCU. - */ -#define __HAL_RCC_MDMA_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_MDMAEN) -#define __HAL_RCC_GPU_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_GPUEN) -#define __HAL_RCC_ETH1CK_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHCKEN) -#define __HAL_RCC_ETH1TX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHTXEN) -#define __HAL_RCC_ETH1RX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHRXEN) -#define __HAL_RCC_ETH1MAC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHMACEN) -#define __HAL_RCC_FMC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_FMCEN) -#define __HAL_RCC_QSPI_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_QSPIEN) -#define __HAL_RCC_SDMMC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC1EN) -#define __HAL_RCC_SDMMC2_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC2EN) -#define __HAL_RCC_CRC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_CRC1EN) -#define __HAL_RCC_USBH_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_USBHEN) - -#define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_MDMAEN) -#define __HAL_RCC_GPU_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_GPUEN) -#define __HAL_RCC_ETH1CK_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHCKEN) -#define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHTXEN) -#define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHRXEN) -#define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHMACEN) -#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_FMCEN) -#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_QSPIEN) -#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC1EN) -#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC2EN) -#define __HAL_RCC_CRC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_CRC1EN) -#define __HAL_RCC_USBH_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_USBHEN) + * using it. It shall be used to allocate a peripheral to the MPU. + */ +#define __HAL_RCC_MDMA_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_MDMAEN) +#define __HAL_RCC_GPU_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_GPUEN) +#define __HAL_RCC_ETH1CK_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHCKEN) +#define __HAL_RCC_ETH1TX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHTXEN) +#define __HAL_RCC_ETH1RX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHRXEN) +#define __HAL_RCC_ETH1MAC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_ETHMACEN) +#define __HAL_RCC_FMC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_FMCEN) +#define __HAL_RCC_QSPI_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_QSPIEN) +#define __HAL_RCC_SDMMC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_SDMMC1EN) +#define __HAL_RCC_SDMMC2_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_SDMMC2EN) +#define __HAL_RCC_CRC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_CRC1EN) +#define __HAL_RCC_USBH_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MP_AHB6ENSETR_USBHEN) + +#define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_MDMAEN) +#define __HAL_RCC_GPU_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_GPUEN) +#define __HAL_RCC_ETH1CK_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHCKEN) +#define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHTXEN) +#define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHRXEN) +#define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_ETHMACEN) +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_FMCEN) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_QSPIEN) +#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_SDMMC1EN) +#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_SDMMC2EN) +#define __HAL_RCC_CRC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_CRC1EN) +#define __HAL_RCC_USBH_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MP_AHB6ENCLRR_USBHEN) /** @brief Enable or disable the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. It shall be used to allocate a peripheral to the MCU. - */ -#define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA1EN) -#define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA2EN) -#define __HAL_RCC_DMAMUX_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMAMUXEN) -#define __HAL_RCC_ADC12_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_ADC12EN) -#define __HAL_RCC_USBO_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_USBOEN) -#define __HAL_RCC_SDMMC3_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_SDMMC3EN) - -#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA1EN) -#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA2EN) -#define __HAL_RCC_DMAMUX_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMAMUXEN) -#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_ADC12EN) -#define __HAL_RCC_USBO_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_USBOEN) -#define __HAL_RCC_SDMMC3_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_SDMMC3EN) + * using it. It shall be used to allocate a peripheral to the MPU. + */ +#define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_DMA1EN) +#define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_DMA2EN) +#define __HAL_RCC_DMAMUX_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_DMAMUXEN) +#define __HAL_RCC_ADC12_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_ADC12EN) +#define __HAL_RCC_USBO_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_USBOEN) +#define __HAL_RCC_SDMMC3_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MP_AHB2ENSETR_SDMMC3EN) + +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_DMA1EN) +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_DMA2EN) +#define __HAL_RCC_DMAMUX_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_DMAMUXEN) +#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_ADC12EN) +#define __HAL_RCC_USBO_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_USBOEN) +#define __HAL_RCC_SDMMC3_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MP_AHB2ENCLRR_SDMMC3EN) /** @brief Enable or disable the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. It shall be used to allocate a peripheral to the MCU. + * using it. It shall be used to allocate a peripheral to the MPU. */ -#define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_DCMIEN) +#define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_DCMIEN) #if defined(CRYP2) -#define __HAL_RCC_CRYP2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRYP2EN) +#define __HAL_RCC_CRYP2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_CRYP2EN) #endif -#define __HAL_RCC_HASH2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_HASH2EN) -#define __HAL_RCC_RNG2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_RNG2EN) -#define __HAL_RCC_CRC2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRC2EN) -#define __HAL_RCC_HSEM_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_HSEMEN) -#define __HAL_RCC_IPCC_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_IPCCEN) +#define __HAL_RCC_HASH2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_HASH2EN) +#define __HAL_RCC_RNG2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_RNG2EN) +#define __HAL_RCC_CRC2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_CRC2EN) +#define __HAL_RCC_HSEM_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_HSEMEN) +#define __HAL_RCC_IPCC_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MP_AHB3ENSETR_IPCCEN) -#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_DCMIEN) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_DCMIEN) #if defined(CRYP2) -#define __HAL_RCC_CRYP2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRYP2EN) +#define __HAL_RCC_CRYP2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_CRYP2EN) #endif -#define __HAL_RCC_HASH2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HASH2EN) -#define __HAL_RCC_RNG2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_RNG2EN) -#define __HAL_RCC_CRC2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRC2EN) -#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HSEMEN) -#define __HAL_RCC_IPCC_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_IPCCEN) +#define __HAL_RCC_HASH2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_HASH2EN) +#define __HAL_RCC_RNG2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_RNG2EN) +#define __HAL_RCC_CRC2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_CRC2EN) +#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_HSEMEN) +#define __HAL_RCC_IPCC_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MP_AHB3ENCLRR_IPCCEN) /** @brief Enable or disable the AHB4 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. It shall be used to allocate a peripheral to the MCU. - */ -#define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOAEN) -#define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOBEN) -#define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOCEN) -#define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIODEN) -#define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOEEN) -#define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOFEN) -#define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOGEN) -#define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOHEN) -#define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOIEN) -#define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOJEN) -#define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOKEN) - -#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOAEN) -#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOBEN) -#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOCEN) -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIODEN) -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOEEN) -#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOFEN) -#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOGEN) -#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOHEN) -#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOIEN) -#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOJEN) -#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOKEN) + * using it. It shall be used to allocate a peripheral to the MPU. + */ +#define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOAEN) +#define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOBEN) +#define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOCEN) +#define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIODEN) +#define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOEEN) +#define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOFEN) +#define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOGEN) +#define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOHEN) +#define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOIEN) +#define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOJEN) +#define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MP_AHB4ENSETR_GPIOKEN) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOAEN) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOBEN) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOCEN) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIODEN) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOEEN) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOFEN) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOGEN) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOHEN) +#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOIEN) +#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOJEN) +#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MP_AHB4ENCLRR_GPIOKEN) /** @brief Enable or disable the MLAHB peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before - * using it. It shall be used to allocate a peripheral to the MCU. + * using it. It shall be used to allocate a peripheral to the MPU. */ -#define __HAL_RCC_RETRAM_CLK_ENABLE() (RCC->MP_MLAHBENSETR = RCC_MC_MLAHBENSETR_RETRAMEN) +#define __HAL_RCC_RETRAM_CLK_ENABLE() (RCC->MP_MLAHBENSETR = RCC_MP_MLAHBENSETR_RETRAMEN) -#define __HAL_RCC_RETRAM_CLK_DISABLE() (RCC->MP_MLAHBENCLRR = RCC_MC_MLAHBENCLRR_RETRAMEN) +#define __HAL_RCC_RETRAM_CLK_DISABLE() (RCC->MP_MLAHBENCLRR = RCC_MP_MLAHBENCLRR_RETRAMEN) /** @brief MCU reset * @note It generates a reset of the MCU core @@ -1786,59 +1782,59 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during CSLEEP mode. */ -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM2LPEN) -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM3LPEN) -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM4LPEN) -#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM5LPEN) -#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM6LPEN) -#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM7LPEN) -#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM12LPEN) -#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM13LPEN) -#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM14LPEN) -#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_LPTIM1LPEN) -#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI2LPEN) -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI3LPEN) -#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART2LPEN) -#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART3LPEN) -#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART4LPEN) -#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART5LPEN) -#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART7LPEN) -#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART8LPEN) -#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C1LPEN) -#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C2LPEN) -#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C3LPEN) -#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C5LPEN) -#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPDIFLPEN) -#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_CECLPEN) -#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_DAC12LPEN) -#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_MDIOSLPEN) - -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM2LPEN) -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM3LPEN) -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM4LPEN) -#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM5LPEN) -#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM6LPEN) -#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM7LPEN) -#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM12LPEN) -#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM13LPEN) -#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM14LPEN) -#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_LPTIM1LPEN) -#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI2LPEN) -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI3LPEN) -#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART2LPEN) -#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART3LPEN) -#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART4LPEN) -#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART5LPEN) -#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART7LPEN) -#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART8LPEN) -#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C1LPEN) -#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C2LPEN) -#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C3LPEN) -#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C5LPEN) -#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPDIFLPEN) -#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_CECLPEN) -#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_DAC12LPEN) -#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_MDIOSLPEN) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM2LPEN) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM3LPEN) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM4LPEN) +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM5LPEN) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM6LPEN) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM7LPEN) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM12LPEN) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM13LPEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_TIM14LPEN) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_LPTIM1LPEN) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_SPI2LPEN) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_SPI3LPEN) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_USART2LPEN) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_USART3LPEN) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART4LPEN) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART5LPEN) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART7LPEN) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_UART8LPEN) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C1LPEN) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C2LPEN) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C3LPEN) +#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_I2C5LPEN) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_SPDIFLPEN) +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_CECLPEN) +#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_DAC12LPEN) +#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MP_APB1LPENSETR_MDIOSLPEN) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM2LPEN) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM3LPEN) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM4LPEN) +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM5LPEN) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM6LPEN) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM7LPEN) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM12LPEN) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM13LPEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_TIM14LPEN) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_LPTIM1LPEN) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_SPI2LPEN) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_SPI3LPEN) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_USART2LPEN) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_USART3LPEN) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART4LPEN) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART5LPEN) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART7LPEN) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_UART8LPEN) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C1LPEN) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C2LPEN) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C3LPEN) +#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_I2C5LPEN) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_SPDIFLPEN) +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_CECLPEN) +#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_DAC12LPEN) +#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MP_APB1LPENCLRR_MDIOSLPEN) /** @brief Enable or disable the APB2 peripheral clock during CSLEEP mode. @@ -1847,37 +1843,37 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during CSLEEP mode. */ -#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM1LPEN) -#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM8LPEN) -#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM15LPEN) -#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM16LPEN) -#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM17LPEN) -#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI1LPEN) -#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI4LPEN) -#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI5LPEN) -#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_USART6LPEN) -#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI1LPEN) -#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI2LPEN) -#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI3LPEN) -#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_DFSDMLPEN) -#define __HAL_RCC_ADFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_ADFSDMLPEN) -#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_FDCANLPEN) - -#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM1LPEN) -#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM8LPEN) -#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM15LPEN) -#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM16LPEN) -#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM17LPEN) -#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI1LPEN) -#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI4LPEN) -#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI5LPEN) -#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_USART6LPEN) -#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI1LPEN) -#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI2LPEN) -#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI3LPEN) -#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_DFSDMLPEN) -#define __HAL_RCC_ADFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_ADFSDMLPEN) -#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_FDCANLPEN) +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM1LPEN) +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM8LPEN) +#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM15LPEN) +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM16LPEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_TIM17LPEN) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SPI1LPEN) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SPI4LPEN) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SPI5LPEN) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_USART6LPEN) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SAI1LPEN) +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SAI2LPEN) +#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_SAI3LPEN) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_DFSDMLPEN) +#define __HAL_RCC_ADFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_ADFSDMLPEN) +#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MP_APB2LPENSETR_FDCANLPEN) + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM1LPEN) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM8LPEN) +#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM15LPEN) +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM16LPEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_TIM17LPEN) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SPI1LPEN) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SPI4LPEN) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SPI5LPEN) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_USART6LPEN) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SAI1LPEN) +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SAI2LPEN) +#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_SAI3LPEN) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_DFSDMLPEN) +#define __HAL_RCC_ADFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_ADFSDMLPEN) +#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MP_APB2LPENCLRR_FDCANLPEN) /** @brief Enable or disable the APB3 peripheral clock during CSLEEP mode. @@ -1886,25 +1882,23 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during CSLEEP mode. */ -#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM2LPEN) -#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM3LPEN) -#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM4LPEN) -#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM5LPEN) -#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_SAI4LPEN) -#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_SYSCFGLPEN) -#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_VREFLPEN) -#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_DTSLPEN) -#define __HAL_RCC_PMBCTRL_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_PMBCTRLLPEN) - -#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM2LPEN) -#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM3LPEN) -#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM4LPEN) -#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM5LPEN) -#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SAI4LPEN) -#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SYSCFGLPEN) -#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_VREFLPEN) -#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_DTSLPEN) -#define __HAL_RCC_PMBCTRL_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_PMBCTRLLPEN) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM2LPEN) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM3LPEN) +#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM4LPEN) +#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_LPTIM5LPEN) +#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_SAI4LPEN) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_SYSCFGLPEN) +#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_VREFLPEN) +#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MP_APB3LPENSETR_DTSLPEN) + +#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM2LPEN) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM3LPEN) +#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM4LPEN) +#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_LPTIM5LPEN) +#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_SAI4LPEN) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_SYSCFGLPEN) +#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_VREFLPEN) +#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MP_APB3LPENCLRR_DTSLPEN) /** @brief Enable or disable the APB4 peripheral clock during CSLEEP mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -1912,21 +1906,21 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during CSLEEP mode. */ -#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_LTDCLPEN) -#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_DSILPEN) -#define __HAL_RCC_DDRPERFM_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_DDRPERFMLPEN) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_LTDCLPEN) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_DSILPEN) +#define __HAL_RCC_DDRPERFM_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_DDRPERFMLPEN) #define __HAL_RCC_IWDG2APB_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_IWDG2APBLPEN) -#define __HAL_RCC_USBPHY_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_USBPHYLPEN) -#define __HAL_RCC_STGENRO_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROLPEN) -#define __HAL_RCC_STGENRO_CLK_STOP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROSTPEN) +#define __HAL_RCC_USBPHY_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_USBPHYLPEN) +#define __HAL_RCC_STGENRO_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_STGENROLPEN) +#define __HAL_RCC_STGENRO_CLK_STOP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_STGENROSTPEN) -#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_LTDCLPEN) -#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DSILPEN) -#define __HAL_RCC_DDRPERFM_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DDRPERFMLPEN) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_LTDCLPEN) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_DSILPEN) +#define __HAL_RCC_DDRPERFM_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_DDRPERFMLPEN) #define __HAL_RCC_IWDG2APB_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_IWDG2APBLPEN) -#define __HAL_RCC_USBPHY_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_USBPHYLPEN) -#define __HAL_RCC_STGENRO_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROLPEN) -#define __HAL_RCC_STGENRO_CLK_STOP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROSTPEN) +#define __HAL_RCC_USBPHY_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_USBPHYLPEN) +#define __HAL_RCC_STGENRO_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_STGENROLPEN) +#define __HAL_RCC_STGENRO_CLK_STOP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_STGENROSTPEN) /** @brief Enable or disable the APB5 peripheral clock during CSLEEP mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -1934,27 +1928,27 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during CSLEEP mode. */ -#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_SPI6LPEN) -#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C4LPEN) -#define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C6LPEN) -#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_USART1LPEN) -#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_RTCAPBLPEN) -#define __HAL_RCC_TZC1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC1LPEN) -#define __HAL_RCC_TZC2_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC2LPEN) -#define __HAL_RCC_TZPC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZPCLPEN) -#define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_BSECLPEN) -#define __HAL_RCC_STGEN_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_STGENLPEN) - -#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_SPI6LPEN) -#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C4LPEN) -#define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C6LPEN) -#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_USART1LPEN) -#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_RTCAPBLPEN) -#define __HAL_RCC_TZC1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC1LPEN) -#define __HAL_RCC_TZC2_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC2LPEN) -#define __HAL_RCC_TZPC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZPCLPEN) -#define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENSETR_BSECLPEN) -#define __HAL_RCC_STGEN_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENSETR_STGENLPEN) +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_SPI6LPEN) +#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_I2C4LPEN) +#define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_I2C6LPEN) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_USART1LPEN) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_RTCAPBLPEN) +#define __HAL_RCC_TZC1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_TZC1LPEN) +#define __HAL_RCC_TZC2_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_TZC2LPEN) +#define __HAL_RCC_TZPC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_TZPCLPEN) +#define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_BSECLPEN) +#define __HAL_RCC_STGEN_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MP_APB5LPENSETR_STGENLPEN) + +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_SPI6LPEN) +#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_I2C4LPEN) +#define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_I2C6LPEN) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_USART1LPEN) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_RTCAPBLPEN) +#define __HAL_RCC_TZC1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_TZC1LPEN) +#define __HAL_RCC_TZC2_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_TZC2LPEN) +#define __HAL_RCC_TZPC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENCLRR_TZPCLPEN) +#define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENSETR_BSECLPEN) +#define __HAL_RCC_STGEN_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MP_APB5LPENSETR_STGENLPEN) /** @brief Enable or disable the AHB5 peripheral clock during CSLEEP mode. @@ -1963,21 +1957,21 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during CSLEEP mode. */ -#define __HAL_RCC_GPIOZ_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_GPIOZLPEN) +#define __HAL_RCC_GPIOZ_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_GPIOZLPEN) #if defined(CRYP1) -#define __HAL_RCC_CRYP1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_CRYP1LPEN) +#define __HAL_RCC_CRYP1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_CRYP1LPEN) #endif -#define __HAL_RCC_HASH1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_HASH1LPEN) -#define __HAL_RCC_RNG1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_RNG1LPEN) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_BKPSRAMLPEN) +#define __HAL_RCC_HASH1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_HASH1LPEN) +#define __HAL_RCC_RNG1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_RNG1LPEN) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MP_AHB5LPENSETR_BKPSRAMLPEN) -#define __HAL_RCC_GPIOZ_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_GPIOZLPEN) +#define __HAL_RCC_GPIOZ_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_GPIOZLPEN) #if defined(CRYP1) -#define __HAL_RCC_CRYP1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_CRYP1LPEN) +#define __HAL_RCC_CRYP1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_CRYP1LPEN) #endif -#define __HAL_RCC_HASH1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_HASH1LPEN) -#define __HAL_RCC_RNG1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_RNG1LPEN) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN) +#define __HAL_RCC_HASH1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_HASH1LPEN) +#define __HAL_RCC_RNG1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_RNG1LPEN) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN) /** @brief Enable or disable the AHB6 peripheral clock during CSLEEP mode. @@ -1986,31 +1980,31 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during CSLEEP mode. */ -#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_MDMALPEN) -#define __HAL_RCC_GPU_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_GPULPEN) -#define __HAL_RCC_ETH1CK_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHCKLPEN) -#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHTXLPEN) -#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHRXLPEN) -#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHMACLPEN) -#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_FMCLPEN) -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_QSPILPEN) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC1LPEN) -#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC2LPEN) -#define __HAL_RCC_CRC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_CRC1LPEN) -#define __HAL_RCC_USBH_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_USBHLPEN) - -#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_MDMALPEN) -#define __HAL_RCC_GPU_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_GPULPEN) -#define __HAL_RCC_ETH1CK_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHCKLPEN) -#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHTXLPEN) -#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHRXLPEN) -#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHMACLPEN) -#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_FMCLPEN) -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_QSPILPEN) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC1LPEN) -#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC2LPEN) -#define __HAL_RCC_CRC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_CRC1LPEN) -#define __HAL_RCC_USBH_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_USBHLPEN) +#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_MDMALPEN) +#define __HAL_RCC_GPU_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_GPULPEN) +#define __HAL_RCC_ETH1CK_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHCKLPEN) +#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHTXLPEN) +#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHRXLPEN) +#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_ETHMACLPEN) +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_FMCLPEN) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_QSPILPEN) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_SDMMC1LPEN) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_SDMMC2LPEN) +#define __HAL_RCC_CRC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_CRC1LPEN) +#define __HAL_RCC_USBH_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MP_AHB6LPENSETR_USBHLPEN) + +#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_MDMALPEN) +#define __HAL_RCC_GPU_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_GPULPEN) +#define __HAL_RCC_ETH1CK_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHCKLPEN) +#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHTXLPEN) +#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHRXLPEN) +#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_ETHMACLPEN) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_FMCLPEN) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_QSPILPEN) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_SDMMC1LPEN) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_SDMMC2LPEN) +#define __HAL_RCC_CRC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_CRC1LPEN) +#define __HAL_RCC_USBH_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MP_AHB6LPENCLRR_USBHLPEN) /** @brief Enable or disable the AHB2 peripheral clock during CSLEEP mode. @@ -2019,19 +2013,19 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during CSLEEP mode. */ -#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA1LPEN) -#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA2LPEN) -#define __HAL_RCC_DMAMUX_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMAMUXLPEN) -#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_ADC12LPEN) -#define __HAL_RCC_USBO_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_USBOLPEN) -#define __HAL_RCC_SDMMC3_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_SDMMC3LPEN) +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_DMA1LPEN) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_DMA2LPEN) +#define __HAL_RCC_DMAMUX_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_DMAMUXLPEN) +#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_ADC12LPEN) +#define __HAL_RCC_USBO_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_USBOLPEN) +#define __HAL_RCC_SDMMC3_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MP_AHB2LPENSETR_SDMMC3LPEN) -#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA1LPEN) -#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA2LPEN) -#define __HAL_RCC_DMAMUX_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMAMUXLPEN) -#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_ADC12LPEN) -#define __HAL_RCC_USBO_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_USBOLPEN) -#define __HAL_RCC_SDMMC3_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_SDMMC3LPEN) +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_DMA1LPEN) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_DMA2LPEN) +#define __HAL_RCC_DMAMUX_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_DMAMUXLPEN) +#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_ADC12LPEN) +#define __HAL_RCC_USBO_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_USBOLPEN) +#define __HAL_RCC_SDMMC3_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MP_AHB2LPENCLRR_SDMMC3LPEN) /** @brief Enable or disable the AHB3 peripheral clock during CSLEEP mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2039,25 +2033,25 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during CSLEEP mode. */ -#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_DCMILPEN) +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_DCMILPEN) #if defined(CRYP2) -#define __HAL_RCC_CRYP2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRYP2LPEN) +#define __HAL_RCC_CRYP2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_CRYP2LPEN) #endif -#define __HAL_RCC_HASH2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HASH2LPEN) -#define __HAL_RCC_RNG2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_RNG2LPEN) -#define __HAL_RCC_CRC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRC2LPEN) -#define __HAL_RCC_HSEM_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HSEMLPEN) -#define __HAL_RCC_IPCC_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_IPCCLPEN) +#define __HAL_RCC_HASH2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_HASH2LPEN) +#define __HAL_RCC_RNG2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_RNG2LPEN) +#define __HAL_RCC_CRC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_CRC2LPEN) +#define __HAL_RCC_HSEM_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_HSEMLPEN) +#define __HAL_RCC_IPCC_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MP_AHB3LPENSETR_IPCCLPEN) -#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_DCMILPEN) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_DCMILPEN) #if defined(CRYP2) -#define __HAL_RCC_CRYP2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRYP2LPEN) +#define __HAL_RCC_CRYP2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_CRYP2LPEN) #endif -#define __HAL_RCC_HASH2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HASH2LPEN) -#define __HAL_RCC_RNG2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_RNG2LPEN) -#define __HAL_RCC_CRC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRC2LPEN) -#define __HAL_RCC_HSEM_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HSEMLPEN) -#define __HAL_RCC_IPCC_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_IPCCLPEN) +#define __HAL_RCC_HASH2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_HASH2LPEN) +#define __HAL_RCC_RNG2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_RNG2LPEN) +#define __HAL_RCC_CRC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_CRC2LPEN) +#define __HAL_RCC_HSEM_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_HSEMLPEN) +#define __HAL_RCC_IPCC_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MP_AHB3LPENCLRR_IPCCLPEN) /** @brief Enable or disable the AHB4 peripheral clock during CSLEEP mode. @@ -2066,29 +2060,29 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during CSLEEP mode. */ -#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOALPEN) -#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOBLPEN) -#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOCLPEN) -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIODLPEN) -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOELPEN) -#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOFLPEN) -#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOGLPEN) -#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOHLPEN) -#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOILPEN) -#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOJLPEN) -#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOKLPEN) - -#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOALPEN) -#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOBLPEN) -#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOCLPEN) -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIODLPEN) -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOELPEN) -#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOFLPEN) -#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOGLPEN) -#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOHLPEN) -#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOILPEN) -#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOJLPEN) -#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOKLPEN) +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOALPEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOBLPEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOCLPEN) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIODLPEN) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOELPEN) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOFLPEN) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOGLPEN) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOHLPEN) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOILPEN) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOJLPEN) +#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MP_AHB4LPENSETR_GPIOKLPEN) + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOALPEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOBLPEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOCLPEN) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIODLPEN) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOELPEN) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOFLPEN) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOGLPEN) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOHLPEN) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOILPEN) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOJLPEN) +#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MP_AHB4LPENCLRR_GPIOKLPEN) /** @brief Enable or disable the AXI peripheral clock during CSLEEP mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -2096,9 +2090,9 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during CSLEEP mode. */ -#define __HAL_RCC_SYSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AXIMLPENSETR = RCC_MC_AXIMLPENSETR_SYSRAMLPEN) +#define __HAL_RCC_SYSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AXIMLPENSETR = RCC_MP_AXIMLPENSETR_SYSRAMLPEN) -#define __HAL_RCC_SYSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AXIMLPENCLRR = RCC_MC_AXIMLPENCLRR_SYSRAMLPEN) +#define __HAL_RCC_SYSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AXIMLPENCLRR = RCC_MP_AXIMLPENCLRR_SYSRAMLPEN) /** @brief Enable or disable the MLAHB peripheral clock during CSLEEP mode. @@ -2107,9 +2101,9 @@ typedef struct * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during CSLEEP mode. */ -#define __HAL_RCC_RETRAM_CLK_SLEEP_ENABLE() (RCC->MP_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_RETRAMLPEN) +#define __HAL_RCC_RETRAM_CLK_SLEEP_ENABLE() (RCC->MP_MLAHBLPENSETR = RCC_MP_MLAHBLPENSETR_RETRAMLPEN) -#define __HAL_RCC_RETRAM_CLK_SLEEP_DISABLE() (RCC->MP_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_RETRAMLPEN) +#define __HAL_RCC_RETRAM_CLK_SLEEP_DISABLE() (RCC->MP_MLAHBLPENCLRR = RCC_MP_MLAHBLPENCLRR_RETRAMLPEN) @@ -2231,7 +2225,6 @@ typedef struct #define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_SYSCFGEN) #define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_VREFEN) #define __HAL_RCC_DTS_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_DTSEN) -#define __HAL_RCC_PMBCTRL_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_PMBCTRLEN) #define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_HDPEN) #define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM2EN) @@ -2242,7 +2235,6 @@ typedef struct #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_SYSCFGEN) #define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_VREFEN) #define __HAL_RCC_DTS_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_DTSEN) -#define __HAL_RCC_PMBCTRL_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_PMBCTRLEN) #define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_HDPEN) /** @brief Enable or disable the APB4 peripheral clock. @@ -2554,7 +2546,6 @@ typedef struct #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_SYSCFGLPEN) #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_VREFLPEN) #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_DTSLPEN) -#define __HAL_RCC_PMBCTRL_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_PMBCTRLLPEN) #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM2LPEN) #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM3LPEN) @@ -2564,7 +2555,6 @@ typedef struct #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SYSCFGLPEN) #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_VREFLPEN) #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_DTSLPEN) -#define __HAL_RCC_PMBCTRL_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_PMBCTRLLPEN) /** @brief Enable or disable the APB4 peripheral clock during CSLEEP mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc_ex.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc_ex.h index 0c555f8271..915255e4e3 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc_ex.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc_ex.h @@ -355,10 +355,10 @@ typedef struct /** @defgroup RCCEx_I2C12_Clock_Source I2C12 Clock Source * @{ */ -#define RCC_I2C12CLKSOURCE_PCLK1 RCC_I2C12CKSELR_I2C12SRC_0 -#define RCC_I2C12CLKSOURCE_PLL4 RCC_I2C12CKSELR_I2C12SRC_1 -#define RCC_I2C12CLKSOURCE_HSI RCC_I2C12CKSELR_I2C12SRC_2 -#define RCC_I2C12CLKSOURCE_CSI RCC_I2C12CKSELR_I2C12SRC_3 +#define RCC_I2C12CLKSOURCE_PCLK1 0U +#define RCC_I2C12CLKSOURCE_PLL4 RCC_I2C12CKSELR_I2C12SRC_0 +#define RCC_I2C12CLKSOURCE_HSI RCC_I2C12CKSELR_I2C12SRC_1 +#define RCC_I2C12CLKSOURCE_CSI (RCC_I2C12CKSELR_I2C12SRC_1 | RCC_I2C12CKSELR_I2C12SRC_0) #define IS_RCC_I2C12CLKSOURCE(SOURCE) \ (((SOURCE) == RCC_I2C12CLKSOURCE_PCLK1) || \ @@ -372,10 +372,10 @@ typedef struct /** @defgroup RCCEx_I2C35_Clock_Source I2C35 Clock Source * @{ */ -#define RCC_I2C35CLKSOURCE_PCLK1 RCC_I2C35CKSELR_I2C35SRC_0 -#define RCC_I2C35CLKSOURCE_PLL4 RCC_I2C35CKSELR_I2C35SRC_1 -#define RCC_I2C35CLKSOURCE_HSI RCC_I2C35CKSELR_I2C35SRC_2 -#define RCC_I2C35CLKSOURCE_CSI RCC_I2C35CKSELR_I2C35SRC_3 +#define RCC_I2C35CLKSOURCE_PCLK1 0U +#define RCC_I2C35CLKSOURCE_PLL4 RCC_I2C35CKSELR_I2C35SRC_0 +#define RCC_I2C35CLKSOURCE_HSI RCC_I2C35CKSELR_I2C35SRC_1 +#define RCC_I2C35CLKSOURCE_CSI (RCC_I2C35CKSELR_I2C35SRC_1 | RCC_I2C35CKSELR_I2C35SRC_0) #define IS_RCC_I2C35CLKSOURCE(SOURCE) \ (((SOURCE) == RCC_I2C35CLKSOURCE_PCLK1) || \ @@ -390,10 +390,10 @@ typedef struct /** @defgroup RCCEx_I2C46_Clock_Source I2C46 Clock Source * @{ */ -#define RCC_I2C46CLKSOURCE_PCLK5 RCC_I2C46CKSELR_I2C46SRC_0 -#define RCC_I2C46CLKSOURCE_PLL3 RCC_I2C46CKSELR_I2C46SRC_1 -#define RCC_I2C46CLKSOURCE_HSI RCC_I2C46CKSELR_I2C46SRC_2 -#define RCC_I2C46CLKSOURCE_CSI RCC_I2C46CKSELR_I2C46SRC_3 +#define RCC_I2C46CLKSOURCE_PCLK5 0U +#define RCC_I2C46CLKSOURCE_PLL3 RCC_I2C46CKSELR_I2C46SRC_0 +#define RCC_I2C46CLKSOURCE_HSI RCC_I2C46CKSELR_I2C46SRC_1 +#define RCC_I2C46CLKSOURCE_CSI (RCC_I2C46CKSELR_I2C46SRC_1 | RCC_I2C46CKSELR_I2C46SRC_0) #define IS_RCC_I2C46CLKSOURCE(SOURCE) \ (((SOURCE) == RCC_I2C46CLKSOURCE_PCLK5) || \ @@ -407,11 +407,11 @@ typedef struct /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source * @{ */ -#define RCC_SAI1CLKSOURCE_PLL4 RCC_SAI1CKSELR_SAI1SRC_0 -#define RCC_SAI1CLKSOURCE_PLL3_Q RCC_SAI1CKSELR_SAI1SRC_1 -#define RCC_SAI1CLKSOURCE_I2SCKIN RCC_SAI1CKSELR_SAI1SRC_2 -#define RCC_SAI1CLKSOURCE_PER RCC_SAI1CKSELR_SAI1SRC_3 -#define RCC_SAI1CLKSOURCE_PLL3_R RCC_SAI1CKSELR_SAI1SRC_4 +#define RCC_SAI1CLKSOURCE_PLL4 0U +#define RCC_SAI1CLKSOURCE_PLL3_Q RCC_SAI1CKSELR_SAI1SRC_0 +#define RCC_SAI1CLKSOURCE_I2SCKIN RCC_SAI1CKSELR_SAI1SRC_1 +#define RCC_SAI1CLKSOURCE_PER (RCC_SAI1CKSELR_SAI1SRC_1 | RCC_SAI1CKSELR_SAI1SRC_0) +#define RCC_SAI1CLKSOURCE_PLL3_R RCC_SAI1CKSELR_SAI1SRC_2 #define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL4) || \ @@ -427,12 +427,12 @@ typedef struct /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source * @{ */ -#define RCC_SAI2CLKSOURCE_PLL4 RCC_SAI2CKSELR_SAI2SRC_0 -#define RCC_SAI2CLKSOURCE_PLL3_Q RCC_SAI2CKSELR_SAI2SRC_1 -#define RCC_SAI2CLKSOURCE_I2SCKIN RCC_SAI2CKSELR_SAI2SRC_2 -#define RCC_SAI2CLKSOURCE_PER RCC_SAI2CKSELR_SAI2SRC_3 -#define RCC_SAI2CLKSOURCE_SPDIF RCC_SAI2CKSELR_SAI2SRC_4 -#define RCC_SAI2CLKSOURCE_PLL3_R RCC_SAI2CKSELR_SAI2SRC_5 +#define RCC_SAI2CLKSOURCE_PLL4 0U +#define RCC_SAI2CLKSOURCE_PLL3_Q RCC_SAI2CKSELR_SAI2SRC_0 +#define RCC_SAI2CLKSOURCE_I2SCKIN RCC_SAI2CKSELR_SAI2SRC_1 +#define RCC_SAI2CLKSOURCE_PER (RCC_SAI2CKSELR_SAI2SRC_1 | RCC_SAI2CKSELR_SAI2SRC_0) +#define RCC_SAI2CLKSOURCE_SPDIF RCC_SAI2CKSELR_SAI2SRC_2 +#define RCC_SAI2CLKSOURCE_PLL3_R (RCC_SAI2CKSELR_SAI2SRC_2 | RCC_SAI2CKSELR_SAI2SRC_0) #define IS_RCC_SAI2CLKSOURCE(__SOURCE__) \ @@ -449,11 +449,11 @@ typedef struct /** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source * @{ */ -#define RCC_SAI3CLKSOURCE_PLL4 RCC_SAI3CKSELR_SAI3SRC_0 -#define RCC_SAI3CLKSOURCE_PLL3_Q RCC_SAI3CKSELR_SAI3SRC_1 -#define RCC_SAI3CLKSOURCE_I2SCKIN RCC_SAI3CKSELR_SAI3SRC_2 -#define RCC_SAI3CLKSOURCE_PER RCC_SAI3CKSELR_SAI3SRC_3 -#define RCC_SAI3CLKSOURCE_PLL3_R RCC_SAI3CKSELR_SAI3SRC_4 +#define RCC_SAI3CLKSOURCE_PLL4 0U +#define RCC_SAI3CLKSOURCE_PLL3_Q RCC_SAI3CKSELR_SAI3SRC_0 +#define RCC_SAI3CLKSOURCE_I2SCKIN RCC_SAI3CKSELR_SAI3SRC_1 +#define RCC_SAI3CLKSOURCE_PER (RCC_SAI3CKSELR_SAI3SRC_1 | RCC_SAI3CKSELR_SAI3SRC_0) +#define RCC_SAI3CLKSOURCE_PLL3_R RCC_SAI3CKSELR_SAI3SRC_2 #define IS_RCC_SAI3CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL4) || \ @@ -469,11 +469,11 @@ typedef struct /** @defgroup RCCEx_SAI4_Clock_Source SAI4 Clock Source * @{ */ -#define RCC_SAI4CLKSOURCE_PLL4 RCC_SAI4CKSELR_SAI4SRC_0 -#define RCC_SAI4CLKSOURCE_PLL3_Q RCC_SAI4CKSELR_SAI4SRC_1 -#define RCC_SAI4CLKSOURCE_I2SCKIN RCC_SAI4CKSELR_SAI4SRC_2 -#define RCC_SAI4CLKSOURCE_PER RCC_SAI4CKSELR_SAI4SRC_3 -#define RCC_SAI4CLKSOURCE_PLL3_R RCC_SAI4CKSELR_SAI4SRC_4 +#define RCC_SAI4CLKSOURCE_PLL4 0U +#define RCC_SAI4CLKSOURCE_PLL3_Q RCC_SAI4CKSELR_SAI4SRC_0 +#define RCC_SAI4CLKSOURCE_I2SCKIN RCC_SAI4CKSELR_SAI4SRC_1 +#define RCC_SAI4CLKSOURCE_PER (RCC_SAI4CKSELR_SAI4SRC_1 | RCC_SAI4CKSELR_SAI4SRC_0) +#define RCC_SAI4CLKSOURCE_PLL3_R RCC_SAI4CKSELR_SAI4SRC_2 #define IS_RCC_SAI4CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SAI4CLKSOURCE_PLL4) || \ @@ -489,11 +489,11 @@ typedef struct /** @defgroup RCCEx_SPI1_Clock_Source SPI/I2S1 Clock Source * @{ */ -#define RCC_SPI1CLKSOURCE_PLL4 RCC_SPI2S1CKSELR_SPI1SRC_0 -#define RCC_SPI1CLKSOURCE_PLL3_Q RCC_SPI2S1CKSELR_SPI1SRC_1 -#define RCC_SPI1CLKSOURCE_I2SCKIN RCC_SPI2S1CKSELR_SPI1SRC_2 -#define RCC_SPI1CLKSOURCE_PER RCC_SPI2S1CKSELR_SPI1SRC_3 -#define RCC_SPI1CLKSOURCE_PLL3_R RCC_SPI2S1CKSELR_SPI1SRC_4 +#define RCC_SPI1CLKSOURCE_PLL4 0U +#define RCC_SPI1CLKSOURCE_PLL3_Q RCC_SPI2S1CKSELR_SPI1SRC_0 +#define RCC_SPI1CLKSOURCE_I2SCKIN RCC_SPI2S1CKSELR_SPI1SRC_1 +#define RCC_SPI1CLKSOURCE_PER (RCC_SPI2S1CKSELR_SPI1SRC_1 | RCC_SPI2S1CKSELR_SPI1SRC_0) +#define RCC_SPI1CLKSOURCE_PLL3_R RCC_SPI2S1CKSELR_SPI1SRC_2 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL4) || \ @@ -508,11 +508,11 @@ typedef struct /** @defgroup RCCEx_SPI23_Clock_Source SPI/I2S2,3 Clock Source * @{ */ -#define RCC_SPI23CLKSOURCE_PLL4 RCC_SPI2S23CKSELR_SPI23SRC_0 -#define RCC_SPI23CLKSOURCE_PLL3_Q RCC_SPI2S23CKSELR_SPI23SRC_1 -#define RCC_SPI23CLKSOURCE_I2SCKIN RCC_SPI2S23CKSELR_SPI23SRC_2 -#define RCC_SPI23CLKSOURCE_PER RCC_SPI2S23CKSELR_SPI23SRC_3 -#define RCC_SPI23CLKSOURCE_PLL3_R RCC_SPI2S23CKSELR_SPI23SRC_4 +#define RCC_SPI23CLKSOURCE_PLL4 0U +#define RCC_SPI23CLKSOURCE_PLL3_Q RCC_SPI2S23CKSELR_SPI23SRC_0 +#define RCC_SPI23CLKSOURCE_I2SCKIN RCC_SPI2S23CKSELR_SPI23SRC_1 +#define RCC_SPI23CLKSOURCE_PER (RCC_SPI2S23CKSELR_SPI23SRC_1 | RCC_SPI2S23CKSELR_SPI23SRC_0) +#define RCC_SPI23CLKSOURCE_PLL3_R RCC_SPI2S23CKSELR_SPI23SRC_2 #define IS_RCC_SPI23CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL4) || \ @@ -527,11 +527,11 @@ typedef struct /** @defgroup RCCEx_SPI45_Clock_Source SPI45 Clock Source * @{ */ -#define RCC_SPI45CLKSOURCE_PCLK2 RCC_SPI45CKSELR_SPI45SRC_0 -#define RCC_SPI45CLKSOURCE_PLL4 RCC_SPI45CKSELR_SPI45SRC_1 -#define RCC_SPI45CLKSOURCE_HSI RCC_SPI45CKSELR_SPI45SRC_2 -#define RCC_SPI45CLKSOURCE_CSI RCC_SPI45CKSELR_SPI45SRC_3 -#define RCC_SPI45CLKSOURCE_HSE RCC_SPI45CKSELR_SPI45SRC_4 +#define RCC_SPI45CLKSOURCE_PCLK2 0U +#define RCC_SPI45CLKSOURCE_PLL4 RCC_SPI45CKSELR_SPI45SRC_0 +#define RCC_SPI45CLKSOURCE_HSI RCC_SPI45CKSELR_SPI45SRC_1 +#define RCC_SPI45CLKSOURCE_CSI (RCC_SPI45CKSELR_SPI45SRC_1 | RCC_SPI45CKSELR_SPI45SRC_0) +#define RCC_SPI45CLKSOURCE_HSE RCC_SPI45CKSELR_SPI45SRC_2 #define IS_RCC_SPI45CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SPI45CLKSOURCE_PCLK2) || \ @@ -546,12 +546,12 @@ typedef struct /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source * @{ */ -#define RCC_SPI6CLKSOURCE_PCLK5 RCC_SPI6CKSELR_SPI6SRC_0 -#define RCC_SPI6CLKSOURCE_PLL4 RCC_SPI6CKSELR_SPI6SRC_1 -#define RCC_SPI6CLKSOURCE_HSI RCC_SPI6CKSELR_SPI6SRC_2 -#define RCC_SPI6CLKSOURCE_CSI RCC_SPI6CKSELR_SPI6SRC_3 -#define RCC_SPI6CLKSOURCE_HSE RCC_SPI6CKSELR_SPI6SRC_4 -#define RCC_SPI6CLKSOURCE_PLL3 RCC_SPI6CKSELR_SPI6SRC_5 +#define RCC_SPI6CLKSOURCE_PCLK5 0U +#define RCC_SPI6CLKSOURCE_PLL4 RCC_SPI6CKSELR_SPI6SRC_0 +#define RCC_SPI6CLKSOURCE_HSI RCC_SPI6CKSELR_SPI6SRC_1 +#define RCC_SPI6CLKSOURCE_CSI (RCC_SPI6CKSELR_SPI6SRC_1 | RCC_SPI6CKSELR_SPI6SRC_0) +#define RCC_SPI6CLKSOURCE_HSE RCC_SPI6CKSELR_SPI6SRC_2 +#define RCC_SPI6CLKSOURCE_PLL3 (RCC_SPI6CKSELR_SPI6SRC_2 | RCC_SPI6CKSELR_SPI6SRC_0) #define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK5) || \ @@ -568,12 +568,12 @@ typedef struct /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source * @{ */ -#define RCC_USART1CLKSOURCE_PCLK5 RCC_UART1CKSELR_UART1SRC_0 -#define RCC_USART1CLKSOURCE_PLL3 RCC_UART1CKSELR_UART1SRC_1 -#define RCC_USART1CLKSOURCE_HSI RCC_UART1CKSELR_UART1SRC_2 -#define RCC_USART1CLKSOURCE_CSI RCC_UART1CKSELR_UART1SRC_3 -#define RCC_USART1CLKSOURCE_PLL4 RCC_UART1CKSELR_UART1SRC_4 -#define RCC_USART1CLKSOURCE_HSE RCC_UART1CKSELR_UART1SRC_5 +#define RCC_USART1CLKSOURCE_PCLK5 0U +#define RCC_USART1CLKSOURCE_PLL3 RCC_UART1CKSELR_UART1SRC_0 +#define RCC_USART1CLKSOURCE_HSI RCC_UART1CKSELR_UART1SRC_1 +#define RCC_USART1CLKSOURCE_CSI (RCC_UART1CKSELR_UART1SRC_1 | RCC_UART1CKSELR_UART1SRC_0) +#define RCC_USART1CLKSOURCE_PLL4 RCC_UART1CKSELR_UART1SRC_2 +#define RCC_USART1CLKSOURCE_HSE (RCC_UART1CKSELR_UART1SRC_2 | RCC_UART1CKSELR_UART1SRC_0) #define IS_RCC_USART1CLKSOURCE(SOURCE) \ (((SOURCE) == RCC_USART1CLKSOURCE_PCLK5) || \ @@ -589,11 +589,11 @@ typedef struct /** @defgroup RCCEx_UART24_Clock_Source UART24 Clock Source * @{ */ -#define RCC_UART24CLKSOURCE_PCLK1 RCC_UART24CKSELR_UART24SRC_0 -#define RCC_UART24CLKSOURCE_PLL4 RCC_UART24CKSELR_UART24SRC_1 -#define RCC_UART24CLKSOURCE_HSI RCC_UART24CKSELR_UART24SRC_2 -#define RCC_UART24CLKSOURCE_CSI RCC_UART24CKSELR_UART24SRC_3 -#define RCC_UART24CLKSOURCE_HSE RCC_UART24CKSELR_UART24SRC_4 +#define RCC_UART24CLKSOURCE_PCLK1 0U +#define RCC_UART24CLKSOURCE_PLL4 RCC_UART24CKSELR_UART24SRC_0 +#define RCC_UART24CLKSOURCE_HSI RCC_UART24CKSELR_UART24SRC_1 +#define RCC_UART24CLKSOURCE_CSI (RCC_UART24CKSELR_UART24SRC_1 | RCC_UART24CKSELR_UART24SRC_0) +#define RCC_UART24CLKSOURCE_HSE RCC_UART24CKSELR_UART24SRC_2 #define IS_RCC_UART24CLKSOURCE(SOURCE) \ (((SOURCE) == RCC_UART24CLKSOURCE_PCLK1) || \ @@ -608,11 +608,11 @@ typedef struct /** @defgroup RCCEx_UART35_Clock_Source UART35 Clock Source * @{ */ -#define RCC_UART35CLKSOURCE_PCLK1 RCC_UART35CKSELR_UART35SRC_0 -#define RCC_UART35CLKSOURCE_PLL4 RCC_UART35CKSELR_UART35SRC_1 -#define RCC_UART35CLKSOURCE_HSI RCC_UART35CKSELR_UART35SRC_2 -#define RCC_UART35CLKSOURCE_CSI RCC_UART35CKSELR_UART35SRC_3 -#define RCC_UART35CLKSOURCE_HSE RCC_UART35CKSELR_UART35SRC_4 +#define RCC_UART35CLKSOURCE_PCLK1 0U +#define RCC_UART35CLKSOURCE_PLL4 RCC_UART35CKSELR_UART35SRC_0 +#define RCC_UART35CLKSOURCE_HSI RCC_UART35CKSELR_UART35SRC_1 +#define RCC_UART35CLKSOURCE_CSI (RCC_UART35CKSELR_UART35SRC_1 | RCC_UART35CKSELR_UART35SRC_0) +#define RCC_UART35CLKSOURCE_HSE RCC_UART35CKSELR_UART35SRC_2 #define IS_RCC_UART35CLKSOURCE(SOURCE) \ (((SOURCE) == RCC_UART35CLKSOURCE_PCLK1) || \ @@ -627,11 +627,11 @@ typedef struct /** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source * @{ */ -#define RCC_USART6CLKSOURCE_PCLK2 RCC_UART6CKSELR_UART6SRC_0 -#define RCC_USART6CLKSOURCE_PLL4 RCC_UART6CKSELR_UART6SRC_1 -#define RCC_USART6CLKSOURCE_HSI RCC_UART6CKSELR_UART6SRC_2 -#define RCC_USART6CLKSOURCE_CSI RCC_UART6CKSELR_UART6SRC_3 -#define RCC_USART6CLKSOURCE_HSE RCC_UART6CKSELR_UART6SRC_4 +#define RCC_USART6CLKSOURCE_PCLK2 0U +#define RCC_USART6CLKSOURCE_PLL4 RCC_UART6CKSELR_UART6SRC_0 +#define RCC_USART6CLKSOURCE_HSI RCC_UART6CKSELR_UART6SRC_1 +#define RCC_USART6CLKSOURCE_CSI (RCC_UART6CKSELR_UART6SRC_1 | RCC_UART6CKSELR_UART6SRC_0) +#define RCC_USART6CLKSOURCE_HSE RCC_UART6CKSELR_UART6SRC_2 #define IS_RCC_USART6CLKSOURCE(SOURCE) \ (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \ @@ -646,11 +646,11 @@ typedef struct /** @defgroup RCCEx_UART78_Clock_Source UART78 Clock Source * @{ */ -#define RCC_UART78CLKSOURCE_PCLK1 RCC_UART78CKSELR_UART78SRC_0 -#define RCC_UART78CLKSOURCE_PLL4 RCC_UART78CKSELR_UART78SRC_1 -#define RCC_UART78CLKSOURCE_HSI RCC_UART78CKSELR_UART78SRC_2 -#define RCC_UART78CLKSOURCE_CSI RCC_UART78CKSELR_UART78SRC_3 -#define RCC_UART78CLKSOURCE_HSE RCC_UART78CKSELR_UART78SRC_4 +#define RCC_UART78CLKSOURCE_PCLK1 0U +#define RCC_UART78CLKSOURCE_PLL4 RCC_UART78CKSELR_UART78SRC_0 +#define RCC_UART78CLKSOURCE_HSI RCC_UART78CKSELR_UART78SRC_1 +#define RCC_UART78CLKSOURCE_CSI (RCC_UART78CKSELR_UART78SRC_1 | RCC_UART78CKSELR_UART78SRC_0) +#define RCC_UART78CLKSOURCE_HSE RCC_UART78CKSELR_UART78SRC_2 #define IS_RCC_UART78CLKSOURCE(SOURCE) \ (((SOURCE) == RCC_UART78CLKSOURCE_PCLK1) || \ @@ -665,10 +665,10 @@ typedef struct /** @defgroup RCCEx_SDMMC12_Clock_Source SDMMC12 Clock Source * @{ */ -#define RCC_SDMMC12CLKSOURCE_HCLK6 RCC_SDMMC12CKSELR_SDMMC12SRC_0 -#define RCC_SDMMC12CLKSOURCE_PLL3 RCC_SDMMC12CKSELR_SDMMC12SRC_1 -#define RCC_SDMMC12CLKSOURCE_PLL4 RCC_SDMMC12CKSELR_SDMMC12SRC_2 -#define RCC_SDMMC12CLKSOURCE_HSI RCC_SDMMC12CKSELR_SDMMC12SRC_3 +#define RCC_SDMMC12CLKSOURCE_HCLK6 0U +#define RCC_SDMMC12CLKSOURCE_PLL3 RCC_SDMMC12CKSELR_SDMMC12SRC_0 +#define RCC_SDMMC12CLKSOURCE_PLL4 RCC_SDMMC12CKSELR_SDMMC12SRC_1 +#define RCC_SDMMC12CLKSOURCE_HSI (RCC_SDMMC12CKSELR_SDMMC12SRC_1 | RCC_SDMMC12CKSELR_SDMMC12SRC_0) #define IS_RCC_SDMMC12CLKSOURCE(SOURCE) \ (((SOURCE) == RCC_SDMMC12CLKSOURCE_HCLK6) || \ @@ -682,10 +682,10 @@ typedef struct /** @defgroup RCCEx_SDMMC3_Clock_Source SDMMC3 Clock Source * @{ */ -#define RCC_SDMMC3CLKSOURCE_HCLK2 RCC_SDMMC3CKSELR_SDMMC3SRC_0 -#define RCC_SDMMC3CLKSOURCE_PLL3 RCC_SDMMC3CKSELR_SDMMC3SRC_1 -#define RCC_SDMMC3CLKSOURCE_PLL4 RCC_SDMMC3CKSELR_SDMMC3SRC_2 -#define RCC_SDMMC3CLKSOURCE_HSI RCC_SDMMC3CKSELR_SDMMC3SRC_3 +#define RCC_SDMMC3CLKSOURCE_HCLK2 0U +#define RCC_SDMMC3CLKSOURCE_PLL3 RCC_SDMMC3CKSELR_SDMMC3SRC_0 +#define RCC_SDMMC3CLKSOURCE_PLL4 RCC_SDMMC3CKSELR_SDMMC3SRC_1 +#define RCC_SDMMC3CLKSOURCE_HSI (RCC_SDMMC3CKSELR_SDMMC3SRC_1 | RCC_SDMMC3CKSELR_SDMMC3SRC_0) #define IS_RCC_SDMMC3CLKSOURCE(SOURCE) \ (((SOURCE) == RCC_SDMMC3CLKSOURCE_HCLK2) || \ @@ -699,9 +699,9 @@ typedef struct /** @defgroup RCCEx_ETH_Clock_Source ETH Clock Source * @{ */ -#define RCC_ETHCLKSOURCE_PLL4 RCC_ETHCKSELR_ETHSRC_0 -#define RCC_ETHCLKSOURCE_PLL3 RCC_ETHCKSELR_ETHSRC_1 -#define RCC_ETHCLKSOURCE_OFF RCC_ETHCKSELR_ETHSRC_2 +#define RCC_ETHCLKSOURCE_PLL4 0U +#define RCC_ETHCLKSOURCE_PLL3 RCC_ETHCKSELR_ETHSRC_0 +#define RCC_ETHCLKSOURCE_OFF RCC_ETHCKSELR_ETHSRC_1 #define IS_RCC_ETHCLKSOURCE(SOURCE) (((SOURCE) == RCC_ETHCLKSOURCE_PLL4) || \ @@ -715,22 +715,22 @@ typedef struct /** @defgroup RCCEx_ETH_PrecisionTimeProtocol_Divider ETH PrecisionTimeProtocol Divider * @{ */ -#define RCC_ETHPTPDIV_1 RCC_ETHCKSELR_ETHPTPDIV_0 /*Bypass (default after reset*/ -#define RCC_ETHPTPDIV_2 RCC_ETHCKSELR_ETHPTPDIV_1 /*Division by 2*/ -#define RCC_ETHPTPDIV_3 RCC_ETHCKSELR_ETHPTPDIV_2 /*Division by 3*/ -#define RCC_ETHPTPDIV_4 RCC_ETHCKSELR_ETHPTPDIV_3 /*Division by 4*/ -#define RCC_ETHPTPDIV_5 RCC_ETHCKSELR_ETHPTPDIV_4 /*Division by 5*/ -#define RCC_ETHPTPDIV_6 RCC_ETHCKSELR_ETHPTPDIV_5 /*Division by 6*/ -#define RCC_ETHPTPDIV_7 RCC_ETHCKSELR_ETHPTPDIV_6 /*Division by 7*/ -#define RCC_ETHPTPDIV_8 RCC_ETHCKSELR_ETHPTPDIV_7 /*Division by 8*/ -#define RCC_ETHPTPDIV_9 RCC_ETHCKSELR_ETHPTPDIV_8 /*Division by 9*/ -#define RCC_ETHPTPDIV_10 RCC_ETHCKSELR_ETHPTPDIV_9 /*Division by 10*/ -#define RCC_ETHPTPDIV_11 RCC_ETHCKSELR_ETHPTPDIV_10 /*Division by 11*/ -#define RCC_ETHPTPDIV_12 RCC_ETHCKSELR_ETHPTPDIV_11 /*Division by 12*/ -#define RCC_ETHPTPDIV_13 RCC_ETHCKSELR_ETHPTPDIV_12 /*Division by 13*/ -#define RCC_ETHPTPDIV_14 RCC_ETHCKSELR_ETHPTPDIV_13 /*Division by 14*/ -#define RCC_ETHPTPDIV_15 RCC_ETHCKSELR_ETHPTPDIV_14 /*Division by 15*/ -#define RCC_ETHPTPDIV_16 RCC_ETHCKSELR_ETHPTPDIV_15 /*Division by 16*/ +#define RCC_ETHPTPDIV_1 0U /*Bypass (default after reset*/ +#define RCC_ETHPTPDIV_2 RCC_ETHCKSELR_ETHPTPDIV_0 /*Division by 2*/ +#define RCC_ETHPTPDIV_3 RCC_ETHCKSELR_ETHPTPDIV_1 /*Division by 3*/ +#define RCC_ETHPTPDIV_4 (RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 4*/ +#define RCC_ETHPTPDIV_5 RCC_ETHCKSELR_ETHPTPDIV_2 /*Division by 5*/ +#define RCC_ETHPTPDIV_6 (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 6*/ +#define RCC_ETHPTPDIV_7 (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1) /*Division by 7*/ +#define RCC_ETHPTPDIV_8 (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 8*/ +#define RCC_ETHPTPDIV_9 RCC_ETHCKSELR_ETHPTPDIV_3 /*Division by 9*/ +#define RCC_ETHPTPDIV_10 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 10*/ +#define RCC_ETHPTPDIV_11 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_1) /*Division by 11*/ +#define RCC_ETHPTPDIV_12 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 12*/ +#define RCC_ETHPTPDIV_13 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2) /*Division by 13*/ +#define RCC_ETHPTPDIV_14 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 14*/ +#define RCC_ETHPTPDIV_15 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1) /*Division by 15*/ +#define RCC_ETHPTPDIV_16 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 16*/ #define IS_RCC_ETHPTPDIV(SOURCE) (((SOURCE) == RCC_ETHPTPDIV_1) || \ @@ -757,10 +757,10 @@ typedef struct /** @defgroup RCCEx_QSPI_Clock_Source QSPI Clock Source * @{ */ -#define RCC_QSPICLKSOURCE_ACLK RCC_QSPICKSELR_QSPISRC_0 -#define RCC_QSPICLKSOURCE_PLL3 RCC_QSPICKSELR_QSPISRC_1 -#define RCC_QSPICLKSOURCE_PLL4 RCC_QSPICKSELR_QSPISRC_2 -#define RCC_QSPICLKSOURCE_PER RCC_QSPICKSELR_QSPISRC_3 +#define RCC_QSPICLKSOURCE_ACLK 0U +#define RCC_QSPICLKSOURCE_PLL3 RCC_QSPICKSELR_QSPISRC_0 +#define RCC_QSPICLKSOURCE_PLL4 RCC_QSPICKSELR_QSPISRC_1 +#define RCC_QSPICLKSOURCE_PER (RCC_QSPICKSELR_QSPISRC_1 | RCC_QSPICKSELR_QSPISRC_0) #define IS_RCC_QSPICLKSOURCE(SOURCE) \ (((SOURCE) == RCC_QSPICLKSOURCE_ACLK) || \ @@ -774,10 +774,10 @@ typedef struct /** @defgroup RCCEx_FMC_Clock_Source FMC Clock Source * @{ */ -#define RCC_FMCCLKSOURCE_ACLK RCC_FMCCKSELR_FMCSRC_0 -#define RCC_FMCCLKSOURCE_PLL3 RCC_FMCCKSELR_FMCSRC_1 -#define RCC_FMCCLKSOURCE_PLL4 RCC_FMCCKSELR_FMCSRC_2 -#define RCC_FMCCLKSOURCE_PER RCC_FMCCKSELR_FMCSRC_3 +#define RCC_FMCCLKSOURCE_ACLK 0U +#define RCC_FMCCLKSOURCE_PLL3 RCC_FMCCKSELR_FMCSRC_0 +#define RCC_FMCCLKSOURCE_PLL4 RCC_FMCCKSELR_FMCSRC_1 +#define RCC_FMCCLKSOURCE_PER (RCC_FMCCKSELR_FMCSRC_1 | RCC_FMCCKSELR_FMCSRC_0) #define IS_RCC_FMCCLKSOURCE(SOURCE) (((SOURCE) == RCC_FMCCLKSOURCE_ACLK) || \ ((SOURCE) == RCC_FMCCLKSOURCE_PLL3) || \ @@ -791,10 +791,10 @@ typedef struct /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source * @{ */ -#define RCC_FDCANCLKSOURCE_HSE RCC_FDCANCKSELR_FDCANSRC_0 -#define RCC_FDCANCLKSOURCE_PLL3 RCC_FDCANCKSELR_FDCANSRC_1 -#define RCC_FDCANCLKSOURCE_PLL4_Q RCC_FDCANCKSELR_FDCANSRC_2 -#define RCC_FDCANCLKSOURCE_PLL4_R RCC_FDCANCKSELR_FDCANSRC_3 +#define RCC_FDCANCLKSOURCE_HSE 0U +#define RCC_FDCANCLKSOURCE_PLL3 RCC_FDCANCKSELR_FDCANSRC_0 +#define RCC_FDCANCLKSOURCE_PLL4_Q RCC_FDCANCKSELR_FDCANSRC_1 +#define RCC_FDCANCLKSOURCE_PLL4_R (RCC_FDCANCKSELR_FDCANSRC_1 | RCC_FDCANCKSELR_FDCANSRC_0) @@ -811,9 +811,9 @@ typedef struct /** @defgroup RCCEx_SPDIFRX_Clock_Source SPDIFRX Clock Source * @{ */ -#define RCC_SPDIFRXCLKSOURCE_PLL4 RCC_SPDIFCKSELR_SPDIFSRC_0 -#define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_SPDIFCKSELR_SPDIFSRC_1 -#define RCC_SPDIFRXCLKSOURCE_HSI RCC_SPDIFCKSELR_SPDIFSRC_2 +#define RCC_SPDIFRXCLKSOURCE_PLL4 0U +#define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_SPDIFCKSELR_SPDIFSRC_0 +#define RCC_SPDIFRXCLKSOURCE_HSI RCC_SPDIFCKSELR_SPDIFSRC_1 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) \ (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL4) || \ @@ -826,9 +826,9 @@ typedef struct /** @defgroup RCCEx_CEC_Clock_Source CEC Clock Source * @{ */ -#define RCC_CECCLKSOURCE_LSE RCC_CECCKSELR_CECSRC_0 -#define RCC_CECCLKSOURCE_LSI RCC_CECCKSELR_CECSRC_1 -#define RCC_CECCLKSOURCE_CSI122 RCC_CECCKSELR_CECSRC_2 +#define RCC_CECCLKSOURCE_LSE 0U +#define RCC_CECCLKSOURCE_LSI RCC_CECCKSELR_CECSRC_0 +#define RCC_CECCLKSOURCE_CSI122 RCC_CECCKSELR_CECSRC_1 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \ ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \ @@ -840,9 +840,9 @@ typedef struct /** @defgroup RCCEx_USBPHY_Clock_Source USBPHY Clock Source * @{ */ -#define RCC_USBPHYCLKSOURCE_HSE RCC_USBCKSELR_USBPHYSRC_0 -#define RCC_USBPHYCLKSOURCE_PLL4 RCC_USBCKSELR_USBPHYSRC_1 -#define RCC_USBPHYCLKSOURCE_HSE2 RCC_USBCKSELR_USBPHYSRC_2 +#define RCC_USBPHYCLKSOURCE_HSE 0U +#define RCC_USBPHYCLKSOURCE_PLL4 RCC_USBCKSELR_USBPHYSRC_0 +#define RCC_USBPHYCLKSOURCE_HSE2 RCC_USBCKSELR_USBPHYSRC_1 #define IS_RCC_USBPHYCLKSOURCE(SOURCE) \ (((SOURCE) == RCC_USBPHYCLKSOURCE_HSE) || \ @@ -855,8 +855,8 @@ typedef struct /** @defgroup RCCEx_USBO_Clock_Source USBO Clock Source * @{ */ -#define RCC_USBOCLKSOURCE_PLL4 RCC_USBCKSELR_USBOSRC_0 -#define RCC_USBOCLKSOURCE_PHY RCC_USBCKSELR_USBOSRC_1 +#define RCC_USBOCLKSOURCE_PLL4 0U +#define RCC_USBOCLKSOURCE_PHY RCC_USBCKSELR_USBOSRC #define IS_RCC_USBOCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBOCLKSOURCE_PLL4) || \ ((SOURCE) == RCC_USBOCLKSOURCE_PHY)) @@ -868,10 +868,10 @@ typedef struct /** @defgroup RCCEx_RNG1_Clock_Source RNG1 Clock Source * @{ */ -#define RCC_RNG1CLKSOURCE_CSI RCC_RNG1CKSELR_RNG1SRC_0 -#define RCC_RNG1CLKSOURCE_PLL4 RCC_RNG1CKSELR_RNG1SRC_1 -#define RCC_RNG1CLKSOURCE_LSE RCC_RNG1CKSELR_RNG1SRC_2 -#define RCC_RNG1CLKSOURCE_LSI RCC_RNG1CKSELR_RNG1SRC_3 +#define RCC_RNG1CLKSOURCE_CSI 0U +#define RCC_RNG1CLKSOURCE_PLL4 RCC_RNG1CKSELR_RNG1SRC_0 +#define RCC_RNG1CLKSOURCE_LSE RCC_RNG1CKSELR_RNG1SRC_1 +#define RCC_RNG1CLKSOURCE_LSI (RCC_RNG1CKSELR_RNG1SRC_1 | RCC_RNG1CKSELR_RNG1SRC_0) #define IS_RCC_RNG1CLKSOURCE(SOURCE) (((SOURCE) == RCC_RNG1CLKSOURCE_CSI) || \ ((SOURCE) == RCC_RNG1CLKSOURCE_PLL4) || \ @@ -886,10 +886,10 @@ typedef struct /** @defgroup RCCEx_RNG2_Clock_Source RNG2 Clock Source * @{ */ -#define RCC_RNG2CLKSOURCE_CSI RCC_RNG2CKSELR_RNG2SRC_0 -#define RCC_RNG2CLKSOURCE_PLL4 RCC_RNG2CKSELR_RNG2SRC_1 -#define RCC_RNG2CLKSOURCE_LSE RCC_RNG2CKSELR_RNG2SRC_2 -#define RCC_RNG2CLKSOURCE_LSI RCC_RNG2CKSELR_RNG2SRC_3 +#define RCC_RNG2CLKSOURCE_CSI 0U +#define RCC_RNG2CLKSOURCE_PLL4 RCC_RNG2CKSELR_RNG2SRC_0 +#define RCC_RNG2CLKSOURCE_LSE RCC_RNG2CKSELR_RNG2SRC_1 +#define RCC_RNG2CLKSOURCE_LSI (RCC_RNG2CKSELR_RNG2SRC_1 | RCC_RNG2CKSELR_RNG2SRC_0) #define IS_RCC_RNG2CLKSOURCE(SOURCE) (((SOURCE) == RCC_RNG2CLKSOURCE_CSI) || \ ((SOURCE) == RCC_RNG2CLKSOURCE_PLL4) || \ @@ -904,10 +904,10 @@ typedef struct /** @defgroup RCCEx_CKPER_Clock_Source CKPER Clock Source * @{ */ -#define RCC_CKPERCLKSOURCE_HSI RCC_CPERCKSELR_CKPERSRC_0 -#define RCC_CKPERCLKSOURCE_CSI RCC_CPERCKSELR_CKPERSRC_1 -#define RCC_CKPERCLKSOURCE_HSE RCC_CPERCKSELR_CKPERSRC_2 -#define RCC_CKPERCLKSOURCE_OFF RCC_CPERCKSELR_CKPERSRC_3 /*Clock disabled*/ +#define RCC_CKPERCLKSOURCE_HSI 0U +#define RCC_CKPERCLKSOURCE_CSI RCC_CPERCKSELR_CKPERSRC_0 +#define RCC_CKPERCLKSOURCE_HSE RCC_CPERCKSELR_CKPERSRC_1 +#define RCC_CKPERCLKSOURCE_OFF (RCC_CPERCKSELR_CKPERSRC_1 | RCC_CPERCKSELR_CKPERSRC_0) /*Clock disabled*/ #define IS_RCC_CKPERCLKSOURCE(SOURCE) (((SOURCE) == RCC_CKPERCLKSOURCE_HSI) || \ ((SOURCE) == RCC_CKPERCLKSOURCE_CSI) || \ @@ -921,9 +921,9 @@ typedef struct /** @defgroup RCCEx_STGEN_Clock_Source STGEN Clock Source * @{ */ -#define RCC_STGENCLKSOURCE_HSI RCC_STGENCKSELR_STGENSRC_0 -#define RCC_STGENCLKSOURCE_HSE RCC_STGENCKSELR_STGENSRC_1 -#define RCC_STGENCLKSOURCE_OFF RCC_STGENCKSELR_STGENSRC_2 +#define RCC_STGENCLKSOURCE_HSI 0U +#define RCC_STGENCLKSOURCE_HSE RCC_STGENCKSELR_STGENSRC_0 +#define RCC_STGENCLKSOURCE_OFF RCC_STGENCKSELR_STGENSRC_1 #define IS_RCC_STGENCLKSOURCE(SOURCE) \ (((SOURCE) == RCC_STGENCLKSOURCE_HSI) || \ @@ -937,8 +937,8 @@ typedef struct /** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source * @{ */ -#define RCC_DSICLKSOURCE_PHY RCC_DSICKSELR_DSISRC_0 -#define RCC_DSICLKSOURCE_PLL4 RCC_DSICKSELR_DSISRC_1 +#define RCC_DSICLKSOURCE_PHY 0U +#define RCC_DSICLKSOURCE_PLL4 RCC_DSICKSELR_DSISRC #define IS_RCC_DSICLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \ @@ -951,9 +951,9 @@ typedef struct /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source * @{ */ -#define RCC_ADCCLKSOURCE_PLL4 RCC_ADCCKSELR_ADCSRC_0 -#define RCC_ADCCLKSOURCE_PER RCC_ADCCKSELR_ADCSRC_1 -#define RCC_ADCCLKSOURCE_PLL3 RCC_ADCCKSELR_ADCSRC_2 +#define RCC_ADCCLKSOURCE_PLL4 0U +#define RCC_ADCCLKSOURCE_PER RCC_ADCCKSELR_ADCSRC_0 +#define RCC_ADCCLKSOURCE_PLL3 RCC_ADCCKSELR_ADCSRC_1 #define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL4) || \ ((SOURCE) == RCC_ADCCLKSOURCE_PER) || \ @@ -966,13 +966,13 @@ typedef struct /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source * @{ */ -#define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CKSELR_LPTIM1SRC_0 -#define RCC_LPTIM1CLKSOURCE_PLL4 RCC_LPTIM1CKSELR_LPTIM1SRC_1 -#define RCC_LPTIM1CLKSOURCE_PLL3 RCC_LPTIM1CKSELR_LPTIM1SRC_2 -#define RCC_LPTIM1CLKSOURCE_LSE RCC_LPTIM1CKSELR_LPTIM1SRC_3 -#define RCC_LPTIM1CLKSOURCE_LSI RCC_LPTIM1CKSELR_LPTIM1SRC_4 -#define RCC_LPTIM1CLKSOURCE_PER RCC_LPTIM1CKSELR_LPTIM1SRC_5 -#define RCC_LPTIM1CLKSOURCE_OFF RCC_LPTIM1CKSELR_LPTIM1SRC_6 +#define RCC_LPTIM1CLKSOURCE_PCLK1 0U +#define RCC_LPTIM1CLKSOURCE_PLL4 RCC_LPTIM1CKSELR_LPTIM1SRC_0 +#define RCC_LPTIM1CLKSOURCE_PLL3 RCC_LPTIM1CKSELR_LPTIM1SRC_1 +#define RCC_LPTIM1CLKSOURCE_LSE (RCC_LPTIM1CKSELR_LPTIM1SRC_1 | RCC_LPTIM1CKSELR_LPTIM1SRC_0) +#define RCC_LPTIM1CLKSOURCE_LSI RCC_LPTIM1CKSELR_LPTIM1SRC_2 +#define RCC_LPTIM1CLKSOURCE_PER (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_0) +#define RCC_LPTIM1CLKSOURCE_OFF (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_1) #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) \ (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ @@ -989,12 +989,12 @@ typedef struct /** @defgroup RCCEx_LPTIM23_Clock_Source LPTIM23 Clock Source * @{ */ -#define RCC_LPTIM23CLKSOURCE_PCLK3 RCC_LPTIM23CKSELR_LPTIM23SRC_0 -#define RCC_LPTIM23CLKSOURCE_PLL4 RCC_LPTIM23CKSELR_LPTIM23SRC_1 -#define RCC_LPTIM23CLKSOURCE_PER RCC_LPTIM23CKSELR_LPTIM23SRC_2 -#define RCC_LPTIM23CLKSOURCE_LSE RCC_LPTIM23CKSELR_LPTIM23SRC_3 -#define RCC_LPTIM23CLKSOURCE_LSI RCC_LPTIM23CKSELR_LPTIM23SRC_4 -#define RCC_LPTIM23CLKSOURCE_OFF RCC_LPTIM23CKSELR_LPTIM23SRC_5 +#define RCC_LPTIM23CLKSOURCE_PCLK3 0U +#define RCC_LPTIM23CLKSOURCE_PLL4 RCC_LPTIM23CKSELR_LPTIM23SRC_0 +#define RCC_LPTIM23CLKSOURCE_PER RCC_LPTIM23CKSELR_LPTIM23SRC_1 +#define RCC_LPTIM23CLKSOURCE_LSE (RCC_LPTIM23CKSELR_LPTIM23SRC_1 | RCC_LPTIM23CKSELR_LPTIM23SRC_0) +#define RCC_LPTIM23CLKSOURCE_LSI RCC_LPTIM23CKSELR_LPTIM23SRC_2 +#define RCC_LPTIM23CLKSOURCE_OFF (RCC_LPTIM23CKSELR_LPTIM23SRC_2 | RCC_LPTIM23CKSELR_LPTIM23SRC_0) #define IS_RCC_LPTIM23CLKSOURCE(SOURCE) \ @@ -1011,13 +1011,13 @@ typedef struct /** @defgroup RCCEx_LPTIM45_Clock_Source LPTIM45 Clock Source * @{ */ -#define RCC_LPTIM45CLKSOURCE_PCLK3 RCC_LPTIM45CKSELR_LPTIM45SRC_0 -#define RCC_LPTIM45CLKSOURCE_PLL4 RCC_LPTIM45CKSELR_LPTIM45SRC_1 -#define RCC_LPTIM45CLKSOURCE_PLL3 RCC_LPTIM45CKSELR_LPTIM45SRC_2 -#define RCC_LPTIM45CLKSOURCE_LSE RCC_LPTIM45CKSELR_LPTIM45SRC_3 -#define RCC_LPTIM45CLKSOURCE_LSI RCC_LPTIM45CKSELR_LPTIM45SRC_4 -#define RCC_LPTIM45CLKSOURCE_PER RCC_LPTIM45CKSELR_LPTIM45SRC_5 -#define RCC_LPTIM45CLKSOURCE_OFF RCC_LPTIM45CKSELR_LPTIM45SRC_6 +#define RCC_LPTIM45CLKSOURCE_PCLK3 0U +#define RCC_LPTIM45CLKSOURCE_PLL4 RCC_LPTIM45CKSELR_LPTIM45SRC_0 +#define RCC_LPTIM45CLKSOURCE_PLL3 RCC_LPTIM45CKSELR_LPTIM45SRC_1 +#define RCC_LPTIM45CLKSOURCE_LSE (RCC_LPTIM45CKSELR_LPTIM45SRC_1 | RCC_LPTIM45CKSELR_LPTIM45SRC_0) +#define RCC_LPTIM45CLKSOURCE_LSI RCC_LPTIM45CKSELR_LPTIM45SRC_2 +#define RCC_LPTIM45CLKSOURCE_PER (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_0) +#define RCC_LPTIM45CLKSOURCE_OFF (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_1) @@ -1037,8 +1037,8 @@ typedef struct /** @defgroup RCCEx_TIMG1_Prescaler_Selection TIMG1 Prescaler Selection * @{ */ -#define RCC_TIMG1PRES_DEACTIVATED RCC_TIMG1PRER_TIMG1PRE_0 -#define RCC_TIMG1PRES_ACTIVATED RCC_TIMG1PRER_TIMG1PRE_1 +#define RCC_TIMG1PRES_DEACTIVATED 0U +#define RCC_TIMG1PRES_ACTIVATED RCC_TIMG1PRER_TIMG1PRE #define IS_RCC_TIMG1PRES(PRES) (((PRES) == RCC_TIMG1PRES_DEACTIVATED) || \ ((PRES) == RCC_TIMG1PRES_ACTIVATED)) @@ -1050,8 +1050,8 @@ typedef struct /** @defgroup RCCEx_TIMG2_Prescaler_Selection TIMG2 Prescaler Selection * @{ */ -#define RCC_TIMG2PRES_DEACTIVATED RCC_TIMG2PRER_TIMG2PRE_0 -#define RCC_TIMG2PRES_ACTIVATED RCC_TIMG2PRER_TIMG2PRE_1 +#define RCC_TIMG2PRES_DEACTIVATED 0U +#define RCC_TIMG2PRES_ACTIVATED RCC_TIMG2PRER_TIMG2PRE #define IS_RCC_TIMG2PRES(PRES) (((PRES) == RCC_TIMG2PRES_DEACTIVATED) || \ ((PRES) == RCC_TIMG2PRES_ACTIVATED)) diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rtc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rtc.h index f049dc966b..dbf67d0f5f 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rtc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rtc.h @@ -702,8 +702,6 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to #elif defined(CORE_CA7) -#else /* !CORE_CA7 */ - #define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI_C1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT) /** @@ -724,6 +722,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to */ #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI_C1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) +#else /* !CORE_CA7 */ + #error Please #define CORE_CM4 or CORE_CA7 #endif diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sai.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sai.h index c9b6c1239b..2a5b4109f1 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sai.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sai.h @@ -66,7 +66,7 @@ typedef struct { FunctionalState Activation; /*!< Enable/disable PDM interface */ uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. - This parameter must be a number between Min_Data = 1 and Max_Data = 3. */ + This parameter must be a number between Min_Data = 1 and Max_Data = 4. */ uint32_t ClockEnable; /*!< Specifies which clock must be enabled. This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ } SAI_PdmInitTypeDef; @@ -113,9 +113,10 @@ typedef struct uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling. This parameter can be a value of @ref SAI_Audio_Frequency */ - uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for - AudioFrequency the user choice - This parameter must be a number between Min_Data = 0 and Max_Data = 63. */ + uint32_t Mckdiv; /*!< Specifies the master clock divider. + This parameter must be a number between Min_Data = 0 and Max_Data = 63. + @note This parameter is used only if AudioFrequency is set to + SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */ uint32_t MckOverSampling; /*!< Specifies the master clock oversampling. This parameter can be a value of @ref SAI_Block_Mck_OverSampling */ @@ -152,6 +153,7 @@ typedef struct /** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition * @brief SAI Frame Init structure definition + * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware). * @{ */ typedef struct @@ -184,6 +186,8 @@ typedef struct /** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition * @brief SAI Block Slot Init Structure definition + * @note For SPDIF protocol, these parameters are not used (set by hardware). + * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware). * @{ */ typedef struct @@ -285,17 +289,17 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Error_Code SAI Error Code * @{ */ -#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun Error */ -#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U) /*!< Underrun error */ -#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U) /*!< Anticipated Frame synchronisation detection */ -#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U) /*!< Late Frame synchronisation detection */ -#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U) /*!< codec not ready */ -#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U) /*!< Wrong clock configuration */ -#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */ -#define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U) /*!< DMA error */ +#define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */ +#define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */ +#define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */ +#define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */ +#define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */ +#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */ +#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */ +#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */ #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) -#define HAL_SAI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid callback error */ +#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */ #endif /** * @} @@ -304,9 +308,9 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_SyncExt SAI External synchronisation * @{ */ -#define SAI_SYNCEXT_DISABLE 0 -#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1 -#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2 +#define SAI_SYNCEXT_DISABLE 0U +#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U +#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U /** * @} */ @@ -314,8 +318,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output * @{ */ -#define SAI_MCK_OUTPUT_DISABLE ((uint32_t)0x00000000U) -#define SAI_MCK_OUTPUT_ENABLE ((uint32_t)SAI_xCR1_MCKEN) +#define SAI_MCK_OUTPUT_DISABLE 0x00000000U +#define SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN /** * @} */ @@ -323,11 +327,11 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Protocol SAI Supported protocol * @{ */ -#define SAI_I2S_STANDARD 0 -#define SAI_I2S_MSBJUSTIFIED 1 -#define SAI_I2S_LSBJUSTIFIED 2 -#define SAI_PCM_LONG 3 -#define SAI_PCM_SHORT 4 +#define SAI_I2S_STANDARD 0U +#define SAI_I2S_MSBJUSTIFIED 1U +#define SAI_I2S_LSBJUSTIFIED 2U +#define SAI_PCM_LONG 3U +#define SAI_PCM_SHORT 4U /** * @} */ @@ -335,10 +339,10 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Protocol_DataSize SAI protocol data size * @{ */ -#define SAI_PROTOCOL_DATASIZE_16BIT 0 -#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1 -#define SAI_PROTOCOL_DATASIZE_24BIT 2 -#define SAI_PROTOCOL_DATASIZE_32BIT 3 +#define SAI_PROTOCOL_DATASIZE_16BIT 0U +#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U +#define SAI_PROTOCOL_DATASIZE_24BIT 2U +#define SAI_PROTOCOL_DATASIZE_32BIT 3U /** * @} */ @@ -346,16 +350,16 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Audio_Frequency SAI Audio Frequency * @{ */ -#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U) -#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U) -#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U) -#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U) -#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U) -#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U) -#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U) -#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U) -#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U) -#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U) +#define SAI_AUDIO_FREQUENCY_192K 192000U +#define SAI_AUDIO_FREQUENCY_96K 96000U +#define SAI_AUDIO_FREQUENCY_48K 48000U +#define SAI_AUDIO_FREQUENCY_44K 44100U +#define SAI_AUDIO_FREQUENCY_32K 32000U +#define SAI_AUDIO_FREQUENCY_22K 22050U +#define SAI_AUDIO_FREQUENCY_16K 16000U +#define SAI_AUDIO_FREQUENCY_11K 11025U +#define SAI_AUDIO_FREQUENCY_8K 8000U +#define SAI_AUDIO_FREQUENCY_MCKDIV 0U /** * @} */ @@ -363,8 +367,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling * @{ */ -#define SAI_MCK_OVERSAMPLING_DISABLE ((uint32_t)0x00000000U) -#define SAI_MCK_OVERSAMPLING_ENABLE ((uint32_t)SAI_xCR1_OSR) +#define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U +#define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR /** * @} */ @@ -372,9 +376,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable * @{ */ -#define SAI_PDM_CLOCK1_ENABLE ((uint32_t)SAI_PDMCR_CKEN1) -#define SAI_PDM_CLOCK2_ENABLE ((uint32_t)SAI_PDMCR_CKEN2) - +#define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1 +#define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2 /** * @} */ @@ -382,10 +385,10 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Mode SAI Block Mode * @{ */ -#define SAI_MODEMASTER_TX ((uint32_t)0x00000000U) -#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0) -#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1) -#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)) +#define SAI_MODEMASTER_TX 0x00000000U +#define SAI_MODEMASTER_RX SAI_xCR1_MODE_0 +#define SAI_MODESLAVE_TX SAI_xCR1_MODE_1 +#define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0) /** * @} @@ -394,9 +397,9 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Protocol SAI Block Protocol * @{ */ -#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000U) -#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0) -#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1) +#define SAI_FREE_PROTOCOL 0x00000000U +#define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0 +#define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1 /** * @} */ @@ -404,12 +407,12 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Data_Size SAI Block Data Size * @{ */ -#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1) -#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) -#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2) -#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0)) -#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1)) -#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) +#define SAI_DATASIZE_8 SAI_xCR1_DS_1 +#define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0) +#define SAI_DATASIZE_16 SAI_xCR1_DS_2 +#define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0) +#define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1) +#define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0) /** * @} */ @@ -417,8 +420,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission * @{ */ -#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U) -#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST) +#define SAI_FIRSTBIT_MSB 0x00000000U +#define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST /** * @} */ @@ -426,8 +429,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing * @{ */ -#define SAI_CLOCKSTROBING_FALLINGEDGE 0 -#define SAI_CLOCKSTROBING_RISINGEDGE 1 +#define SAI_CLOCKSTROBING_FALLINGEDGE 0U +#define SAI_CLOCKSTROBING_RISINGEDGE 1U /** * @} */ @@ -435,10 +438,16 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Synchronization SAI Block Synchronization * @{ */ -#define SAI_ASYNCHRONOUS 0 /*!< Asynchronous */ -#define SAI_SYNCHRONOUS 1 /*!< Synchronous with other block of same SAI */ -#define SAI_SYNCHRONOUS_EXT_SAI1 2 /*!< Synchronous with other SAI, SAI1 */ -#define SAI_SYNCHRONOUS_EXT_SAI2 3 /*!< Synchronous with other SAI, SAI2 */ +#define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */ +#define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */ +#define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */ +#define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */ +#if defined(SAI3) +#define SAI_SYNCHRONOUS_EXT_SAI3 4U /*!< Synchronous with other SAI, SAI3 */ +#endif +#if defined(SAI4) +#define SAI_SYNCHRONOUS_EXT_SAI4 5U /*!< Synchronous with other SAI, SAI4 */ +#endif /** * @} */ @@ -446,8 +455,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive * @{ */ -#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U) -#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV) +#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U +#define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV /** * @} */ @@ -455,8 +464,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_NoDivider SAI Block NoDivider * @{ */ -#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U) -#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV) +#define SAI_MASTERDIVIDER_ENABLE 0x00000000U +#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV /** * @} */ @@ -464,8 +473,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition * @{ */ -#define SAI_FS_STARTFRAME ((uint32_t)0x00000000U) -#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF) +#define SAI_FS_STARTFRAME 0x00000000U +#define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF /** * @} */ @@ -473,8 +482,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity * @{ */ -#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U) -#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL) +#define SAI_FS_ACTIVE_LOW 0x00000000U +#define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL /** * @} */ @@ -482,8 +491,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset * @{ */ -#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000U) -#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF) +#define SAI_FS_FIRSTBIT 0x00000000U +#define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF /** * @} */ @@ -491,9 +500,9 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size * @{ */ -#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U) -#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0) -#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1) +#define SAI_SLOTSIZE_DATASIZE 0x00000000U +#define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0 +#define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1 /** * @} */ @@ -501,24 +510,24 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active * @{ */ -#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U) -#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U) -#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U) -#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U) -#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U) -#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U) -#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U) -#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U) -#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U) -#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U) -#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U) -#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U) -#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U) -#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U) -#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U) -#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U) -#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U) -#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU) +#define SAI_SLOT_NOTACTIVE 0x00000000U +#define SAI_SLOTACTIVE_0 0x00000001U +#define SAI_SLOTACTIVE_1 0x00000002U +#define SAI_SLOTACTIVE_2 0x00000004U +#define SAI_SLOTACTIVE_3 0x00000008U +#define SAI_SLOTACTIVE_4 0x00000010U +#define SAI_SLOTACTIVE_5 0x00000020U +#define SAI_SLOTACTIVE_6 0x00000040U +#define SAI_SLOTACTIVE_7 0x00000080U +#define SAI_SLOTACTIVE_8 0x00000100U +#define SAI_SLOTACTIVE_9 0x00000200U +#define SAI_SLOTACTIVE_10 0x00000400U +#define SAI_SLOTACTIVE_11 0x00000800U +#define SAI_SLOTACTIVE_12 0x00001000U +#define SAI_SLOTACTIVE_13 0x00002000U +#define SAI_SLOTACTIVE_14 0x00004000U +#define SAI_SLOTACTIVE_15 0x00008000U +#define SAI_SLOTACTIVE_ALL 0x0000FFFFU /** * @} */ @@ -526,8 +535,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode * @{ */ -#define SAI_STEREOMODE ((uint32_t)0x00000000U) -#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO) +#define SAI_STEREOMODE 0x00000000U +#define SAI_MONOMODE SAI_xCR1_MONO /** * @} */ @@ -535,8 +544,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_TRIState_Management SAI TRIState Management * @{ */ -#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U) -#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS) +#define SAI_OUTPUT_NOTRELEASED 0x00000000U +#define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS /** * @} */ @@ -544,11 +553,11 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold * @{ */ -#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U) -#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0)) -#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1)) -#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)) -#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2)) +#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U +#define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0 +#define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1 +#define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0) +#define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2 /** * @} */ @@ -556,11 +565,11 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode * @{ */ -#define SAI_NOCOMPANDING ((uint32_t)0x00000000U) -#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1)) -#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)) -#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL)) -#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)) +#define SAI_NOCOMPANDING 0x00000000U +#define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1 +#define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0) +#define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL) +#define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL) /** * @} */ @@ -568,8 +577,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value * @{ */ -#define SAI_ZERO_VALUE ((uint32_t)0x00000000U) -#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL) +#define SAI_ZERO_VALUE 0x00000000U +#define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL /** * @} */ @@ -577,13 +586,13 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition * @{ */ -#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE) -#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE) -#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE) -#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE) -#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE) -#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE) -#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE) +#define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE +#define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE +#define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE +#define SAI_IT_FREQ SAI_xIMR_FREQIE +#define SAI_IT_CNRDY SAI_xIMR_CNRDYIE +#define SAI_IT_AFSDET SAI_xIMR_AFSDETIE +#define SAI_IT_LFSDET SAI_xIMR_LFSDETIE /** * @} */ @@ -591,13 +600,13 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition * @{ */ -#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR) -#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET) -#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG) -#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ) -#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY) -#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET) -#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET) +#define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR +#define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET +#define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG +#define SAI_FLAG_FREQ SAI_xSR_FREQ +#define SAI_FLAG_CNRDY SAI_xSR_CNRDY +#define SAI_FLAG_AFSDET SAI_xSR_AFSDET +#define SAI_FLAG_LFSDET SAI_xSR_LFSDET /** * @} */ @@ -605,12 +614,12 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); /** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level * @{ */ -#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U) -#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U) -#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U) -#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U) -#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U) -#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U) +#define SAI_FIFOSTATUS_EMPTY 0x00000000U +#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U +#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U +#define SAI_FIFOSTATUS_HALFFULL 0x00030000U +#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U +#define SAI_FIFOSTATUS_FULL 0x00050000U /** * @} */ @@ -815,7 +824,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); */ /* Private macros ------------------------------------------------------------*/ -/** @addtogroup SAI_Private_Macros +/** @defgroup SAI_Private_Macros SAI Private Macros * @{ */ #define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ @@ -842,7 +851,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \ ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE)) -#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U)) +#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 4U)) #define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \ (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U)) @@ -869,10 +878,19 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \ ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE)) -#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ - ((SYNCHRO) == SAI_SYNCHRONOUS) || \ - ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \ +#if defined(SAI3) && defined(SAI4) +#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI3) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI4)) +#else +#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \ ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)) +#endif #define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \ ((VALUE) == SAI_MCK_OUTPUT_DISABLE)) @@ -883,7 +901,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \ ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) -#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63) +#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U) #define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \ ((VALUE) == SAI_LAST_SENT_VALUE)) @@ -908,13 +926,13 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL) -#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) +#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U)) #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \ ((SIZE) == SAI_SLOTSIZE_16B) || \ ((SIZE) == SAI_SLOTSIZE_32B)) -#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) +#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U) #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \ ((OFFSET) == SAI_FS_BEFOREFIRSTBIT)) @@ -925,11 +943,11 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \ ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) -#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63) +#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U) -#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) +#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U)) -#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) +#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U)) /** * @} diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smartcard.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smartcard.h new file mode 100644 index 0000000000..2595ad811c --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smartcard.h @@ -0,0 +1,1074 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_hal_smartcard.h + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief Header file of SMARTCARD HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32MP1xx_HAL_SMARTCARD_H +#define __STM32MP1xx_HAL_SMARTCARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal_def.h" + +/** @addtogroup STM32MP1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SMARTCARD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types + * @{ + */ + +/** + * @brief SMARTCARD Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate. + The baud rate register is computed using the following formula: + Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */ + + uint32_t StopBits; /*!< Specifies the number of stop bits. + This parameter can be a value of @ref SMARTCARD_Stop_Bits. */ + + uint16_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref SMARTCARD_Parity + @note The parity is enabled by default (PCE is forced to 1). + Since the WordLength is forced to 8 bits + parity, M is + forced to 1 and the parity bit is the 9th bit. */ + + uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref SMARTCARD_Mode */ + + uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref SMARTCARD_Clock_Polarity */ + + uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SMARTCARD_Clock_Phase */ + + uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref SMARTCARD_Last_Bit */ + + uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ + + uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. */ + + uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ + + uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled + in case of parity error. + This parameter can be a value of @ref SMARTCARD_NACK_Enable */ + + uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled. + This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/ + + uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks: + it is used to implement the Character Wait Time (CWT) and + Block Wait Time (BWT). It is coded over 24 bits. */ + + uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode. + This parameter can be any value from 0x0 to 0xFF */ + + uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in + receive and transmit mode). When set to 0, retransmission is + disabled. Otherwise, its maximum value is 7 (before signalling + an error) */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value + of @ref SMARTCARD_FIFO_mode */ + + uint32_t TXFIFOThreshold; /*!< Specifies the TXFIFO threshold level. + This parameter can be a value of @ref SMARTCARD_TXFIFO_threshold_level */ + + uint32_t RXFIFOThreshold; /*!< Specifies the RXFIFO threshold level. + This parameter can be a value of @ref SMARTCARD_RXFIFO_threshold_level */ + +}SMARTCARD_InitTypeDef; + +/** + * @brief SMARTCARD advanced features initalization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several + advanced features may be initialized at the same time. This parameter + can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref SMARTCARD_Tx_Inv */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref SMARTCARD_Rx_Inv */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref SMARTCARD_Data_Inv */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref SMARTCARD_Overrun_Disable */ + + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref SMARTCARD_MSB_First */ + + uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when + relevant flag is available) or once guard time period has elapsed. + This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */ +}SMARTCARD_AdvFeatureInitTypeDef; + +/** + * @brief HAL SMARTCARD State structures definition + * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState. + * - gState contains SMARTCARD state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef enum +{ + HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ + HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ +}HAL_SMARTCARD_StateTypeDef; + +/** + * @brief HAL SMARTCARD Error Code structure definition + */ +typedef enum +{ + HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */ + HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */ + HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */ + HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */ + HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */ + HAL_SMARTCARD_ERROR_DMA = 0x10, /*!< DMA transfer error */ + HAL_SMARTCARD_ERROR_UDR = 0x11, /*!< SPI UnderRun error */ + HAL_SMARTCARD_ERROR_RTO = 0x20 /*!< Receiver TimeOut error */ +}HAL_SMARTCARD_ErrorTypeDef; + +/** + * @brief SMARTCARD handle Structure definition + */ +typedef struct +{ + USART_TypeDef *Instance; /*!< USART registers base address */ + + SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */ + + SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ + + DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + + __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. + This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + + uint32_t ErrorCode; /*!< SmartCard Error code */ + +}SMARTCARD_HandleTypeDef; + +/** + * @brief SMARTCARD clock sources + */ +typedef enum +{ + SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + SMARTCARD_CLOCKSOURCE_PCLK5 = 0x02U, /*!< PCLK5 clock source (only used by USART1) */ + SMARTCARD_CLOCKSOURCE_PLL3Q = 0x04U, /*!< PLL3Q clock source (only used by USART1) */ + SMARTCARD_CLOCKSOURCE_PLL4Q = 0x08U, /*!< PLL4Q clock source */ + SMARTCARD_CLOCKSOURCE_HSI = 0x10U, /*!< HSI clock source */ + SMARTCARD_CLOCKSOURCE_CSI = 0x20U, /*!< CSI clock source */ + SMARTCARD_CLOCKSOURCE_HSE = 0x40U, /*!< HSE clock source */ + SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x80U /*!< Undefined clock source */ +}SMARTCARD_ClockSourceTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants + * @{ + */ + +/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length + * @{ + */ +#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< SMARTCARD frame length */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits + * @{ + */ +#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< SMARTCARD frame with 0.5 stop bit */ +#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Parity SMARTCARD Parity + * @{ + */ +#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< SMARTCARD frame even parity */ +#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode + * @{ + */ +#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) /*!< SMARTCARD RX mode */ +#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) /*!< SMARTCARD TX mode */ +#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< SMARTCARD RX and TX mode */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity + * @{ + */ +#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000) /*!< SMARTCARD frame low polarity */ +#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< SMARTCARD frame high polarity */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase + * @{ + */ +#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000) /*!< SMARTCARD frame phase on first clock transition */ +#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< SMARTCARD frame phase on second clock transition */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit + * @{ + */ +#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */ +#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */ +/** + * @} + */ + +/** @defgroup SMARTCARD_FIFO_mode SMARTCARD FIFO mode + * @brief SMARTCARD FIFO mode + * @{ + */ +#define SMARTCARD_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */ +#define SMARTCARD_FIFOMODE_ENABLE ((uint32_t)USART_CR1_FIFOEN) /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level + * @brief SMARTCARD TXFIFO level + * @{ + */ +#define SMARTCARD_TXFIFO_THRESHOLD_1EIGHTHFULL ((uint32_t)0x00000000) /*!< TXFIFO threshold 1 eighth full configuration */ +#define SMARTCARD_TXFIFO_THRESHOLD_1QUARTERFULL ((uint32_t)USART_CR3_TXFTCFG_0) /*!< TXFIFO threshold 1 quart full configuration */ +#define SMARTCARD_TXFIFO_THRESHOLD_HALFFULL ((uint32_t)USART_CR3_TXFTCFG_1) /*!< TXFIFO threshold half full configuration */ +#define SMARTCARD_TXFIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)) /*!< TXFIFO threshold 3 quarts full configuration */ +#define SMARTCARD_TXFIFO_THRESHOLD_7EIGHTHFULL ((uint32_t)USART_CR3_TXFTCFG_2) /*!< TXFIFO threshold 7 eighth full configuration */ +#define SMARTCARD_TXFIFO_THRESHOLD_EMPTY ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup SMARTCARD_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level + * @brief SMARTCARD RXFIFO level + * @{ + */ +#define SMARTCARD_RXFIFO_THRESHOLD_1EIGHTHFULL ((uint32_t)0x00000000) /*!< RXFIFO threshold 1 eighth full configuration */ +#define SMARTCARD_RXFIFO_THRESHOLD_1QUARTERFULL ((uint32_t)USART_CR3_RXFTCFG_0) /*!< RXFIFO threshold 1 quart full configuration */ +#define SMARTCARD_RXFIFO_THRESHOLD_HALFFULL ((uint32_t)USART_CR3_RXFTCFG_1) /*!< RXFIFO threshold half full configuration */ +#define SMARTCARD_RXFIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)) /*!< RXFIFO threshold 3 quarts full configuration */ +#define SMARTCARD_RXFIFO_THRESHOLD_7EIGHTHFULL ((uint32_t)USART_CR3_RXFTCFG_2) /*!< RXFIFO threshold 7 eighth full configuration */ +#define SMARTCARD_RXFIFO_THRESHOLD_FULL ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)) /*!< RXFIFO becomes Full */ +/** + * @} + */ + +/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method + * @{ + */ +#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD frame one-bit sample disabled */ +#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< SMARTCARD frame one-bit sample enabled */ +/** + * @} + */ + + +/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable + * @{ + */ +#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) /*!< SMARTCARD NACK transmission disabled */ +#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD NACK transmission enabled */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable + * @{ + */ +#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD receiver timeout disabled */ +#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< SMARTCARD receiver timeout enabled */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion + * @{ + */ +#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /*!< TX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion + * @{ + */ +#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /*!< RX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion + * @{ + */ +#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /*!< Binary data inversion disable */ +#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap + * @{ + */ +#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /*!< TX/RX pins swap disable */ +#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable + * @{ + */ +#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /*!< RX overrun enable */ +#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error + * @{ + */ +#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /*!< DMA enable on Reception Error */ +#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */ +/** + * @} + */ + +/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first + * @{ + */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /*!< Most significant bit sent/received first disable */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters + * @{ + */ +#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive data flush request */ +#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush request */ +/** + * @} + */ + +/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register + * @{ + */ +#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) /*!< SMARTCARD auto retry counter LSB position in CR3 register */ +/** + * @} + */ + +/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register + * @{ + */ +#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) /*!< SMARTCARD guard time value LSB position in GTPR register */ +/** + * @} + */ + +/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register + * @{ + */ +#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) /*!< SMARTCARD block length LSB position in RTOR register */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask + * @{ + */ +#define SMARTCARD_IT_MASK ((uint16_t)0x001F) /*!< SMARTCARD interruptions flags mask */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros + * @{ + */ + +/** @brief Reset SMARTCARD handle state. + * @param __HANDLE__: SMARTCARD handle. + * @retval None + */ +#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + } while(0) + +/** @brief Flush the Smartcard Data registers. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ + } while(0) + +/** @brief Clear the specified SMARTCARD pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag + * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag + * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag + * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag + * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag + * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag + * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag + * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the SMARTCARD PE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF) + + +/** @brief Clear the SMARTCARD FE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF) + +/** @brief Clear the SMARTCARD NE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF) + +/** @brief Clear the SMARTCARD ORE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF) + +/** @brief Clear the SMARTCARD IDLE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF) + +/** @brief Check whether the specified Smartcard flag is set or not. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag + * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag + * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref SMARTCARD_FLAG_BUSY Busy flag + * @arg @ref SMARTCARD_FLAG_EOBF End of block flag + * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag + * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag + * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag + * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag + * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag + * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag + * @arg @ref SMARTCARD_FLAG_NE Noise error flag + * @arg @ref SMARTCARD_FLAG_FE Framing error flag + * @arg @ref SMARTCARD_FLAG_PE Parity error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + + +/** @brief Enable the specified SmartCard interrupt. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) + +/** @brief Disable the specified SmartCard interrupt. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) + + +/** @brief Check whether the specified SmartCard interrupt has occurred or not. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __IT__: specifies the SMARTCARD interrupt to check. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_ORE Overrun error interrupt + * @arg @ref SMARTCARD_IT_NE Noise error interrupt + * @arg @ref SMARTCARD_IT_FE Framing error interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08))) + +/** @brief Check whether the specified SmartCard interrupt source is enabled or not. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __IT__: specifies the SMARTCARD interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_ERR Framing, overrun or noise error interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK))) + + +/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag + * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag + * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag + * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag + * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag + * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag + * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available) + * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Clear the SMARTCARD TX FIFO empty clear flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_TXFECF(__HANDLE__) __HAL_SMARTCARD_CLEAR_IT((__HANDLE__), SMARTCARD_CLEAR_TXFECF) + +/** @brief Set a specific SMARTCARD request flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __REQ__: specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request + * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request + * + * @retval None + */ +#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the SMARTCARD one bit sample method. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the SMARTCARD one bit sample method. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) + +/** @brief Enable the USART associated to the SMARTCARD Handle. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable the USART associated to the SMARTCARD Handle + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ + +/* Private macros -------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros + * @{ + */ + +/** @brief Check the Baud rate range. + * @param __BAUDRATE__: Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on MP1 (i.e. 100 MHz) + * divided by the smallest oversampling used on the SMARTCARD (i.e. 8). + * @retval Test result (TRUE or FALSE). + */ +#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U) + +/** @brief Check the block length range. + * @note The maximum SMARTCARD block length is 0xFF. + * @param __LENGTH__: block length. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF) + +/** @brief Check the receiver timeout value. + * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__: receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF) + +/** @brief Check the SMARTCARD autoretry counter value. + * @note The maximum number of retransmissions is 0x7. + * @param __COUNT__: number of retransmissions. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7) + +/** + * @brief Ensure that SMARTCARD frame length is valid. + * @param __LENGTH__: SMARTCARD frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) + +/** + * @brief Ensure that SMARTCARD frame number of stop bits is valid. + * @param __STOPBITS__: SMARTCARD frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\ + ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)) + +/** + * @brief Ensure that SMARTCARD frame parity is valid. + * @param __PARITY__: SMARTCARD frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \ + ((__PARITY__) == SMARTCARD_PARITY_ODD)) + +/** + * @brief Ensure that SMARTCARD communication mode is valid. + * @param __MODE__: SMARTCARD communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00)) + +/** + * @brief Ensure that SMARTCARD frame polarity is valid. + * @param __CPOL__: SMARTCARD frame polarity. + * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) + */ +#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) + +/** + * @brief Ensure that SMARTCARD frame phase is valid. + * @param __CPHA__: SMARTCARD frame phase. + * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) + */ +#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE)) + +/** + * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. + * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting. + * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) + */ +#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \ + ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE)) + +/** + * @brief Ensure that SMARTCARD frame sampling is valid. + * @param __ONEBIT__: SMARTCARD frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that SMARTCARD NACK transmission setting is valid. + * @param __NACK__: SMARTCARD NACK transmission setting. + * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid) + */ +#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \ + ((__NACK__) == SMARTCARD_NACK_DISABLE)) + +/** + * @brief Ensure that SMARTCARD receiver timeout setting is valid. + * @param __TIMEOUT__: SMARTCARD receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE)) + +/** + * @brief Ensure that SMARTCARD advanced features initialization is valid. + * @param __INIT__: SMARTCARD advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ + SMARTCARD_ADVFEATURE_TXINVERT_INIT | \ + SMARTCARD_ADVFEATURE_RXINVERT_INIT | \ + SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \ + SMARTCARD_ADVFEATURE_SWAP_INIT | \ + SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \ + SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) + +/** + * @brief Ensure that SMARTCARD frame TX inversion setting is valid. + * @param __TXINV__: SMARTCARD frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that SMARTCARD frame RX inversion setting is valid. + * @param __RXINV__: SMARTCARD frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that SMARTCARD frame data inversion setting is valid. + * @param __DATAINV__: SMARTCARD frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. + * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that SMARTCARD frame overrun setting is valid. + * @param __OVERRUN__: SMARTCARD frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. + * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR)) + +/** + * @brief Ensure that SMARTCARD frame MSB first setting is valid. + * @param __MSBFIRST__: SMARTCARD frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE)) + +/** + * @brief Ensure that SMARTCARD request parameter is valid. + * @param __PARAM__: SMARTCARD request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that SMARTCARD FIFO mode is valid. + * @param __STATE__: SMARTCARD FIFO mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_SMARTCARD_FIFO_MODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \ + ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) + +/** + * @brief Ensure that SMARTCARD TXFIFO threshold level is valid. + * @param __THRESHOLD__: SMARTCARD TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1EIGHTHFULL ) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1QUARTERFULL ) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_HALFFULL) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3QUARTERSFULL) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7EIGHTHFULL) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_EMPTY)) + +/** + * @brief Ensure that SMARTCARD RXFIFO threshold level is valid. + * @param __THRESHOLD__: SMARTCARD RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1EIGHTHFULL ) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1QUARTERFULL ) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_HALFFULL) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3QUARTERSFULL) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7EIGHTHFULL) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_FULL)) + +/** + * @} + */ + +/* Include SMARTCARD HAL Extended module */ +#include "stm32mp1xx_hal_smartcard_ex.h" + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMARTCARD_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/** @addtogroup SMARTCARD_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); + +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup SMARTCARD_Exported_Functions_Group2 + * @{ + */ + +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard); + +/** + * @} + */ + +/* Peripheral Control functions ***********************************************/ +/* Peripheral State and Error functions ***************************************/ +/** @addtogroup SMARTCARD_Exported_Functions_Group4 + * @{ + */ + +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard); +uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32MP1xx_HAL_SMARTCARD_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smartcard_ex.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smartcard_ex.h new file mode 100644 index 0000000000..4a2d885645 --- /dev/null +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smartcard_ex.h @@ -0,0 +1,337 @@ +/** + ****************************************************************************** + * @file stm32mp1xx_hal_smartcard_ex.h + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief Header file of SMARTCARD HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32MP1xx_HAL_SMARTCARD_EX_H +#define __STM32MP1xx_HAL_SMARTCARD_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32mp1xx_hal_def.h" + +/** @addtogroup STM32MP1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SMARTCARDEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants + * @{ + */ + +/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication + * @{ + */ +#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */ +#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type + * @{ + */ +#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */ +#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */ +#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */ +#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */ +#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */ +#define SMARTCARD_ADVFEATURE_TXCOMPLETION ((uint32_t)0x00000100) /*!< TX completion indication before of after guard time */ +/** + * @} + */ + + + + +/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */ +#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */ +#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */ +#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */ +#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */ +#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */ +#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */ +#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */ +#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */ +#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */ +#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */ +#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */ +#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */ +#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */ +#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT /*!< SMARTCARD TXFIFO threshold flag */ +#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT /*!< SMARTCARD RXFIFO threshold flag */ +#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF /*!< SMARTCARD RXFIFO Fullflag */ +#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE /*!< SMARTCARD TXFIFO Empty flag */ + +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5 bits) + * - XX : Interrupt source register (2 bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5 bits) + * @{ + */ +#define SMARTCARD_IT_PE ((uint16_t)0x0028) /*!< SMARTCARD parity error interruption */ +#define SMARTCARD_IT_TXE ((uint16_t)0x0727) /*!< SMARTCARD transmit data register empty interruption */ +#define SMARTCARD_IT_TC ((uint16_t)0x0626) /*!< SMARTCARD transmission complete interruption */ +#define SMARTCARD_IT_RXNE ((uint16_t)0x0525) /*!< SMARTCARD read data register not empty interruption */ +#define SMARTCARD_IT_IDLE ((uint16_t)0x0424) /*!< SMARTCARD idle line detection interruption */ + +#define SMARTCARD_IT_ERR ((uint16_t)0x0060) /*!< SMARTCARD error interruption */ +#define SMARTCARD_IT_ORE ((uint16_t)0x0300) /*!< SMARTCARD overrun error interruption */ +#define SMARTCARD_IT_NE ((uint16_t)0x0200) /*!< SMARTCARD noise error interruption */ +#define SMARTCARD_IT_FE ((uint16_t)0x0100) /*!< SMARTCARD frame error interruption */ + +#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B) /*!< SMARTCARD end of block interruption */ +#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A) /*!< SMARTCARD receiver timeout interruption */ + +#define SMARTCARD_IT_RXFF ((uint16_t)0x183F) +#define SMARTCARD_IT_TXFE ((uint16_t)0x173E) +#define SMARTCARD_IT_RXFT ((uint16_t)0x187C) +#define SMARTCARD_IT_TXFT ((uint16_t)0x1B77) +#define SMARTCARD_IT_TCBGT ((uint16_t)0x1978) /*!< SMARTCARD transmission complete before guard time completion interruption */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags + * @{ + */ +#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */ +#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */ +#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise detected clear flag */ +#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */ +#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */ +#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */ +#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */ +#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */ +#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */ +#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF /*!< SMARTCARD TXFIFO empty clear flag */ +#define SMARTCARD_CLEAR_UDRCF USART_ICR_UDRCF /*!< SMARTCARD UnderRun Error Clear Flag */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macros -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros + * @{ + */ + +/** @brief Report the SMARTCARD clock source. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __CLOCKSOURCE__: output variable. + * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. + */ +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK5: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK5; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_PLL4: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL4Q; \ + break; \ + case RCC_USART1CLKSOURCE_HSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSE; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_UART24_SOURCE()) \ + { \ + case RCC_UART24CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART24CLKSOURCE_PLL4: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL4Q; \ + break; \ + case RCC_UART24CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART24CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART24CLKSOURCE_HSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSE; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_UART35_SOURCE()) \ + { \ + case RCC_UART35CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART35CLKSOURCE_PLL4: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL4Q; \ + break; \ + case RCC_UART35CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART35CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART35CLKSOURCE_HSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSE; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART6CLKSOURCE_PLL4: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL4Q; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART6CLKSOURCE_HSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSE; \ + break; \ + } \ + } \ + } while(0) + + +/** @brief Set the Transmission Completion flag + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ + do { \ + if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ + { \ + (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ + } \ + else \ + { \ + assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \ + } \ + } while(0) + +/** @brief Return the transmission completion flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. + * @retval Transmission completion flag + */ +#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \ + (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT)) + +/** + * @brief Ensure that SMARTCARD frame transmission completion used flag is valid. + * @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag. + * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid) + */ +#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\ + ((__TXCOMPLETE__) == SMARTCARD_TC)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMARTCARDEx_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/* IO operation methods *******************************************************/ + +/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength); +void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue); +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32MP1xx_HAL_SMARTCARD_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h index 8a3980fe45..3f387897a8 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h @@ -73,7 +73,8 @@ extern "C" { #define ADC_SQR3_REGOFFSET (0x00000200UL) #define ADC_SQR4_REGOFFSET (0x00000300UL) -#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) +#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \ + | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) @@ -110,7 +111,8 @@ extern "C" { #define ADC_JDR3_REGOFFSET (0x00000200UL) #define ADC_JDR4_REGOFFSET (0x00000300UL) -#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) +#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \ + | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */ @@ -193,7 +195,8 @@ extern "C" { #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH) #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH) #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */ -#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) +#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \ + | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ @@ -214,25 +217,26 @@ extern "C" { /* Definition of channels ID number information to be inserted into */ /* channels literals definition. */ #define ADC_CHANNEL_0_NUMBER (0x00000000UL) -#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 ) -#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 ) -#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 ) -#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 ) -#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 ) -#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 ) -#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 ) -#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 ) -#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 ) -#define ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2) +#define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3) +#define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2) +#define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \ + ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4) +#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) /* Definition of channels ID bitfield information to be inserted into */ /* channels literals definition. */ @@ -340,7 +344,8 @@ extern "C" { #define ADC_OFR2_REGOFFSET (0x00000001UL) #define ADC_OFR3_REGOFFSET (0x00000002UL) #define ADC_OFR4_REGOFFSET (0x00000003UL) -#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) +#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \ + | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) /* ADC registers bits positions */ @@ -413,7 +418,7 @@ typedef struct { uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE - @note On this STM32 serie, if ADC group injected is used, some + @note On this STM32 series, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual. @@ -498,7 +503,7 @@ typedef struct { uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE - @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge + @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). @@ -558,7 +563,7 @@ typedef struct { uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE - @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge + @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge(). @@ -632,7 +637,7 @@ typedef struct #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */ #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */ #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */ -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ @@ -665,7 +670,7 @@ typedef struct #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ #if defined(ADC_MULTIMODE_SUPPORT) #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ @@ -700,7 +705,7 @@ typedef struct /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSEEN) /*!< ADC measurement path to internal channel temperature sensor */ #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */ @@ -1316,8 +1321,8 @@ typedef struct /* configuration (system clock versus ADC clock), */ /* and therefore must be defined in user application. */ /* Indications for estimation of ADC timeout delays, for this */ -/* STM32 serie: */ -/* - ADC calibration time: maximum delay is 16384/fADC. */ +/* STM32 series: */ +/* - ADC calibration time: maximum delay is 16384/fADC. */ /* (refer to device datasheet, parameter "tCAL") */ /* - ADC enable time: maximum delay is 1 conversion cycle. */ /* (refer to device datasheet, parameter "tSTAB") */ @@ -1338,22 +1343,22 @@ typedef struct /* Delay set to maximum value (refer to device datasheet, */ /* parameter "ts_vrefint"). */ /* Unit: us */ -#define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */ +#define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */ /* Delay for temperature sensor stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART_RUN"). */ /* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */ /* Delay required between ADC end of calibration and ADC enable. */ -/* Note: On this STM32 serie, a minimum number of ADC clock cycles */ +/* Note: On this STM32 series, a minimum number of ADC clock cycles */ /* are required between ADC end of calibration and ADC enable. */ /* Wait time can be computed in user application by waiting for the */ /* equivalent number of CPU cycles, by taking into account */ /* ratio of CPU clock versus ADC clock prescalers. */ /* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */ /* Fixed timeout value for ADC linearity word bit set/clear delay. */ /* Values defined to be higher than worst cases: low clock frequency, */ @@ -1452,10 +1457,10 @@ typedef struct * @retval Value between Min_Data=0 and Max_Data=18 */ #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \ - ? ( \ + ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \ + ( \ ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ - ) \ + ) \ : \ ( \ (uint32_t)POSITION_VAL((__CHANNEL__)) \ @@ -1505,12 +1510,12 @@ typedef struct * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) <= 9UL) \ - ? ( \ + (((__DECIMAL_NB__) <= 9UL) ? \ + ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ + ) \ : \ ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ @@ -1902,7 +1907,7 @@ typedef struct */ #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ #if defined(ADC_MULTIMODE_SUPPORT) /** @@ -1924,7 +1929,7 @@ typedef struct : \ (__ADCx__) \ ) -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Helper macro to select the ADC common instance @@ -1999,11 +2004,11 @@ typedef struct */ #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ - __ADC_RESOLUTION_TARGET__) \ - (((__DATA__) \ - << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ - >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ - ) + __ADC_RESOLUTION_TARGET__) \ +(((__DATA__) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ +) /** * @brief Helper macro to calculate the voltage (unit: mVolt) @@ -2024,10 +2029,10 @@ typedef struct */ #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ - __ADC_RESOLUTION__) \ - ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - ) + __ADC_RESOLUTION__) \ +((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ +) /** * @brief Helper macro to calculate analog reference voltage (Vref+) @@ -2039,7 +2044,7 @@ typedef struct * connected to pin Vref+. * On devices with small package, the pin Vref+ is not present * and internally bonded to pin Vdda. - * @note On this STM32 serie, calibration data of internal voltage reference + * @note On this STM32 series, calibration data of internal voltage reference * VrefInt corresponds to a resolution of 16 bits, * this is the recommended ADC resolution to convert voltage of * internal voltage reference VrefInt. @@ -2056,11 +2061,12 @@ typedef struct * @retval Analog reference voltage (unit: mV) */ #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ - / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_16B)) + __ADC_RESOLUTION__) \ +(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ + / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_16B) \ +) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -2089,7 +2095,7 @@ typedef struct * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note On this STM32 serie, calibration data of temperature sensor + * @note On this STM32 series, calibration data of temperature sensor * corresponds to a resolution of 16 bits, * this is the recommended ADC resolution to convert voltage of * temperature sensor. @@ -2110,17 +2116,17 @@ typedef struct */ #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_16B) \ - * (__VREFANALOG_VOLTAGE__)) \ - / TEMPSENSOR_CAL_VREFANALOG) \ - - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ - ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ - ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ - ) + TEMPSENSOR_CAL1_TEMP \ - ) + __ADC_RESOLUTION__) \ +(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_16B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ +) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -2172,18 +2178,17 @@ typedef struct __TEMPSENSOR_CALX_TEMP__,\ __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - ((( ( \ - (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ - * 1000UL) \ - - \ - (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ - * 1000UL) \ - ) \ - ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ - ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ - ) + __ADC_RESOLUTION__) \ +(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000UL) \ + - \ + (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000UL) \ + ) \ + ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ +) /** * @} @@ -2236,7 +2241,7 @@ typedef struct #if defined(ADC_MULTIMODE_SUPPORT) __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Register == LL_ADC_DMA_REG_REGULAR_DATA) { @@ -2260,7 +2265,7 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis /* Retrieve address of register DR */ return (uint32_t) &(ADCx->DR); } -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} @@ -2272,11 +2277,11 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis /** * @brief Set parameter common to several ADC: Clock source and prescaler. - * @note On this STM32 serie, if ADC group injected is used, some + * @note On this STM32 series, if ADC group injected is used, some * clock ratio constraints between ADC clock and AHB clock * must be respected. * Refer to reference manual. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -2356,7 +2361,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) * For ADC conversion of internal channels, * a sampling time minimum value is required. * Refer to device datasheet. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -2408,7 +2413,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO * For ADC conversion of internal channels, * a sampling time minimum value is required. * Refer to device datasheet. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -2449,7 +2454,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -2533,7 +2538,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx * both calibration factors must be concatenated. * To perform this processing, use helper macro * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled, without calibration on going, without conversion * on going on group regular. @@ -2578,7 +2583,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui /* "SingleDiff". */ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ /* containing other bits reserved for other purpose. */ - return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); + return (uint32_t)(READ_BIT(ADCx->CALFACT, + (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> + ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); } /** @@ -2586,7 +2593,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui * @note This function is intended to set linear calibration parameters * without having to perform a new calibration using * @ref LL_ADC_StartCalibration(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled, without calibration on going, without conversion * on going on group regular. @@ -2605,7 +2612,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui */ __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor) { - register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT; + uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT; MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor); MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord); while ((READ_BIT(ADCx->CR, LinearityWord)==0UL) && (timeout_cpu_cycles > 0UL)) @@ -2632,7 +2639,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord) { - register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT; + uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT; CLEAR_BIT(ADCx->CR, LinearityWord); while ((READ_BIT(ADCx->CR, LinearityWord)!=0UL) && (timeout_cpu_cycles > 0UL)) { @@ -2644,7 +2651,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, ui * @brief Set ADC resolution. * Refer to reference manual for alignments formats * dependencies to ADC resolutions. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -2698,9 +2705,12 @@ __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -2718,7 +2728,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) * Therefore, the ADC conversion data may be outdated: does not * correspond to the current voltage level on the selected * ADC channel. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -2751,9 +2761,12 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -2797,7 +2810,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) * to disable state using function LL_ADC_SetOffsetState(). * @note If a channel is mapped on several offsets numbers, only the offset * with the lowest value is considered for the subtraction. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -2857,7 +2870,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, @@ -2929,7 +2942,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); } @@ -2955,7 +2968,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); } @@ -3020,8 +3033,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Of */ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation); } /** @@ -3043,7 +3056,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_ */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE); } @@ -3059,7 +3072,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uin * @brief Set ADC group regular conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). - * @note On this STM32 serie, setting trigger source to external trigger + * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). @@ -3067,7 +3080,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uin * function @ref LL_ADC_REG_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3141,11 +3154,11 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { - register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); + __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ /* to match with triggers literals definition. */ @@ -3174,7 +3187,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) /** * @brief Set ADC group regular conversion trigger polarity. * @note Applicable only for trigger source set to external trigger. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3235,7 +3248,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) * function "LL_ADC_REG_SetSequencerChannels()". * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3327,7 +3340,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) * continuous mode and sequencer discontinuous mode. * @note It is not possible to enable both ADC auto-injected mode * and ADC group regular sequencer discontinuous mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3380,17 +3393,17 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * @note This function performs configuration of: * - Channels ordering into each rank of scan sequence: * whatever channel can be placed into whatever rank. - * @note On this STM32 serie, ADC group regular sequencer is + * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3467,7 +3480,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), @@ -3477,7 +3490,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /** * @brief Get ADC group regular sequence: channel on the selected * scan sequence rank. - * @note On this STM32 serie, ADC group regular sequencer is + * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). @@ -3565,7 +3578,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); return (uint32_t)((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) @@ -3581,7 +3594,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ * conversions launched successively automatically. * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3617,9 +3630,9 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) * @brief Set ADC data transfer mode * @note Conversion data can be either: * - Available in Data Register - * - Transfered by DMA in one shot mode - * - Transfered by DMA in circular mode - * - Transfered to DFSDM data register + * - Transferred by DMA in one shot mode + * - Transferred by DMA in circular mode + * - Transferred to DFSDM data register * @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode * @param ADCx ADC instance * @param DataTransferMode This parameter can be one of the following values: @@ -3639,9 +3652,9 @@ __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t * @brief Get ADC data transfer mode * @note Conversion data can be either: * - Available in Data Register - * - Transfered by DMA in one shot mode - * - Transfered by DMA in circular mode - * - Transfered to DFSDM data register + * - Transferred by DMA in one shot mode + * - Transferred by DMA in circular mode + * - Transferred to DFSDM data register * @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -3665,7 +3678,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx) * The default setting of overrun is data preserved. * Therefore, for compatibility with all devices, parameter * overrun should be set to data overwritten. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3707,7 +3720,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) * @brief Set ADC group injected conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). - * @note On this STM32 serie, setting trigger source to external trigger + * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). @@ -3715,7 +3728,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) * function @ref LL_ADC_INJ_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -3789,11 +3802,11 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) { - register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); + __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ /* to match with triggers literals definition. */ @@ -3822,7 +3835,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) /** * @brief Set ADC group injected conversion trigger polarity. * Applicable only for trigger source set to external trigger. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -3862,7 +3875,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) * scan direction is forward (from rank 1 to rank n). * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -3939,13 +3952,13 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * sequence rank. * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On STM32MP1, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN0..5). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4091,7 +4104,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ * from ADC group regular. * @note It is not possible to enable both ADC group injected * auto-injected mode and sequencer discontinuous mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4149,7 +4162,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) * on either groups regular or injected. * @note A modification of the context mode (bit JQDIS) causes the contexts * queue to be flushed and the register JSQR is cleared. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4199,13 +4212,13 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_GetTriggerSource() * @arg @ref LL_ADC_INJ_GetTriggerEdge() * @arg @ref LL_ADC_INJ_GetSequencerRanks() - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On STM32MP1, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN0..5). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4391,7 +4404,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, /* because containing other bits reserved for other purpose. */ /* If parameter "TriggerSource" is set to SW start, then parameter */ /* "ExternalTriggerEdge" is discarded. */ - register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); + uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | @@ -4431,7 +4444,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * Refer to device datasheet for timings values (parameters TS_vrefint, * TS_temp, ...). * @note Conversion time is the addition of sampling time and processing time. - * On this STM32 serie, ADC processing time is: + * On this STM32 series, ADC processing time is: * - 12.5 ADC clock cycles at ADC resolution 12 bits * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits @@ -4440,7 +4453,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * temperature sensor, ...), a sampling time minimum value * is required. * Refer to device datasheet. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4512,7 +4525,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), @@ -4525,7 +4538,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @note On this device, sampling time is on channel scope: independently * of channel mapped on ADC group regular or injected. * @note Conversion time is the addition of sampling time and processing time. - * On this STM32 serie, ADC processing time is: + * On this STM32 series, ADC processing time is: * - 12.5 ADC clock cycles at ADC resolution 12 bits * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits @@ -4593,7 +4606,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) @@ -4623,7 +4636,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * @note For ADC channels configured in differential mode, both inputs * should be biased at (Vref+)/2 +/-200mV. * (Vref+ is the analog voltage reference) - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @note One or several values can be selected. @@ -4713,7 +4726,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * @note In case of need to define a single channel to monitor * with analog watchdog from sequencer channel definition, * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -4734,7 +4747,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4843,8 +4856,8 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), @@ -4866,7 +4879,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Applicable only when the analog watchdog is set to monitor * one channel. - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -4887,7 +4900,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4978,10 +4991,10 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); + uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ /* (parameter value LL_ADC_AWD_DISABLE). */ @@ -5038,7 +5051,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -5064,7 +5077,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint * on oversampling intermediate computation (after ratio, before shift * application): intermediate register bitfield [32:7] * (26 most significant bits). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either ADC groups regular or injected. @@ -5093,7 +5106,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL) + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL) + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL) + (AWDThresholdsHighLow)); @@ -5125,7 +5138,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL) + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL) + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL) + (AWDThresholdsHighLow)); @@ -5149,7 +5162,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_ * the oversampling on ADC group regular is either * temporary stopped and continued, or resumed from start * (oversampler buffer reset). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -5203,11 +5216,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) * are done from 1 trigger) * - discontinuous mode (each conversion of oversampling ratio * needs a trigger) - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @note On this STM32 serie, oversampling discontinuous mode + * @note On this STM32 series, oversampling discontinuous mode * (triggered mode) can be used only when oversampling is * set on group regular only and in resumed mode. * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont @@ -5247,7 +5260,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) * @note This function set the 2 items of oversampling configuration: * - ratio * - shift - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -5320,7 +5333,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) */ /** * @brief Set ADC boost mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC boost must be configured, without calibration on going, without conversion * on going on group regular. @@ -5338,7 +5351,7 @@ __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode) /** * @brief Get ADC boost mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC boost must be configured, without calibration on going, without conversion * on going on group regular. @@ -5360,7 +5373,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx) * @note If multimode configuration: the selected ADC instance is * either master or slave depending on hardware. * Refer to reference manual. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -5439,7 +5452,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) * A macro is available to get the conversion data of * ADC master or ADC slave: see helper macro * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled * or enabled without conversion on going on group regular. @@ -5507,7 +5520,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_CO * - ADC resolution 10 bits can have maximum delay of 10 cycles. * - ADC resolution 8 bits can have maximum delay of 8 cycles. * - ADC resolution 6 bits can have maximum delay of 6 cycles. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -5586,7 +5599,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADC * state, the internal analog calibration is lost. After exiting from * deep power down, calibration must be relaunched or calibration factor * (preliminarily saved) must be set back into calibration register. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown @@ -5609,7 +5622,7 @@ __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx) * state, the internal analog calibration is lost. After exiting from * deep power down, calibration must be relaunched or calibration factor * (preliminarily saved) must be set back into calibration register. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown @@ -5637,12 +5650,12 @@ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) /** * @brief Enable ADC instance internal voltage regulator. - * @note On this STM32 serie, after ADC internal voltage regulator enable, + * @note On this STM32 series, after ADC internal voltage regulator enable, * a delay for ADC internal voltage regulator stabilization * is required before performing a ADC calibration or ADC enable. * Refer to device datasheet, parameter tADCVREG_STUP. * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator @@ -5661,7 +5674,7 @@ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) /** * @brief Disable ADC internal voltage regulator. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator @@ -5686,14 +5699,14 @@ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) /** * @brief Enable the selected ADC instance. - * @note On this STM32 serie, after ADC enable, a delay for + * @note On this STM32 series, after ADC enable, a delay for * ADC internal analog stabilization is required before performing a * ADC conversion start. * Refer to device datasheet, parameter tSTAB. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled and ADC internal voltage regulator enabled. * @rmtoll CR ADEN LL_ADC_Enable @@ -5712,7 +5725,7 @@ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) /** * @brief Disable the selected ADC instance. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be not disabled. Must be enabled without conversion on going * on either groups regular or injected. @@ -5732,7 +5745,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) /** * @brief Get the selected ADC instance enable state. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll CR ADEN LL_ADC_IsEnabled @@ -5758,7 +5771,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) /** * @brief Start ADC calibration in the mode single-ended * or differential (for devices with differential mode available). - * @note On this STM32 serie, a minimum number of ADC clock cycles + * @note On this STM32 series, a minimum number of ADC clock cycles * are required between ADC end of calibration and ADC enable. * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. * @note Calibration duration: @@ -5773,7 +5786,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) * Calibration of linearity is common to both * single-ended and differential modes * (calibration run can be performed only once). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADCAL LL_ADC_StartCalibration\n @@ -5819,14 +5832,14 @@ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) /** * @brief Start ADC group regular conversion. - * @note On this STM32 serie, this function is relevant for both + * @note On this STM32 series, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion * will start at next trigger event (on the selected trigger edge) * following the ADC start conversion command. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, @@ -5847,7 +5860,7 @@ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) /** * @brief Stop ADC group regular conversion. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled with conversion on going on group regular, * without ADC disable command on going. @@ -6016,14 +6029,14 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef /** * @brief Start ADC group injected conversion. - * @note On this STM32 serie, this function is relevant for both + * @note On this STM32 series, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion * will start at next trigger event (on the selected trigger edge) * following the ADC start conversion command. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group injected, * without conversion stop command on going on group injected, @@ -6044,7 +6057,7 @@ __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx) /** * @brief Stop ADC group injected conversion. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled with conversion on going on group injected, * without ADC disable command on going. @@ -6103,7 +6116,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6130,7 +6143,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6157,7 +6170,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6184,7 +6197,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6211,7 +6224,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6238,7 +6251,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -6255,7 +6268,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 /** * @brief Get flag ADC ready. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY @@ -6379,7 +6392,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) /** * @brief Clear flag ADC ready. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rcc.h b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rcc.h index 5f7bb05319..5eaf21a173 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rcc.h +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rcc.h @@ -288,10 +288,10 @@ typedef struct /** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider * @{ */ -#define LL_RCC_HSI_DIV_1 RCC_HSICFGR_HSIDIV_0 -#define LL_RCC_HSI_DIV_2 RCC_HSICFGR_HSIDIV_1 -#define LL_RCC_HSI_DIV_4 RCC_HSICFGR_HSIDIV_2 -#define LL_RCC_HSI_DIV_8 RCC_HSICFGR_HSIDIV_3 +#define LL_RCC_HSI_DIV_1 0U +#define LL_RCC_HSI_DIV_2 RCC_HSICFGR_HSIDIV_0 +#define LL_RCC_HSI_DIV_4 RCC_HSICFGR_HSIDIV_1 +#define LL_RCC_HSI_DIV_8 (RCC_HSICFGR_HSIDIV_0 | RCC_HSICFGR_HSIDIV_1) /** * @} */ @@ -299,18 +299,18 @@ typedef struct /** @defgroup RCC_LL_EC_MCOxSOURCE MCO SOURCE selection * @{ */ -#define LL_RCC_MCO1SOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_0) -#define LL_RCC_MCO1SOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_1) -#define LL_RCC_MCO1SOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_2) -#define LL_RCC_MCO1SOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_3) -#define LL_RCC_MCO1SOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_4) +#define LL_RCC_MCO1SOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, 0) +#define LL_RCC_MCO1SOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_0) +#define LL_RCC_MCO1SOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_1) +#define LL_RCC_MCO1SOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, (RCC_MCO1CFGR_MCO1SEL_0 | RCC_MCO1CFGR_MCO1SEL_1)) +#define LL_RCC_MCO1SOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_2) -#define LL_RCC_MCO2SOURCE_MPU LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_0) -#define LL_RCC_MCO2SOURCE_AXI LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_1) -#define LL_RCC_MCO2SOURCE_MCU LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_2) -#define LL_RCC_MCO2SOURCE_PLL4 LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_3) -#define LL_RCC_MCO2SOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_4) -#define LL_RCC_MCO2SOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_5) +#define LL_RCC_MCO2SOURCE_MPU LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, 0) +#define LL_RCC_MCO2SOURCE_AXI LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_0) +#define LL_RCC_MCO2SOURCE_MCU LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_1) +#define LL_RCC_MCO2SOURCE_PLL4 LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, (RCC_MCO2CFGR_MCO2SEL_1 | RCC_MCO2CFGR_MCO2SEL_0)) +#define LL_RCC_MCO2SOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_2) +#define LL_RCC_MCO2SOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, (RCC_MCO2CFGR_MCO2SEL_2 | RCC_MCO2CFGR_MCO2SEL_0)) /** * @} */ @@ -318,22 +318,22 @@ typedef struct /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler * @{ */ -#define LL_RCC_MCO1_DIV_1 RCC_MCO1CFGR_MCO1DIV_0 /*!< MCO not divided */ -#define LL_RCC_MCO1_DIV_2 RCC_MCO1CFGR_MCO1DIV_1 /*!< MCO divided by 2 */ -#define LL_RCC_MCO1_DIV_3 RCC_MCO1CFGR_MCO1DIV_2 /*!< MCO divided by 3 */ -#define LL_RCC_MCO1_DIV_4 RCC_MCO1CFGR_MCO1DIV_3 /*!< MCO divided by 4 */ -#define LL_RCC_MCO1_DIV_5 RCC_MCO1CFGR_MCO1DIV_4 /*!< MCO divided by 5 */ -#define LL_RCC_MCO1_DIV_6 RCC_MCO1CFGR_MCO1DIV_5 /*!< MCO divided by 6 */ -#define LL_RCC_MCO1_DIV_7 RCC_MCO1CFGR_MCO1DIV_6 /*!< MCO divided by 7 */ -#define LL_RCC_MCO1_DIV_8 RCC_MCO1CFGR_MCO1DIV_7 /*!< MCO divided by 8 */ -#define LL_RCC_MCO1_DIV_9 RCC_MCO1CFGR_MCO1DIV_8 /*!< MCO divided by 9 */ -#define LL_RCC_MCO1_DIV_10 RCC_MCO1CFGR_MCO1DIV_9 /*!< MCO divided by 10 */ -#define LL_RCC_MCO1_DIV_11 RCC_MCO1CFGR_MCO1DIV_10 /*!< MCO divided by 11 */ -#define LL_RCC_MCO1_DIV_12 RCC_MCO1CFGR_MCO1DIV_11 /*!< MCO divided by 12 */ -#define LL_RCC_MCO1_DIV_13 RCC_MCO1CFGR_MCO1DIV_12 /*!< MCO divided by 13 */ -#define LL_RCC_MCO1_DIV_14 RCC_MCO1CFGR_MCO1DIV_13 /*!< MCO divided by 14 */ -#define LL_RCC_MCO1_DIV_15 RCC_MCO1CFGR_MCO1DIV_14 /*!< MCO divided by 15 */ -#define LL_RCC_MCO1_DIV_16 RCC_MCO1CFGR_MCO1DIV_15 /*!< MCO divided by 16 */ +#define LL_RCC_MCO1_DIV_1 0U /*!< MCO not divided */ +#define LL_RCC_MCO1_DIV_2 RCC_MCO1CFGR_MCO1DIV_0 /*!< MCO divided by 2 */ +#define LL_RCC_MCO1_DIV_3 RCC_MCO1CFGR_MCO1DIV_1 /*!< MCO divided by 3 */ +#define LL_RCC_MCO1_DIV_4 (RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 4 */ +#define LL_RCC_MCO1_DIV_5 RCC_MCO1CFGR_MCO1DIV_2 /*!< MCO divided by 5 */ +#define LL_RCC_MCO1_DIV_6 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 6 */ +#define LL_RCC_MCO1_DIV_7 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1) /*!< MCO divided by 7 */ +#define LL_RCC_MCO1_DIV_8 (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1| RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 8 */ +#define LL_RCC_MCO1_DIV_9 RCC_MCO1CFGR_MCO1DIV_3 /*!< MCO divided by 9 */ +#define LL_RCC_MCO1_DIV_10 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 10 */ +#define LL_RCC_MCO1_DIV_11 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1) /*!< MCO divided by 11 */ +#define LL_RCC_MCO1_DIV_12 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 12 */ +#define LL_RCC_MCO1_DIV_13 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2) /*!< MCO divided by 13 */ +#define LL_RCC_MCO1_DIV_14 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 14 */ +#define LL_RCC_MCO1_DIV_15 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1) /*!< MCO divided by 15 */ +#define LL_RCC_MCO1_DIV_16 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0) /*!< MCO divided by 16 */ /** * @} */ @@ -435,10 +435,10 @@ typedef struct /** @defgroup RCC_LL_EC_MPU_CLKSOURCE MPU clock switch * @{ */ -#define LL_RCC_MPU_CLKSOURCE_HSI RCC_MPCKSELR_MPUSRC_0 /*!< HSI selection as MPU clock */ -#define LL_RCC_MPU_CLKSOURCE_HSE RCC_MPCKSELR_MPUSRC_1 /*!< HSE selection as MPU clock */ -#define LL_RCC_MPU_CLKSOURCE_PLL1 RCC_MPCKSELR_MPUSRC_2 /*!< PLL1 selection as MPU clock */ -#define LL_RCC_MPU_CLKSOURCE_MPUDIV RCC_MPCKSELR_MPUSRC_3 /*!< MPUDIV selection as MPU clock */ +#define LL_RCC_MPU_CLKSOURCE_HSI 0U /*!< HSI selection as MPU clock */ +#define LL_RCC_MPU_CLKSOURCE_HSE RCC_MPCKSELR_MPUSRC_0 /*!< HSE selection as MPU clock */ +#define LL_RCC_MPU_CLKSOURCE_PLL1 RCC_MPCKSELR_MPUSRC_1 /*!< PLL1 selection as MPU clock */ +#define LL_RCC_MPU_CLKSOURCE_MPUDIV (RCC_MPCKSELR_MPUSRC_1 | RCC_MPCKSELR_MPUSRC_0) /*!< MPUDIV selection as MPU clock */ /** * @} */ @@ -469,10 +469,10 @@ typedef struct /** @defgroup RCC_LL_EC_AXISS_CLKSOURCE AXISS clock switch * @{ */ -#define LL_RCC_AXISS_CLKSOURCE_HSI RCC_ASSCKSELR_AXISSRC_0 /*!< HSI selection as AXISS clock */ -#define LL_RCC_AXISS_CLKSOURCE_HSE RCC_ASSCKSELR_AXISSRC_1 /*!< HSE selection as AXISS clock */ -#define LL_RCC_AXISS_CLKSOURCE_PLL2 RCC_ASSCKSELR_AXISSRC_2 /*!< PLL2 selection as AXISS clock */ -#define LL_RCC_AXISS_CLKSOURCE_OFF RCC_ASSCKSELR_AXISSRC_3 /*!< AXISS is gated */ +#define LL_RCC_AXISS_CLKSOURCE_HSI 0U /*!< HSI selection as AXISS clock */ +#define LL_RCC_AXISS_CLKSOURCE_HSE RCC_ASSCKSELR_AXISSRC_0 /*!< HSE selection as AXISS clock */ +#define LL_RCC_AXISS_CLKSOURCE_PLL2 RCC_ASSCKSELR_AXISSRC_1 /*!< PLL2 selection as AXISS clock */ +#define LL_RCC_AXISS_CLKSOURCE_OFF (RCC_ASSCKSELR_AXISSRC_1 | RCC_ASSCKSELR_AXISSRC_0) /*!< AXISS is gated */ /** * @} */ @@ -480,10 +480,10 @@ typedef struct /** @defgroup RCC_LL_EC_AXISS_CLKSOURCE_STATUS AXISS clock switch status * @{ */ -#define LL_RCC_AXISS_CLKSOURCE_STATUS_HSI RCC_ASSCKSELR_AXISSRC_0 /*!< HSI used as AXISS clock */ -#define LL_RCC_AXISS_CLKSOURCE_STATUS_HSE RCC_ASSCKSELR_AXISSRC_1 /*!< HSE used as AXISS clock */ -#define LL_RCC_AXISS_CLKSOURCE_STATUS_PLL2 RCC_ASSCKSELR_AXISSRC_2 /*!< PLL2 used as AXISS clock */ -#define LL_RCC_AXISS_CLKSOURCE_STATUS_OFF RCC_ASSCKSELR_AXISSRC_3 /*!< AXISS is gated */ +#define LL_RCC_AXISS_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as AXISS clock */ +#define LL_RCC_AXISS_CLKSOURCE_STATUS_HSE RCC_ASSCKSELR_AXISSRC_0 /*!< HSE used as AXISS clock */ +#define LL_RCC_AXISS_CLKSOURCE_STATUS_PLL2 RCC_ASSCKSELR_AXISSRC_1 /*!< PLL2 used as AXISS clock */ +#define LL_RCC_AXISS_CLKSOURCE_STATUS_OFF (RCC_ASSCKSELR_AXISSRC_1 | RCC_ASSCKSELR_AXISSRC_0) /*!< AXISS is gated */ /** * @} */ @@ -502,10 +502,10 @@ typedef struct /** @defgroup RCC_LL_EC_MCUSS_CLKSOURCE MCUSS clock switch * @{ */ -#define LL_RCC_MCUSS_CLKSOURCE_HSI RCC_MSSCKSELR_MCUSSRC_0 /*!< HSI selection as MCUSS clock */ -#define LL_RCC_MCUSS_CLKSOURCE_HSE RCC_MSSCKSELR_MCUSSRC_1 /*!< HSE selection as MCUSS clock */ -#define LL_RCC_MCUSS_CLKSOURCE_CSI RCC_MSSCKSELR_MCUSSRC_2 /*!< CSI selection as MCUSS clock */ -#define LL_RCC_MCUSS_CLKSOURCE_PLL3 RCC_MSSCKSELR_MCUSSRC_3 /*!< PLL3 selection as MCUSS clock */ +#define LL_RCC_MCUSS_CLKSOURCE_HSI 0U /*!< HSI selection as MCUSS clock */ +#define LL_RCC_MCUSS_CLKSOURCE_HSE RCC_MSSCKSELR_MCUSSRC_0 /*!< HSE selection as MCUSS clock */ +#define LL_RCC_MCUSS_CLKSOURCE_CSI RCC_MSSCKSELR_MCUSSRC_1 /*!< CSI selection as MCUSS clock */ +#define LL_RCC_MCUSS_CLKSOURCE_PLL3 (RCC_MSSCKSELR_MCUSSRC_1 | RCC_MSSCKSELR_MCUSSRC_0) /*!< PLL3 selection as MCUSS clock */ /** * @} */ @@ -541,11 +541,11 @@ typedef struct /** @defgroup RCC_LL_EC_APB1_DIV APB1 prescaler * @{ */ -#define LL_RCC_APB1_DIV_1 RCC_APB1DIVR_APB1DIV_0 /*!< mlhclk not divided (default after reset) */ -#define LL_RCC_APB1_DIV_2 RCC_APB1DIVR_APB1DIV_1 /*!< mlhclk divided by 2 */ -#define LL_RCC_APB1_DIV_4 RCC_APB1DIVR_APB1DIV_2 /*!< mlhclk divided by 4 */ -#define LL_RCC_APB1_DIV_8 RCC_APB1DIVR_APB1DIV_3 /*!< mlhclk divided by 8 */ -#define LL_RCC_APB1_DIV_16 RCC_APB1DIVR_APB1DIV_4 /*!< mlhclk divided by 16 */ +#define LL_RCC_APB1_DIV_1 0U /*!< mlhclk not divided (default after reset) */ +#define LL_RCC_APB1_DIV_2 RCC_APB1DIVR_APB1DIV_0 /*!< mlhclk divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_APB1DIVR_APB1DIV_1 /*!< mlhclk divided by 4 */ +#define LL_RCC_APB1_DIV_8 (RCC_APB1DIVR_APB1DIV_1 | RCC_APB1DIVR_APB1DIV_0) /*!< mlhclk divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_APB1DIVR_APB1DIV_2 /*!< mlhclk divided by 16 */ /** * @} */ @@ -553,11 +553,11 @@ typedef struct /** @defgroup RCC_LL_EC_APB2_DIV APB2 prescaler * @{ */ -#define LL_RCC_APB2_DIV_1 RCC_APB2DIVR_APB2DIV_0 /*!< mlhclk not divided (default after reset) */ -#define LL_RCC_APB2_DIV_2 RCC_APB2DIVR_APB2DIV_1 /*!< mlhclk divided by 2 */ -#define LL_RCC_APB2_DIV_4 RCC_APB2DIVR_APB2DIV_2 /*!< mlhclk divided by 4 */ -#define LL_RCC_APB2_DIV_8 RCC_APB2DIVR_APB2DIV_3 /*!< mlhclk divided by 8 */ -#define LL_RCC_APB2_DIV_16 RCC_APB2DIVR_APB2DIV_4 /*!< mlhclk divided by 16 */ +#define LL_RCC_APB2_DIV_1 0U /*!< mlhclk not divided (default after reset) */ +#define LL_RCC_APB2_DIV_2 RCC_APB2DIVR_APB2DIV_0 /*!< mlhclk divided by 2 */ +#define LL_RCC_APB2_DIV_4 RCC_APB2DIVR_APB2DIV_1 /*!< mlhclk divided by 4 */ +#define LL_RCC_APB2_DIV_8 (RCC_APB2DIVR_APB2DIV_1 | RCC_APB2DIVR_APB2DIV_0) /*!< mlhclk divided by 8 */ +#define LL_RCC_APB2_DIV_16 RCC_APB2DIVR_APB2DIV_2 /*!< mlhclk divided by 16 */ /** * @} */ @@ -565,11 +565,11 @@ typedef struct /** @defgroup RCC_LL_EC_APB3_DIV APB3 prescaler * @{ */ -#define LL_RCC_APB3_DIV_1 RCC_APB3DIVR_APB3DIV_0 /*!< mlhclk not divided (default after reset) */ -#define LL_RCC_APB3_DIV_2 RCC_APB3DIVR_APB3DIV_1 /*!< mlhclk divided by 2 */ -#define LL_RCC_APB3_DIV_4 RCC_APB3DIVR_APB3DIV_2 /*!< mlhclk divided by 4 */ -#define LL_RCC_APB3_DIV_8 RCC_APB3DIVR_APB3DIV_3 /*!< mlhclk divided by 8 */ -#define LL_RCC_APB3_DIV_16 RCC_APB3DIVR_APB3DIV_4 /*!< mlhclk divided by 16 */ +#define LL_RCC_APB3_DIV_1 0U /*!< mlhclk not divided (default after reset) */ +#define LL_RCC_APB3_DIV_2 RCC_APB3DIVR_APB3DIV_0 /*!< mlhclk divided by 2 */ +#define LL_RCC_APB3_DIV_4 RCC_APB3DIVR_APB3DIV_1 /*!< mlhclk divided by 4 */ +#define LL_RCC_APB3_DIV_8 (RCC_APB3DIVR_APB3DIV_1| RCC_APB3DIVR_APB3DIV_0) /*!< mlhclk divided by 8 */ +#define LL_RCC_APB3_DIV_16 RCC_APB3DIVR_APB3DIV_2 /*!< mlhclk divided by 16 */ /** * @} */ @@ -577,11 +577,11 @@ typedef struct /** @defgroup RCC_LL_EC_APB4_DIV APB4 prescaler * @{ */ -#define LL_RCC_APB4_DIV_1 RCC_APB4DIVR_APB4DIV_0 /*!< aclk not divided (default after reset) */ -#define LL_RCC_APB4_DIV_2 RCC_APB4DIVR_APB4DIV_1 /*!< aclk divided by 2 */ -#define LL_RCC_APB4_DIV_4 RCC_APB4DIVR_APB4DIV_2 /*!< aclk divided by 4 */ -#define LL_RCC_APB4_DIV_8 RCC_APB4DIVR_APB4DIV_3 /*!< aclk divided by 8 */ -#define LL_RCC_APB4_DIV_16 RCC_APB4DIVR_APB4DIV_4 /*!< aclk divided by 16 */ +#define LL_RCC_APB4_DIV_1 0U /*!< aclk not divided (default after reset) */ +#define LL_RCC_APB4_DIV_2 RCC_APB4DIVR_APB4DIV_0 /*!< aclk divided by 2 */ +#define LL_RCC_APB4_DIV_4 RCC_APB4DIVR_APB4DIV_1 /*!< aclk divided by 4 */ +#define LL_RCC_APB4_DIV_8 (RCC_APB4DIVR_APB4DIV_1 | RCC_APB4DIVR_APB4DIV_0) /*!< aclk divided by 8 */ +#define LL_RCC_APB4_DIV_16 RCC_APB4DIVR_APB4DIV_2 /*!< aclk divided by 16 */ /** * @} */ @@ -589,11 +589,11 @@ typedef struct /** @defgroup RCC_LL_EC_APB5_DIV APB5 prescaler * @{ */ -#define LL_RCC_APB5_DIV_1 RCC_APB5DIVR_APB5DIV_0 /*!< aclk not divided (default after reset) */ -#define LL_RCC_APB5_DIV_2 RCC_APB5DIVR_APB5DIV_1 /*!< aclk divided by 2 */ -#define LL_RCC_APB5_DIV_4 RCC_APB5DIVR_APB5DIV_2 /*!< aclk divided by 4 */ -#define LL_RCC_APB5_DIV_8 RCC_APB5DIVR_APB5DIV_3 /*!< aclk divided by 8 */ -#define LL_RCC_APB5_DIV_16 RCC_APB5DIVR_APB5DIV_4 /*!< aclk divided by 16 */ +#define LL_RCC_APB5_DIV_1 0U /*!< aclk not divided (default after reset) */ +#define LL_RCC_APB5_DIV_2 RCC_APB5DIVR_APB5DIV_0 /*!< aclk divided by 2 */ +#define LL_RCC_APB5_DIV_4 RCC_APB5DIVR_APB5DIV_1 /*!< aclk divided by 4 */ +#define LL_RCC_APB5_DIV_8 (RCC_APB5DIVR_APB5DIV_1 | RCC_APB5DIVR_APB5DIV_0) /*!< aclk divided by 8 */ +#define LL_RCC_APB5_DIV_16 RCC_APB5DIVR_APB5DIV_2 /*!< aclk divided by 16 */ /** * @} */ @@ -624,20 +624,20 @@ typedef struct /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection * @{ */ -#define LL_RCC_I2C12_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_0) -#define LL_RCC_I2C12_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_1) -#define LL_RCC_I2C12_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_2) -#define LL_RCC_I2C12_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_3) +#define LL_RCC_I2C12_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, 0) +#define LL_RCC_I2C12_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_0) +#define LL_RCC_I2C12_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_1) +#define LL_RCC_I2C12_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, (RCC_I2C12CKSELR_I2C12SRC_1 | RCC_I2C12CKSELR_I2C12SRC_0)) -#define LL_RCC_I2C35_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_0) -#define LL_RCC_I2C35_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_1) -#define LL_RCC_I2C35_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_2) -#define LL_RCC_I2C35_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_3) +#define LL_RCC_I2C35_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, 0) +#define LL_RCC_I2C35_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_0) +#define LL_RCC_I2C35_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_1) +#define LL_RCC_I2C35_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, (RCC_I2C35CKSELR_I2C35SRC_1 | RCC_I2C35CKSELR_I2C35SRC_0)) -#define LL_RCC_I2C46_CLKSOURCE_PCLK5 LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_0) -#define LL_RCC_I2C46_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_1) -#define LL_RCC_I2C46_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_2) -#define LL_RCC_I2C46_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_3) +#define LL_RCC_I2C46_CLKSOURCE_PCLK5 LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, 0) +#define LL_RCC_I2C46_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_0) +#define LL_RCC_I2C46_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_1) +#define LL_RCC_I2C46_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, (RCC_I2C46CKSELR_I2C46SRC_1 | RCC_I2C46CKSELR_I2C46SRC_0)) /** * @} */ @@ -645,30 +645,30 @@ typedef struct /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection * @{ */ -#define LL_RCC_SAI1_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_0) -#define LL_RCC_SAI1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_1) -#define LL_RCC_SAI1_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_2) -#define LL_RCC_SAI1_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_3) -#define LL_RCC_SAI1_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_4) - -#define LL_RCC_SAI2_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_0) -#define LL_RCC_SAI2_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_1) -#define LL_RCC_SAI2_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_2) -#define LL_RCC_SAI2_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_3) -#define LL_RCC_SAI2_CLKSOURCE_SPDIF LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_4) -#define LL_RCC_SAI2_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_5) - -#define LL_RCC_SAI3_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_0) -#define LL_RCC_SAI3_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_1) -#define LL_RCC_SAI3_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_2) -#define LL_RCC_SAI3_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_3) -#define LL_RCC_SAI3_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_4) - -#define LL_RCC_SAI4_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_0) -#define LL_RCC_SAI4_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_1) -#define LL_RCC_SAI4_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_2) -#define LL_RCC_SAI4_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_3) -#define LL_RCC_SAI4_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_4) +#define LL_RCC_SAI1_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, 0) +#define LL_RCC_SAI1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_0) +#define LL_RCC_SAI1_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_1) +#define LL_RCC_SAI1_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, (RCC_SAI1CKSELR_SAI1SRC_1 | RCC_SAI1CKSELR_SAI1SRC_0)) +#define LL_RCC_SAI1_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_2) + +#define LL_RCC_SAI2_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, 0) +#define LL_RCC_SAI2_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_0) +#define LL_RCC_SAI2_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_1) +#define LL_RCC_SAI2_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, (RCC_SAI2CKSELR_SAI2SRC_1 | RCC_SAI2CKSELR_SAI2SRC_0)) +#define LL_RCC_SAI2_CLKSOURCE_SPDIF LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_2) +#define LL_RCC_SAI2_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, (RCC_SAI2CKSELR_SAI2SRC_2 | RCC_SAI2CKSELR_SAI2SRC_0)) + +#define LL_RCC_SAI3_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, 0) +#define LL_RCC_SAI3_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_0) +#define LL_RCC_SAI3_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_1) +#define LL_RCC_SAI3_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, (RCC_SAI3CKSELR_SAI3SRC_1 | RCC_SAI3CKSELR_SAI3SRC_0)) +#define LL_RCC_SAI3_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_2) + +#define LL_RCC_SAI4_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, 0) +#define LL_RCC_SAI4_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_0) +#define LL_RCC_SAI4_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_1) +#define LL_RCC_SAI4_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, (RCC_SAI4CKSELR_SAI4SRC_1 | RCC_SAI4CKSELR_SAI4SRC_0)) +#define LL_RCC_SAI4_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_2) /** * @} */ @@ -676,30 +676,30 @@ typedef struct /** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI/I2S clock source selection * @{ */ -#define LL_RCC_SPI1_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_0) -#define LL_RCC_SPI1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_1) -#define LL_RCC_SPI1_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_2) -#define LL_RCC_SPI1_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_3) -#define LL_RCC_SPI1_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_4) - -#define LL_RCC_SPI23_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_0) -#define LL_RCC_SPI23_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_1) -#define LL_RCC_SPI23_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_2) -#define LL_RCC_SPI23_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_3) -#define LL_RCC_SPI23_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_4) - -#define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_0) -#define LL_RCC_SPI45_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_1) -#define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_2) -#define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_3) -#define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_4) - -#define LL_RCC_SPI6_CLKSOURCE_PCLK5 LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_0) -#define LL_RCC_SPI6_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_1) -#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_2) -#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_3) -#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_4) -#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_5) +#define LL_RCC_SPI1_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, 0) +#define LL_RCC_SPI1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_0) +#define LL_RCC_SPI1_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_1) +#define LL_RCC_SPI1_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, (RCC_SPI2S1CKSELR_SPI1SRC_1 | RCC_SPI2S1CKSELR_SPI1SRC_0)) +#define LL_RCC_SPI1_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_2) + +#define LL_RCC_SPI23_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, 0) +#define LL_RCC_SPI23_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_0) +#define LL_RCC_SPI23_CLKSOURCE_I2SCKIN LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_1) +#define LL_RCC_SPI23_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, (RCC_SPI2S23CKSELR_SPI23SRC_1 | RCC_SPI2S23CKSELR_SPI23SRC_0)) +#define LL_RCC_SPI23_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_2) + +#define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, 0) +#define LL_RCC_SPI45_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_0) +#define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_1) +#define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, (RCC_SPI45CKSELR_SPI45SRC_1 | RCC_SPI45CKSELR_SPI45SRC_0)) +#define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_2) + +#define LL_RCC_SPI6_CLKSOURCE_PCLK5 LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, 0) +#define LL_RCC_SPI6_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_0) +#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_1) +#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, (RCC_SPI6CKSELR_SPI6SRC_1 | RCC_SPI6CKSELR_SPI6SRC_0)) +#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_2) +#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, (RCC_SPI6CKSELR_SPI6SRC_2 | RCC_SPI6CKSELR_SPI6SRC_0)) /** * @} */ @@ -707,36 +707,36 @@ typedef struct /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection * @{ */ -#define LL_RCC_USART1_CLKSOURCE_PCLK5 LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_0) -#define LL_RCC_USART1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_1) -#define LL_RCC_USART1_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_2) -#define LL_RCC_USART1_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_3) -#define LL_RCC_USART1_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_4) -#define LL_RCC_USART1_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_5) - -#define LL_RCC_UART24_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_0) -#define LL_RCC_UART24_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_1) -#define LL_RCC_UART24_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_2) -#define LL_RCC_UART24_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_3) -#define LL_RCC_UART24_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_4) - -#define LL_RCC_UART35_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_0) -#define LL_RCC_UART35_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_1) -#define LL_RCC_UART35_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_2) -#define LL_RCC_UART35_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_3) -#define LL_RCC_UART35_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_4) - -#define LL_RCC_USART6_CLKSOURCE_PCLK2 LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_0) -#define LL_RCC_USART6_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_1) -#define LL_RCC_USART6_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_2) -#define LL_RCC_USART6_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_3) -#define LL_RCC_USART6_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_4) - -#define LL_RCC_UART78_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_0) -#define LL_RCC_UART78_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_1) -#define LL_RCC_UART78_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_2) -#define LL_RCC_UART78_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_3) -#define LL_RCC_UART78_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_4) +#define LL_RCC_USART1_CLKSOURCE_PCLK5 LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, 0) +#define LL_RCC_USART1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_0) +#define LL_RCC_USART1_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_1) +#define LL_RCC_USART1_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, (RCC_UART1CKSELR_UART1SRC_1 | RCC_UART1CKSELR_UART1SRC_0)) +#define LL_RCC_USART1_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_2) +#define LL_RCC_USART1_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, (RCC_UART1CKSELR_UART1SRC_2 | RCC_UART1CKSELR_UART1SRC_0)) + +#define LL_RCC_UART24_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, 0) +#define LL_RCC_UART24_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_0) +#define LL_RCC_UART24_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_1) +#define LL_RCC_UART24_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, (RCC_UART24CKSELR_UART24SRC_1 | RCC_UART24CKSELR_UART24SRC_0)) +#define LL_RCC_UART24_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_2) + +#define LL_RCC_UART35_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, 0) +#define LL_RCC_UART35_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_0) +#define LL_RCC_UART35_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_1) +#define LL_RCC_UART35_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, (RCC_UART35CKSELR_UART35SRC_1 | RCC_UART35CKSELR_UART35SRC_0)) +#define LL_RCC_UART35_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_2) + +#define LL_RCC_USART6_CLKSOURCE_PCLK2 LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, 0) +#define LL_RCC_USART6_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_0) +#define LL_RCC_USART6_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_1) +#define LL_RCC_USART6_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, (RCC_UART6CKSELR_UART6SRC_1 | RCC_UART6CKSELR_UART6SRC_0)) +#define LL_RCC_USART6_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_2) + +#define LL_RCC_UART78_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, 0) +#define LL_RCC_UART78_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_0) +#define LL_RCC_UART78_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_1) +#define LL_RCC_UART78_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, (RCC_UART78CKSELR_UART78SRC_1 | RCC_UART78CKSELR_UART78SRC_0)) +#define LL_RCC_UART78_CLKSOURCE_HSE LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_2) /** * @} */ @@ -744,15 +744,15 @@ typedef struct /** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE Peripheral SDMMC clock source selection * @{ */ -#define LL_RCC_SDMMC12_CLKSOURCE_HCLK6 LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_0) -#define LL_RCC_SDMMC12_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_1) -#define LL_RCC_SDMMC12_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_2) -#define LL_RCC_SDMMC12_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_3) +#define LL_RCC_SDMMC12_CLKSOURCE_HCLK6 LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, 0) +#define LL_RCC_SDMMC12_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_0) +#define LL_RCC_SDMMC12_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_1) +#define LL_RCC_SDMMC12_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, (RCC_SDMMC12CKSELR_SDMMC12SRC_1 | RCC_SDMMC12CKSELR_SDMMC12SRC_0)) -#define LL_RCC_SDMMC3_CLKSOURCE_HCLK2 LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_0) -#define LL_RCC_SDMMC3_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_1) -#define LL_RCC_SDMMC3_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_2) -#define LL_RCC_SDMMC3_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_3) +#define LL_RCC_SDMMC3_CLKSOURCE_HCLK2 LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, 0) +#define LL_RCC_SDMMC3_CLKSOURCE_PLL3R LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_0) +#define LL_RCC_SDMMC3_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_1) +#define LL_RCC_SDMMC3_CLKSOURCE_HSI LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, (RCC_SDMMC3CKSELR_SDMMC3SRC_1 | RCC_SDMMC3CKSELR_SDMMC3SRC_0)) /** * @} */ @@ -760,9 +760,9 @@ typedef struct /** @defgroup RCC_LL_EC_ETH_CLKSOURCE Peripheral ETH clock source selection * @{ */ -#define LL_RCC_ETH_CLKSOURCE_PLL4P RCC_ETHCKSELR_ETHSRC_0 -#define LL_RCC_ETH_CLKSOURCE_PLL3Q RCC_ETHCKSELR_ETHSRC_1 -#define LL_RCC_ETH_CLKSOURCE_OFF RCC_ETHCKSELR_ETHSRC_2 +#define LL_RCC_ETH_CLKSOURCE_PLL4P 0U +#define LL_RCC_ETH_CLKSOURCE_PLL3Q RCC_ETHCKSELR_ETHSRC_0 +#define LL_RCC_ETH_CLKSOURCE_OFF RCC_ETHCKSELR_ETHSRC_1 /** * @} */ @@ -770,10 +770,10 @@ typedef struct /** @defgroup RCC_LL_EC_QSPI_CLKSOURCE Peripheral QSPI clock source selection * @{ */ -#define LL_RCC_QSPI_CLKSOURCE_ACLK RCC_QSPICKSELR_QSPISRC_0 -#define LL_RCC_QSPI_CLKSOURCE_PLL3R RCC_QSPICKSELR_QSPISRC_1 -#define LL_RCC_QSPI_CLKSOURCE_PLL4P RCC_QSPICKSELR_QSPISRC_2 -#define LL_RCC_QSPI_CLKSOURCE_PER RCC_QSPICKSELR_QSPISRC_3 +#define LL_RCC_QSPI_CLKSOURCE_ACLK 0U +#define LL_RCC_QSPI_CLKSOURCE_PLL3R RCC_QSPICKSELR_QSPISRC_0 +#define LL_RCC_QSPI_CLKSOURCE_PLL4P RCC_QSPICKSELR_QSPISRC_1 +#define LL_RCC_QSPI_CLKSOURCE_PER (RCC_QSPICKSELR_QSPISRC_1 | RCC_QSPICKSELR_QSPISRC_0) /** * @} */ @@ -781,10 +781,10 @@ typedef struct /** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection * @{ */ -#define LL_RCC_FMC_CLKSOURCE_ACLK RCC_FMCCKSELR_FMCSRC_0 -#define LL_RCC_FMC_CLKSOURCE_PLL3R RCC_FMCCKSELR_FMCSRC_1 -#define LL_RCC_FMC_CLKSOURCE_PLL4P RCC_FMCCKSELR_FMCSRC_2 -#define LL_RCC_FMC_CLKSOURCE_PER RCC_FMCCKSELR_FMCSRC_3 +#define LL_RCC_FMC_CLKSOURCE_ACLK 0U +#define LL_RCC_FMC_CLKSOURCE_PLL3R RCC_FMCCKSELR_FMCSRC_0 +#define LL_RCC_FMC_CLKSOURCE_PLL4P RCC_FMCCKSELR_FMCSRC_1 +#define LL_RCC_FMC_CLKSOURCE_PER (RCC_FMCCKSELR_FMCSRC_1 | RCC_FMCCKSELR_FMCSRC_0) /** * @} */ @@ -793,10 +793,10 @@ typedef struct /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection * @{ */ -#define LL_RCC_FDCAN_CLKSOURCE_HSE RCC_FDCANCKSELR_FDCANSRC_0 -#define LL_RCC_FDCAN_CLKSOURCE_PLL3Q RCC_FDCANCKSELR_FDCANSRC_1 -#define LL_RCC_FDCAN_CLKSOURCE_PLL4Q RCC_FDCANCKSELR_FDCANSRC_2 -#define LL_RCC_FDCAN_CLKSOURCE_PLL4R RCC_FDCANCKSELR_FDCANSRC_3 +#define LL_RCC_FDCAN_CLKSOURCE_HSE 0U +#define LL_RCC_FDCAN_CLKSOURCE_PLL3Q RCC_FDCANCKSELR_FDCANSRC_0 +#define LL_RCC_FDCAN_CLKSOURCE_PLL4Q RCC_FDCANCKSELR_FDCANSRC_1 +#define LL_RCC_FDCAN_CLKSOURCE_PLL4R (RCC_FDCANCKSELR_FDCANSRC_1 | RCC_FDCANCKSELR_FDCANSRC_0) /** * @} */ @@ -805,9 +805,9 @@ typedef struct /** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection * @{ */ -#define LL_RCC_SPDIFRX_CLKSOURCE_PLL4P RCC_SPDIFCKSELR_SPDIFSRC_0 -#define LL_RCC_SPDIFRX_CLKSOURCE_PLL3Q RCC_SPDIFCKSELR_SPDIFSRC_1 -#define LL_RCC_SPDIFRX_CLKSOURCE_HSI RCC_SPDIFCKSELR_SPDIFSRC_2 +#define LL_RCC_SPDIFRX_CLKSOURCE_PLL4P 0U +#define LL_RCC_SPDIFRX_CLKSOURCE_PLL3Q RCC_SPDIFCKSELR_SPDIFSRC_0 +#define LL_RCC_SPDIFRX_CLKSOURCE_HSI RCC_SPDIFCKSELR_SPDIFSRC_1 /** * @} */ @@ -815,9 +815,9 @@ typedef struct /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection * @{ */ -#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CECCKSELR_CECSRC_0 -#define LL_RCC_CEC_CLKSOURCE_LSI RCC_CECCKSELR_CECSRC_1 -#define LL_RCC_CEC_CLKSOURCE_CSI122 RCC_CECCKSELR_CECSRC_2 +#define LL_RCC_CEC_CLKSOURCE_LSE 0U +#define LL_RCC_CEC_CLKSOURCE_LSI RCC_CECCKSELR_CECSRC_0 +#define LL_RCC_CEC_CLKSOURCE_CSI122 RCC_CECCKSELR_CECSRC_1 /** * @} */ @@ -825,9 +825,9 @@ typedef struct /** @defgroup RCC_LL_EC_USBPHY_CLKSOURCE Peripheral USBPHY clock source selection * @{ */ -#define LL_RCC_USBPHY_CLKSOURCE_HSE RCC_USBCKSELR_USBPHYSRC_0 -#define LL_RCC_USBPHY_CLKSOURCE_PLL4R RCC_USBCKSELR_USBPHYSRC_1 -#define LL_RCC_USBPHY_CLKSOURCE_HSE2 RCC_USBCKSELR_USBPHYSRC_2 +#define LL_RCC_USBPHY_CLKSOURCE_HSE 0U +#define LL_RCC_USBPHY_CLKSOURCE_PLL4R RCC_USBCKSELR_USBPHYSRC_0 +#define LL_RCC_USBPHY_CLKSOURCE_HSE2 RCC_USBCKSELR_USBPHYSRC_1 /** * @} */ @@ -835,8 +835,8 @@ typedef struct /** @defgroup RCC_LL_EC_USBO_CLKSOURCE Peripheral USBO clock source selection * @{ */ -#define LL_RCC_USBO_CLKSOURCE_PLL4R RCC_USBCKSELR_USBOSRC_0 -#define LL_RCC_USBO_CLKSOURCE_PHY RCC_USBCKSELR_USBOSRC_1 +#define LL_RCC_USBO_CLKSOURCE_PLL4R 0U +#define LL_RCC_USBO_CLKSOURCE_PHY RCC_USBCKSELR_USBOSRC /** * @} */ @@ -844,15 +844,15 @@ typedef struct /** @defgroup RCC_LL_EC_RNGx_CLKSOURCE Peripheral RNG clock source selection * @{ */ -#define LL_RCC_RNG1_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_0) -#define LL_RCC_RNG1_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_1) -#define LL_RCC_RNG1_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_2) -#define LL_RCC_RNG1_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_3) +#define LL_RCC_RNG1_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, 0) +#define LL_RCC_RNG1_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_0) +#define LL_RCC_RNG1_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_1) +#define LL_RCC_RNG1_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, (RCC_RNG1CKSELR_RNG1SRC_1 | RCC_RNG1CKSELR_RNG1SRC_0)) -#define LL_RCC_RNG2_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_0) -#define LL_RCC_RNG2_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_1) -#define LL_RCC_RNG2_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_2) -#define LL_RCC_RNG2_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_3) +#define LL_RCC_RNG2_CLKSOURCE_CSI LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, 0) +#define LL_RCC_RNG2_CLKSOURCE_PLL4R LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_0) +#define LL_RCC_RNG2_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_1) +#define LL_RCC_RNG2_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, (RCC_RNG2CKSELR_RNG2SRC_1 | RCC_RNG2CKSELR_RNG2SRC_0)) /** * @} */ @@ -860,10 +860,10 @@ typedef struct /** @defgroup RCC_LL_EC_CKPER_CLKSOURCE Peripheral CKPER clock source selection * @{ */ -#define LL_RCC_CKPER_CLKSOURCE_HSI RCC_CPERCKSELR_CKPERSRC_0 -#define LL_RCC_CKPER_CLKSOURCE_CSI RCC_CPERCKSELR_CKPERSRC_1 -#define LL_RCC_CKPER_CLKSOURCE_HSE RCC_CPERCKSELR_CKPERSRC_2 -#define LL_RCC_CKPER_CLKSOURCE_OFF RCC_CPERCKSELR_CKPERSRC_3 /*Clock disabled*/ +#define LL_RCC_CKPER_CLKSOURCE_HSI 0U +#define LL_RCC_CKPER_CLKSOURCE_CSI RCC_CPERCKSELR_CKPERSRC_0 +#define LL_RCC_CKPER_CLKSOURCE_HSE RCC_CPERCKSELR_CKPERSRC_1 +#define LL_RCC_CKPER_CLKSOURCE_OFF (RCC_CPERCKSELR_CKPERSRC_1 | RCC_CPERCKSELR_CKPERSRC_0) /*Clock disabled*/ /** * @} */ @@ -871,9 +871,9 @@ typedef struct /** @defgroup RCC_LL_EC_STGEN_CLKSOURCE Peripheral STGEN clock source selection * @{ */ -#define LL_RCC_STGEN_CLKSOURCE_HSI RCC_STGENCKSELR_STGENSRC_0 -#define LL_RCC_STGEN_CLKSOURCE_HSE RCC_STGENCKSELR_STGENSRC_1 -#define LL_RCC_STGEN_CLKSOURCE_OFF RCC_STGENCKSELR_STGENSRC_2 +#define LL_RCC_STGEN_CLKSOURCE_HSI 0U +#define LL_RCC_STGEN_CLKSOURCE_HSE RCC_STGENCKSELR_STGENSRC_0 +#define LL_RCC_STGEN_CLKSOURCE_OFF RCC_STGENCKSELR_STGENSRC_1 /** * @} */ @@ -882,8 +882,8 @@ typedef struct /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection * @{ */ -#define LL_RCC_DSI_CLKSOURCE_PHY RCC_DSICKSELR_DSISRC_0 -#define LL_RCC_DSI_CLKSOURCE_PLL4P RCC_DSICKSELR_DSISRC_1 +#define LL_RCC_DSI_CLKSOURCE_PHY 0U +#define LL_RCC_DSI_CLKSOURCE_PLL4P RCC_DSICKSELR_DSISRC /** * @} */ @@ -892,9 +892,9 @@ typedef struct /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection * @{ */ -#define LL_RCC_ADC_CLKSOURCE_PLL4R RCC_ADCCKSELR_ADCSRC_0 -#define LL_RCC_ADC_CLKSOURCE_PER RCC_ADCCKSELR_ADCSRC_1 -#define LL_RCC_ADC_CLKSOURCE_PLL3Q RCC_ADCCKSELR_ADCSRC_2 +#define LL_RCC_ADC_CLKSOURCE_PLL4R 0U +#define LL_RCC_ADC_CLKSOURCE_PER RCC_ADCCKSELR_ADCSRC_0 +#define LL_RCC_ADC_CLKSOURCE_PLL3Q RCC_ADCCKSELR_ADCSRC_1 /** * @} */ @@ -902,28 +902,28 @@ typedef struct /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection * @{ */ -#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_0) -#define LL_RCC_LPTIM1_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_1) -#define LL_RCC_LPTIM1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_2) -#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_3) -#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_4) -#define LL_RCC_LPTIM1_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_5) -#define LL_RCC_LPTIM1_CLKSOURCE_OFF LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_6) - -#define LL_RCC_LPTIM23_CLKSOURCE_PCLK3 LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_0) -#define LL_RCC_LPTIM23_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_1) -#define LL_RCC_LPTIM23_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_2) -#define LL_RCC_LPTIM23_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_3) -#define LL_RCC_LPTIM23_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_4) -#define LL_RCC_LPTIM23_CLKSOURCE_OFF LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_5) - -#define LL_RCC_LPTIM45_CLKSOURCE_PCLK3 LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_0) -#define LL_RCC_LPTIM45_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_1) -#define LL_RCC_LPTIM45_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_2) -#define LL_RCC_LPTIM45_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_3) -#define LL_RCC_LPTIM45_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_4) -#define LL_RCC_LPTIM45_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_5) -#define LL_RCC_LPTIM45_CLKSOURCE_OFF LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_6) +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, 0) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_0) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (RCC_LPTIM1CKSELR_LPTIM1SRC_1 | RCC_LPTIM1CKSELR_LPTIM1SRC_0)) +#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_2) +#define LL_RCC_LPTIM1_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_0)) +#define LL_RCC_LPTIM1_CLKSOURCE_OFF LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_1)) + +#define LL_RCC_LPTIM23_CLKSOURCE_PCLK3 LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, 0) +#define LL_RCC_LPTIM23_CLKSOURCE_PLL4Q LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_0) +#define LL_RCC_LPTIM23_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_1) +#define LL_RCC_LPTIM23_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, (RCC_LPTIM23CKSELR_LPTIM23SRC_1 | RCC_LPTIM23CKSELR_LPTIM23SRC_0)) +#define LL_RCC_LPTIM23_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_2) +#define LL_RCC_LPTIM23_CLKSOURCE_OFF LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, (RCC_LPTIM23CKSELR_LPTIM23SRC_2 | RCC_LPTIM23CKSELR_LPTIM23SRC_0)) + +#define LL_RCC_LPTIM45_CLKSOURCE_PCLK3 LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, 0) +#define LL_RCC_LPTIM45_CLKSOURCE_PLL4P LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_0) +#define LL_RCC_LPTIM45_CLKSOURCE_PLL3Q LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_1) +#define LL_RCC_LPTIM45_CLKSOURCE_LSE LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (RCC_LPTIM45CKSELR_LPTIM45SRC_1 | RCC_LPTIM45CKSELR_LPTIM45SRC_0)) +#define LL_RCC_LPTIM45_CLKSOURCE_LSI LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_2) +#define LL_RCC_LPTIM45_CLKSOURCE_PER LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_0)) +#define LL_RCC_LPTIM45_CLKSOURCE_OFF LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_1)) /** * @} */ @@ -931,11 +931,11 @@ typedef struct /** @defgroup RCC_LL_EC_TIMGx_Prescaler_Selection TIMG Prescaler selection * @{ */ -#define LL_RCC_TIMG1PRES_DEACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, RCC_TIMG1PRER_TIMG1PRE_0) -#define LL_RCC_TIMG1PRES_ACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, RCC_TIMG1PRER_TIMG1PRE_1) +#define LL_RCC_TIMG1PRES_DEACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, 0) +#define LL_RCC_TIMG1PRES_ACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, RCC_TIMG1PRER_TIMG1PRE) -#define LL_RCC_TIMG2PRES_DEACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, RCC_TIMG2PRER_TIMG2PRE_0) -#define LL_RCC_TIMG2PRES_ACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, RCC_TIMG2PRER_TIMG2PRE_1) +#define LL_RCC_TIMG2PRES_DEACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, 0) +#define LL_RCC_TIMG2PRES_ACTIVATED LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, RCC_TIMG2PRER_TIMG2PRE) /** * @} */ @@ -943,10 +943,10 @@ typedef struct /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection * @{ */ -#define LL_RCC_RTC_CLKSOURCE_NONE RCC_BDCR_RTCSRC_0 /*!< No clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSRC_1 /*!< LSE oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSRC_2 /*!< LSI oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_HSE_DIV RCC_BDCR_RTCSRC_3 /*!< HSE oscillator clock divided by RTCDIV used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSRC_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSRC_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV (RCC_BDCR_RTCSRC_1 | RCC_BDCR_RTCSRC_0) /*!< HSE oscillator clock divided by RTCDIV used as RTC clock */ /** * @} */ @@ -1144,9 +1144,9 @@ typedef struct /** @defgroup RCC_LL_EC_PLL12SOURCE PLL1 and PLL2 entry clock source * @{ */ -#define LL_RCC_PLL12SOURCE_HSI RCC_RCK12SELR_PLL12SRC_0 /*!< HSI clock selected as PLL12 entry clock source */ -#define LL_RCC_PLL12SOURCE_HSE RCC_RCK12SELR_PLL12SRC_1 /*!< HSE clock selected as PLL12 entry clock source */ -#define LL_RCC_PLL12SOURCE_NONE RCC_RCK12SELR_PLL12SRC_2 /*!< No clock */ +#define LL_RCC_PLL12SOURCE_HSI 0U /*!< HSI clock selected as PLL12 entry clock source */ +#define LL_RCC_PLL12SOURCE_HSE RCC_RCK12SELR_PLL12SRC_0 /*!< HSE clock selected as PLL12 entry clock source */ +#define LL_RCC_PLL12SOURCE_NONE RCC_RCK12SELR_PLL12SRC_1 /*!< No clock */ /** * @} */ @@ -1154,10 +1154,10 @@ typedef struct /** @defgroup RCC_LL_EC_PLL3SOURCE PLL3 entry clock source * @{ */ -#define LL_RCC_PLL3SOURCE_HSI RCC_RCK3SELR_PLL3SRC_0 /*!< HSI clock selected as PLL3 entry clock source */ -#define LL_RCC_PLL3SOURCE_HSE RCC_RCK3SELR_PLL3SRC_1 /*!< HSE clock selected as PLL3 entry clock source */ -#define LL_RCC_PLL3SOURCE_CSI RCC_RCK3SELR_PLL3SRC_2 /*!< CSI clock selected as PLL3 entry clock source */ -#define LL_RCC_PLL3SOURCE_NONE RCC_RCK3SELR_PLL3SRC_3 /*!< No clock */ +#define LL_RCC_PLL3SOURCE_HSI 0U /*!< HSI clock selected as PLL3 entry clock source */ +#define LL_RCC_PLL3SOURCE_HSE RCC_RCK3SELR_PLL3SRC_0 /*!< HSE clock selected as PLL3 entry clock source */ +#define LL_RCC_PLL3SOURCE_CSI RCC_RCK3SELR_PLL3SRC_1 /*!< CSI clock selected as PLL3 entry clock source */ +#define LL_RCC_PLL3SOURCE_NONE (RCC_RCK3SELR_PLL3SRC_1 | RCC_RCK3SELR_PLL3SRC_0) /*!< No clock */ /** * @} */ @@ -1165,10 +1165,10 @@ typedef struct /** @defgroup RCC_LL_EC_PLL4SOURCE PLL4 entry clock source * @{ */ -#define LL_RCC_PLL4SOURCE_HSI RCC_RCK4SELR_PLL4SRC_0 /*!< HSI clock selected as PLL4 entry clock source */ -#define LL_RCC_PLL4SOURCE_HSE RCC_RCK4SELR_PLL4SRC_1 /*!< HSE clock selected as PLL4 entry clock source */ -#define LL_RCC_PLL4SOURCE_CSI RCC_RCK4SELR_PLL4SRC_2 /*!< CSI clock selected as PLL4 entry clock source */ -#define LL_RCC_PLL4SOURCE_I2SCKIN RCC_RCK4SELR_PLL4SRC_3 /*!< Signal I2S_CKIN selected as PLL4 entry clock source */ +#define LL_RCC_PLL4SOURCE_HSI 0U /*!< HSI clock selected as PLL4 entry clock source */ +#define LL_RCC_PLL4SOURCE_HSE RCC_RCK4SELR_PLL4SRC_0 /*!< HSE clock selected as PLL4 entry clock source */ +#define LL_RCC_PLL4SOURCE_CSI RCC_RCK4SELR_PLL4SRC_1 /*!< CSI clock selected as PLL4 entry clock source */ +#define LL_RCC_PLL4SOURCE_I2SCKIN (RCC_RCK4SELR_PLL4SRC_1 | RCC_RCK4SELR_PLL4SRC_0) /*!< Signal I2S_CKIN selected as PLL4 entry clock source */ /** * @} */ diff --git a/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html index 4e497c8196..c7f20aa978 100644 --- a/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32MP1xx_HAL_Driver/Release_Notes.html @@ -174,10 +174,10 @@

Purpose

-

V1.2.0 / 03-Feb-2020

+

V1.3.0 / 20-Oct-2020

-

Main changes :

  • General updates to fix known defects and enhancements implementation
  • Major update of drivers for STM32MP15xx devices:
    • ADC:
        • Update HAL_ADC_Start_DMA() API to enable DMA mode
        • LL : new function to add or remove paths.
          • LL_ADC_SetCommonPathInternalChAdd and LL_ADC_SetCommonPathInternalChAdd : New API
    • CORTEX:
      • Implement LL Driver
    • FMC:
      • Implement PSRAM Driver: New API
    • GENERIC:
      • Add EXTERNAL_CLOCK_VALUE in conf_template file.
    • RTC:
      • HAL&LL : Implement RTC Driver (including TAMP) : New API
    • TIM:
        • HAL&LL: Remove reference to COMP1 and COMP2
        • LL: 
          • Fix TIM Break source definition
          • RepetitionCounter value depends on GP or Advanced tmers
    • UART:
      • HAL: Alignment with  STM32F0/F3/H7 (for inter STM32 families portability)
        • some API's change to take in consideration
    • UTILS:
      • LL: Add new Part Number defines related to LL_GetDevicePartNumber()

Supported Devices and boards

+

Main changes :

  • General updates to fix known defects and enhancements implementation
  • Major update of drivers for STM32MP15xx devices:
    • ADC: No API change
        • Typo corrections in HAL & LL drivers
        • LL - assert_param should check constraint between modes continuous and discontinuous
        • HAL - Fix IRQ handler in case of injected conversion + IT mode + trigger timer
    • CRYP:
      • Support several call to decrypt API without initialize Key and IVR:
        • Add init parameters KeyIVConfigSkip : CRYP_KEYIVCONFIG_ONCE or CRYP_KEYIVCONFIG_ALWAYS
        • Add SizesSum & KeyIVConfig in handle
    • DFSDM: No API change
        • MISRA update
        • rework "Callback registration" section
    • EXTI: No API change
        • Define missing EXTI_REG3
    • GENERIC: No API change
      • HAL configuration file : add SMARTCARD and SRAM in template file
    • RCC: No API change
        • Important define update to be compliant with Header file update ( CMSIS device)
        • LL - Fix compilation issue ( to be compliant with Header file update on CMSIS device)
    • SAI: 
        • HAL: Alignment for inter STM32 families portability.
          • some API's change to take in consideration
    • SDMMC: No API change
      • HAL - Fix loop increment in SD_HighSpeed and SD_UltraHighSpeed function
    • SMARTCARD: 
        • HAL: Implement SMARTCARD Driver: New API
        • HAL - rename UART_FIFOMODE_ENABLE into SMARTCARD_FIFOMODE_ENABLE

Supported Devices and boards

  • STM32MP157C-EV1  revC
  • STM32MP157C-DK2  revC

    •  @@ -190,11 +190,14 @@

    Main changes :