diff --git a/cores/arduino/stm32/usb/usbd_conf.c b/cores/arduino/stm32/usb/usbd_conf.c index 109f2f56f5..6040c5dede 100644 --- a/cores/arduino/stm32/usb/usbd_conf.c +++ b/cores/arduino/stm32/usb/usbd_conf.c @@ -465,7 +465,15 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) USBD_reenumerate(); /* Set common LL Driver parameters */ g_hpcd.Init.dev_endpoints = DEV_NUM_EP; +#ifdef DEP0CTL_MPS_64 g_hpcd.Init.ep0_mps = DEP0CTL_MPS_64; +#else +#ifdef EP_MPS_64 + g_hpcd.Init.ep0_mps = EP_MPS_64; +#else +#error "Missing EP0 MPS definition: DEP0CTL_MPS_64 or EP_MPS_64!" +#endif +#endif #if !defined(STM32F1xx) && !defined(STM32F2xx) || defined(USB) g_hpcd.Init.lpm_enable = DISABLE; g_hpcd.Init.battery_charging_enable = DISABLE; diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h index 24b71a35b3..8fbdf4a298 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -2251,6 +2251,14 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[6:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ +#define CRS_CR_TRIM_6 (0x40UL << CRS_CR_TRIM_Pos) /*!< 0x00004000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l422xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l422xx.h index 3f66bee675..7bf419a518 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l422xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l422xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -2286,6 +2286,14 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[6:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ +#define CRS_CR_TRIM_6 (0x40UL << CRS_CR_TRIM_Pos) /*!< 0x00004000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h index 06d4a03ac7..65102d27cd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -5722,6 +5722,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -9270,13 +9277,15 @@ typedef struct /*!< HSITRIM configuration */ #define RCC_ICSCR_HSITRIM_Pos (24U) -#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */ -#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */ +#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */ +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */ #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */ #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */ #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */ #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */ +#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */ /******************** Bit definition for RCC_CFGR register ******************/ /*!< SW configuration */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h index dfb9f6f99c..3c455ff490 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -5707,6 +5707,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -8931,13 +8938,15 @@ typedef struct /*!< HSITRIM configuration */ #define RCC_ICSCR_HSITRIM_Pos (24U) -#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */ -#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */ +#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */ +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */ #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */ #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */ #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */ #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */ +#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */ /******************** Bit definition for RCC_CFGR register ******************/ /*!< SW configuration */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h index 458c242fc6..60bb2f87bb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -5781,6 +5781,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -9362,13 +9369,15 @@ typedef struct /*!< HSITRIM configuration */ #define RCC_ICSCR_HSITRIM_Pos (24U) -#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */ -#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */ +#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */ +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */ #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */ #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */ #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */ #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */ +#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */ /******************** Bit definition for RCC_CFGR register ******************/ /*!< SW configuration */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h index fee55f7b7a..d3475ed766 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -5742,6 +5742,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -9147,13 +9154,15 @@ typedef struct /*!< HSITRIM configuration */ #define RCC_ICSCR_HSITRIM_Pos (24U) -#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */ -#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */ +#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */ +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */ #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */ #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */ #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */ #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */ +#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */ /******************** Bit definition for RCC_CFGR register ******************/ /*!< SW configuration */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l443xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l443xx.h index f05605be2f..5d782d2205 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l443xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l443xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -5816,6 +5816,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -9578,13 +9585,15 @@ typedef struct /*!< HSITRIM configuration */ #define RCC_ICSCR_HSITRIM_Pos (24U) -#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */ -#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */ +#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */ +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */ #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */ #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */ #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */ #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */ +#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */ /******************** Bit definition for RCC_CFGR register ******************/ /*!< SW configuration */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l451xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l451xx.h index f011a1d1d5..9a26b04fe5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l451xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l451xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -5772,6 +5772,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l452xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l452xx.h index a5c2e0d28f..38e64b0907 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l452xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l452xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -5814,6 +5814,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l462xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l462xx.h index f083925847..1f5e86c12d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l462xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l462xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -5849,6 +5849,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l471xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l471xx.h index ba028e6aeb..8347a8ea09 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l471xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l471xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h index 142e91cc1e..09a3ca2bf3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l475xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h index 4fd882959a..61341a7f0d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l485xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l485xx.h index 56ef4dfb79..1bc37e586f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l485xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l485xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l486xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l486xx.h index 8f8e382d87..172b2608ba 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l486xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l486xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h index 877cb1639b..ba26b78fcd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -6265,6 +6265,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h index 89ccca657c..ee4a05903a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -6329,6 +6329,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4p5xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4p5xx.h index c1d7d59483..49a0f6e8e5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4p5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4p5xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -6474,6 +6474,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -12412,9 +12419,11 @@ typedef struct #define RCC_HSI48_SUPPORT #define RCC_PLLM_DIV_1_16_SUPPORT #define RCC_PLLP_DIV_2_31_SUPPORT +#define RCC_PLLSAI1N_MUL_8_127_SUPPORT #define RCC_PLLSAI1M_DIV_1_16_SUPPORT #define RCC_PLLSAI1P_DIV_2_31_SUPPORT #define RCC_PLLSAI2_SUPPORT +#define RCC_PLLSAI2N_MUL_8_127_SUPPORT #define RCC_PLLSAI2M_DIV_1_16_SUPPORT #define RCC_PLLSAI2P_DIV_2_31_SUPPORT #define RCC_PLLSAI2Q_DIV_SUPPORT @@ -15773,11 +15782,11 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ -#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Pos (3U) #define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ #define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) -#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */ +#define OCTOSPI_DCR1_CSHT_Msk (0x3FUL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00003F00 */ #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */ #define OCTOSPI_DCR1_DEVSIZE_Pos (16U) #define OCTOSPI_DCR1_DEVSIZE_Msk (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos) /*!< 0x001F0000 */ @@ -15793,12 +15802,6 @@ typedef struct #define OCTOSPI_DCR2_PRESCALER_Pos (0U) #define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */ #define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */ -#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U) -#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */ -#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */ -#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */ -#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */ -#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for OCTOSPI_DCR3 register ******************/ #define OCTOSPI_DCR3_MAXTRAN_Pos (0U) @@ -15846,8 +15849,8 @@ typedef struct #define OCTOSPI_FCR_CSMF_Pos (3U) #define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */ #define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */ -#define OCTOSPI_FCR_TOF_Pos (8U) -#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000100 */ +#define OCTOSPI_FCR_TOF_Pos (4U) +#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000010 */ #define OCTOSPI_FCR_TOF OCTOSPI_FCR_TOF_Msk /*!< Clear Timeout Flag */ /**************** Bit definition for OCTOSPI_DLR register *******************/ @@ -16020,9 +16023,6 @@ typedef struct #define OCTOSPI_WCCR_DQSE_Pos (29U) #define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */ #define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */ -#define OCTOSPI_WCCR_SIOO_Pos (31U) -#define OCTOSPI_WCCR_SIOO_Msk (0x1UL << OCTOSPI_WCCR_SIOO_Pos) /*!< 0x80000000 */ -#define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */ /**************** Bit definition for OCTOSPI_WTCR register ******************/ #define OCTOSPI_WTCR_DCYC_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4q5xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4q5xx.h index 3c60a8c3ac..11fbc9a060 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4q5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4q5xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -6526,6 +6526,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -12905,9 +12912,11 @@ typedef struct #define RCC_HSI48_SUPPORT #define RCC_PLLM_DIV_1_16_SUPPORT #define RCC_PLLP_DIV_2_31_SUPPORT +#define RCC_PLLSAI1N_MUL_8_127_SUPPORT #define RCC_PLLSAI1M_DIV_1_16_SUPPORT #define RCC_PLLSAI1P_DIV_2_31_SUPPORT #define RCC_PLLSAI2_SUPPORT +#define RCC_PLLSAI2N_MUL_8_127_SUPPORT #define RCC_PLLSAI2M_DIV_1_16_SUPPORT #define RCC_PLLSAI2P_DIV_2_31_SUPPORT #define RCC_PLLSAI2Q_DIV_SUPPORT @@ -16284,11 +16293,11 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ -#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Pos (3U) #define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ #define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) -#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */ +#define OCTOSPI_DCR1_CSHT_Msk (0x3FUL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00003F00 */ #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */ #define OCTOSPI_DCR1_DEVSIZE_Pos (16U) #define OCTOSPI_DCR1_DEVSIZE_Msk (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos) /*!< 0x001F0000 */ @@ -16304,12 +16313,6 @@ typedef struct #define OCTOSPI_DCR2_PRESCALER_Pos (0U) #define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */ #define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */ -#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U) -#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */ -#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */ -#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */ -#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */ -#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for OCTOSPI_DCR3 register ******************/ #define OCTOSPI_DCR3_MAXTRAN_Pos (0U) @@ -16357,8 +16360,8 @@ typedef struct #define OCTOSPI_FCR_CSMF_Pos (3U) #define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */ #define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */ -#define OCTOSPI_FCR_TOF_Pos (8U) -#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000100 */ +#define OCTOSPI_FCR_TOF_Pos (4U) +#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000010 */ #define OCTOSPI_FCR_TOF OCTOSPI_FCR_TOF_Msk /*!< Clear Timeout Flag */ /**************** Bit definition for OCTOSPI_DLR register *******************/ @@ -16531,9 +16534,6 @@ typedef struct #define OCTOSPI_WCCR_DQSE_Pos (29U) #define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */ #define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */ -#define OCTOSPI_WCCR_SIOO_Pos (31U) -#define OCTOSPI_WCCR_SIOO_Msk (0x1UL << OCTOSPI_WCCR_SIOO_Pos) /*!< 0x80000000 */ -#define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */ /**************** Bit definition for OCTOSPI_WTCR register ******************/ #define OCTOSPI_WTCR_DCYC_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h index b85460afb9..cd0528e436 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -6191,6 +6191,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -11629,9 +11636,11 @@ typedef struct #define RCC_HSI48_SUPPORT #define RCC_PLLM_DIV_1_16_SUPPORT #define RCC_PLLP_DIV_2_31_SUPPORT +#define RCC_PLLSAI1N_MUL_8_127_SUPPORT #define RCC_PLLSAI1M_DIV_1_16_SUPPORT #define RCC_PLLSAI1P_DIV_2_31_SUPPORT #define RCC_PLLSAI2_SUPPORT +#define RCC_PLLSAI2N_MUL_8_127_SUPPORT #define RCC_PLLSAI2M_DIV_1_16_SUPPORT #define RCC_PLLSAI2P_DIV_2_31_SUPPORT #define RCC_PLLSAI2Q_DIV_SUPPORT @@ -14791,7 +14800,7 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ -#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Pos (3U) #define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ #define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) @@ -14811,12 +14820,6 @@ typedef struct #define OCTOSPI_DCR2_PRESCALER_Pos (0U) #define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */ #define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */ -#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U) -#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */ -#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */ -#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */ -#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */ -#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for OCTOSPI_DCR3 register ******************/ #define OCTOSPI_DCR3_CSBOUND_Pos (16U) @@ -14856,8 +14859,8 @@ typedef struct #define OCTOSPI_FCR_CSMF_Pos (3U) #define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */ #define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */ -#define OCTOSPI_FCR_TOF_Pos (8U) -#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000100 */ +#define OCTOSPI_FCR_TOF_Pos (4U) +#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000010 */ #define OCTOSPI_FCR_TOF OCTOSPI_FCR_TOF_Msk /*!< Clear Timeout Flag */ /**************** Bit definition for OCTOSPI_DLR register *******************/ @@ -15030,9 +15033,6 @@ typedef struct #define OCTOSPI_WCCR_DQSE_Pos (29U) #define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */ #define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */ -#define OCTOSPI_WCCR_SIOO_Pos (31U) -#define OCTOSPI_WCCR_SIOO_Msk (0x1UL << OCTOSPI_WCCR_SIOO_Pos) /*!< 0x80000000 */ -#define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */ /**************** Bit definition for OCTOSPI_WTCR register ******************/ #define OCTOSPI_WTCR_DCYC_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r7xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r7xx.h index dce37da112..9980337848 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r7xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -6277,6 +6277,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -12110,9 +12117,11 @@ typedef struct #define RCC_HSI48_SUPPORT #define RCC_PLLM_DIV_1_16_SUPPORT #define RCC_PLLP_DIV_2_31_SUPPORT +#define RCC_PLLSAI1N_MUL_8_127_SUPPORT #define RCC_PLLSAI1M_DIV_1_16_SUPPORT #define RCC_PLLSAI1P_DIV_2_31_SUPPORT #define RCC_PLLSAI2_SUPPORT +#define RCC_PLLSAI2N_MUL_8_127_SUPPORT #define RCC_PLLSAI2M_DIV_1_16_SUPPORT #define RCC_PLLSAI2P_DIV_2_31_SUPPORT #define RCC_PLLSAI2Q_DIV_SUPPORT @@ -15290,7 +15299,7 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ -#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Pos (3U) #define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ #define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) @@ -15310,12 +15319,6 @@ typedef struct #define OCTOSPI_DCR2_PRESCALER_Pos (0U) #define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */ #define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */ -#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U) -#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */ -#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */ -#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */ -#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */ -#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for OCTOSPI_DCR3 register ******************/ #define OCTOSPI_DCR3_CSBOUND_Pos (16U) @@ -15355,8 +15358,8 @@ typedef struct #define OCTOSPI_FCR_CSMF_Pos (3U) #define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */ #define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */ -#define OCTOSPI_FCR_TOF_Pos (8U) -#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000100 */ +#define OCTOSPI_FCR_TOF_Pos (4U) +#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000010 */ #define OCTOSPI_FCR_TOF OCTOSPI_FCR_TOF_Msk /*!< Clear Timeout Flag */ /**************** Bit definition for OCTOSPI_DLR register *******************/ @@ -15529,9 +15532,6 @@ typedef struct #define OCTOSPI_WCCR_DQSE_Pos (29U) #define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */ #define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */ -#define OCTOSPI_WCCR_SIOO_Pos (31U) -#define OCTOSPI_WCCR_SIOO_Msk (0x1UL << OCTOSPI_WCCR_SIOO_Pos) /*!< 0x80000000 */ -#define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */ /**************** Bit definition for OCTOSPI_WTCR register ******************/ #define OCTOSPI_WTCR_DCYC_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h index 1ecad70cc1..d7f4b02a13 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -6359,6 +6359,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -15229,9 +15236,11 @@ typedef struct #define RCC_HSI48_SUPPORT #define RCC_PLLM_DIV_1_16_SUPPORT #define RCC_PLLP_DIV_2_31_SUPPORT +#define RCC_PLLSAI1N_MUL_8_127_SUPPORT #define RCC_PLLSAI1M_DIV_1_16_SUPPORT #define RCC_PLLSAI1P_DIV_2_31_SUPPORT #define RCC_PLLSAI2_SUPPORT +#define RCC_PLLSAI2N_MUL_8_127_SUPPORT #define RCC_PLLSAI2M_DIV_1_16_SUPPORT #define RCC_PLLSAI2P_DIV_2_31_SUPPORT #define RCC_PLLSAI2Q_DIV_SUPPORT @@ -18422,7 +18431,7 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ -#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Pos (3U) #define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ #define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) @@ -18442,12 +18451,6 @@ typedef struct #define OCTOSPI_DCR2_PRESCALER_Pos (0U) #define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */ #define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */ -#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U) -#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */ -#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */ -#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */ -#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */ -#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for OCTOSPI_DCR3 register ******************/ #define OCTOSPI_DCR3_CSBOUND_Pos (16U) @@ -18487,8 +18490,8 @@ typedef struct #define OCTOSPI_FCR_CSMF_Pos (3U) #define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */ #define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */ -#define OCTOSPI_FCR_TOF_Pos (8U) -#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000100 */ +#define OCTOSPI_FCR_TOF_Pos (4U) +#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000010 */ #define OCTOSPI_FCR_TOF OCTOSPI_FCR_TOF_Msk /*!< Clear Timeout Flag */ /**************** Bit definition for OCTOSPI_DLR register *******************/ @@ -18661,9 +18664,6 @@ typedef struct #define OCTOSPI_WCCR_DQSE_Pos (29U) #define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */ #define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */ -#define OCTOSPI_WCCR_SIOO_Pos (31U) -#define OCTOSPI_WCCR_SIOO_Msk (0x1UL << OCTOSPI_WCCR_SIOO_Pos) /*!< 0x80000000 */ -#define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */ /**************** Bit definition for OCTOSPI_WTCR register ******************/ #define OCTOSPI_WTCR_DCYC_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s5xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s5xx.h index 52391e14de..ce71ac829f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s5xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -6255,6 +6255,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -11958,9 +11965,11 @@ typedef struct #define RCC_HSI48_SUPPORT #define RCC_PLLM_DIV_1_16_SUPPORT #define RCC_PLLP_DIV_2_31_SUPPORT +#define RCC_PLLSAI1N_MUL_8_127_SUPPORT #define RCC_PLLSAI1M_DIV_1_16_SUPPORT #define RCC_PLLSAI1P_DIV_2_31_SUPPORT #define RCC_PLLSAI2_SUPPORT +#define RCC_PLLSAI2N_MUL_8_127_SUPPORT #define RCC_PLLSAI2M_DIV_1_16_SUPPORT #define RCC_PLLSAI2P_DIV_2_31_SUPPORT #define RCC_PLLSAI2Q_DIV_SUPPORT @@ -15138,7 +15147,7 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ -#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Pos (3U) #define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ #define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) @@ -15158,12 +15167,6 @@ typedef struct #define OCTOSPI_DCR2_PRESCALER_Pos (0U) #define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */ #define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */ -#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U) -#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */ -#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */ -#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */ -#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */ -#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for OCTOSPI_DCR3 register ******************/ #define OCTOSPI_DCR3_CSBOUND_Pos (16U) @@ -15203,8 +15206,8 @@ typedef struct #define OCTOSPI_FCR_CSMF_Pos (3U) #define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */ #define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */ -#define OCTOSPI_FCR_TOF_Pos (8U) -#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000100 */ +#define OCTOSPI_FCR_TOF_Pos (4U) +#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000010 */ #define OCTOSPI_FCR_TOF OCTOSPI_FCR_TOF_Msk /*!< Clear Timeout Flag */ /**************** Bit definition for OCTOSPI_DLR register *******************/ @@ -15377,9 +15380,6 @@ typedef struct #define OCTOSPI_WCCR_DQSE_Pos (29U) #define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */ #define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */ -#define OCTOSPI_WCCR_SIOO_Pos (31U) -#define OCTOSPI_WCCR_SIOO_Msk (0x1UL << OCTOSPI_WCCR_SIOO_Pos) /*!< 0x80000000 */ -#define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */ /**************** Bit definition for OCTOSPI_WTCR register ******************/ #define OCTOSPI_WTCR_DCYC_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s7xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s7xx.h index 8640468a79..f03a528b84 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s7xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -6341,6 +6341,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -12439,9 +12446,11 @@ typedef struct #define RCC_HSI48_SUPPORT #define RCC_PLLM_DIV_1_16_SUPPORT #define RCC_PLLP_DIV_2_31_SUPPORT +#define RCC_PLLSAI1N_MUL_8_127_SUPPORT #define RCC_PLLSAI1M_DIV_1_16_SUPPORT #define RCC_PLLSAI1P_DIV_2_31_SUPPORT #define RCC_PLLSAI2_SUPPORT +#define RCC_PLLSAI2N_MUL_8_127_SUPPORT #define RCC_PLLSAI2M_DIV_1_16_SUPPORT #define RCC_PLLSAI2P_DIV_2_31_SUPPORT #define RCC_PLLSAI2Q_DIV_SUPPORT @@ -15637,7 +15646,7 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ -#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Pos (3U) #define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ #define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) @@ -15657,12 +15666,6 @@ typedef struct #define OCTOSPI_DCR2_PRESCALER_Pos (0U) #define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */ #define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */ -#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U) -#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */ -#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */ -#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */ -#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */ -#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for OCTOSPI_DCR3 register ******************/ #define OCTOSPI_DCR3_CSBOUND_Pos (16U) @@ -15702,8 +15705,8 @@ typedef struct #define OCTOSPI_FCR_CSMF_Pos (3U) #define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */ #define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */ -#define OCTOSPI_FCR_TOF_Pos (8U) -#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000100 */ +#define OCTOSPI_FCR_TOF_Pos (4U) +#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000010 */ #define OCTOSPI_FCR_TOF OCTOSPI_FCR_TOF_Msk /*!< Clear Timeout Flag */ /**************** Bit definition for OCTOSPI_DLR register *******************/ @@ -15876,9 +15879,6 @@ typedef struct #define OCTOSPI_WCCR_DQSE_Pos (29U) #define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */ #define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */ -#define OCTOSPI_WCCR_SIOO_Pos (31U) -#define OCTOSPI_WCCR_SIOO_Msk (0x1UL << OCTOSPI_WCCR_SIOO_Pos) /*!< 0x80000000 */ -#define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */ /**************** Bit definition for OCTOSPI_WTCR register ******************/ #define OCTOSPI_WTCR_DCYC_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s9xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s9xx.h index cbcfabe9af..9160a0f48b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s9xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s9xx.h @@ -15,10 +15,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -6423,6 +6423,13 @@ typedef struct #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */ +#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */ +#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */ +#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */ +#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */ +#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ @@ -15558,9 +15565,11 @@ typedef struct #define RCC_HSI48_SUPPORT #define RCC_PLLM_DIV_1_16_SUPPORT #define RCC_PLLP_DIV_2_31_SUPPORT +#define RCC_PLLSAI1N_MUL_8_127_SUPPORT #define RCC_PLLSAI1M_DIV_1_16_SUPPORT #define RCC_PLLSAI1P_DIV_2_31_SUPPORT #define RCC_PLLSAI2_SUPPORT +#define RCC_PLLSAI2N_MUL_8_127_SUPPORT #define RCC_PLLSAI2M_DIV_1_16_SUPPORT #define RCC_PLLSAI2P_DIV_2_31_SUPPORT #define RCC_PLLSAI2Q_DIV_SUPPORT @@ -18769,7 +18778,7 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ -#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Pos (3U) #define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ #define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) @@ -18789,12 +18798,6 @@ typedef struct #define OCTOSPI_DCR2_PRESCALER_Pos (0U) #define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */ #define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */ -#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U) -#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */ -#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */ -#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */ -#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */ -#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for OCTOSPI_DCR3 register ******************/ #define OCTOSPI_DCR3_CSBOUND_Pos (16U) @@ -18834,8 +18837,8 @@ typedef struct #define OCTOSPI_FCR_CSMF_Pos (3U) #define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */ #define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */ -#define OCTOSPI_FCR_TOF_Pos (8U) -#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000100 */ +#define OCTOSPI_FCR_TOF_Pos (4U) +#define OCTOSPI_FCR_TOF_Msk (0x1UL << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000010 */ #define OCTOSPI_FCR_TOF OCTOSPI_FCR_TOF_Msk /*!< Clear Timeout Flag */ /**************** Bit definition for OCTOSPI_DLR register *******************/ @@ -19008,9 +19011,6 @@ typedef struct #define OCTOSPI_WCCR_DQSE_Pos (29U) #define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */ #define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */ -#define OCTOSPI_WCCR_SIOO_Pos (31U) -#define OCTOSPI_WCCR_SIOO_Msk (0x1UL << OCTOSPI_WCCR_SIOO_Pos) /*!< 0x80000000 */ -#define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */ /**************** Bit definition for OCTOSPI_WTCR register ******************/ #define OCTOSPI_WTCR_DCYC_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h index 619e8c06b4..89875b40ab 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h @@ -19,10 +19,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ @@ -106,8 +106,8 @@ * @brief CMSIS Device version number */ #define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4_CMSIS_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32L4_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ +#define __STM32L4_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h index 70c38997b5..00166a5179 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h @@ -9,10 +9,10 @@ *

© Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, + * This software component is licensed by ST under Apache License, Version 2.0, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/Apache-2.0 * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/License.md b/system/Drivers/CMSIS/Device/ST/STM32L4xx/License.md new file mode 100644 index 0000000000..e0d829b638 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/License.md @@ -0,0 +1,83 @@ +Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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Accepting Warranty or Additional Liability. + +While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS + +APPENDIX: + + Copyright [2019] [STMicroelectronics] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/README.md b/system/Drivers/CMSIS/Device/ST/STM32L4xx/README.md new file mode 100644 index 0000000000..f0fa4930f7 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/README.md @@ -0,0 +1,42 @@ +# STM32CubeL4 CMSIS Device MCU Component + +## Overview + +**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. + +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product + * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio + * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series + * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ... + * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series + +Two models of publication are proposed for the STM32Cube embedded software : + * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series) + * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions. + +## Description + +This **cmsis_device_l4** MCU component repo is one element of the STM32CubeL4 MCU embedded software package, providing the **cmsis device** part. + +## Release note + +Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_l4/blob/master/Release_Notes.html). + +## Compatibility information + +In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package: + +CMSIS Device L4 | CMSIS Core | Was delivered in the full MCU package +--------------- | ---------- | ------------------------------------- +Tag v1.5.1 | Tag v5.4.0_cm4 | Tag v1.14.0 (and following, if any, till next new tag) +Tag v1.6.0 | Tag v5.4.0_cm4 | Tag v1.15.0 (and following, if any, till next new tag) +Tag v1.6.1 | Tag v5.4.0_cm4 | Tag v1.15.1 (and following, if any, till next new tag) +Tag v1.7.0 | Tag v5.6.0_cm4 | Tag v1.16.0 (and following, if any, till next new tag) + +The full **STM32CubeL4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL4). + +## Troubleshooting +If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_l4/issues/new). + +For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Release_Notes.html index c427881ea9..48c9b38c7f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Release_Notes.html @@ -30,8 +30,8 @@

Release Notes for

License

-

Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:

-

https://opensource.org/licenses/BSD-3-Clause

+

This software component is licensed by ST under Apache-2.0 license, the "License"; You may not use this component except in compliance with the License. You may obtain a copy of the License at:

+

Apache License v2.0

Purpose

This driver provides the CMSIS device for the stm32l4xx products. This covers