-
Main Changes
+
Main Changes
- First official release for STM32H743xx/753xx devices
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
index c52df22d8f..861bf403b9 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
@@ -47,10 +47,10 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
- * @brief STM32H7xx HAL Driver version number V1.7.0
+ * @brief STM32H7xx HAL Driver version number V1.8.0
*/
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
-#define __STM32H7xx_HAL_VERSION_SUB1 (0x07UL) /*!< [23:16] sub1 version */
+#define __STM32H7xx_HAL_VERSION_SUB1 (0x08UL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
@@ -134,6 +134,8 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
HAL_StatusTypeDef HAL_Init(void)
{
+uint32_t common_system_clock;
+
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure Cortex-M4 Instruction cache through ART accelerator */
__HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */
@@ -146,18 +148,24 @@ HAL_StatusTypeDef HAL_Init(void)
/* Update the SystemCoreClock global variable */
#if defined(RCC_D1CFGR_D1CPRE)
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
#else
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
#endif
/* Update the SystemD2Clock global variable */
#if defined(RCC_D1CFGR_HPRE)
- SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
- SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
@@ -259,32 +267,11 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
return HAL_ERROR;
}
-#if defined(DUAL_CORE)
- if (HAL_GetCurrentCPUID() == CM7_CPUID)
- {
- /* Cortex-M7 detected */
- /* Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
- {
- return HAL_ERROR;
- }
- }
- else
- {
- /* Cortex-M4 detected */
- /* Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000UL / (uint32_t)uwTickFreq)) > 0U)
- {
- return HAL_ERROR;
- }
- }
-#else
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
-#endif
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c
index a9437eb650..89fbd803ea 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c
@@ -1112,15 +1112,15 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
/* Clear DAC_MCR_MODEx bits */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
/* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
- if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_EXTERNAL) == DAC_CHIPCONNECT_EXTERNAL)
+ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
{
connectOnChip = 0x00000000UL;
}
- else if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_INTERNAL) == DAC_CHIPCONNECT_INTERNAL)
+ else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
{
connectOnChip = DAC_MCR_MODE1_0;
}
- else /* (sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_BOTH) == DAC_CHIPCONNECT_BOTH */
+ else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
{
if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
{
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
index 399ae0e0b8..aeabc95a27 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
@@ -146,6 +146,19 @@ typedef struct
#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)
+#if defined(UART9)
+#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
+ (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
+ (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
+ (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \
+ (((__REQUEST__) >= DMA_REQUEST_UART9_RX) && ((__REQUEST__) <= DMA_REQUEST_USART10_TX )))
+#else
+#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
+ (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
+ (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
+ (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )))
+
+#endif
/**
* @}
*/
@@ -278,6 +291,20 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
}
+ /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be
+ lock when transfering data to/from USART/UART */
+#if (STM32H7_DEV_ID == 0x450UL)
+ if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
+ {
+#endif /* STM32H7_DEV_ID == 0x450UL */
+ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
+ {
+ registerValue |= DMA_SxCR_TRBUFF;
+ }
+#if (STM32H7_DEV_ID == 0x450UL)
+ }
+#endif /* STM32H7_DEV_ID == 0x450UL */
+
/* Write to DMA Stream CR register */
((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
index 641c7e9342..25a19dea36 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
@@ -198,26 +198,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
if (iocurrent != 0x00U)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
- /* In case of Alternate function mode selection */
- if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
- {
- /* Check the Alternate function parameters */
- assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
- assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3U];
- temp &= ~(0xFU << ((position & 0x07U) * 4U));
- temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
- GPIOx->AFR[position >> 3U] = temp;
- }
-
- /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- temp = GPIOx->MODER;
- temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
- GPIOx->MODER = temp;
-
/* In case of Output or Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
@@ -243,6 +223,26 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
+ /* In case of Alternate function mode selection */
+ if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3U];
+ temp &= ~(0xFU << ((position & 0x07U) * 4U));
+ temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
+ GPIOx->AFR[position >> 3U] = temp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ GPIOx->MODER = temp;
+
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
@@ -333,9 +333,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
tmp &= (0x0FUL << (4U * (position & 0x03U)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
- tmp = 0x0FUL << (4U * (position & 0x03U));
- SYSCFG->EXTICR[position >> 2U] &= ~tmp;
-
/* Clear EXTI line configuration for Current CPU */
EXTI_CurrentCPU->IMR1 &= ~(iocurrent);
EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
@@ -343,6 +340,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Clear Rising Falling edge configuration */
EXTI->RTSR1 &= ~(iocurrent);
EXTI->FTSR1 &= ~(iocurrent);
+
+ tmp = 0x0FUL << (4U * (position & 0x03U));
+ SYSCFG->EXTICR[position >> 2U] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
@@ -352,14 +352,14 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ;
- /* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
- /* Deactivate the Pull-up and Pull-down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
}
position++;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
index 1b8c17920e..a9e7408ce6 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
@@ -351,13 +351,13 @@
/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT (0x00000001U)
-#define I2C_XFER_RX_IT (0x00000002U)
-#define I2C_XFER_LISTEN_IT (0x00000004U)
+#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
-#define I2C_XFER_ERROR_IT (0x00000011U)
-#define I2C_XFER_CPLT_IT (0x00000012U)
-#define I2C_XFER_RELOAD_IT (0x00000012U)
+#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */
+#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */
/* Private define Sequential Transfer Options default/reset value */
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
@@ -410,6 +410,9 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+/* Private function to treat different error callback */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
+
/* Private function to flush TXDR register */
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
@@ -4251,9 +4254,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
/* Set State at HAL_I2C_STATE_ABORT */
hi2c->State = HAL_I2C_STATE_ABORT;
@@ -5001,6 +5016,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t treatdmanack = 0U;
+ HAL_I2C_StateTypeDef tmpstate;
/* Process locked */
__HAL_LOCK(hi2c);
@@ -5079,8 +5095,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
+ tmpstate = hi2c->State;
+
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
{
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
@@ -5369,9 +5401,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
*/
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
+ uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
+ /* If a DMA is ongoing, Update handle size context */
+ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
+ else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
@@ -5426,19 +5476,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmperror;
+ uint32_t tmpITFlags = ITFlags;
+ uint32_t tmp;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ /* Disable Interrupts and Store Previous state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
/* Reset handle parameters */
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
+ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -5447,12 +5514,18 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
+ /* Fetch Last receive data if any */
+ if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
+ {
+ /* Read data from RXDR */
+ tmp = (uint8_t)hi2c->Instance->RXDR;
+
+ UNUSED(tmp);
+ }
+
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
- /* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
-
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
@@ -5466,6 +5539,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@@ -5500,6 +5574,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
@@ -5546,12 +5621,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
+ HAL_I2C_StateTypeDef tmpstate = hi2c->State;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- /* Disable all interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+ /* Disable Interrupts and Store Previous state */
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ }
+ else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ }
+ else
+ {
+ /* Do nothing */
+ }
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -5565,6 +5654,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
if (hi2c->hdmatx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
@@ -5572,6 +5664,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
if (hi2c->hdmarx != NULL)
{
hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
@@ -5608,7 +5703,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@@ -5631,6 +5725,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5646,6 +5741,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5660,6 +5756,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
else
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5733,6 +5830,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ uint32_t tmppreviousstate;
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -5752,7 +5850,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
/* keep HAL_I2C_STATE_LISTEN if set */
hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = I2C_Slave_ISR_IT;
}
else
@@ -5767,16 +5864,19 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
}
- hi2c->PreviousState = I2C_STATE_NONE;
hi2c->XferISR = NULL;
}
/* Abort DMA TX transfer if any */
- if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ tmppreviousstate = hi2c->PreviousState;
+ if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
- hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ }
- if (hi2c->hdmatx != NULL)
+ if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@@ -5792,13 +5892,20 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
}
/* Abort DMA RX transfer if any */
- else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
{
- hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ }
- if (hi2c->hdmarx != NULL)
+ if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
@@ -5814,10 +5921,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
}
- else if (hi2c->State == HAL_I2C_STATE_ABORT)
+ else
+ {
+ I2C_TreatErrorCallback(hi2c);
+ }
+}
+
+/**
+ * @brief I2C Error callback treatment.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -5831,6 +5956,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
}
else
{
+ hi2c->PreviousState = I2C_STATE_NONE;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -6062,30 +6189,16 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Reset AbortCpltCallback */
- hi2c->hdmatx->XferAbortCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
-
- /* Check if come from abort from user */
- if (hi2c->State == HAL_I2C_STATE_ABORT)
+ if (hi2c->hdmatx != NULL)
{
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->AbortCpltCallback(hi2c);
-#else
- HAL_I2C_AbortCpltCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ hi2c->hdmatx->XferAbortCallback = NULL;
}
- else
+ if (hi2c->hdmarx != NULL)
{
- /* Call the corresponding callback to inform upper layer of End of Transfer */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- hi2c->ErrorCallback(hi2c);
-#else
- HAL_I2C_ErrorCallback(hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ hi2c->hdmarx->XferAbortCallback = NULL;
}
+
+ I2C_TreatErrorCallback(hi2c);
}
/**
@@ -6362,19 +6475,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
- tmpisr |= I2C_IT_STOPI;
+ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
}
- if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
@@ -6400,7 +6513,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
@@ -6454,19 +6567,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
- if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c
index d60bdd05ee..223574f42e 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c
@@ -1100,7 +1100,11 @@ HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg
HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf)
{
uint32_t error;
- uint32_t numberMCU, hfactor, vfactor, hMCU, vMCU;
+ uint32_t numberMCU;
+ uint32_t hfactor;
+ uint32_t vfactor;
+ uint32_t hMCU;
+ uint32_t vMCU;
/* Check the JPEG handle allocation */
if ((hjpeg == NULL) || (pConf == NULL))
@@ -1285,7 +1289,9 @@ HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTy
*/
HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo)
{
- uint32_t yblockNb, cBblockNb, cRblockNb;
+ uint32_t yblockNb;
+ uint32_t cBblockNb;
+ uint32_t cRblockNb;
/* Check the JPEG handle allocation */
if ((hjpeg == NULL) || (pInfo == NULL))
@@ -2192,7 +2198,8 @@ void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputB
*/
HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg)
{
- uint32_t tickstart, tmpContext;
+ uint32_t tickstart;
+ uint32_t tmpContext;
tmpContext = hjpeg->Context;
/*Reset the Context operation and method*/
@@ -2522,7 +2529,11 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg)
*/
static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK)
{
- uint32_t i, p, l, code, si;
+ uint32_t i;
+ uint32_t p;
+ uint32_t l;
+ uint32_t code;
+ uint32_t si;
/* Figure C.1: Generation of table of Huffman code sizes */
p = 0;
@@ -2688,7 +2699,9 @@ static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCH
{
HAL_StatusTypeDef error;
JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable;
- uint32_t i, lsb, msb;
+ uint32_t i;
+ uint32_t lsb;
+ uint32_t msb;
__IO uint32_t *address, *addressDef;
if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC0))
@@ -3053,7 +3066,11 @@ static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg)
static uint32_t JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable,
__IO uint32_t *QTableAddress)
{
- uint32_t i, j, quantRow, quantVal, ScaleFactor;
+ uint32_t i;
+ uint32_t j;
+ uint32_t quantRow;
+ uint32_t quantVal;
+ uint32_t ScaleFactor;
__IO uint32_t *tableAddress;
tableAddress = QTableAddress;
@@ -3455,7 +3472,10 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg)
*/
static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords)
{
- uint32_t index, nBwords, nbBytes, dataword;
+ uint32_t index;
+ uint32_t nb_words;
+ uint32_t nb_bytes;
+ uint32_t dataword;
if (hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords * 4UL)))
{
@@ -3482,8 +3502,8 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
}
else if (hjpeg->OutDataLength > hjpeg->JpegOutCount)
{
- nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL;
- for (index = 0; index < nBwords; index++)
+ nb_words = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL;
+ for (index = 0; index < nb_words; index++)
{
/*Transfer 32 bits from the JPEG output FIFO*/
dataword = hjpeg->Instance->DOR;
@@ -3505,9 +3525,9 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
}
else
{
- nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;
+ nb_bytes = hjpeg->OutDataLength - hjpeg->JpegOutCount;
dataword = hjpeg->Instance->DOR;
- for (index = 0; index < nbBytes; index++)
+ for (index = 0; index < nb_bytes; index++)
{
hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * (index & 0x3UL))) & 0xFFUL);
hjpeg->JpegOutCount++;
@@ -3521,8 +3541,8 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
hjpeg->JpegOutCount = 0;
- nbBytes = 4UL - nbBytes;
- for (index = nbBytes; index < 4UL; index++)
+ nb_bytes = 4UL - nb_bytes;
+ for (index = nb_bytes; index < 4UL; index++)
{
hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * index)) & 0xFFUL);
hjpeg->JpegOutCount++;
@@ -3546,7 +3566,11 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor
*/
static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords)
{
- uint32_t nbBytes = 0, nBwords, index, Dataword, inputCount;
+ uint32_t nb_bytes = 0;
+ uint32_t nb_words;
+ uint32_t index;
+ uint32_t dataword;
+ uint32_t input_count;
if ((hjpeg->InDataLength == 0UL) || (nbRequestWords == 0UL))
{
@@ -3555,7 +3579,7 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord
}
else if (hjpeg->InDataLength > hjpeg->JpegInCount)
{
- nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount;
+ nb_bytes = hjpeg->InDataLength - hjpeg->JpegInCount;
}
else if (hjpeg->InDataLength == hjpeg->JpegInCount)
{
@@ -3571,39 +3595,39 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord
hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL);
}
hjpeg->JpegInCount = 0;
- nbBytes = hjpeg->InDataLength;
+ nb_bytes = hjpeg->InDataLength;
}
else
{
/* Nothing to do */
}
- if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nbBytes > 0UL))
+ if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nb_bytes > 0UL))
{
- nBwords = nbBytes / 4UL;
- if (nBwords >= nbRequestWords)
+ nb_words = nb_bytes / 4UL;
+ if (nb_words >= nbRequestWords)
{
for (index = 0; index < nbRequestWords; index++)
{
- inputCount = hjpeg->JpegInCount;
- hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24));
+ input_count = hjpeg->JpegInCount;
+ hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24));
hjpeg->JpegInCount += 4UL;
}
}
- else /*nBwords < nbRequestWords*/
+ else /*nb_words < nbRequestWords*/
{
- if (nBwords > 0UL)
+ if (nb_words > 0UL)
{
- for (index = 0; index < nBwords; index++)
+ for (index = 0; index < nb_words; index++)
{
- inputCount = hjpeg->JpegInCount;
- hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \
- (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24));
+ input_count = hjpeg->JpegInCount;
+ hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \
+ (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24));
hjpeg->JpegInCount += 4UL;
}
@@ -3611,13 +3635,13 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord
else
{
/* end of file*/
- Dataword = 0;
- for (index = 0; index < nbBytes; index++)
+ dataword = 0;
+ for (index = 0; index < nb_bytes; index++)
{
- Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL));
+ dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL));
hjpeg->JpegInCount++;
}
- hjpeg->Instance->DIR = Dataword;
+ hjpeg->Instance->DIR = dataword;
}
}
}
@@ -3850,7 +3874,9 @@ static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)
*/
static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg)
{
- uint32_t tmpContext, count, dataOut;
+ uint32_t tmpContext;
+ uint32_t count;
+ uint32_t dataOut;
for (count = JPEG_FIFO_SIZE; count > 0UL; count--)
{
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c
index b11c521a7a..0a579dcec7 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c
@@ -174,7 +174,6 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
/** @addtogroup LPTIM_Private_Constants
* @{
*/
@@ -183,6 +182,7 @@
* @}
*/
+/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
@@ -235,17 +235,20 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
- if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
- assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
- assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
}
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
+ {
+ assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
+ assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
+ }
assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
@@ -278,13 +281,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
- if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL));
}
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
+ {
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL));
+ }
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
- tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
+ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT));
}
/* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
@@ -298,25 +305,35 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
hlptim->Init.UpdateMode |
hlptim->Init.CounterSource);
- if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
+ /* Glitch filters for internal triggers and external inputs are configured
+ * only if an internal clock source is provided to the LPTIM
+ */
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
- tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
+ tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
hlptim->Init.UltraLowPowerClock.SampleTime);
}
- if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
+ /* Configure the active edge or edges used by the counter only if LPTIM is
+ * clocked by an external clock source
+ */
+ if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+ {
+ tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity);
+ }
+
+ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable External trigger and set the trigger source */
- tmpcfgr |= (hlptim->Init.Trigger.Source |
- hlptim->Init.Trigger.ActiveEdge |
- hlptim->Init.Trigger.SampleTime);
+ tmpcfgr |= (hlptim->Init.Trigger.Source |
+ hlptim->Init.Trigger.ActiveEdge);
}
/* Write to LPTIMx CFGR */
hlptim->Instance->CFGR = tmpcfgr;
/* Configure LPTIM input sources */
- if ((hlptim->Instance == LPTIM1)||(hlptim->Instance == LPTIM2))
+ if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
{
/* Check LPTIM Input1 and Input2 sources */
assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
@@ -327,7 +344,7 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
}
else
{
- if(hlptim->Instance == LPTIM3)
+ if (hlptim->Instance == LPTIM3)
{
/* Check LPTIM3 Input1 source */
assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
@@ -2307,17 +2324,17 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t
{
HAL_StatusTypeDef result = HAL_OK;
uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
- do
+ do
+ {
+ count--;
+ if (count == 0UL)
{
- count--;
- if (count == 0UL)
- {
- result = HAL_TIMEOUT;
- }
+ result = HAL_TIMEOUT;
}
- while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
+ }
+ while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
- return result;
+ return result;
}
/**
@@ -2344,29 +2361,29 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
/* Save LPTIM source clock */
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
- break;
- case LPTIM2_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
- break;
+ case LPTIM1_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
+ break;
+ case LPTIM2_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
+ break;
#if defined(LPTIM3)
- case LPTIM3_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM3_SOURCE();
- break;
+ case LPTIM3_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM3_SOURCE();
+ break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
- case LPTIM4_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM4_SOURCE();
- break;
+ case LPTIM4_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM4_SOURCE();
+ break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
- case LPTIM5_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM5_SOURCE();
- break;
+ case LPTIM5_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM5_SOURCE();
+ break;
#endif /* LPTIM5 */
- default:
- break;
+ default:
+ break;
}
/* Save LPTIM configuration registers */
@@ -2379,34 +2396,34 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
/*********** Reset LPTIM ***********/
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_FORCE_RESET();
- __HAL_RCC_LPTIM1_RELEASE_RESET();
- break;
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_FORCE_RESET();
- __HAL_RCC_LPTIM2_RELEASE_RESET();
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_FORCE_RESET();
+ __HAL_RCC_LPTIM1_RELEASE_RESET();
+ break;
+ case LPTIM2_BASE:
+ __HAL_RCC_LPTIM2_FORCE_RESET();
+ __HAL_RCC_LPTIM2_RELEASE_RESET();
+ break;
#if defined(LPTIM3)
- case LPTIM3_BASE:
- __HAL_RCC_LPTIM3_FORCE_RESET();
- __HAL_RCC_LPTIM3_RELEASE_RESET();
- break;
+ case LPTIM3_BASE:
+ __HAL_RCC_LPTIM3_FORCE_RESET();
+ __HAL_RCC_LPTIM3_RELEASE_RESET();
+ break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
- case LPTIM4_BASE:
- __HAL_RCC_LPTIM4_FORCE_RESET();
- __HAL_RCC_LPTIM4_RELEASE_RESET();
- break;
+ case LPTIM4_BASE:
+ __HAL_RCC_LPTIM4_FORCE_RESET();
+ __HAL_RCC_LPTIM4_RELEASE_RESET();
+ break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
- case LPTIM5_BASE:
- __HAL_RCC_LPTIM5_FORCE_RESET();
- __HAL_RCC_LPTIM5_RELEASE_RESET();
- break;
+ case LPTIM5_BASE:
+ __HAL_RCC_LPTIM5_FORCE_RESET();
+ __HAL_RCC_LPTIM5_RELEASE_RESET();
+ break;
#endif /* LPTIM5 */
- default:
- break;
+ default:
+ break;
}
/*********** Restore LPTIM Config ***********/
@@ -2415,29 +2432,29 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_D2PCLK1);
- break;
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_D3PCLK1);
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_D2PCLK1);
+ break;
+ case LPTIM2_BASE:
+ __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_D3PCLK1);
+ break;
#if defined(LPTIM3)
- case LPTIM3_BASE:
- __HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_D3PCLK1);
- break;
+ case LPTIM3_BASE:
+ __HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_D3PCLK1);
+ break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
- case LPTIM4_BASE:
- __HAL_RCC_LPTIM4_CONFIG(RCC_LPTIM4CLKSOURCE_D3PCLK1);
- break;
+ case LPTIM4_BASE:
+ __HAL_RCC_LPTIM4_CONFIG(RCC_LPTIM4CLKSOURCE_D3PCLK1);
+ break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
- case LPTIM5_BASE:
- __HAL_RCC_LPTIM5_CONFIG(RCC_LPTIM5CLKSOURCE_D3PCLK1);
- break;
+ case LPTIM5_BASE:
+ __HAL_RCC_LPTIM5_CONFIG(RCC_LPTIM5CLKSOURCE_D3PCLK1);
+ break;
#endif /* LPTIM5 */
- default:
- break;
+ default:
+ break;
}
if (tmpCMP != 0UL)
@@ -2472,29 +2489,29 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
/* Restore LPTIM source kernel clock */
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
- break;
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_CONFIG(tmpclksource);
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
+ break;
+ case LPTIM2_BASE:
+ __HAL_RCC_LPTIM2_CONFIG(tmpclksource);
+ break;
#if defined(LPTIM3)
- case LPTIM3_BASE:
- __HAL_RCC_LPTIM3_CONFIG(tmpclksource);
- break;
+ case LPTIM3_BASE:
+ __HAL_RCC_LPTIM3_CONFIG(tmpclksource);
+ break;
#endif /* LPTIM3 */
#if defined(LPTIM4)
- case LPTIM4_BASE:
- __HAL_RCC_LPTIM4_CONFIG(tmpclksource);
- break;
+ case LPTIM4_BASE:
+ __HAL_RCC_LPTIM4_CONFIG(tmpclksource);
+ break;
#endif /* LPTIM4 */
#if defined(LPTIM5)
- case LPTIM5_BASE:
- __HAL_RCC_LPTIM5_CONFIG(tmpclksource);
- break;
+ case LPTIM5_BASE:
+ __HAL_RCC_LPTIM5_CONFIG(tmpclksource);
+ break;
#endif /* LPTIM5 */
- default:
- break;
+ default:
+ break;
}
}
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c
index 36e0325faf..29f5f6077b 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c
@@ -387,7 +387,6 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
{
uint32_t errorstate;
MMC_InitTypeDef Init;
- HAL_StatusTypeDef status;
/* Default SDMMC peripheral configuration for MMC card initialization */
Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
@@ -397,18 +396,10 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
Init.ClockDiv = SDMMC_INIT_CLK_DIV;
/* Initialize SDMMC peripheral interface with default configuration */
- status = SDMMC_Init(hmmc->Instance, Init);
- if(status == HAL_ERROR)
- {
- return HAL_ERROR;
- }
+ (void)SDMMC_Init(hmmc->Instance, Init);
/* Set Power State to ON */
- status = SDMMC_PowerState_ON(hmmc->Instance);
- if(status == HAL_ERROR)
- {
- return HAL_ERROR;
- }
+ (void)SDMMC_PowerState_ON(hmmc->Instance);
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
@@ -428,6 +419,17 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
return HAL_ERROR;
}
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
return HAL_OK;
}
@@ -568,20 +570,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
add *= 512U;
}
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
@@ -755,20 +743,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
add *= 512U;
}
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
@@ -943,20 +917,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
add *= 512U;
}
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
@@ -1050,20 +1010,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData
add *= 512U;
}
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
@@ -1158,20 +1104,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData
add *= 512U;
}
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode = errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
@@ -1268,20 +1200,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat
add *= 512U;
}
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
@@ -2755,29 +2673,6 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData,
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
- /* Configure the MMC DPSM (Data Path State Machine) */
- config.DataTimeOut = SDMMC_DATATIMEOUT;
- config.DataLength = 0;
- config.DataBlockSize = SDMMC_DATABLOCK_SIZE_1B;
- config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
- config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
- config.DPSM = SDMMC_DPSM_DISABLE;
- (void)SDMMC_ConfigData(hmmc->Instance, &config);
-
- if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)
- {
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- hmmc->State = HAL_MMC_STATE_READY;
- return HAL_ERROR;
- }
- }
-
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 512;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c
index d1f70d3268..978ac175c6 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c
@@ -377,11 +377,8 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
#endif
/* Configure the default timeout for the OSPI memory access */
- status = HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
- }
+ (void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
- if (status == HAL_OK)
- {
/* Configure memory type, device size, chip select high time, clocked chip select high time, delay block bypass, free running clock, clock mode */
MODIFY_REG(hospi->Instance->DCR1,
(OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_CKCSHT |
@@ -408,33 +405,33 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
if (status == HAL_OK)
{
- /* Configure clock prescaler */
- MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
-
- /* Configure Dual Quad mode */
- MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
-
- /* Configure sample shifting and delay hold quarter cycle */
- MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
-
- /* Enable OctoSPI */
- __HAL_OSPI_ENABLE(hospi);
-
- /* Enable free running clock if needed : must be done after OSPI enable */
- if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE)
- {
- SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
- }
-
- /* Initialize the OSPI state */
- if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
- {
- hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT;
- }
- else
- {
- hospi->State = HAL_OSPI_STATE_READY;
- }
+ /* Configure clock prescaler */
+ MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
+
+ /* Configure Dual Quad mode */
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
+
+ /* Configure sample shifting and delay hold quarter cycle */
+ MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
+
+ /* Enable OctoSPI */
+ __HAL_OSPI_ENABLE(hospi);
+
+ /* Enable free running clock if needed : must be done after OSPI enable */
+ if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE)
+ {
+ SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
+ }
+
+ /* Initialize the OSPI state */
+ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
+ {
+ hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT;
+ }
+ else
+ {
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
}
}
}
@@ -2457,6 +2454,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
assert_param(IS_OSPIM_PORT(cfg->NCSPort));
assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort));
assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort));
+ assert_param(IS_OSPIM_REQ2ACKTIME(cfg->Req2AckTime));
if (hospi->Instance == OCTOSPI1)
{
@@ -2494,13 +2492,29 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
}
/***************** Deactivation of previous configuration *****************/
- if (IOM_cfg[instance].ClkPort != 0U)
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
+ if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
{
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ /* De-multiplexing should be performed */
+ CLEAR_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
+
+ if (other_instance == 1U)
+ {
+ SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKSRC);
+ SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSSRC);
+ SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLSRC_1);
+ SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHSRC_1);
+ }
+ }
+ else
+ {
+ if (IOM_cfg[instance].ClkPort != 0U)
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ }
}
/********************* Deactivation of other instance *********************/
@@ -2508,38 +2522,79 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
(cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) ||
(cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
{
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) &&
+ (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
+ {
+ /* Multiplexing should be performed */
+ SET_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
+ }
+ else
+ {
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ }
}
/******************** Activation of new configuration *********************/
- MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
- MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
- if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos))
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
- (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
- }
- else
- {
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
- (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->CR, OCTOSPIM_CR_REQ2ACK_TIME, ((cfg->Req2AckTime - 1U) << OCTOSPIM_CR_REQ2ACK_TIME_Pos));
}
- if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
- (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN);
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN);
+
+ if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
+ }
+ else
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
+ }
+
+ if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
+ }
+ else
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
+ }
}
else
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
- (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
+
+ if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+ (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ }
+ else
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+ (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ }
+
+ if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ }
+ else
+ {
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ }
}
/******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/
@@ -2905,7 +2960,14 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *
if (instance_nb == 2U)
{
- value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
+ if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U)
+ {
+ value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
+ }
+ else
+ {
+ value = OCTOSPIM_PCR_NCSSRC;
+ }
}
/* Get the information about the instance */
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c
index 5db2fc8c92..19f0a69362 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c
@@ -185,6 +185,7 @@ void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
void PSSI_DMAError(DMA_HandleTypeDef *hdma);
void PSSI_DMAAbort(DMA_HandleTypeDef *hdma);
+
/* Private functions to handle IT transfer */
static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode);
@@ -613,6 +614,10 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
uint32_t tickstart;
uint32_t transfer_size = Size;
+#if defined (__GNUC__)
+ __IO uint16_t *pdr_16bits = (__IO uint16_t *)(&(hpssi->Instance->DR));
+#endif /* __GNUC__ */
+
if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) ||
((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size%4U) != 0U)))
@@ -682,7 +687,11 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
return HAL_ERROR;
}
/* Write data to DR */
+#if defined (__GNUC__)
+ *pdr_16bits = *pbuffer;
+#else
*(__IO uint16_t *)((uint32_t)(&hpssi->Instance->DR)) = *pbuffer;
+#endif /* __GNUC__ */
/* Increment Buffer pointer */
pbuffer++;
@@ -763,6 +772,9 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
{
uint32_t tickstart;
uint32_t transfer_size = Size;
+#if defined (__GNUC__)
+ __IO uint16_t *pdr_16bits = (__IO uint16_t *)(&(hpssi->Instance->DR));
+#endif /* __GNUC__ */
if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) ||
@@ -833,7 +845,12 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
}
/* Read data from DR */
+#if defined (__GNUC__)
+ *pbuffer = *pdr_16bits;
+#else
*pbuffer = *(__IO uint16_t *)((uint32_t)&hpssi->Instance->DR);
+#endif /* __GNUC__ */
+
pbuffer++;
transfer_size -= 2U;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c
index 7b41ec24d8..74505b35b9 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c
@@ -24,7 +24,7 @@
[..]
(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
- (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
+ (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
(++) If interrupt mode is used, enable and configure QuadSPI global
@@ -64,7 +64,7 @@
(++) In polling mode, the output of the function is done when the transfer is complete.
(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
+ (++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
*** Auto-polling functional mode ***
====================================
@@ -137,7 +137,7 @@
(++) In polling mode, the output of the function is done when the transfer
complete bit is set and the busy bit cleared.
(++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
- the transfer complete bi is set.
+ the transfer complete bit is set.
*** Control functions ***
=========================
@@ -146,6 +146,7 @@
(#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
(#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
(#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
+ (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.
*** Callback registration ***
=============================================
@@ -218,7 +219,7 @@
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -226,18 +227,17 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
+#if defined(QUADSPI)
+
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
-#ifdef HAL_QSPI_MODULE_ENABLED
-
-#if defined(QUADSPI)
-
/** @defgroup QSPI QSPI
* @brief QSPI HAL module driver
* @{
*/
+#ifdef HAL_QSPI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
@@ -245,7 +245,7 @@
/** @defgroup QSPI_Private_Constants QSPI Private Constants
* @{
*/
-#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!
Init.FlashID));
}
- /* Process locked */
- __HAL_LOCK(hqspi);
-
if(hqspi->State == HAL_QSPI_STATE_RESET)
{
- /* Allocate lock resource and initialize it */
- hqspi->Lock = HAL_UNLOCKED;
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
@@ -359,8 +354,9 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
/* Init the low level hardware : GPIO, CLOCK */
HAL_QSPI_MspInit(hqspi);
#endif
+
/* Configure the default timeout for the QSPI memory access */
- HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
+ HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
}
/* Configure QSPI FIFO Threshold */
@@ -392,16 +388,13 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
hqspi->State = HAL_QSPI_STATE_READY;
}
- /* Release Lock */
- __HAL_UNLOCK(hqspi);
-
/* Return function status */
return status;
}
/**
* @brief De-Initialize the QSPI peripheral.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
@@ -412,9 +405,6 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hqspi);
-
/* Disable the QSPI Peripheral Clock */
__HAL_QSPI_DISABLE(hqspi);
@@ -437,15 +427,12 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
/* Initialize the QSPI state */
hqspi->State = HAL_QSPI_STATE_RESET;
- /* Release Lock */
- __HAL_UNLOCK(hqspi);
-
return HAL_OK;
}
/**
* @brief Initialize the QSPI MSP.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
@@ -460,7 +447,7 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
/**
* @brief DeInitialize the QSPI MSP.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
@@ -499,7 +486,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
/**
* @brief Handle QSPI interrupt request.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
@@ -509,7 +496,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
uint32_t itsource = READ_REG(hqspi->Instance->CR);
/* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
- if(((flag & QSPI_FLAG_FT) == QSPI_FLAG_FT) && ((itsource & QSPI_IT_FT) == QSPI_IT_FT))
+ if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
{
data_reg = &hqspi->Instance->DR;
@@ -521,7 +508,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
if (hqspi->TxXferCount > 0U)
{
/* Fill the FIFO until the threshold is reached */
- *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr;
+ *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
@@ -542,7 +529,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
if (hqspi->RxXferCount > 0U)
{
/* Read the FIFO until the threshold is reached */
- *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
+ *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
@@ -559,6 +546,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
{
/* Nothing to do */
}
+
/* FIFO Threshold callback */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
hqspi->FifoThresholdCallback(hqspi);
@@ -568,7 +556,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Transfer Complete interrupt occurred -------------------------------*/
- else if(((flag & QSPI_FLAG_TC) == QSPI_FLAG_TC) && ((itsource & QSPI_IT_TC) == QSPI_IT_TC))
+ else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
@@ -579,7 +567,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/* Transfer complete callback */
if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
{
- if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@@ -588,6 +576,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
__HAL_MDMA_DISABLE(hqspi->hmdma);
}
+
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@@ -600,7 +589,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
{
- if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@@ -616,7 +605,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
if (hqspi->RxXferCount > 0U)
{
/* Read the last data received in the FIFO until it is empty */
- *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
+ *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
@@ -628,6 +617,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
}
+
/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
@@ -688,7 +678,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Status Match interrupt occurred ------------------------------------*/
- else if(((flag & QSPI_FLAG_SM)== QSPI_FLAG_SM) && ((itsource & QSPI_IT_SM) == QSPI_IT_SM))
+ else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
@@ -712,7 +702,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Transfer Error interrupt occurred ----------------------------------*/
- else if(((flag & QSPI_FLAG_TE) == QSPI_FLAG_TE) && ((itsource & QSPI_IT_TE) == QSPI_IT_TE))
+ else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
@@ -723,7 +713,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/* Set error code */
hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
- if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@@ -761,7 +751,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
/* QSPI Timeout interrupt occurred -----------------------------------------*/
- else if(((flag & QSPI_FLAG_TO) == QSPI_FLAG_TO) && ((itsource & QSPI_IT_TO) == QSPI_IT_TO))
+ else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
{
/* Clear interrupt */
WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
@@ -773,6 +763,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
HAL_QSPI_TimeOutCallback(hqspi);
#endif
}
+
else
{
/* Nothing to do */
@@ -781,7 +772,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
/**
* @brief Set the command configuration.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Read or Write Modes
@@ -849,7 +840,6 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe
/* Update QSPI state */
hqspi->State = HAL_QSPI_STATE_READY;
}
-
}
else
{
@@ -872,7 +862,7 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe
/**
* @brief Set the command configuration in interrupt mode.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @param cmd : structure that contains the command configuration information
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
@@ -971,10 +961,11 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp
/**
* @brief Transmit an amount of data in blocking mode.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Write Mode
+
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
@@ -1013,7 +1004,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
break;
}
- *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr;
+ *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
hqspi->pTxBuffPtr++;
hqspi->TxXferCount--;
}
@@ -1054,8 +1045,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
/**
* @brief Receive an amount of data in blocking mode.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Read Mode
* @retval HAL status
@@ -1100,7 +1091,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
break;
}
- *hqspi->pRxBuffPtr = *(__IO uint8_t *)data_reg;
+ *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
hqspi->pRxBuffPtr++;
hqspi->RxXferCount--;
}
@@ -1114,6 +1105,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
{
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+
}
}
@@ -1139,8 +1131,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
/**
* @brief Send an amount of data in non-blocking mode with interrupt.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
@@ -1199,8 +1191,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData
/**
* @brief Receive an amount of data in non-blocking mode with interrupt.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1263,18 +1255,15 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
/**
* @brief Send an amount of data in non-blocking mode with DMA.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
- * @note If MDMA peripheral access is configured as halfword, the number
- * of data and the fifo threshold should be aligned on halfword
- * @note If MDMA peripheral access is configured as word, the number
- * of data and the fifo threshold should be aligned on word
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
{
HAL_StatusTypeDef status = HAL_OK;
+ uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
/* Process locked */
__HAL_LOCK(hqspi);
@@ -1286,64 +1275,75 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
if(pData != NULL )
{
+ /* Configure counters of the handle */
+ hqspi->TxXferCount = data_size;
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
- /* Configure counters and size of the handle */
- hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->pTxBuffPtr = pData;
+ /* Configure size and pointer of the handle */
+ hqspi->TxXferSize = hqspi->TxXferCount;
+ hqspi->pTxBuffPtr = pData;
- /* Configure QSPI: CCR register with functional mode as indirect write */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
+ /* Configure QSPI: CCR register with functional mode as indirect write */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
- /* Set the QSPI MDMA transfer complete callback */
- hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt;
+ /* Set the QSPI MDMA transfer complete callback */
+ hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt;
- /* Set the MDMA error callback */
- hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
+ /* Set the MDMA error callback */
+ hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
- /* Clear the MDMA abort callback */
- hqspi->hmdma->XferAbortCallback = NULL;
+ /* Clear the MDMA abort callback */
+ hqspi->hmdma->XferAbortCallback = NULL;
- /* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */
- MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
+ /* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */
+ MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
- /* Update MDMA configuration with the correct SourceInc field for Write operation */
- if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
- {
- MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
- }
- else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
- {
- MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
- }
- else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
- {
- MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
- }
- else
- {
- /* in case of incorrect source data size */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
- status = HAL_ERROR;
- }
+ /* Update MDMA configuration with the correct SourceInc field for Write operation */
+ if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
+ {
+ MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
+ }
+ else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
+ {
+ MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
+ }
+ else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
+ {
+ MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
+ }
+ else
+ {
+ /* in case of incorrect source data size */
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ status = HAL_ERROR;
+ }
- /* Enable the QSPI transfer error and complete Interrupts : Workaround for QSPI low kernel clock frequency */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE |QSPI_IT_TC);
+ /* Enable the QSPI transmit MDMA */
+ if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
- /* Enable the QSPI transmit MDMA */
- if(HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
+ /* Enable the QSPI transfer error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
- /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
- }
+ /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
}
else
{
@@ -1367,8 +1367,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer.
+ * @param hqspi : QSPI handle
+ * @param pData : pointer to data buffer.
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1376,6 +1376,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
+ uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
/* Process locked */
__HAL_LOCK(hqspi);
@@ -1387,35 +1388,26 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
if(pData != NULL )
{
+ /* Configure counters of the handle */
+ hqspi->RxXferCount = data_size;
+ /* Update state */
+ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
- /* Update state */
- hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
-
- /* Clear interrupt */
- __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
-
- /* Configure counters and size of the handle */
- hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
- hqspi->pRxBuffPtr = pData;
-
- /* Set the QSPI DMA transfer complete callback */
- hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt;
+ /* Clear interrupt */
+ __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
- /* Set the MDMA error callback */
- hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
+ /* Configure size and pointer of the handle */
+ hqspi->RxXferSize = hqspi->RxXferCount;
+ hqspi->pRxBuffPtr = pData;
- /* Clear the MDMA abort callback */
- hqspi->hmdma->XferAbortCallback = NULL;
+ /* Set the QSPI MDMA transfer complete callback */
+ hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt;
+ /* Set the MDMA error callback */
+ hqspi->hmdma->XferErrorCallback = QSPI_DMAError;
- /* QSPI need to be configured to indirect mode before starting
- the MDMA to avoid primatury triggering for the MDMA transfert */
- /* Configure QSPI: CCR register with functional as indirect read */
- MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
-
- /* Start the transfer by re-writing the address in AR register */
- WRITE_REG(hqspi->Instance->AR, addr_reg);
+ /* Clear the MDMA abort callback */
+ hqspi->hmdma->XferAbortCallback = NULL;
/* In Receive mode , the MDMA source is the QSPI DR register : Force the MDMA Source Increment to disable */
MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE);
@@ -1439,21 +1431,37 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
status = HAL_ERROR;
}
+ /* Configure QSPI: CCR register with functional as indirect read */
+ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
- /* Enable the MDMA */
- if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hqspi);
+ /* Start the transfer by re-writing the address in AR register */
+ WRITE_REG(hqspi->Instance->AR, addr_reg);
+
+ /* Enable the MDMA */
+ if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
- /* Enable the QSPI transfer error Interrupt */
- __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
+ /* Enable the QSPI transfer error Interrupt */
+ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
- /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
- }
+ /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */
+ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ hqspi->State = HAL_QSPI_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hqspi);
+ }
}
else
{
+ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
/* Process unlocked */
@@ -1473,9 +1481,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
/**
* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the polling configuration information.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information.
+ * @param cfg : structure that contains the polling configuration information.
* @param Timeout : Timeout duration
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
@@ -1574,9 +1582,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy
/**
* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the polling configuration information.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information.
+ * @param cfg : structure that contains the polling configuration information.
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
@@ -1678,9 +1686,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman
/**
* @brief Configure the Memory Mapped mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the memory mapped configuration information.
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information.
+ * @param cfg : structure that contains the memory mapped configuration information.
* @note This function is used only in Memory mapped Mode
* @retval HAL status
*/
@@ -1733,9 +1741,9 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT
if (status == HAL_OK)
{
/* Configure QSPI: CR register with timeout counter enable */
- MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
+ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
- if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
+ if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
{
assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
@@ -1767,7 +1775,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT
/**
* @brief Transfer Error callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
@@ -1782,7 +1790,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Abort completed callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1797,7 +1805,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Command completed callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1812,7 +1820,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Rx Transfer completed callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1827,10 +1835,10 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Tx Transfer completed callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
- __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
+__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hqspi);
@@ -1843,7 +1851,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief FIFO Threshold callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
@@ -1858,7 +1866,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Status Match callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
@@ -1873,7 +1881,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
/**
* @brief Timeout callback.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
@@ -2115,7 +2123,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS
/**
* @brief Return the QSPI handle state.
- * @param hqspi: QSPI handle
+ * @param hqspi : QSPI handle
* @retval HAL state
*/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
@@ -2126,7 +2134,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
/**
* @brief Return the QSPI error code.
-* @param hqspi: QSPI handle
+* @param hqspi : QSPI handle
* @retval QSPI Error Code
*/
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
@@ -2136,7 +2144,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
/**
* @brief Abort the current transmission.
-* @param hqspi: QSPI handle
+* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
@@ -2150,7 +2158,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
/* Process unlocked */
__HAL_UNLOCK(hqspi);
- if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@@ -2169,7 +2177,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
/* Wait until TC flag is set to go back in idle state */
status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
- if(status == HAL_OK)
+ if (status == HAL_OK)
{
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
@@ -2179,6 +2187,9 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
if (status == HAL_OK)
{
+ /* Reset functional mode configuration to indirect write mode by default */
+ CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+
/* Update state */
hqspi->State = HAL_QSPI_STATE_READY;
}
@@ -2189,7 +2200,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
/**
* @brief Abort the current transmission (non-blocking function)
-* @param hqspi: QSPI handle
+* @param hqspi : QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
@@ -2208,7 +2219,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
/* Disable all interrupts */
__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
- if (READ_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN) != 0U)
+ if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
@@ -2217,10 +2228,15 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK)
{
- /* Set error code to DMA */
- hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ /* Change state of QSPI */
+ hqspi->State = HAL_QSPI_STATE_READY;
- status = HAL_ERROR;
+ /* Abort Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+ hqspi->AbortCpltCallback(hqspi);
+#else
+ HAL_QSPI_AbortCpltCallback(hqspi);
+#endif
}
}
else
@@ -2239,8 +2255,8 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
}
/** @brief Set QSPI timeout.
- * @param hqspi: QSPI handle.
- * @param Timeout: Timeout for the QSPI memory access.
+ * @param hqspi : QSPI handle.
+ * @param Timeout : Timeout for the QSPI memory access.
* @retval None
*/
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
@@ -2249,8 +2265,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
}
/** @brief Set QSPI Fifo threshold.
- * @param hqspi: QSPI handle.
- * @param Threshold: Threshold of the Fifo (value between 1 and 16).
+ * @param hqspi : QSPI handle.
+ * @param Threshold : Threshold of the Fifo (value between 1 and 16).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
@@ -2282,7 +2298,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t
}
/** @brief Get QSPI Fifo threshold.
- * @param hqspi: QSPI handle.
+ * @param hqspi : QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
@@ -2331,14 +2347,22 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashI
* @}
*/
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_Private_Functions QSPI Private Functions
+ * @{
+ */
+
/**
* @brief DMA QSPI receive process complete callback.
- * @param hmdma: MDMA handle
+ * @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent);
hqspi->RxXferCount = 0U;
/* Enable the QSPI transfer complete Interrupt */
@@ -2347,12 +2371,12 @@ static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
/**
* @brief DMA QSPI transmit process complete callback.
- * @param hmdma: MDMA handle
+ * @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent);
hqspi->TxXferCount = 0U;
/* Enable the QSPI transfer complete Interrupt */
@@ -2361,12 +2385,12 @@ static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
/**
* @brief DMA QSPI communication error callback.
- * @param hmdma: MDMA handle
+ * @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent);
hqspi->RxXferCount = 0U;
hqspi->TxXferCount = 0U;
@@ -2382,12 +2406,12 @@ static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
/**
* @brief MDMA QSPI abort complete callback.
- * @param hmdma: MDMA handle
+ * @param hmdma : MDMA handle
* @retval None
*/
static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
{
- QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((MDMA_HandleTypeDef* )hmdma)->Parent;
+ QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent);
hqspi->RxXferCount = 0U;
hqspi->TxXferCount = 0U;
@@ -2418,13 +2442,14 @@ static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
#endif
}
}
+
/**
* @brief Wait for a flag state until timeout.
- * @param hqspi: QSPI handle
- * @param Flag: Flag checked
- * @param State: Value of the flag expected
- * @param Tickstart: Tick start value
- * @param Timeout: Duration of the timeout
+ * @param hqspi : QSPI handle
+ * @param Flag : Flag checked
+ * @param State : Value of the flag expected
+ * @param Tickstart : Tick start value
+ * @param Timeout : Duration of the timeout
* @retval HAL status
*/
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
@@ -2450,9 +2475,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp
/**
* @brief Configure the communication registers.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information
- * @param FunctionalMode: functional mode to configured
+ * @param hqspi : QSPI handle
+ * @param cmd : structure that contains the command configuration information
+ * @param FunctionalMode : functional mode to configured
* This parameter can be one of the following values:
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
@@ -2606,16 +2631,15 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
* @}
*/
+#endif /* HAL_QSPI_MODULE_ENABLED */
/**
* @}
*/
-#endif /* QUADSPI */
-
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
/**
* @}
*/
+#endif /* defined(QUADSPI) */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
index 5be9eb10fc..17c241b8d6 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
@@ -228,8 +228,9 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
- /* Update the SystemCoreClock global variable */
+ /* Update the SystemCoreClock and SystemD2Clock global variables */
SystemCoreClock = HSI_VALUE;
+ SystemD2Clock = HSI_VALUE;
/* Adapt Systick interrupt period */
if(HAL_InitTick(uwTickPrio) != HAL_OK)
@@ -859,7 +860,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
* contains the configuration information for the RCC peripheral.
* @param FLatency: FLASH Latency, this parameter depend on device selected
*
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * @note The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency
* and updated by HAL_InitTick() function called within this function
*
* @note The HSI is used (enabled by hardware) as system clock source after
@@ -882,6 +883,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
{
HAL_StatusTypeDef halstatus;
uint32_t tickstart;
+ uint32_t common_system_clock;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
@@ -1174,10 +1176,23 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
/* Update the SystemCoreClock global variable */
#if defined(RCC_D1CFGR_D1CPRE)
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+#else
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
/* Configure the source of time base considering new system clocks settings*/
halstatus = HAL_InitTick (uwTickPrio);
@@ -1429,11 +1444,26 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
+uint32_t common_system_clock;
+
+#if defined(RCC_D1CFGR_D1CPRE)
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+#else
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+#endif
+
#if defined(RCC_D1CFGR_HPRE)
- SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
- SystemD2Clock = (HAL_RCCEx_GetD1SysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
return SystemD2Clock;
}
@@ -1451,7 +1481,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
#else
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> POSITION_VAL(RCC_CDCFGR2_CDPPRE1_0)]);
+ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
#endif
}
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
index e8cfbf23d2..22c9e940ca 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
@@ -2635,21 +2635,37 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
}
/**
- * @brief Returns the main Core frequency
- * @note Each time core clock changes, this function must be called to update the
- * right system core clock value. Otherwise, any configuration based on this function will be incorrect.
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * @brief Returns the main System frequency
+ * @note Each time System clock changes, this function must be called to update the
+ * right core clock value. Otherwise, any configuration based on this function will be incorrect.
+ * @note The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
{
+uint32_t common_system_clock;
+
#if defined(RCC_D1CFGR_D1CPRE)
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
#else
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+ common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
#endif
- return SystemCoreClock;
+
+ /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+
+ return common_system_clock;
}
/**
* @}
@@ -2683,6 +2699,28 @@ void HAL_RCCEx_DisableLSECSS(void)
__HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
}
+/**
+ * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
+ * @note LSE Clock Security System Interrupt is mapped on EXTI line 18
+ * @retval None
+ */
+void HAL_RCCEx_EnableLSECSS_IT(void)
+{
+ /* Enable LSE CSS */
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
+
+ /* Enable LSE CSS IT */
+ __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
+
+ /* Enable IT on EXTI Line 18 */
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT();
+#else
+ __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
+#endif /* DUAL_CORE && CORE_CM4 */
+ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
+}
+
/**
* @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock
* @param WakeUpClk: Wakeup clock
@@ -3351,6 +3389,38 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D
return status;
}
+/**
+ * @brief Handle the RCC LSE Clock Security System interrupt request.
+ * @retval None
+ */
+void HAL_RCCEx_LSECSS_IRQHandler(void)
+{
+ /* Check RCC LSE CSSF flag */
+ if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
+ {
+
+ /* Clear RCC LSE CSS pending bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
+
+ /* RCC LSE Clock Security System interrupt user callback */
+ HAL_RCCEx_LSECSS_Callback();
+
+ }
+}
+
+/**
+ * @brief RCCEx LSE Clock Security System interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCCEx_LSECSS_Callback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
+ */
+}
+
+
+
/**
* @}
*/
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c
index 9ef4e90ce8..02aaa0231c 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c
@@ -464,7 +464,6 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
{
uint32_t errorstate;
- HAL_StatusTypeDef status;
SD_InitTypeDef Init;
uint32_t sdmmc_clk;
@@ -475,27 +474,22 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
Init.ClockDiv = SDMMC_INIT_CLK_DIV;
-#if (USE_SD_TRANSCEIVER != 0U) || defined (USE_SD_DIRPOL)
+#if (USE_SD_TRANSCEIVER != 0U)
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
/* Set Transceiver polarity */
hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
}
+#elif defined (USE_SD_DIRPOL)
+ /* Set Transceiver polarity */
+ hsd->Instance->POWER |= SDMMC_POWER_DIRPOL;
#endif /* USE_SD_TRANSCEIVER */
/* Initialize SDMMC peripheral interface with default configuration */
- status = SDMMC_Init(hsd->Instance, Init);
- if(status != HAL_OK)
- {
- return HAL_ERROR;
- }
+ (void)SDMMC_Init(hsd->Instance, Init);
/* Set Power State to ON */
- status = SDMMC_PowerState_ON(hsd->Instance);
- if(status != HAL_OK)
- {
- return HAL_ERROR;
- }
+ (void)SDMMC_PowerState_ON(hsd->Instance);
/* wait 74 Cycles: required power up waiting time before starting
the SD initialization sequence */
@@ -528,6 +522,17 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
return HAL_ERROR;
}
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
return HAL_OK;
}
@@ -684,17 +689,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * BLOCKSIZE;
@@ -877,17 +871,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * BLOCKSIZE;
@@ -1071,17 +1054,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@@ -1175,17 +1147,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@@ -1281,17 +1242,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@@ -1390,16 +1340,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@@ -2342,6 +2282,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
{
uint32_t sd_status[16];
uint32_t errorstate;
+ HAL_StatusTypeDef status = HAL_OK;
errorstate = SD_SendSDStatus(hsd, sd_status);
if(errorstate != HAL_SD_ERROR_NONE)
@@ -2350,7 +2291,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
hsd->ErrorCode |= errorstate;
hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
+ status = HAL_ERROR;
}
else
{
@@ -2380,7 +2321,18 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
pStatus->VideoSpeedClass = (uint8_t)((sd_status[4] & 0xFF000000U) >> 24U);
}
- return HAL_OK;
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode = errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ status = HAL_ERROR;
+ }
+
+ return status;
}
/**
@@ -2419,6 +2371,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
{
SDMMC_InitTypeDef Init;
uint32_t errorstate;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_SDMMC_BUS_WIDE(WideMode));
@@ -2460,8 +2413,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
+ status = HAL_ERROR;
}
else
{
@@ -2495,10 +2447,20 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
(void)SDMMC_Init(hsd->Instance, Init);
}
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ status = HAL_ERROR;
+ }
+
/* Change State */
hsd->State = HAL_SD_STATE_READY;
- return HAL_OK;
+ return status;
}
/**
@@ -2516,6 +2478,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode)
{
uint32_t tickstart;
+ uint32_t errorstate;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
@@ -2743,6 +2706,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
}
}
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ status = HAL_ERROR;
+ }
+
/* Change State */
hsd->State = HAL_SD_STATE_READY;
return status;
@@ -3548,7 +3521,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
if (errorstate != HAL_SD_ERROR_NONE)
{
@@ -3557,16 +3530,13 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
/* Configure the SD DPSM (Data Path State Machine) */
sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
- sdmmc_datainitstructure.DataLength = 64;
+ sdmmc_datainitstructure.DataLength = 64U;
sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
- if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
- {
- return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
- }
+ (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
errorstate = SDMMC_CmdSwitch(hsd->Instance,SDMMC_SDR25_SWITCH_PATTERN);
@@ -3662,7 +3632,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
if (errorstate != HAL_SD_ERROR_NONE)
{
@@ -3671,7 +3641,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
/* Configure the SD DPSM (Data Path State Machine) */
sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
- sdmmc_datainitstructure.DataLength = 64;
+ sdmmc_datainitstructure.DataLength = 64U;
sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
@@ -3790,7 +3760,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
if (errorstate != HAL_SD_ERROR_NONE)
{
@@ -3799,7 +3769,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd)
/* Configure the SD DPSM (Data Path State Machine) */
sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
- sdmmc_datainitstructure.DataLength = 64;
+ sdmmc_datainitstructure.DataLength = 64U;
sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c
index cc7844774d..7c4da99d30 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c
@@ -139,17 +139,6 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
@@ -231,17 +220,6 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint
add *= 512U;
}
- /* Set Block Size for Card */
- errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
- if(errorstate != HAL_SD_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS);
- hsd->ErrorCode |= errorstate;
- hsd->State = HAL_SD_STATE_READY;
- return HAL_ERROR;
- }
-
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = BLOCKSIZE * NumberOfBlocks;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
index 0b2bcb493b..38731139df 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c
@@ -2617,10 +2617,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
}
/* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
@@ -2783,7 +2783,7 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
switch (Channel)
@@ -2827,7 +2827,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -2873,7 +2873,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
/* Enable the capture compare Interrupts 1 and/or 2 */
@@ -2923,7 +2923,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
@@ -2978,7 +2978,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
uint32_t *pData2, uint16_t Length)
{
/* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
if (htim->State == HAL_TIM_STATE_BUSY)
{
@@ -3112,7 +3112,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c
index 0458da47f7..8f9d2b629d 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c
@@ -317,7 +317,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+ - HDSEL, SCEN and IREN bits in the USART_CR3 register.
+ */
husart->Instance->CR2 &= ~USART_CR2_LINEN;
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
@@ -2091,7 +2092,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
uint32_t errorcode;
/* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR));
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | USART_ISR_UDR));
if (errorflags == 0U)
{
/* USART in mode Receiver ---------------------------------------------------*/
@@ -2146,6 +2147,14 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
+ /* USART Receiver Timeout interrupt occurred ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(husart, UART_CLEAR_RTOF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_RTO;
+ }
+
/* USART SPI slave underrun error interrupt occurred -------------------------*/
if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c
index 5a2f54ef8f..f38b03d203 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c
@@ -57,10 +57,10 @@
/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
* @{
*/
-/* UART RX FIFO depth */
+/* USART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
-/* UART TX FIFO depth */
+/* USART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
/**
* @}
@@ -243,7 +243,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart)
/* Restore USART configuration */
WRITE_REG(husart->Instance->CR1, tmpcr1);
- husart->SlaveMode = USART_SLAVEMODE_ENABLE;
+ husart->SlaveMode = USART_SLAVEMODE_DISABLE;
husart->State = HAL_USART_STATE_READY;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c
index 6e223901f9..52d1d8008d 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c
@@ -194,6 +194,8 @@
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
{
uint32_t flashaccess;
+ uint32_t btcr_reg;
+ uint32_t mask;
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
@@ -226,38 +228,42 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini
flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
}
- MODIFY_REG(Device->BTCR[Init->NSBank],
- (FMC_BCRx_MBKEN |
- FMC_BCRx_MUXEN |
- FMC_BCRx_MTYP |
- FMC_BCRx_MWID |
- FMC_BCRx_FACCEN |
- FMC_BCRx_BURSTEN |
- FMC_BCRx_WAITPOL |
- FMC_BCRx_WAITCFG |
- FMC_BCRx_WREN |
- FMC_BCRx_WAITEN |
- FMC_BCRx_EXTMOD |
- FMC_BCRx_ASYNCWAIT |
- FMC_BCRx_CBURSTRW |
- FMC_BCR1_CCLKEN |
- FMC_BCR1_WFDIS |
- FMC_BCRx_CPSIZE),
- (flashaccess |
- Init->DataAddressMux |
- Init->MemoryType |
- Init->MemoryDataWidth |
- Init->BurstAccessMode |
- Init->WaitSignalPolarity |
- Init->WaitSignalActive |
- Init->WriteOperation |
- Init->WaitSignal |
- Init->ExtendedMode |
- Init->AsynchronousWait |
- Init->WriteBurst |
- Init->ContinuousClock |
- Init->WriteFifo |
- Init->PageSize));
+ btcr_reg = (flashaccess | \
+ Init->DataAddressMux | \
+ Init->MemoryType | \
+ Init->MemoryDataWidth | \
+ Init->BurstAccessMode | \
+ Init->WaitSignalPolarity | \
+ Init->WaitSignalActive | \
+ Init->WriteOperation | \
+ Init->WaitSignal | \
+ Init->ExtendedMode | \
+ Init->AsynchronousWait | \
+ Init->WriteBurst);
+
+ btcr_reg |= Init->ContinuousClock;
+ btcr_reg |= Init->WriteFifo;
+ btcr_reg |= Init->PageSize;
+
+ mask = (FMC_BCRx_MBKEN |
+ FMC_BCRx_MUXEN |
+ FMC_BCRx_MTYP |
+ FMC_BCRx_MWID |
+ FMC_BCRx_FACCEN |
+ FMC_BCRx_BURSTEN |
+ FMC_BCRx_WAITPOL |
+ FMC_BCRx_WAITCFG |
+ FMC_BCRx_WREN |
+ FMC_BCRx_WAITEN |
+ FMC_BCRx_EXTMOD |
+ FMC_BCRx_ASYNCWAIT |
+ FMC_BCRx_CBURSTRW);
+
+ mask |= FMC_BCR1_CCLKEN;
+ mask |= FMC_BCR1_WFDIS;
+ mask |= FMC_BCRx_CPSIZE;
+
+ MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
@@ -556,6 +562,9 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FMC_NAND_BANK(Bank));
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
@@ -583,6 +592,9 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FMC_NAND_BANK(Bank));
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
@@ -608,6 +620,9 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
__FMC_NAND_DISABLE(Device, Bank);
/* De-initialize the NAND Bank */
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
/* Set the FMC_NAND_BANK3 registers to their reset values */
WRITE_REG(Device->PCR, 0x00000018U);
WRITE_REG(Device->SR, 0x00000040U);
@@ -650,6 +665,9 @@ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
assert_param(IS_FMC_NAND_BANK(Bank));
/* Enable ECC feature */
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
SET_BIT(Device->PCR, FMC_PCR_ECCEN);
return HAL_OK;
@@ -669,6 +687,9 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
assert_param(IS_FMC_NAND_BANK(Bank));
/* Disable ECC feature */
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
return HAL_OK;
@@ -706,6 +727,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui
}
}
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ UNUSED(Bank);
+
/* Get the ECCR register value */
*ECCval = (uint32_t)Device->ECCR;
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c
index 30f8662a28..773ee0a68e 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c
@@ -220,8 +220,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
if (currentpin != 0x00000000U)
{
- /* Pin Mode configuration */
- LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
@@ -230,6 +228,13 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
/* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+
+ /* Check Output mode parameters */
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+
}
/* Pull-up Pull down resistor configuration*/
@@ -240,7 +245,7 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
/* Check Alternate parameter */
assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
- /* Speed mode configuration */
+ /* Alternate function configuration */
if (currentpin < LL_GPIO_PIN_8)
{
LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
@@ -250,19 +255,13 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
}
+
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
}
pinpos++;
}
- if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
- {
- /* Check Output mode parameters */
- assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
-
- /* Output mode configuration*/
- LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
-
- }
return (SUCCESS);
}
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c
index 139764c54e..ff1ee656cc 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c
@@ -226,25 +226,25 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
/* Save LPTIM source clock */
switch ((uint32_t)LPTIMx)
{
- case LPTIM1_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
- break;
- case LPTIM2_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
- break;
+ case LPTIM1_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
+ break;
+ case LPTIM2_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
+ break;
#if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5)
- case LPTIM3_BASE:
- case LPTIM4_BASE:
- case LPTIM5_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE);
- break;
+ case LPTIM3_BASE:
+ case LPTIM4_BASE:
+ case LPTIM5_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE);
+ break;
#elif defined(LPTIM3)
- case LPTIM3_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE);
- break;
+ case LPTIM3_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE);
+ break;
#endif /* LPTIM3 && LPTIM4 && LPTIM5 */
- default:
- break;
+ default:
+ break;
}
/* Save LPTIM configuration registers */
@@ -265,25 +265,25 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)LPTIMx)
{
- case LPTIM1_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
- break;
- case LPTIM2_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK4);
- break;
+ case LPTIM1_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
+ break;
+ case LPTIM2_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK4);
+ break;
#if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5)
- case LPTIM3_BASE:
- case LPTIM4_BASE:
- case LPTIM5_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE_PCLK4);
- break;
+ case LPTIM3_BASE:
+ case LPTIM4_BASE:
+ case LPTIM5_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE_PCLK4);
+ break;
#elif defined(LPTIM3)
- case LPTIM3_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK4);
- break;
+ case LPTIM3_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK4);
+ break;
#endif /* LPTIM3 && LPTIM4 && LPTIM5*/
- default:
- break;
+ default:
+ break;
}
if (tmpCMP != 0UL)
@@ -296,7 +296,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ }
+ while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
}
@@ -311,7 +312,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ }
+ while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_ARROK(LPTIMx);
}
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c
index 30e3be71a7..a11ca8368a 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c
@@ -338,7 +338,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
+ TIM_InitStruct->RepetitionCounter = 0x00000000U;
}
/**
diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c
index a4836fd994..a039e79811 100644
--- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c
+++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c
@@ -224,8 +224,6 @@
* @{
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
-static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency);
-static ErrorStatus UTILS_SetFlashLatency(uint32_t latency);
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
static ErrorStatus UTILS_IsPLLsReady(void);
/**
@@ -341,7 +339,7 @@ void LL_mDelay(uint32_t Delay)
(++) +----------------------------------------------------------------------------+
#else
- (+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 140 MHz.
+ (+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 280 MHz.
(+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 140 MHz.
@endverbatim
@internal
@@ -399,14 +397,6 @@ void LL_SetSystemCoreClock(uint32_t CPU_Frequency)
{
/* HCLK clock frequency */
SystemCoreClock = CPU_Frequency;
-
- /* Update the SystemD2Clock global variable */
-#if defined(RCC_D1CFGR_HPRE)
- SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
-#else
- SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
-#endif
-
}
/**
@@ -505,7 +495,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS
* @note Function is based on the following formula:
* - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
- * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+ * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(*) (PLLVCO_output = PLLVCO_input * PLLN)
* - PLLP: ensure that max frequency at 400000000 Hz or 280000000 Hz(*) is reached (PLLVCO_output / PLLP)
* @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
* @param HSEBypass This parameter can be one of the following values:
@@ -609,36 +599,24 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa
*/
/**
- * @}
- */
-
-/** @addtogroup UTILS_LL_Private_Functions
- * @{
- */
-
-/**
- * @brief Calculate and check the Flash wait states number according to the
- new HCLK frequency and current voltage range.
+ * @brief Update number of Flash wait states in line with new frequency and current
+ voltage range.
* @param HCLK_Frequency HCLK frequency
- * @param latency This parameter can be one of the following values:
- * @arg @ref LL_FLASH_LATENCY_0
- * @arg @ref LL_FLASH_LATENCY_1
- * @arg @ref LL_FLASH_LATENCY_2
- * @arg @ref LL_FLASH_LATENCY_3
- * @arg @ref LL_FLASH_LATENCY_4
- * @arg @ref LL_FLASH_LATENCY_5
- * @arg @ref LL_FLASH_LATENCY_6
- * @arg @ref LL_FLASH_LATENCY_7
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
-static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t *latency)
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
{
ErrorStatus status = SUCCESS;
+ uint32_t timeout;
+ uint32_t getlatency;
+ uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
+
+
/* Frequency cannot be equal to 0 */
- if(HCLK_Frequency == 0U)
+ if (HCLK_Frequency == 0U)
{
status = ERROR;
}
@@ -650,37 +628,36 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
if((HCLK_Frequency > UTILS_SCALE0_LATENCY5_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY6_FREQ))
{
/* 264 < HCLK <= 280 => 6WS (7 CPU cycles) */
- *latency = LL_FLASH_LATENCY_6;
+ latency = LL_FLASH_LATENCY_6;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ))
{
/* 220 < HCLK <= 264 => 5WS (6 CPU cycles) */
- *latency = LL_FLASH_LATENCY_5;
+ latency = LL_FLASH_LATENCY_5;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ))
{
/* 176 < HCLK <= 220 => 4WS (5 CPU cycles) */
- *latency = LL_FLASH_LATENCY_4;
+ latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ))
{
/* 132 < HCLK <= 176 => 3WS (4 CPU cycles) */
- *latency = LL_FLASH_LATENCY_3;
+ latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ))
{
/* 88 < HCLK <= 132 => 2WS (3 CPU cycles) */
- *latency = LL_FLASH_LATENCY_2;
+ latency = LL_FLASH_LATENCY_2;
}
else if((HCLK_Frequency > UTILS_SCALE0_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ))
{
/* 44 < HCLK <= 88 => 1WS (2 CPU cycles) */
- *latency = LL_FLASH_LATENCY_1;
+ latency = LL_FLASH_LATENCY_1;
}
else if(HCLK_Frequency <= UTILS_SCALE0_LATENCY0_FREQ)
{
- /* HCLK <= 44 => 0WS (1 CPU cycles) */
- *latency = LL_FLASH_LATENCY_0;
+ /* HCLK <= 44 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
}
else
{
@@ -692,17 +669,17 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ))
{
/* 210 < HCLK <= 225 => 5WS (6 CPU cycles) */
- *latency = LL_FLASH_LATENCY_5;
+ latency = LL_FLASH_LATENCY_5;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ))
{
/* 168 < HCLK <= 210 => 4WS (5 CPU cycles) */
- *latency = LL_FLASH_LATENCY_4;
+ latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ))
{
/* 126 < HCLK <= 168 => 3WS (4 CPU cycles) */
- *latency = LL_FLASH_LATENCY_3;
+ latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
#else
@@ -712,17 +689,16 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
#endif /*POWER_DOMAINS_NUMBER == 2U*/
{
/* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */
- *latency = LL_FLASH_LATENCY_2;
+ latency = LL_FLASH_LATENCY_2;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ))
{
/* 70 < HCLK <= 140 => 1WS (2 CPU cycles) */
- *latency = LL_FLASH_LATENCY_1;
+ latency = LL_FLASH_LATENCY_1;
}
else if(HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ)
{
- /* HCLK <= 70 => 0WS (1 CPU cycles) */
- *latency = LL_FLASH_LATENCY_0;
+ /* HCLK <= 70 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
}
else
{
@@ -735,7 +711,7 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY4_FREQ))
{
/* 136 < HCLK <= 160 => 4WS (5 CPU cycles) */
- *latency = LL_FLASH_LATENCY_4;
+ latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
#else
@@ -743,22 +719,21 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
#endif /*POWER_DOMAINS_NUMBER == 2U*/
{
/* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */
- *latency = LL_FLASH_LATENCY_3;
+ latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
{
/* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */
- *latency = LL_FLASH_LATENCY_2;
+ latency = LL_FLASH_LATENCY_2;
}
else if((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ))
{
/* 55 < HCLK <= 110 => 1WS (2 CPU cycles) */
- *latency = LL_FLASH_LATENCY_1;
+ latency = LL_FLASH_LATENCY_1;
}
else if(HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ)
{
- /* HCLK <= 55 => 0WS (1 CPU cycles) */
- *latency = LL_FLASH_LATENCY_0;
+ /* HCLK <= 55 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
}
else
{
@@ -771,7 +746,7 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ))
{
/* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */
- *latency = LL_FLASH_LATENCY_4;
+ latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
#else
@@ -779,55 +754,62 @@ static ErrorStatus UTILS_CalculateFlashLatency(uint32_t HCLK_Frequency, uint32_t
#endif /*POWER_DOMAINS_NUMBER == 3U*/
{
/* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */
- *latency = LL_FLASH_LATENCY_3;
+ latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
{
/* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */
- *latency = LL_FLASH_LATENCY_2;
+ latency = LL_FLASH_LATENCY_2;
}
else if((HCLK_Frequency > UTILS_SCALE3_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ))
{
/* 45 < HCLK <= 90 => 1WS (2 CPU cycles) */
- *latency = LL_FLASH_LATENCY_1;
+ latency = LL_FLASH_LATENCY_1;
}
else if(HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ)
{
- /* HCLK <= 45 => 0WS (1 CPU cycles) */
- *latency = LL_FLASH_LATENCY_0;
+ /* HCLK <= 45 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
}
else
{
status = ERROR;
}
}
+
+ if(status == SUCCESS)
+ {
+ LL_FLASH_SetLatency(latency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ timeout = 2;
+ do
+ {
+ /* Wait for Flash latency to be updated */
+ getlatency = LL_FLASH_GetLatency();
+ timeout--;
+ } while ((getlatency != latency) && (timeout > 0U));
+
+ if(getlatency != latency)
+ {
+ status = ERROR;
+ }
+ }
+
}
return status;
}
+
/**
- * @brief Update number of Flash wait states
- * @param latency Flash Latency
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Latency has been modified
- * - ERROR: Latency cannot be modified
+ * @}
*/
-static ErrorStatus UTILS_SetFlashLatency(uint32_t latency)
-{
- ErrorStatus status = SUCCESS;
- LL_FLASH_SetLatency(latency);
+/** @addtogroup UTILS_LL_Private_Functions
+ * @{
+ */
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if(LL_FLASH_GetLatency() != latency)
- {
- status = ERROR;
- }
-
- return status;
-}
/**
* @brief Function to check that PLL can be modified
@@ -896,8 +878,8 @@ static ErrorStatus UTILS_IsPLLsReady(void)
*/
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
- ErrorStatus status;
- uint32_t new_hclk_frequency, new_latency;
+ ErrorStatus status = SUCCESS;
+ uint32_t new_hclk_frequency;
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider));
assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
@@ -909,63 +891,72 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_
/* Calculate the new HCLK frequency */
new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
- /* Calculate the new FLASH latency according to the new HCLK frequency */
- status = UTILS_CalculateFlashLatency(new_hclk_frequency, &new_latency);
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if (SystemD2Clock < new_hclk_frequency)
+ {
+ /* Set FLASH latency to highest latency */
+ status = LL_SetFlashLatency(new_hclk_frequency);
+ }
+ /* Update system clock configuration */
if(status == SUCCESS)
{
- /* Increasing the number of wait states because of higher CPU frequency */
- if(LL_FLASH_GetLatency() < new_latency)
+ /* Enable PLL */
+ LL_RCC_PLL1_Enable();
+ while (LL_RCC_PLL1_IsReady() != 1U)
{
- status = UTILS_SetFlashLatency(new_latency);
+ /* Wait for PLL ready */
}
- /* Update system clock configuration */
- if(status == SUCCESS)
- {
- /* Enable PLL */
- LL_RCC_PLL1_Enable();
- while (LL_RCC_PLL1_IsReady() != 1U)
- {
- /* Wait for PLL ready */
- }
-
- /* Set All APBxPrescaler to the Highest Divider */
- LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
- LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
- LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
- LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
-
- /* Set SYS prescaler*/
- LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
-
- /* Set AHB prescaler*/
- LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ /* Set All APBxPrescaler to the Highest Divider */
+ LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
+ LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
+ LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
+ LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
- /* Sysclk activation on the main PLL */
- LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
- while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
- {
- /* Wait for system clock switch to PLL */
- }
+ /* Set SYS prescaler*/
+ LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
- /* Set APBn prescaler*/
- LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
- LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
- LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
- LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
+ /* Set AHB prescaler*/
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
- /* Update SystemCoreClock variable */
- LL_SetSystemCoreClock(SYSCLK_Frequency);
+ /* Sysclk activation on the main PLL */
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
+ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
+ {
+ /* Wait for system clock switch to PLL */
}
+ /* Set APBn prescaler*/
+ LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+ LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+ LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
+ LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
+
/* Decreasing the number of wait states because of lower CPU frequency */
- if(LL_FLASH_GetLatency() > new_latency)
+ if (SystemD2Clock > new_hclk_frequency)
{
- status = UTILS_SetFlashLatency(new_latency);
+ /* Set FLASH latency to lowest latency */
+ status = LL_SetFlashLatency(new_hclk_frequency);
}
+
+ /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+ SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+ SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+
+ /* Update SystemCoreClock variable */
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ LL_SetSystemCoreClock(SystemD2Clock);
+#else
+ LL_SetSystemCoreClock(SYSCLK_Frequency);
+#endif /* DUAL_CORE && CORE_CM4 */
+
}
+
return status;
}
diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md
index bb74fc0c96..7417c0aea4 100644
--- a/system/Drivers/STM32YYxx_HAL_Driver_version.md
+++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md
@@ -8,7 +8,7 @@
* STM32F7: 1.2.7
* STM32G0: 1.3.0
* STM32G4: 1.1.1
- * STM32H7: 1.7.0
+ * STM32H7: 1.8.0
* STM32L0: 1.10.2
* STM32L1: 1.4.0
* STM32L4: 1.11.1
diff --git a/system/STM32H7xx/system_stm32h7xx.c b/system/STM32H7xx/system_stm32h7xx.c
index 5af504250d..42400ed61f 100644
--- a/system/STM32H7xx/system_stm32h7xx.c
+++ b/system/STM32H7xx/system_stm32h7xx.c
@@ -2,9 +2,7 @@
******************************************************************************
* @file system_stm32h7xx.c
* @author MCD Application Team
- * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
- * This provides system initialization template function is case of
- * an application using a single core STM32H7 device
+ * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
@@ -12,7 +10,7 @@
* before branch to main program. This call is made inside
* the "startup_stm32h7xx.s" file.
*
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * - SystemCoreClock variable: Contains the core clock, it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
@@ -67,7 +65,7 @@
*/
/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM */
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
/* #define DATA_IN_D2_SRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
@@ -149,6 +147,7 @@ void SystemInit (void)
/* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= 0xEAF6ED7FU;
+#if defined(D3_SRAM_BASE)
/* Reset D1CFGR register */
RCC->D1CFGR = 0x00000000;
@@ -157,7 +156,16 @@ void SystemInit (void)
/* Reset D3CFGR register */
RCC->D3CFGR = 0x00000000;
+#else
+ /* Reset CDCFGR1 register */
+ RCC->CDCFGR1 = 0x00000000;
+
+ /* Reset CDCFGR2 register */
+ RCC->CDCFGR2 = 0x00000000;
+ /* Reset SRDCFGR register */
+ RCC->SRDCFGR = 0x00000000;
+#endif
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x00000000;
@@ -186,27 +194,48 @@ void SystemInit (void)
/* Disable all interrupts */
RCC->CIER = 0x00000000;
+#if (STM32H7_DEV_ID == 0x450UL)
+ /* dual core CM7 or single core line */
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{
/* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U;
}
+#endif
#if defined (DATA_IN_D2_SRAM)
- /* in case of initialized data in D2 SRAM , enable the D2 SRAM clock */
+ /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+#elif defined(RCC_AHB2ENR_D2SRAM2EN)
+ RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+#else
+ RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+
tmpreg = RCC->AHB2ENR;
(void) tmpreg;
#endif /* DATA_IN_D2_SRAM */
- /* Configure the Vector Table location add offset address ------------------*/
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif /* VECT_TAB_SRAM */
+
+#else
+
+ /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
#ifdef VECT_TAB_SRAM
- SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+ SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
#else
SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
+#endif /*DUAL_CORE && CORE_CM4*/
}
@@ -250,22 +279,24 @@ void SystemInit (void)
void SystemCoreClockUpdate (void)
{
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+ uint32_t common_system_clock;
float_t fracn1, pllvco;
+
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
- SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
break;
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
- SystemCoreClock = CSI_VALUE;
+ common_system_clock = CSI_VALUE;
break;
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
- SystemCoreClock = HSE_VALUE;
+ common_system_clock = HSE_VALUE;
break;
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
@@ -302,29 +333,48 @@ void SystemCoreClockUpdate (void)
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
- SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
+ common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
}
else
{
- SystemCoreClock = 0U;
+ common_system_clock = 0U;
}
break;
default:
- SystemCoreClock = CSI_VALUE;
+ common_system_clock = CSI_VALUE;
break;
}
/* Compute SystemClock frequency --------------------------------------------------*/
+#if defined (RCC_D1CFGR_D1CPRE)
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
- /* SystemCoreClock frequency : CM7 CPU frequency */
- SystemCoreClock >>= tmp;
+ /* common_system_clock frequency : CM7 CPU frequency */
+ common_system_clock >>= tmp;
+
+ /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#else
+ tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+
+ /* common_system_clock frequency : CM7 CPU frequency */
+ common_system_clock >>= tmp;
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
- SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
}
+
/**
* @}
*/