From 1bbc34abbd5751b4cb9947af90cd2bbee55c18f7 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 6 May 2020 14:55:15 +0200 Subject: [PATCH 1/2] [L4] Update STM32L4xx HAL Drivers to v1.11.1 Included in STM32CubeL4 FW v1.15.1 Signed-off-by: Frederic Pillon --- .../Inc/stm32l4xx_hal_cortex.h | 28 +- .../Inc/stm32l4xx_hal_rtc_ex.h | 1 - .../Inc/stm32l4xx_hal_smbus.h | 8 +- .../Inc/stm32l4xx_ll_cortex.h | 28 +- .../Inc/stm32l4xx_ll_utils.h | 1 + .../STM32L4xx_HAL_Driver/Release_Notes.html | 124 ++++-- .../STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c | 2 +- .../Src/stm32l4xx_hal_cortex.c | 50 +-- .../Src/stm32l4xx_hal_gpio.c | 40 +- .../Src/stm32l4xx_hal_i2c.c | 228 ++++++++--- .../Src/stm32l4xx_hal_mmc.c | 42 +- .../Src/stm32l4xx_hal_sd.c | 14 +- .../Src/stm32l4xx_hal_smbus.c | 32 +- .../Src/stm32l4xx_ll_utils.c | 368 ++++++++++-------- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 15 files changed, 563 insertions(+), 405 deletions(-) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h index 785cf797ee..7dc071f58e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h index 9123bf2cbd..171a4bf812 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h @@ -1594,7 +1594,6 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupReg /** @defgroup RTCEx_Private_Constants RTCEx Private Constants * @{ */ -//#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM18 /*!< External interrupt line 18 Connected to the RTC Alarm event */ #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) #define RTC_EXTI_LINE_SSRU_EVENT EXTI_IMR1_IM18 /*!< External interrupt line 18 Connected to the RTC SSR Underflow event */ #endif diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h index 9871c85dfa..66fad3a30f 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h @@ -132,7 +132,11 @@ typedef struct * @brief SMBUS handle Structure definition * @{ */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) typedef struct __SMBUS_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ { I2C_TypeDef *Instance; /*!< SMBUS registers base address */ @@ -326,6 +330,7 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) @@ -582,11 +587,12 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t ((REQUEST) == SMBUS_NO_STARTSTOP)) -#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ ((REQUEST) == SMBUS_FIRST_FRAME) || \ ((REQUEST) == SMBUS_NEXT_FRAME) || \ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h index 0a84990b59..2cb0a8891c 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h @@ -21,29 +21,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h index 5db2e3a84b..bb0f3b8690 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h +++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h @@ -297,6 +297,7 @@ void LL_mDelay(uint32_t Delay); */ void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency); ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html index 31e2183283..bc56f54779 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html @@ -46,10 +46,57 @@

Purpose

Update History

- +

Main Changes

    +
  • Patch release of HAL and Low Layer drivers to include latest corrections
    • +
+

Contents

+

HAL drivers changes

+
    +
  • HAL GPIO driver +
      +
    • Update HAL_GPIO_Init() initialization sequence to modify the order of GPIO registers update
      • +
    • +
  • HAL I2C driver +
      +
    • Update I2C_Enable_IRQ() function to remove incorrect interrupts enable when InterruptRequest = I2C_XFER_CPLT_IT
      • +
    • Update I2C_DMAXferCplt(), I2C_DMAError() and I2C_DMAAbort() functions to avoid null pointer exceptions
      • +
    • Update HAL_I2C_Master_Seq_Transmit/Receive_IT/DMA() functions to set correct condition range
      • +
    • Update I2C_ITMasterCplt() to remove C++ compilation warning due to unused variable
      • +
    • +
  • HAL RTC driver +
      +
    • Correct MISRA C:2012-Rule-3.1 warning in RTC driver
      • +
    • +
  • HAL SDMMC driver +
      +
    • Update MMC_InitCard() function to add missing correction for eMMC card size computation issue
      • +
    • Update SD_UltraHighSpeed() and SD_DDR_Mode() functions to remove useless assignment
      • +
    • Correct MISRA C:2012 warnings in SDMMC driver (rules 10.4_a, 10.7, 13.5, 15.7, 2.2_c)
      • +
    • +
  • HAL SMBUS driver +
      +
    • Update IS_SMBUS_TRANSFER_OPTIONS_REQUEST macro definition to include transfers with PEC
      • +
    • Correct MISRA C:2012-Rule-2.4 warning in structure __SMBUS_HandleTypeDef definition
      • +
    • +
+

LL drivers changes

+
    +
  • LL UTILS driver +
      +
    • Change private UTILS_SetFlashLatency() function into LL_SetFlashLatency() public function
      • +
    • Update LL_PLL_ConfigSystemClock_MSI/HSI/HSE() functions to set expected AHB prescaler value
      • +
    • +
+
+
+
+ +
+

Main Changes

+
  • Release of HAL and Low Layer drivers to add support of STM32L4P5xx/STM32L4Q5xx devices
    • New PKA and PSSI peripherals supported in new HAL/LL PKA and HAL PSSI drivers
      • @@ -58,6 +105,7 @@

      Main Changes

    • Correction of several issues applicable to other devices
    +

    Contents

    HAL drivers changes

    • HAL driver @@ -397,10 +445,11 @@

      Main Changes

      -

      Main Changes

      +

      Main Changes

      • Delivery of the new HAL MMC driver
      +

      Contents

      HAL drivers changes

      • HAL ADC driver @@ -688,12 +737,13 @@

        Main Changes

        -

        Main Changes

        +

        Main Changes

        • Release of HAL and Low Layer drivers to add support of STM32L412xx/STM32L422xx
        • Superset features device STM32L422xx API User Manual available (STM32L422xx_User_Manual.chm)  
        • MISRA C:2012 corrections
        +

        Contents

        HAL drivers changes

        MISRA C:2012 corrections listed hereafter are applicable to LL driver as well.

          @@ -879,7 +929,7 @@

          Main Changes

          -

          Main Changes

          +

          Main Changes

          Maintenance Release of HAL and Low Layer drivers

          Add support of HAL callback registration feature

            @@ -889,6 +939,7 @@

            Main Changes

          • Once enabled, the user application may resort to HAL_PPP_RegisterCallback() to register specific callback function(s) and unregister it(them) with HAL_PPP_UnRegisterCallback().

          MISRAC-2012 corrections

          +

          Contents

          HAL drivers changes

          • HAL generic driver

            @@ -1236,10 +1287,11 @@

            Main Changes

            -

            Main Changes

            +

            Main Changes

            • Maintenance Release of HAL and Low Layer drivers
            +

            Contents

            HAL drivers changes

            • HAL CAN driver
              • @@ -1317,10 +1369,11 @@

              Main Changes

              -

              Main Changes

              +

              Main Changes

              • Maintenance Release of HAL and Low Layer drivers
              +

              Contents

              HAL drivers changes

              • HAL generic driver

                @@ -1398,13 +1451,14 @@

                Main Changes

                -

                Main Changes

                +

                Main Changes

                • Release of HAL and Low Layer drivers to add support of STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx devices

                • New OctoSPI, DSI, LTDC, GFXMMU peripherals supported in new HAL OSPI, HAL DSI, HAL LTDC and HAL GFXMMU drivers

                • Superset features device STM32L4S9xx API User Manual available (STM32L4S9xx_User_Manual.chm)  

                -

                    HAL drivers changes

                +

                    ## Contents

                +

                HAL drivers changes

                • HAL DSI driver (NEW): stm32l4xx_hal_dsi.h/.c files
                • HAL GFXMMU driver (NEW):stm32l4xx_hal_gfxmmu.h/.c files
                  • @@ -1654,10 +1708,11 @@

                  Main Changes

                  -

                  Main Changes

                  +

                  Main Changes

                  • Maintenance Release of HAL and Low Layer drivers
                  +

                  Contents

                  HAL drivers changes

                  • HAL CAN driver

                    @@ -1709,10 +1764,11 @@

                    Main Changes

                    -

                    Main Changes

                    +

                    Main Changes

                    • Maintenance Release of HAL and Low Layer drivers
                    +

                    Contents

                    HAL drivers changes

                    • HAL generic driver

                      @@ -1752,7 +1808,7 @@

                      Main Changes

                      -

                      Main Changes

                      +

                      Main Changes

                      • Release of HAL and Low Layer drivers to add support of STM32L496xx/STM32L4A6xx devices
                      • New DCMI, DMA2D, HASH peripherals supported in new HAL DCMI, HAL & LL DMA2D and HAL HASH drivers
                        • @@ -1761,6 +1817,7 @@

                        Main Changes

                      • Superset features device STM32L4A6xx API User Manual available (STM32L4A6xx_User_Manual.chm) 
                      +

                      Contents

                      HAL drivers changes

                      • HAL DCMI driver (NEW): stm32l4xx_hal_dcmi.h/.c files
                        • @@ -1860,11 +1917,12 @@

                        Main Changes

                        -

                        Main Changes

                        +

                        Main Changes

                        • Release of HAL and Low Layer drivers to add support of STM32L451xx/STM32L452xx/STM32L462xx devices
                        • Superset features device STM32L462xx API User Manual available (STM32L462xx_User_Manual.chm)
                        +

                        Contents

                        HAL drivers changes

                        • HAL CRYP driver

                          @@ -1924,6 +1982,7 @@

                          Main Changes

                          +

                          Contents

                          HAL drivers changes

                          • HAL ADC driver

                            @@ -2015,6 +2074,7 @@

                            Main Changes

                            +

                            Contents

                            HAL drivers changes

                            • HAL ADC driver

                              @@ -2042,10 +2102,11 @@

                              Main Changes

                              -

                              Main Changes

                              +

                              Main Changes

                              • Maintenance Release of HAL and Low Layer drivers
                              +

                              Contents

                              HAL drivers changes

                              Enhance HAL delay and timebase implementation

                                @@ -2225,7 +2286,7 @@

                                Main Changes

                              • Update initialization sequence in voltage class B
                            -

                            HAL drivers changes

                            +

                            LL drivers changes

                            • LL ADC driver
                                @@ -2291,7 +2352,7 @@

                                Main Changes

                                -

                                Main Changes

                                +

                                Main Changes

                                • Release of HAL and Low Layer drivers to add support of STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx devices
                                • Low Layer driver initialization/de-initialization APIs applicable to all STM32L4xx devices
                                  • @@ -2299,6 +2360,7 @@

                                  Main Changes

                                • Superset features device STM32L443xx API User Manual available (STM32L443xx_User_Manual.chm) 
                                +

                                Contents

                                HAL drivers changes

                                • HAL generic update

                                  @@ -2315,9 +2377,11 @@

                                  Main Changes

                              LL drivers changes

                              -

                              New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs

                                -

                              • stm32l4xx_ll_crs.c

                                • +
                              • New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs +
                                  +
                                • stm32l4xx_ll_crs.c
                                  • +
                              • LL BUS update
                                • Add read-back register on clock enable functions to take into account any delay on bus
                                  • @@ -2360,15 +2424,20 @@

                                  Main Changes

                                  -

                                  Main Changes

                                  -

                                  New Low Layer driver initialization/de-initialization APIs

                                  -

                                  Naming rule is LL_PPP_Init(), LL_PPP_StructInit(), LL_PPP_DeInit() and more initialization APIs when applicable for peripheral PPP: ADC, COMP, CRC, DAC, DMA, EXTI, GPIO, I2C, LPTIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, SWPMI, TIM and USART. 

                                  -

                                  New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs

                                  +

                                  Main Changes

                                  +
                                    +
                                  • New Low Layer driver initialization/de-initialization APIs +
                                      +
                                    • Naming rule is LL_PPP_Init(), LL_PPP_StructInit(), LL_PPP_DeInit() and more initialization APIs when applicable for peripheral PPP: ADC, COMP, CRC, DAC, DMA, EXTI, GPIO, I2C, LPTIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, SWPMI, TIM and USART. 
                                      • +
                                    • +
                                  • New C files requiring to use USE_FULL_LL_DRIVER compilation switch in user project to benefit from new APIs
                                    • stm32l4xx_ll_adc.c, stm32l4xx_ll_comp.c, stm32l4xx_ll_crc.c, stm32l4xx_ll_dac.c, stm32l4xx_ll_dma.c, stm32l4xx_ll_exti.c, stm32l4xx_ll_gpio.c, stm32l4xx_ll_i2c.c, stm32l4xx_ll_lptim.c, stm32l4xx_ll_lpuart.c, stm32l4xx_ll_opamp.c, stm32l4xx_ll_pwr.c, stm32l4xx_ll_rcc.c, stm32l4xx_ll_rng.c, stm32l4xx_ll_rtc.c, stm32l4xx_ll_spi.c, stm32l4xx_ll_swpmi.c, stm32l4xx_ll_tim.c and stm32l4xx_ll_usart.c
                                    • stm32l4xx_ll_utils.c contains some Low Layer utilities for SysTick, Flash latency and clock configuration. 
                                      • +
                                    • +
                                  • Fix "parameter unused" GCC compilation warnings on __weak functions
                                  -

                                  Fix "parameter unused" GCC compilation warnings on __weak functions

                                  +

                                  Contents

                                  HAL drivers changes

                                  • HAL generic update

                                    @@ -2516,7 +2585,7 @@

                                    Main Changes

                                    -

                                    Main Changes

                                    +

                                    Main Changes

                                    • HAL generic update
                                        @@ -2573,7 +2642,7 @@

                                        Main Changes

                                        -

                                        Main Changes

                                        +

                                        Main Changes

                                        • HAL generic update

                                            @@ -2603,13 +2672,16 @@

                                            Main Changes

                                            -

                                            Main Changes

                                            +

                                            Main Changes

                                            Add Low Layer drivers allowing performance and footprint optimization

                                            • Low Layer drivers APIs provide register level programming: they require deep knowledge of peripherals described in STM32L4x6 Reference Manual

                                            • Low Layer drivers are available for: ADC, COMP, Cortex, CRC, DAC, DMA, EXTI, GPIO, I2C, IWDG, LPYIM, LPUART, OPAMP, PWR, RCC, RNG, RTC, SPI, SWPMI, TIM, USART, WWDG peripherals and additionnal Low Level Bus, System and Utilities APIs.

                                            • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l4xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l4xx_ll_ppp.h file must be included in user code.

                                              • +
                                            +

                                            Contents

                                            +

                                            • HAL ADC update

                                              • Channel 5 is not usable for ADC3
                                                • @@ -2673,7 +2745,7 @@

                                                Main Changes

                                                -

                                                Main Changes

                                                +

                                                Main Changes

                                                • First official release of STM32L4xx HAL Drivers for STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx and STM32L486xx devices
                                                diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c index 5ff687dc9c..e9e30ae8fe 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c @@ -53,7 +53,7 @@ */ #define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define STM32L4XX_HAL_VERSION_SUB1 (0x0BU) /*!< [23:16] sub1 version */ -#define STM32L4XX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define STM32L4XX_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\ |(STM32L4XX_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c index b63d4f7a80..967a247f70 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c @@ -90,29 +90,13 @@ ****************************************************************************** * @attention * - *

                                                © COPYRIGHT(c) 2016 STMicroelectronics

                                                + *

                                                © Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

                                                * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -161,7 +145,7 @@ /** * @brief Set the priority grouping field (pre-emption priority and subpriority) * using the required unlock sequence. - * @param PriorityGroup The priority grouping bits length. + * @param PriorityGroup: The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, * 4 bits for subpriority @@ -188,13 +172,13 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) /** * @brief Set the priority of an interrupt. - * @param IRQn External interrupt number. + * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @param PreemptPriority The pre-emption priority for the IRQn channel. + * @param PreemptPriority: The pre-emption priority for the IRQn channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority - * @param SubPriority the subpriority level for the IRQ channel. + * @param SubPriority: the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None @@ -259,7 +243,7 @@ void HAL_NVIC_SystemReset(void) /** * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ @@ -299,7 +283,7 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void) /** * @brief Get the priority of an interrupt. - * @param IRQn External interrupt number. + * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) * @param PriorityGroup: the priority grouping bits length. @@ -314,8 +298,8 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void) * 1 bit for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, * 0 bit for subpriority - * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority: Pointer on the Subpriority value (starting from 0). * @retval None */ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) @@ -392,7 +376,7 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) /** * @brief Configure the SysTick clock source. - * @param CLKSource specifies the SysTick clock source. + * @param CLKSource: specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. @@ -435,7 +419,7 @@ __weak void HAL_SYSTICK_Callback(void) #if (__MPU_PRESENT == 1) /** * @brief Enable the MPU. - * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, * NMI, FAULTMASK and privileged accessto the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE @@ -471,7 +455,7 @@ void HAL_MPU_Disable(void) /** * @brief Initialize and configure the Region and the memory to be protected. - * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c index 412be3d444..7454bec27e 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c @@ -190,26 +190,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) if (iocurrent != 0x00u) { /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3u]; - temp &= ~(0xFu << ((position & 0x07u) * 4u)); - temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); - GPIOx->AFR[position >> 3u] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); - GPIOx->MODER = temp; - /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) @@ -249,6 +229,26 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= ((GPIO_Init->Pull) << (position * 2u)); GPIOx->PUPDR = temp; + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + GPIOx->AFR[position >> 3u] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + GPIOx->MODER = temp; + /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c index 40afa7f956..5ea8fd3a48 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c @@ -351,13 +351,13 @@ /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (0x00000001U) -#define I2C_XFER_RX_IT (0x00000002U) -#define I2C_XFER_LISTEN_IT (0x00000004U) +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ -#define I2C_XFER_ERROR_IT (0x00000011U) -#define I2C_XFER_CPLT_IT (0x00000012U) -#define I2C_XFER_RELOAD_IT (0x00000012U) +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -410,6 +410,9 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + /* Private function to flush TXDR register */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); @@ -3200,7 +3203,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3285,7 +3288,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3446,7 +3449,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3531,7 +3534,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -4251,9 +4254,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Locked */ __HAL_LOCK(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Set State at HAL_I2C_STATE_ABORT */ hi2c->State = HAL_I2C_STATE_ABORT; @@ -5001,6 +5016,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hi2c); @@ -5079,8 +5095,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -5369,9 +5401,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ @@ -5426,19 +5476,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -5447,12 +5514,17 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + /* Flush TX register */ I2C_Flush_TXDR(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); - /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; @@ -5466,6 +5538,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5500,6 +5573,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5546,12 +5620,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -5565,6 +5653,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if (hi2c->hdmatx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); @@ -5572,6 +5663,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if (hi2c->hdmarx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); @@ -5608,7 +5702,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -5631,6 +5724,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5646,6 +5740,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5660,6 +5755,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5733,6 +5829,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; @@ -5752,7 +5849,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = I2C_Slave_ISR_IT; } else @@ -5767,16 +5863,19 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } - if (hi2c->hdmatx != NULL) + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5792,13 +5891,20 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } /* Abort DMA RX transfer if any */ - else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } - if (hi2c->hdmarx != NULL) + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5814,10 +5920,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } - else if (hi2c->State == HAL_I2C_STATE_ABORT) + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5831,6 +5955,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } else { + hi2c->PreviousState = I2C_STATE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -6041,30 +6167,16 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if (hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->hdmatx != NULL) { - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AbortCpltCallback(hi2c); -#else - HAL_I2C_AbortCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmatx->XferAbortCallback = NULL; } - else + if (hi2c->hdmarx != NULL) { - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ErrorCallback(hi2c); -#else - HAL_I2C_ErrorCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmarx->XferAbortCallback = NULL; } + + I2C_TreatErrorCallback(hi2c); } /** @@ -6341,19 +6453,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -6379,7 +6491,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; @@ -6433,19 +6545,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_mmc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_mmc.c index 2085432aec..d52f6db8ea 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_mmc.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_mmc.c @@ -2532,7 +2532,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { case SDMMC_SPEED_MODE_AUTO: { - if (((device_type & 0x04U) != 0U) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U)) + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U)) { /* High Speed DDR mode allowed */ errorstate = MMC_HighSpeed(hmmc, ENABLE); @@ -2558,11 +2558,15 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 hmmc->ErrorCode |= errorstate; } } + else + { + /* Nothing to do : keep current speed */ + } break; } case SDMMC_SPEED_MODE_DDR: { - if (((device_type & 0x04U) != 0U) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U)) + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U)) { /* High Speed DDR mode allowed */ errorstate = MMC_HighSpeed(hmmc, ENABLE); @@ -3022,9 +3026,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) HAL_MMC_CardCSDTypeDef CSD; uint32_t errorstate; uint16_t mmc_rca = 1U; -#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) MMC_InitTypeDef Init; -#endif /* Check the power State */ if(SDMMC_GetPowerState(hmmc->Instance) == 0U) @@ -3077,23 +3079,6 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Get the Card Class */ hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U); -#if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) - /* Get CSD parameters */ - if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK) - { - return hmmc->ErrorCode; - } - - /* Select the Card */ - errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) - { - return errorstate; - } - - /* Configure SDMMC peripheral interface */ - (void)SDMMC_Init(hmmc->Instance, hmmc->Init); -#else /* Select the Card */ errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); if(errorstate != HAL_MMC_ERROR_NONE) @@ -3121,7 +3106,6 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl; Init.ClockDiv = hmmc->Init.ClockDiv; (void)SDMMC_Init(hmmc->Instance, Init); -#endif /* All cards are initialized */ return HAL_MMC_ERROR_NONE; @@ -3274,7 +3258,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel tmp_data = SDMMC_ReadFIFO(hmmc->Instance); /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */ - if ((i + count) == (FieldIndex/4)) + if ((i + count) == ((uint32_t)FieldIndex/4U)) { *pFieldData = tmp_data; } @@ -3395,16 +3379,16 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) { uint32_t errorstate = HAL_MMC_ERROR_NONE; - uint32_t response = 0U, count = 0U; + uint32_t response, count; SDMMC_InitTypeDef Init; - if ((state == DISABLE) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U)) + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE)) { /* Index : 185 - Value : 0 */ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U); } - if ((state != DISABLE) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U)) + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE)) { /* Index : 185 - Value : 1 */ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U); @@ -3479,9 +3463,9 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) { uint32_t errorstate = HAL_MMC_ERROR_NONE; - uint32_t response = 0U, count = 0U; + uint32_t response, count; - if ((state == DISABLE) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U)) + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE)) { if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U) { @@ -3495,7 +3479,7 @@ static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) } } - if ((state != DISABLE) && ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U)) + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) && (state != DISABLE)) { if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U) { diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c index 37ef756b24..2a00821593 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c @@ -3556,8 +3556,6 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Clean Status flags */ hsd->Instance->ICR = 0xFFFFFFFFU; } - - hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; } } #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ @@ -3732,7 +3730,7 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) */ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) { - uint32_t scr[2U] = {0U, 0U}; + uint32_t scr[2U] = {0UL, 0UL}; uint32_t errorstate; if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) @@ -3779,7 +3777,7 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) */ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) { - uint32_t scr[2U] = {0U, 0U}; + uint32_t scr[2U] = {0UL, 0UL}; uint32_t errorstate; if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) @@ -3832,7 +3830,7 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); uint32_t index = 0U; - uint32_t tempscr[2U] = {0U, 0U}; + uint32_t tempscr[2U] = {0UL, 0UL}; uint32_t *scr = pSCR; /* Set Block Size To 8 Bytes */ @@ -4086,8 +4084,6 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - errorstate = 0; - return errorstate; } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) @@ -4201,8 +4197,6 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - errorstate = 0; - return errorstate; } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) @@ -4332,8 +4326,6 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - errorstate = 0; - return errorstate; } else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c index 29618a0974..fa269e9beb 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c @@ -203,18 +203,18 @@ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); -static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); -static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /** * @} */ @@ -1801,7 +1801,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { uint16_t DevAddress; @@ -2085,7 +2085,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { uint8_t TransferDirection; uint16_t SlaveAddrCode; @@ -2341,7 +2341,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, u * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) { uint32_t tmpisr = 0UL; @@ -2381,7 +2381,7 @@ static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Inte * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) { uint32_t tmpisr = 0UL; uint32_t tmpstate = hsmbus->State; @@ -2453,7 +2453,7 @@ static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Int * @param hsmbus SMBUS handle. * @retval None */ -static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus) +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) { uint32_t itflags = READ_REG(hsmbus->Instance->ISR); uint32_t itsources = READ_REG(hsmbus->Instance->CR1); @@ -2554,7 +2554,7 @@ static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2603,7 +2603,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeD * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -2620,7 +2620,7 @@ static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t * @param hsmbus SMBUS handle. * @retval None */ -static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus) +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) { /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ /* it request implicitly to generate a restart condition */ diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c index 0f1999b45d..b1dd002362 100644 --- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c +++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c @@ -41,7 +41,8 @@ /** @addtogroup UTILS_LL_Private_Constants * @{ */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define UTILS_MAX_FREQUENCY_SCALE1 120000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ #define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ #else @@ -60,7 +61,8 @@ #define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */ /* Defines used for FLASH latency according to HCLK Frequency */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define UTILS_SCALE1_LATENCY1_FREQ 20000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ #define UTILS_SCALE1_LATENCY2_FREQ 40000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ #define UTILS_SCALE1_LATENCY3_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ @@ -143,7 +145,6 @@ */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); -static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency); static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_PLL_IsBusy(void); /** @@ -227,7 +228,7 @@ void LL_mDelay(uint32_t Delay) Depending on the device voltage range, the maximum frequency should be adapted accordingly: - (++) Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices + (++) Table 1. HCLK clock frequency for STM32L4+ Series devices (++) +--------------------------------------------------------+ (++) | Latency | HCLK clock frequency (MHz) | (++) | |--------------------------------------| @@ -247,7 +248,7 @@ void LL_mDelay(uint32_t Delay) (++) |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 | (++) +--------------------------------------------------------+ - (++) Table 2. HCLK clock frequency for other STM32L4 devices + (++) Table 2. HCLK clock frequency for STM32L4 Series devices (++) +-------------------------------------------------------+ (++) | Latency | HCLK clock frequency (MHz) | (++) | |-------------------------------------| @@ -281,6 +282,150 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency) SystemCoreClock = HCLKFrequency; } +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param HCLKFrequency HCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency) +{ + ErrorStatus status = SUCCESS; + + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + + /* Frequency cannot be equal to 0 or greater than max clock */ + if ((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE1)) + { + status = ERROR; + } + else + { + if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + { +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(HCLKFrequency > UTILS_SCALE1_LATENCY5_FREQ) + { + /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */ + latency = LL_FLASH_LATENCY_5; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ) + { + /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ) + { + /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ) + { + /* 40 < HCLK <= 20 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ) + { + /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ + } +#else + if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ) + { + /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ) + { + /* 48 < HCLK <= 64 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ) + { + /* 32 < HCLK <= 48 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ) + { + /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 16MHz default LL_FLASH_LATENCY_0 0WS */ + } +#endif + } + else /* SCALE2 */ + { +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + if(HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE2) + { + /* Unexpected HCLK > 26 */ + status = ERROR; + } + else if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ) + { + /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ) + { + /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */ + } +#else + if(HCLKFrequency > UTILS_MAX_FREQUENCY_SCALE2) + { + /* Unexpected HCLK > 26 */ + status = ERROR; + } + else if(HCLKFrequency > UTILS_SCALE2_LATENCY3_FREQ) + { + /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ) + { + /* 12 < HCLK <= 18 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ) + { + /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 6MHz default LL_FLASH_LATENCY_0 0WS */ + } +#endif + } + + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(LL_FLASH_GetLatency() != latency) + { + status = ERROR; + } + } + return status; +} + /** * @brief This function configures system clock with MSI as clock source of the PLL * @note The application needs to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled. @@ -302,7 +447,8 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS { ErrorStatus status = SUCCESS; uint32_t pllfreq, msi_range; -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) uint32_t hpre = 0U; /* Set default value */ #endif @@ -374,26 +520,34 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->PLLR); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ if(pllfreq > 80000000U) { - hpre = UTILS_ClkInitStruct->AHBCLKDivider; - if(hpre == LL_RCC_SYSCLK_DIV_1) + if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1) { UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + hpre = LL_RCC_SYSCLK_DIV_2; } } #endif /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Apply definitive AHB prescaler value if necessary */ - if((status == SUCCESS) && (hpre != 0U)) + if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1)) { - UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(pllfreq); + if(status == SUCCESS) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_SetSystemCoreClock(pllfreq); + } } #endif } @@ -428,8 +582,9 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS { ErrorStatus status; uint32_t pllfreq; -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t hpre = 0U; /* Set default value */ +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + uint32_t hpre = LL_RCC_SYSCLK_DIV_1; /* Set default value */ #endif /* Check if one of the PLL is enabled */ @@ -452,26 +607,34 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->PLLR); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ if(pllfreq > 80000000U) { - hpre = UTILS_ClkInitStruct->AHBCLKDivider; - if(hpre == LL_RCC_SYSCLK_DIV_1) + if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1) { UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + hpre = LL_RCC_SYSCLK_DIV_2; } } #endif /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Apply definitive AHB prescaler value if necessary */ - if((status == SUCCESS) && (hpre != 0U)) + if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1)) { - UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(pllfreq); + if(status == SUCCESS) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_SetSystemCoreClock(pllfreq); + } } #endif } @@ -509,7 +672,8 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa { ErrorStatus status; uint32_t pllfreq; -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) uint32_t hpre = 0U; /* Set default value */ #endif @@ -548,26 +712,34 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->PLLR); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ if(pllfreq > 80000000U) { - hpre = UTILS_ClkInitStruct->AHBCLKDivider; - if(hpre == LL_RCC_SYSCLK_DIV_1) + if(UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1) { UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + hpre = LL_RCC_SYSCLK_DIV_2; } } #endif /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) /* Apply definitive AHB prescaler value if necessary */ - if((status == SUCCESS) && (hpre != 0U)) + if((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1)) { - UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(pllfreq); + if(status == SUCCESS) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_SetSystemCoreClock(pllfreq); + } } #endif } @@ -591,138 +763,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa /** @addtogroup UTILS_LL_Private_Functions * @{ */ -/** - * @brief Update number of Flash wait states in line with new frequency and current - voltage range. - * @param HCLK_Frequency HCLK frequency - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified - */ -static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) -{ - ErrorStatus status = SUCCESS; - - uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ - - /* Frequency cannot be equal to 0 */ - if(HCLK_Frequency == 0U) - { - status = ERROR; - } - else - { - if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) - { -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - if(HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) - { - /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */ - latency = LL_FLASH_LATENCY_5; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) - { - /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */ - latency = LL_FLASH_LATENCY_4; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) - { - /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) - { - /* 40 < HCLK <= 20 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) - { - /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ - } -#else - if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) - { - /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */ - latency = LL_FLASH_LATENCY_4; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) - { - /* 48 < HCLK <= 64 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) - { - /* 32 < HCLK <= 48 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) - { - /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency <= 16MHz default LL_FLASH_LATENCY_0 0WS */ - } -#endif - } - else /* SCALE2 */ - { -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) - { - /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) - { - /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */ - } -#else - if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) - { - /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) - { - /* 12 < HCLK <= 18 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) - { - /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency <= 6MHz default LL_FLASH_LATENCY_0 0WS */ - } -#endif - } - - LL_FLASH_SetLatency(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(LL_FLASH_GetLatency() != latency) - { - status = ERROR; - } - } - return status; -} - /** * @brief Function to check that PLL can be modified * @param PLL_InputFrequency PLL input frequency (in Hz) @@ -818,7 +858,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if(SystemCoreClock < hclk_frequency) { /* Set FLASH latency to highest latency */ - status = UTILS_SetFlashLatency(hclk_frequency); + status = LL_SetFlashLatency(hclk_frequency); } /* Update system clock configuration */ @@ -849,7 +889,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if(SystemCoreClock > hclk_frequency) { /* Set FLASH latency to lowest latency */ - status = UTILS_SetFlashLatency(hclk_frequency); + status = LL_SetFlashLatency(hclk_frequency); } /* Update SystemCoreClock variable */ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 37e40ec5aa..fac9df9db7 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -11,7 +11,7 @@ * STM32H7: 1.7.0 * STM32L0: 1.10.2 * STM32L1: 1.4.0 - * STM32L4: 1.11.0 + * STM32L4: 1.11.1 * STM32MP1: 1.2.0 * STM32WB: 1.5.0 From 46940eff6557a4adf785ababd378b1f7dd9c8f14 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 6 May 2020 14:55:18 +0200 Subject: [PATCH 2/2] [L4] Update STM32L4xx CMSIS Drivers to v1.6.1 Included in STM32CubeL4 FW v1.15.1 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32L4xx/Include/stm32l4p5xx.h | 6 ++ .../Device/ST/STM32L4xx/Include/stm32l4q5xx.h | 6 ++ .../Device/ST/STM32L4xx/Include/stm32l4r5xx.h | 3 + .../Device/ST/STM32L4xx/Include/stm32l4r7xx.h | 3 + .../Device/ST/STM32L4xx/Include/stm32l4r9xx.h | 3 + .../Device/ST/STM32L4xx/Include/stm32l4s5xx.h | 3 + .../Device/ST/STM32L4xx/Include/stm32l4s7xx.h | 3 + .../Device/ST/STM32L4xx/Include/stm32l4s9xx.h | 3 + .../Device/ST/STM32L4xx/Include/stm32l4xx.h | 2 +- .../Device/ST/STM32L4xx/Release_Notes.html | 55 +++++++++++++------ .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 11 files changed, 69 insertions(+), 20 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4p5xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4p5xx.h index 5c9c8122eb..c1d7d59483 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4p5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4p5xx.h @@ -15773,6 +15773,9 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ +#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ +#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) #define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */ #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */ @@ -15798,6 +15801,9 @@ typedef struct #define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for OCTOSPI_DCR3 register ******************/ +#define OCTOSPI_DCR3_MAXTRAN_Pos (0U) +#define OCTOSPI_DCR3_MAXTRAN_Msk (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */ +#define OCTOSPI_DCR3_MAXTRAN OCTOSPI_DCR3_MAXTRAN_Msk /*!< Maximum Transfer */ #define OCTOSPI_DCR3_CSBOUND_Pos (16U) #define OCTOSPI_DCR3_CSBOUND_Msk (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */ #define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk /*!< CS Boundary */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4q5xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4q5xx.h index fa0ba38f99..3c60a8c3ac 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4q5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4q5xx.h @@ -16284,6 +16284,9 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ +#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ +#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) #define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */ #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */ @@ -16309,6 +16312,9 @@ typedef struct #define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ /**************** Bit definition for OCTOSPI_DCR3 register ******************/ +#define OCTOSPI_DCR3_MAXTRAN_Pos (0U) +#define OCTOSPI_DCR3_MAXTRAN_Msk (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */ +#define OCTOSPI_DCR3_MAXTRAN OCTOSPI_DCR3_MAXTRAN_Msk /*!< Maximum Transfer */ #define OCTOSPI_DCR3_CSBOUND_Pos (16U) #define OCTOSPI_DCR3_CSBOUND_Msk (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */ #define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk /*!< CS Boundary */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h index 769e380077..b85460afb9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h @@ -14791,6 +14791,9 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ +#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ +#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) #define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */ #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r7xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r7xx.h index 7ad84b6427..dce37da112 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r7xx.h @@ -15290,6 +15290,9 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ +#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ +#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) #define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */ #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h index af54842977..1ecad70cc1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h @@ -18422,6 +18422,9 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ +#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ +#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) #define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */ #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s5xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s5xx.h index caf70bae13..52391e14de 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s5xx.h @@ -15138,6 +15138,9 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ +#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ +#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) #define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */ #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s7xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s7xx.h index d7731cbb97..8640468a79 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s7xx.h @@ -15637,6 +15637,9 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ +#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ +#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) #define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */ #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s9xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s9xx.h index c10d10b371..cbcfabe9af 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s9xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4s9xx.h @@ -18769,6 +18769,9 @@ typedef struct #define OCTOSPI_DCR1_FRCK_Pos (1U) #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ +#define OCTOSPI_DCR1_DLYBYP_Pos (1U) +#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000004 */ +#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block Bypass */ #define OCTOSPI_DCR1_CSHT_Pos (8U) #define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */ #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h index a59a81b8ed..619e8c06b4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h @@ -107,7 +107,7 @@ */ #define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L4_CMSIS_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Release_Notes.html index 60490740fb..c427881ea9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L4xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32L4xx/Release_Notes.html @@ -54,10 +54,29 @@

                                                Purpose

                                                Update History

                                                - +

                                                Main Changes

                                                  +
                                                • Add bit definitions in OCTOSPI registers +
                                                    +
                                                  • stm32l4p5xx.h, stm32l4q5xx.h, stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h and stm32l4s9xx.h +
                                                      +
                                                    • Add OCTOSPI DLYBYP field definition in DCR1 register
                                                      • +
                                                    • +
                                                  • stm32L4p5xx.h and stm32L4q5xx.h +
                                                      +
                                                    • Add OCTOSPI MAXTRAN field definition in DCR3 register
                                                      • +
                                                    • +
                                                  • +
                                                +
                                                +
                                                +
                                                + +
                                                +

                                                Main Changes

                                                +
                                                • Add the support of STM32L4P5xx/STM32L4Q5xx devices
                                                  • Add stm32l4p5xx.h and stm32l4q5xx.h device description files
                                                    • @@ -110,7 +129,7 @@

                                                    Main Changes

                                                    -

                                                    Main Changes

                                                    +

                                                    Main Changes

                                                    • stm32l412xx.h, stm32l422xx.h, stm32l431xx.h, stm32l432xx.h, stm32l433xx.h, stm32l442xx.h, stm32l443xx.h, stm32l451xx.h, stm32l452xx.h, stm32l462xx.h and stm32l471xx.h
                                                        @@ -151,7 +170,7 @@

                                                        Main Changes

                                                        -

                                                        Main Changes

                                                        +

                                                        Main Changes

                                                        • Add stm32l412xx.h and stm32l422xx.hdevice description files
                                                        • Add startup filesstartup_stm32l412xx.sand startup_stm32l422xx.sfor EWARM, MDK-ARM and SW4STM32 toolchains
                                                          • @@ -184,7 +203,7 @@

                                                          Main Changes

                                                          -

                                                          Main Changes

                                                          +

                                                          Main Changes

                                                          • All stm32l4XXxx.h device description files

                                                              @@ -207,7 +226,7 @@

                                                              Main Changes

                                                              -

                                                              Main Changes

                                                              +

                                                              Main Changes

                                                              • SPI_TypeDef cleanup of Reserved fields.
                                                              @@ -216,7 +235,7 @@

                                                              Main Changes

                                                              -

                                                              Main Changes

                                                              +

                                                              Main Changes

                                                              stm32l4r5xx.h and stm32l4s5xx.h description files

                                                              • Remove LTDC peripheral definitions as LTDC not available on STM32L4R5xx/STM32L4S5xx devices
                                                                • @@ -226,7 +245,7 @@

                                                                Main Changes

                                                                -

                                                                Main Changes

                                                                +

                                                                Main Changes

                                                                • Add the support of STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx devices

                                                                    @@ -263,7 +282,7 @@

                                                                    Main Changes

                                                                    -

                                                                    Main Changes

                                                                    +

                                                                    Main Changes

                                                                    • stm32l451xx.h, stm32l452xx.h, stm32l462xx.h description files

                                                                        @@ -290,7 +309,7 @@

                                                                        Main Changes

                                                                        -

                                                                        Main Changes

                                                                        +

                                                                        Main Changes

                                                                        • stm32l496xx.h and stm32l4a6xx.h device description files

                                                                            @@ -309,7 +328,7 @@

                                                                            Main Changes

                                                                            -

                                                                            Main Changes

                                                                            +

                                                                            Main Changes

                                                                            • Add the support of STM32L496xx/STM32L4A6xx devices

                                                                                @@ -336,7 +355,7 @@

                                                                                Main Changes

                                                                                -

                                                                                Main Changes

                                                                                +

                                                                                Main Changes

                                                                                • Add the support of STM32L451xx/STM32L452xx/STM32L462xx devices

                                                                                    @@ -370,7 +389,7 @@

                                                                                    Main Changes

                                                                                    -

                                                                                    Main Changes

                                                                                    +

                                                                                    Main Changes

                                                                                    • Fix DAC_SR_BWST1 bit definition

                                                                                    • Fix SDMMC_DCTRL_DBLOCKSIZE_2 and SDMMC_DCTRL_DBLOCKSIZE_3 bits definition

                                                                                      • @@ -386,7 +405,7 @@

                                                                                      Main Changes

                                                                                      -

                                                                                      Main Changes

                                                                                      +

                                                                                      Main Changes

                                                                                      • All device register description files enriched with _Pos and _Msk defines to be used with _VAL2FLD(field, value) and _FLD2VAL(field, value) from CMSIS Core (previous defines are kept for compatibility)

                                                                                      • stm32l471xx.h, stm32l475xx.h, stm32l476xx.h, stm32l485xx.h and stm32l486xx.h device description files

                                                                                        @@ -442,7 +461,7 @@

                                                                                        Main Changes

                                                                                        -

                                                                                        Main Changes

                                                                                        +

                                                                                        Main Changes

                                                                                        • Add the support of STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx devices

                                                                                            @@ -476,7 +495,7 @@

                                                                                            Main Changes

                                                                                            -

                                                                                            Main Changes

                                                                                            +

                                                                                            Main Changes

                                                                                            • stm32l471xx.h, stm32l475xx.h, stm32l476xx.h, stm32l485xx.h and stm32l486xx.h device description files

                                                                                                @@ -500,7 +519,7 @@

                                                                                                Main Changes

                                                                                                -

                                                                                                Main Changes

                                                                                                +

                                                                                                Main Changes

                                                                                                • stm32l471xx.h, stm32l475xx.h, stm32l476xx.h, stm32l485xx.h and stm32l486xx.h device description files

                                                                                                    @@ -537,7 +556,7 @@

                                                                                                    Main Changes

                                                                                                    -

                                                                                                    Main Changes

                                                                                                    +

                                                                                                    Main Changes

                                                                                                    • stm32l471xx.h, stm32l475xx.h, stm32l476xx.h, stm32l485xx.h and stm32l486xx.h devicedescription files

                                                                                                        @@ -569,7 +588,7 @@

                                                                                                        Main Changes

                                                                                                        -

                                                                                                        Main Changes

                                                                                                        +

                                                                                                        Main Changes

                                                                                                        • First official release for STM32L471xx, STM32L475xx, STM32L476xx, STM32L485xx and STM32L486xx devices
                                                                                                          • diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index bdece64190..5c51e64392 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -11,7 +11,7 @@ * STM32H7: 1.7.0 * STM32L0: 1.9.0 * STM32L1: 2.3.0 - * STM32L4: 1.6.0 + * STM32L4: 1.6.1 * STM32MP1: 1.2.0 * STM32WB: 1.4.0